SLVS262 − FEBRUARY 2000 D High-Speed Output Circuit to Drive PNP D D D D D D D D D Power Transistor Precision Reference Voltage . . . 1.5 V ±2% at TA = 25°C Oscillator Frequency . . . 50 kHz to 0.8 MHz Low Supply Voltage Operation VCC = 2.5 V to 12 V Output Voltage Limit (Channel 5 and 6) Low Supply Current Internal Undervoltage Lockout Protection Internal Short-Circuit Protection Shutdown Function External Sink Current Setting on Output Stage description The TL1466I is a six channel pulse-width-modulation (PWM) control circuit. This device contains reference voltage with a precision of ±2%, a triangle wave oscillator capable of high frequency oscillation up to 0.8 MHz, various protection circuitry, and shutdown circuitry. The output regulation voltage for each channel is set by an external resistor divider. Moreover, the output stage is capable of driving a PNP power transistor with high speed. The high frequency/efficiency switching operation eliminates switching loss by using internal over-drive circuitry at the rising edge and with reverse bias connecting external bootstrap capacitor at the falling edge. The MOSFET can be used in parallel with the output diode at channel 1 and 4. This results in further high efficiency operation replacing the constant time with this MOSFET when the output diode is turned on. Furthermore, it operates 2.5 V supply voltage and balances switching current by switching repeatedly at the reverse phase with two pairs (channel 1, 4, 6, and 2, 3, 5) of the six channels. The oscillator output of channel 1, 4, and 6 is reverse phase for channel 2, 3, and 5. As a result of these features, this device is well-suited for power supply of portable systems in battery-powered equipment. FUNCTION TABLE FOR STANDBY INPUT STANDBY VI ≤ 0.4 V OUTPUT STANDBY-3 X† VI ≥ 2 V VI ≤ 0.4 V † X: High-level or low-level VI ≥ 2 V VREF OUTPUT1, 2, 4, 5, 6 OUTPUT3 OFF OFF OFF ON ON ON ON ON OFF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLVS262 − FEBRUARY 2000 pin assignments 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FEED BACK−5 COMP−4 INV INPUT−4 FEED BACK−4 RT CT SCP MOS DUTY GND SOFT START VREF VCC STANDBY−3 STANDBY DTC−3 FEED BACK−3 BOOT CAP.L−5 BOOT CAP.H−5 OUTPUT BIAS−5 OUTPUT−6 BOOT CAP.L−6 BOOTCAD.H−6 OUTPUT BIAS−6 OVP−5,6 COMP−6 NONINV INPUT−6 INV INPUT−6 FEED BACK−6 COMP COMP−5 NONINV INPUT−5 INV INPUT−5 OUTPUT−2 BOOT CAP.L−2 OUTPUT−5 OUTPUT V CC −4,5,6 OUTPUT BIAS−4 OUTPUT GND−4,5,6 MOS GATE−4 BOOTCAP.H−4 BOOT CAP.L−4 OUTPUT−4 OUTPUT−3 BOOT CAP.L−3 BOOT CAP.H−3 OUTPUT GND−1,2,3 OUTPUT BIAS−3 OUTPUT V CC −2 PM PACKAGE (TOP VIEW) 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 BOOT CAP.H−2 OUTPUT BIAS−2 OUTPUT−1 BOOT CAP.L−1 BOOT CAP.H−1 MOS GATE−1 OUTPUT VCC−1,3 OUTPUT BIAS−1 COMP−1 INV INPUT−1 FEED BACK−1 COMP−2 INV INPUT−2 FEED BACK−2 COMP−3 INV INPUT−3 SLVS262 − FEBRUARY 2000 functional block diagram OUT CH−1 IN OUTVCC13 ERR AMP1 FB COMP1 INV SCP MOSG1 COMP OUT CH−2 IN OUTVCC2 ERR AMP1 COMP2 SCP DTC3 OUT CH−3 IN ERR AMP3 COMP3 SCP OUT CH−4 IN ERR AMP4 COMP4 SCP MOSG4 OUT CH−5 IN ERR AMP5 COMP5 SCP OUT CH−6 IN ERR AMP6 COMP6 OVP SCP VI MOS DUTY TIMER and LATCH MDUTY CTR LOGIC CS OSC SCP COMP VREF STANDBY VCC STANDBY LOGIC VOLTAGE REF U.V.L.O STANDBY3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLVS262 − FEBRUARY 2000 Terminal Functions TERMINAL NAME DESCRIPTION NO. BOOT CAP.H−1 44 BOOT CAP.L−1 45 BOOT CAP.H−2 48 BOOT CAP.L−2 49 BOOT CAP.H−3 54 BOOT CAP.L−3 55 BOOT CAP.L−4 58 BOOT CAP.H−4 59 BOOT CAP.L−5 1 BOOT CAP.H−5 2 BOOT CAP.L−6 5 BOOT CAP.H−6 6 COMP 13 Output regulation voltage monitor terminal. When this terminal voltage drops below VREF voltage (1.5 V), charging to capacitor connected to SCP terminal (pin 23) is initiated. COMP−1 40 Output regulation voltage monitor terminal (channel 1). When this terminal voltage drops below VREF voltage (1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated. COMP−2 37 Output regulation voltage monitor terminal (channel 2). When this terminal voltage drops below VREF voltage (1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated. COMP−3 34 Output regulation voltage monitor terminal (channel 3). When this terminal voltage drops below VREF voltage (1.5 V), charging to capacitor connected to SCP terminal (pin 23) is initiated. COMP−4 18 Output regulation voltage monitor terminal (channel 4). When this terminal voltage drops below VREF voltage (1.5 V) charging to capacitor connected to SCP terminal (pin 23) is initiated. COMP−5 14 Output regulation voltage monitor terminal (channel 5). When this terminal voltage drops below NONINV INPUT−5 terminal voltage − 0.55 V, charging to capacitor connected to SCP terminal (pin 23) is initiated. COMP−6 9 Output regulation voltage monitor terminal (channel 6). When this terminal voltage drops below NONINV INPUT−6 terminal voltage − 0.55 V, charging to capacitor connected to SCP terminal (pin 23) is initiated. CT 22 Timing capacitor connection for oscillation frequency setting. DTC−3 31 Dead-time control input for channel 3. The maximum ON duty cycle for OUTPUT−3 terminal is determined by comparing the input voltage of this terminal with the oscillator output (triangle wave). FEEDBACK−1 38 Error amplifier output terminal (channel 1) FEEDBACK−2 35 Error amplifier output terminal (channel 2) FEEDBACK−3 32 Error amplifier output terminal (channel 3) FEEDBACK−4 20 Error amplifier output terminal (channel 4) FEEDBACK−5 17 Error amplifier output terminal (channel 5) FEEDBACK−6 12 Error amplifier output terminal (channel 6) GND 25 Logic ground INV INPUT−1 39 Error amplifier inverting input terminal (channel 1) INV INPUT−2 36 Error amplifier inverting input terminal (channel 2) INV INPUT−3 33 Error amplifier inverting input terminal (channel 3) INV INPUT−4 19 Error amplifier inverting input terminal (channel 4) INV INPUT−5 16 Error amplifier inverting input terminal (channel 5) INV INPUT−6 11 Error amplifier inverting input terminal (channel 6) MOS DUTY 24 N-channel MOSFET ON duty cycle setting for the synchronous rectification of channel 1 and 4. The MOSFET ON duty cycle for the synchronous rectification is determined by the resistor value connected between this terminal and GND. 4 Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 1. Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 2. Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 3 Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 4. Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 5. Bootstrap capacitor connection. The connection allows reverse-bias for external PNP transistor of channel 6. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS262 − FEBRUARY 2000 Terminal Functions (Continued) TERMINAL NAME DESCRIPTION NO. MOS GATE−1 43 N-Channel MOSFET gate drive for the synchronous rectification of channel 1. The ON duty cycle for this terminal is determined by the resistor value connected to MOS DUTY (pin 24). MOS GATE−4 60 N-Channel MOSFET gate drive for the synchronous rectification of channel 4. The ON duty cycle for this terminal is determined by the resistor value connected to MOS DUTY (pin 24). NONINV INPUT−5 15 Error amplifier noninverting input terminal (channel 6). By connecting resistor and capacitor to this terminal, soft start function is accomplished increasing this terminal voltage slowly. NONINV INPUT−6 10 Error amplifier noninverting input terminal (channel 6). By connecting resistor and capacitor to this terminal, soft start function is accomplished increasing this terminal voltage slowly. OUTPUT−1 46 Output terminal to drive base for external PNP transistor of channel 1. OUTPUT−2 50 Output terminal to drive base for external PNP transistor of channel 2. OUTPUT−3 56 Output terminal to drive base for external PNP transistor of channel 3. OUTPUT−4 57 Output terminal to drive base for external PNP transistor of channel 4. OUTPUT−5 64 Output terminal to drive base for external PNP transistor of channel 5. OUTPUT−6 4 Output terminal to drive base for external PNP transistor of channel 6. OUTPUT BIAS−1 41 Resistor connection to set output sink current for OUTPUT−1 terminal (pin 46) of channel 1. OUTPUT BIAS−2 47 Resistor connection to set output sink current for OUTPUT−2 terminal (pin 50) of channel 2. OUTPUT BIAS−3 52 Resistor connection to set output sink current for OUTPUT−3 terminal (pin 56) of channel 3. OUTPUT BIAS−4 62 Resistor connection to set output sink current for OUTPUT−4 terminal (pin 57) of channel 4. OUTPUT BIAS−5 3 Resistor connection to set output sink current for OUTPUT−5 terminal (pin 64) of channel 5. OUTPUT BIAS−6 7 Resistor connection to set output sink current for OUTPUT−6 terminal (pin 4) of channel 6. OUTPUT GND−1,2,3 53 Ground for channel 1, 2, and 3 output. OUTPUT GND−4,5,6 61 Ground for channel 4, 5, and 6 output. OUTPUT VCC−1,3 42 Supply voltage for channel 1 and 3 outputs. OUTPUT VCC−2 51 Supply voltage for channel 2 output. OUTPUT VCC−4,5,6 63 Supply voltage for channel 4, 5, and 6 outputs. OVP−5,6 8 Over-voltage threshold voltage setting for output regulation voltage of channel 5 and 6. RT 21 Timing resistor connection for oscillation frequency setting. SCP 23 Capacitor connection for short-circuit protection. When voltage across COMP terminal for each channel is dropped below the specified threshold voltage, the capacitor connected between SCP and GND is charged by the constant current source (2.5 µA Typ). If the voltage reaches to 1.5 V, the timer latch circuitry is set and all channel outputs are forced to turn off. SOFT START 26 Soft start operation for channel 1 to 4. By connecting a capacitor between this terminal connected internally to error amplifier noninverting input for channel 1 to 4 and GND, soft start operation is enabled charging a capacitor with the constant current source (3 µA Typ). Moreover, the same soft start operation is also enabled at the standby release using STANDBY−3 terminal only for channel 3. STANDBY 30 ON/OFF common control input for all channels. The all channels output is turned off by adding low-level input voltage (0.4 V Max) to this terminal, and the reference voltage is also shutdown. STANDBY−3 29 ON/OFF control input for channel 3. The channel 3 output is turned off by adding low-level input voltage (0.4 V Max) to this terminal. VCC VREF 28 Supply voltage 27 1.5 V reference voltage output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SLVS262 − FEBRUARY 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V Input voltage, VI at OVP, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V Error amplifier input voltage, V(AMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V Peak output sink current, I(SINK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Peak output source current, I(SOURCE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 A Continuous power total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . . . . 1785 mW Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20°C to 75°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to GND. 2. Device mounted on a 50 mm × 1.6 mm, fFR4 printed-circuit board. recommended operating conditions MIN Supply voltage, VCC High-level standby input voltage (pin 29, 30), VI(HS) NOM 12 V 2 VCC 0.4 V 12 V Output voltage, VO Channel 1, 4 −30 Channel 2, 3, 5, 6 −45 Feedback capacitance, C(NF) 0.5 5 Bootstrap capacitance, C(BOOT) 100 500 Bias resistor, R(BIAS) Timing resistor, R(T) Timing capacitor, C(T) UNIT 2.5 Low-level standby input voltage (pin 29, 30), VI(LS) Current into feedback terminal, IOAMP MAX 100 V µA A nF pF 3 20 kΩ 12 100 kΩ 68 1000 Oscillator frequency, f(osc) 0.05 0.8 MHz pF Operating free-air temperature, TA −20 75 °C electrical characteristics over recommended operating free-air temperature range, VCC = 6 V, f = 0.43 MHz (unless otherwise noted) reference section PARAMETER Vref R(EGIN) Output voltage (pin 27) R(EGL) Load regulation TEST CONDITIONS TA = 25°C, VCC = 2.5 V to 12 V, Line regulation V(RTC1) V(RTC2) Output voltage change with temperature IOS Short-circuit output current 6 IOR = −1 mA IOR = −1 mA MIN TYP MAX UNIT 1.47 1.50 1.53 V 2 12.5 mV 1 7.5 mV −0.2% ±2% −0.2% ±2% IOL = −0.1 mA to −1 mA TA = −20°C to 25°C TA = 25°C to 75°C Vref = 0 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 −4 −20 mA SLVS262 − FEBRUARY 2000 electrical characteristics over recommended operating free-air temperature range, VCC = 6 V, f = 0.43 MHz (unless otherwise noted) (continued) undervoltage lockout section PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(th) V(tl) High-level threshold voltage 2.45 V Low-level threshold voltage 2.35 V Vhys V(R) Hysteresis 0.05 0.1 V 2.1 2.2 V TA = 25°C Reset threshold voltage (VCC) oscillator section PARAMETER TEST CONDITIONS f(OSC) f(dev) Oscillator frequency C(T) = 100 pF, Standard deviation of frequency All the values are constant f(dv) f(dT1) Frequency change with voltage VCC = 2.5 V to 12 V TA = −20°C to 25°C f(dT2) Frequency change with temperature MIN R(T) = 47 kΩ TYP MAX 0.43 UNIT MHz 7% 1% −0.5% ±4% 0.5% ±4% MIN TYP MAX UNIT 1.45 1.50 1.55 V TA = 20°C to 75°C output voltage monitor section PARAMETER TEST CONDITIONS V(tOM) Input threshold voltage (COMP terminals: pin 13, 18, 34, 37, 40) TA = 25°C (channel 1, 2, 3, 4) V(IOOM) Input offset voltage (pin 9, 14) VI(10, 15 pin) = 1.5 V, TA = 25°C (channel 5,6) 0.55 I(ICOMP) Input bias current VI = 1 V VI = 0.5 V, −0.8 −2 Pin 13, 18, 34, 37, 40 Pin 9, 14 VI(10, 15 pin) = 1.5 V V µA short-circuit protection control section PARAMETER V(tPC) Input threshold voltage (pin 23) V(STBY) UVLO standby voltage (pin 23) VI I(bPC) TEST CONDITIONS MIN TYP MAX UNIT TA = 25°C 1.45 1.53 1.61 V 20 60 100 mV 10 30 mV −1 −2.5 −3.5 µA MIN TYP MAX UNIT −1 −6 Latched input voltage (pin 23) Input source current (pin 23) TA = 25°C dead-time control section (channel 3) PARAMETER I(Idt) V(t) V(t100) TEST CONDITIONS Input current (DTC−3 terminal: pin 31) Input threshold voltage POST OFFICE BOX 655303 VI(31 pin) = 0.5 V Duty cycle = 0% 0.55 0.65 0.75 Duty cycle = 100% 1.25 1.35 1.45 • DALLAS, TEXAS 75265 µA V 7 SLVS262 − FEBRUARY 2000 electrical characteristics over recommended operating free-air temperature range, VCC = 6 V, f = 0.43 MHz (unless otherwise noted) (continued) error-amplifier section PARAMETER TEST CONDITIONS MIN TYP MAX 1.46 1.50 1.54 5 40 INV INPUT (pin 11, 16, 19, 33, 36, 39) −200 −500 nA INV INPUT (pin 10, 15) −0.9 −2.5 µA V(t) VIO Input threshold voltage Input offset current VO = 1 V (channel 1, 2, 3, 4) VO = 1 V (channel 5, 6) IIB Input bias current VO = 1 V VICR Common-mode input voltage range VCC = 2.5 V to 12 V A(v) Open-loop voltage amplification B1 Unity-gain bandwidth VOM+ VOM− Positive output voltage swing IOM+ Output sink current IOM− 0 to VCC−1 70 dB 6 MHz V Negative output voltage swing Output source current 0.2 VO = 1 V V mV V Vref−0.1 VO = 1 V UNIT 0.5 2 Channel 1, 4 −30 −80 Channel 2, 3, 5, 6 −45 −100 MIN TYP MAX V mA µA output voltage limit section (channel 5, 6) PARAMETER V(tOV) V(BOV) TEST CONDITIONS Input threshold voltage VI(10, 15 pin) = 1 V VI(8 pin) = 1.5 V, VI(10, 15 pin) = 1 V Input bias current 0.95 UNIT 1 1.05 V −0.7 −2 µA MIN TYP MAX −1 −2.5 −4 TYP MAX UNIT UNIT soft start section PARAMETER I(bss) TEST CONDITIONS STANDBY−3 terminal = 2 V SOFT START terminal = 1 V Input source current (pin 26) UNIT µA MOSFET DUTY setting section (channel 1, 4) PARAMETER D(MOS) TEST CONDITIONS ON DUTY V(FB) = 1 V MIN RDUTY = 5 kΩ 20% RDUTY = 25 kΩ 40% output section PARAMETER TEST CONDITIONS I(SINK) Output sink current I(GSOURCE) I(GSINK) MOS gate source current I(GOH) I(GOL) MOS gate high-level output voltage MIN TYP MAX R(BIAS) = 6.8 kΩ 6.3 8.5 10.7 R(BIAS) = 10 kΩ 4.5 6 7.5 VO(43, 60 pin) = 1 V, VO(43, 60 pin) = 2 V, MOS gate sink current TA = 25°C TA = 25°C 3.5 MOS gate low-level output voltage mA −50 mA 50 mA 4 0.1 0.3 TYP MAX V total device PARAMETER I(ccs) I(cca) 8 TEST CONDITIONS MIN UNIT Standby supply current STANDBY terminal = 0 V 1 10 µA Average supply current R(T) = 47 kΩ 6 9 mA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS262 − FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION Oscillator Triangle Waveform (Note A) Error Amplifier Output (FEED BACK1, 4) 1.35 V 0.65 V H PWM Comparator Output Voltage L Dead Time 100% Output Waveform (OUTPUT1, 4) H Synchronous Rectification Output Waveform (MOS GATE1, 4) (Note B) H L L Output Regulation Voltage Monitor Waveform (COMP1, 4) 1.5 V 1.5 V 1.5 V 0V Vref +0.7 1.5 V SCP Terminal Waveform tpe H SCP Comparator Output L Power Supply Voltage VCC 2.45 V TYP 0V † Protection enable time, tpe = (588 × 103 × Cpe) in seconds NOTES: A. The oscillator output of channel 1, 4, and 6 is reverse phase for channel 2, 3, and 5. B. The ON (high-level output state) time for the synchronous rectification output (MOS GATE1, 4) is determined by the resistor value connected to MOS DUTY terminal (pin 24) and this time is controlled internally without exceeding OFF (high-level output state) of output (OUTPUT1,4). Figure 1. Timing Diagram (channel 1, 4) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLVS262 − FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION Oscillator Triangle Waveform (Note A) Error Amplifier Output (FEED BACK) 1.35 V 0.65 V H PWM Comparator Output Voltage L Dead Time 100% H Output Waveform (OUTPUT2) L Output Regulation Voltage Monitor Waveform (COMP2) 1.5 V 1.5 V 1.5 V 0V Vref +0.7 1.5 V SCP Terminal Waveform tpe H SCP Comparator Output L Power Supply Voltage VCC 2.45 V TYP 0V † Protection enable time, tpe = (588 × 103 × Cpe) in seconds NOTE A: The oscillator output of channel 1, 4, and 6 is reverse phase for channel 2, 3, and 5. Figure 2. Timing Diagram (channel 2) 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS262 − FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION Oscillator Triangle Waveform (Note A) Dead−Time Input Voltage (DTC−3) Error Amplifier Output (FEED BACK3) 1.35 V 0.65 V H PWM Comparator Output Voltage L Dead Time 100% H Output Waveform (OUTPUT3) L Output Regulation Voltage Monitor Waveform (COMP3) 1.5 V 1.5 V 1.5 V 0V Vref +0.7 1.5 V SCP Terminal Waveform tpe H SCP Comparator Output L Power Supply Voltage VCC 2.45 V TYP 0V † Protection enable time, tpe = (588 × 103 × Cpe) in seconds NOTE A: The oscillator output of channel 1, 4, and 6 is reverse phase for channel 2, 3, and 5. Figure 3. Timing Diagram (channel 3) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLVS262 − FEBRUARY 2000 PARAMETER MEASUREMENT INFORMATION Oscillator Triangle Waveform (Note A) Error Amplifier Output (FEED BACK5, 6) 1.35 V 0.65 V H PWM Comparator Output Voltage L Dead Time 100% H Output Waveform (OUTPUT5, 6) L Output Regulation Voltage Monitor Waveform (COMP5, 6) (Note B) 1.5 V 1.5 V 1.5 V 0V Vref +0.7 1.5 V SCP Terminal Waveform tpe H SCP Comparator Output L Power Supply Voltage VCC 2.45 V TYP 0V † Protection enable time, tpe = (588 × 103 × Cpe) in seconds NOTES: A. The oscillator output of channel 1, 4, and 6 is reverse phase for channel 2, 3, and 5. B. The threshold voltage at V(A) is set by following the formula below: V(A) Input voltage of NONINV INPUT terminal (pin 10, 15) −0.55 V Figure 4. Timing Diagram (channel 5, 6) 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS262 − FEBRUARY 2000 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs TIMING RESISTANCE OSCILLATOR FREQUENCY vs FREE-AIR TEMPERATURE 450 VCC=6 V TA = 25°C CT = 150 pF 1M f (osc) −− Oscillator Frequency − kHz f (osc) −− Oscillator Frequency − Hz 10M CT = 220 pF CT = 68 pF 100k CT = 330 pF CT = 470 pF 10k CT = 1000 pF 1k 1k 10k 100k VCC = 6V RT = 47 kΩ CT = 100 pF 440 430 420 410 400 −50 1M RT − Timing Resistance − Ω AVERAGE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 100 AVERAGE SUPPLY CURRENT vs SUPPLY VOLTAGE 6.0 10.0 VCC = 6V RT = 47 kΩ f (cca) −− Average Supply Current − mA f (cca) −− Average Supply Current − mA 50 Figure 6 Figure 5 5.5 5.0 4.5 −50 0 TA − Free-Air Temperature − °C RT = 47 kΩ TA = 25°C 7.5 5.0 2.5 0.0 0 50 100 TA − Free-Air Temperature − °C 0 3 6 9 12 TA − Free-Air Temperature −°C Figure 8 Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLVS262 − FEBRUARY 2000 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs FREE-AIR TEMPERATURE VOLTAGE REFERENCE vs SUPPLY VOLTAGE − 1 1.51 2.0 Vref −− Voltage Reference − V Vref −− Voltage Reference − V TA = 65 °C 1.50 1.49 VCC = 6 V IOR = 1 mA 1.48 −50 1.5 1.0 0.5 0.0 0 50 100 0 1 TA − Free-Air Temperature −°C Figure 10 Figure 9 VOLTAGE REFERENCE vs SUPPLY VOLTAGE − 2 2.0 Vref −− Voltage Reference − V TA = 65 °C 1.5 1.0 0.5 0.0 0 3 6 9 VCC − Supply Voltage − V Figure 11 14 2 VCC − Supply Voltage − V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 3 SLVS262 − FEBRUARY 2000 TYPICAL CHARACTERISTICS OUTPUT SINK CURRENT vs BIAS RESISTANCE OUTPUT SINK CURRENT vs FREE-AIR TEMPERATURE 30 12 TA = 65 °C 10 I (SINK) − Output Sink Current − mA 25 I (SINK) − Output Sink Current − mA VCC = 6 V VCC = 10 V 20 15 10 VCC = 6 V 5 VCC = 3 V 0 0 5 10 15 20 25 8 R(BIAS) = 6.8 kΩ 6 R(BIAS) = 10 kΩ 4 2 0 −50 30 0 R(BIAS) − Bias Resistance − kΩ OUTPUT ON DUTY CYCLE vs DEAD-TIME INPUT VOLTAGE 150 MOSFET ON DUTY CYCLE vs RESISTANCE 125 75 D(MOS) − MOSFET ”ON” Dity Cycle − % VCC = 6 V TA = 65 °C Duty − Output”On” Dity Cycle − % 100 Figure 13 Figure 12 100 75 50 25 0 0.0 50 TA − Free-Air Temperature −°C PNP Transistor Collector Waveform (Assuming duty cycle = 50%) 50 T This Graph is Simulation Data ton(MOS) D(MOS)(%)=ton(MOS)/T 25 0 0.5 1.0 1.5 0 Dead-Time Input Voltage − V 25 50 75 R(DUTY) − Resistance − kΩ Figure 15 Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLVS262 − FEBRUARY 2000 TYPICAL CHARACTERISTICS MOSFET ON DUTY CYCLE vs FREE-AIR TEMPERATURE MOSFET GATE HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 4.4 VCC = 6V Ct = 100 pF/Rt =47 kΩ VFB = 1 V CH1 40 R(DUTY) = 25 kΩ 20 R(DUTY) = 5 kΩ 0 −50 0 50 V(GOH) − MOSFET Gate High-Level Voltage − V D(MOS) − MOSFET Gate ”ON” Dity Cycle −% 60 100 VCC = 6V CH1 4.2 4.0 3.8 −50 TA − Free-Air Temperature − °C V(GOL) − MOSFET Gate High-Level Voltage − V 0.15 VCC = 6V CH1 0.10 0.05 50 100 TA − Free-Air Temperature − °C I (GSOURCE) − MOSFET Gate Output Source Current − mA MOSFET GATE HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 0 100 MOSFET GATE OUTPUT SOURCE CURRENT vs FREE-AIR TEMPERATURE − 150 VCC = 6V CH1 − 100 − 50 − 0 −50 0 50 TA − Free-Air Temperature − °C Figure 19 Figure 18 16 50 Figure 17 Figure 16 0.00 −50 0 TA − Free-Air Temperature − °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 SLVS262 − FEBRUARY 2000 TYPICAL CHARACTERISTICS U.V.L.O THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE 150 2.5 VCC = 6V CH1 VCC = 6V V(th/thl) − U.V.L.O Threshold Voltage −V I (GSINK) − MOSFET Gate Output Sink Current − mA MOSFET GATE OUTPUT SINK CURRENT vs FREE-AIR TEMPERATURE 100 50 0 −50 0 50 V(th) 2.4 V(tl) 2.3 2.2 −50 100 TA − Free-Air Temperature − °C 1.5 VCC = 6V V(t100) 1.0 V(t0) 0 100 ERROR AMPLIFIER INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE VT − Error Amplifier Input Threshold Voltage − V V(t0) /V(t100) − Dead-Time Input Threshold Voltage − V PWM COMPARATOR THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE 0.0 −50 50 Figure 21 Figure 20 0.5 0 TA − Free-Air Temperature − °C 50 100 1.51 VCC = 6V VO = 1 V CH1 1.50 1.49 1.48 −50 TA − Free-Air Temperature − °C 0 50 100 TA − Free-Air Temperature − °C Figure 23 Figure 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SLVS262 − FEBRUARY 2000 TYPICAL CHARACTERISTICS ERROR AMPLIFIER OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 1.51 VCC = 6V CH1 1.50 1.49 1.48 −50 0 50 100 VOM− − Error Amplifier Low-evel Output Voltage − V VOM+ − Error Amplifier High-Level Output Voltage − V ERROR AMPLIFIER OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 0.06 VCC = 6V CH1 0.04 0.02 0.00 −50 0 TA − Free-Air Temperature − °C 2.0 VCC = 6V CH4 TA = 25°C 1.5 1.0 0.5 0.0 − 50 − 75 − 100 ERROR AMPLIFIER OUTPUT VOLTAGE vs OUTPUT SINK CURRENT VOM− − Error Amplifier Low-Level Output Voltage − V VOM+ − Error Amplifier High-Level Output Voltage − V ERROR AMPLIFIER OUTPUT VOLTAGE vs OUTPUT SOURCE CURRENT − 25 2.0 VCC = 6V CH4 TA = 25°C 1.5 1.0 0.5 0.0 0 IOM− − Output Source Current − µA 1 2 IOM− − Output Sink Current − µA Figure 27 Figure 26 18 100 Figure 25 Figure 24 0 50 TA − Free-Air Temperature − °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLVS262 − FEBRUARY 2000 TYPICAL CHARACTERISTICS 80 ERROR AMPLIFIER OPEN-LOOP GAIN AND PHASE SHIFT vs FREE-AIR TEMPERATURE S.C.P INPUT SOURCE CURRENT vs FREE-AIR TEMPERATURE −2.0 0 VCC = 6 V −36 Phase Shift (Right Scale) 40 −72 20 −108 0 −144 VCC = 5 V TA = 25°C −20 100 1k 10k 100k 1M I (bpc) − S.C.P Input Source Current − µ A 60 Phase Shift − ° AV − Open-Loop Gain − dB AV = (Left Scale) −2.2 −2.4 −2.6 −50 −180 10M Figure 28 100 SOFT START TIME vs SOFT START CAPACITANCE 100 100 VCC = 6 V TA = 25°C VCC = 6 V TA = 25°C 80 80 t (ss) − Soft Start Time − mS t (PE) − Protection Enable Time − µ A 50 Figure 29 PROTECTION ENABLE TIME vs S.C.P CAPACITANCE 60 40 20 0 0.00 0 TA − Free-Air Temperature − °C f − Frequency − MHz 0.05 0.10 0.15 60 40 20 0 0.00 C(SCP) − S.C.P Capacitance − µF 0.05 0.10 0.15 C(SS) − Soft Start Capacitance − µF Figure 30 Figure 31 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SLVS262 − FEBRUARY 2000 APPLICATION INFORMATION bias resistance connection for output sink current setting The bias resistance connection to set output sink current for each output of channel 1 through 6 (OUTPUT−1 to 6) should be connected as follows (refer to Figure 32): D For channel 1 and 3, connect OUTPUT BIAS to OUTPUT VCC−1,3 across bias resistance. D For channel 2, connect OUTPUT BIAS−2 to OUTPUT VCC−2 across bias resistance D For channel 4, 5, and 6, connect OUTPUT BIAS to OUTPUT VCC−4,5,6 across bias resistance. OUTPUT VCC−1,3 R−BIAS1 OUTPUT BIAS−1 R−BIAS3 OUTPUT BIAS−3 OUTPUT VCC−2 R−BIAS2 OUTPUT BIAS−2 OUTPUT VCC−4,5,6 R−BIAS4 OUTPUT BIAS−4 R−BIAS5 OUTPUT BIAS−5 R−BIAS6 OUTPUT BIAS−6 TL1466IPM Figure 32. Bias Resistance Connection for Output Sink Current Setting 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLVS262 − FEBRUARY 2000 MECHANICAL DATA PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°−ā 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 PACKAGE OPTION ADDENDUM www.ti.com 27-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TL1466IPMR ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TL1466IPMRG4 ACTIVE LQFP PM 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. 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