TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. D D D Power-On Reset Generator Automatic Reset Generation After Voltage Drop RESET Output Defined From VCC ≥ 1 V Precision Voltage Sensor TL77xxBC . . . D OR P PACKAGE TL7705BM . . . JG PACKAGE TL7705BQ . . . D PACKAGE (TOP VIEW) REF RESIN CT GND 1 8 2 7 3 6 4 5 VCC SENSE RESET RESET D D Temperature-Compensated Voltage Reference True and Complement Reset Outputs Externally Adjustable Pulse Duration TL7705BM . . . U PACKAGE (TOP VIEW) NC REF RESIN CT GND 1 10 2 9 3 8 4 7 5 6 NC VCC SENSE RESET RESET NC RESIN NC CT NC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 NC SENSE NC RESET NC NC GND NC RESET NC NC – No internal connection TL7705BM . . . FK PACKAGE (TOP VIEW) NC REF NC VCC NC D D SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 NC – No internal connection description/ordering information The TL7702B, TL7705B, and TL7733B are integrated-circuit supply-voltage supervisors designed for use as reset controllers in microcomputer and microprocessor systems. The supply-voltage supervisor monitors the supply for undervoltage conditions at the SENSE input. During power up, the RESET output becomes active (low) when VCC attains a value approaching 1 V. As VCC approaches 3 V (assuming that SENSE is above VT+), the delay-timer function activates a time delay, after which outputs RESET and RESET go inactive (high and low, respectively). When an undervoltage condition occurs during normal operation, outputs RESET and RESET go active. To ensure that a complete reset occurs, the reset outputs remain active for a time delay after the voltage at the SENSE input exceeds the positive-going threshold value. The time delay is determined by the value of the external capacitor CT: td ≈ 2.6 × 104 × CT, where CT is in farads (F) and td is in seconds (s). An external capacitor (typically 0.1 µF) must be connected to REF to reduce the influence of fast transients in the supply voltage. The TL7702BC, TL7705BC, and TL7733BC are characterized for operation from 0°C to 70°C. The TL7702BI, TL7705BI, and TL7733BI are characterized for operation from –40°C to 85°C. The TL7705BQ is characterized for operation from –40°C to 125°C. The TL7705BM is characterized for operation from –55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 description/ordering information (continued) ORDERING INFORMATION PDIP (P) SOIC (D) PDIP (P) 0°C to 70°C SOIC (D) PDIP (P) SOIC (D) PDIP (P) SOIC (D) PDIP (P) –40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA SOIC (D) PDIP (P) SOIC (D) Tube of 50 TL7702BCP Tube of 75 TL7702BCD Reel of 2500 TL7702BCDR Tube of 50 TL7705BCP Tube of 75 TL7705BCD Reel of 2500 TL7705BCDR Tube of 50 TL7733BCP Tube of 75 TL7733BCD Reel of 2500 TL7733BCDR Tube of 50 TL7702BIP Tube of 75 TL7702BID Reel of 2500 TL7702BIDR Tube of 50 TL7705BIP Tube of 75 TL7705BID Reel of 2500 TL7705BIDR Tube of 50 TL7733BIP Tube of 75 TL7733BID Reel of 2500 TL7733BIDR TOP-SIDE MARKING TL7702BCP 7702BC TL7705BCP 7705BC TL7733BCP 7733BC TL7702BIP 7702BI TL7705BIP 7705BI TL7705BIP 7733BI –40°C to 125°C SOIC (D) Tube of 75 TL7705BQD TL7705BQD † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 functional block diagram The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming network to adjust the reference voltage and sense-comparator trip point. VCC 8 Reference Voltage 1 CT ≈70 µA 6 3 7 Reference Voltage 2 Vx SENSE 5 RESET RESET R1 (see Note A) R2 (see Note A) 2 RESIN 1 REF 4 GND Pin numbers shown are for the D, JG, and P packages. NOTE A: TL7702B: R1 = 0 Ω, R2 = open, Vx = VREF1 TL7705B: R1 = 23 kΩ, R2 = 10 kΩ, nominal, Vx ≈1.43 V TL7733B: R1 = 11.3 kΩ, R2 = 10 kΩ, nominal, Vx ≈1.43 V typical timing diagram VCC and SENSE VIT+ VIT– VIT+ Vres VIT– Vres 0 RESET ÎÎÎÎ ÎÎÎÎ td td ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Output Undefined Output Undefined 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Input voltage range, VI: RESIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 20 V SENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 20 V High-level output current, IOH (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA Low-level output current, IOL (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Package thermal impedance, θJA (see Notes 2 and 3):D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Case temperature for 60 seconds, TC: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or U packages . . . . . . . . . . . . . . 300°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P packages . . . . . . . . . . . . . . . . 260°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the network ground terminal. 2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MAX 3.6 18 UNIT V 2 18 V 0 0.8 V Supply voltage High-level input voltage RESIN VIL VI Low-level input voltage RESIN Input voltage SENSE 0 18 V IOH IOL High-level output current RESET –20 mA Low-level output current RESET 20 mA TL77xxBC TA 4 MIN VCC VIH Operating temperature O erating free-air tem erature range POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 70 TL77xxBI –40 85 TL7705BQ –40 125 TL7705BM –55 125 °C TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 electrical characteristics over recommended operating conditions (unless otherwise noted) TL77xxBC TL77xxBI TL7705BQ TEST CONDITIONS† PARAMETER MIN VOH VOL High-level output voltage, RESET Low-level output voltage, RESET IOH = –16 mA IOL = 16 mA Vref Reference voltage, REF Iref = –500 µA, TA = 25°C V 2.53 2.58 2.53 2.555 4.5 4.55 4.6 TL7733B 3.03 3.08 3.13 TL7702B 2.48 2.53 2.58 4.45 4.55 4.65 3 3.08 3.16 TA = 25°C TA = full range g ‡ TL7733B TL7702B Vhys y Hysteresis, H t i SENSE (VIT+ – VIT– IT ) Vres§ Power-up reset voltage II Input current IOH IOL High-level output current, RESET ICC V 2.48 TL7705B TL7705B RESIN TL7702B Low-level output current, RESET Supply current V 10 VCC = 3.6 V to 18 V, TA = 25°C IOL at RESET = 2 mA, TA = 25°C mV 30 TL7733B SENSE V 0.4 2.505 TL7705B VIT IT– MAX VCC–1.5 TL7702B Negative-going input threshold voltage input at SENSE in ut TYP UNIT 10 1 VI = 0.4 V to VCC VI = Vref to 18 V –10 –0.1 –2 V µA VO = 18 V, VO = 0 V, See Figure 1 50 µA See Figure 1 –50 µA VSENSE = 15 V, RESIN ≥ 2 V 1.8 3 3.5 VCC = 18 V, TA = full range‡ † All electrical characteristics are measured with 0.1-µF capacitors connected at REF, CT, and VCC to GND. ‡ Full range is 0°C to 70°C for the C-suffix devices, –40°C to 85°C for the I-suffix devices, and –40°C to 125°C for the Q-suffix device. § This is the lowest voltage at which RESET becomes active. mA switching characteristics, VCC = 5 V, CT open, TA = 25°C PARAMETER FROM ((INPUT)) TO (OUTPUT) ( ) TEST CONDITIONS TL77xxBC TL77xxBI TL7705BQ MIN tPLH Propagation delay time from low- to high-level output RESIN RESET tPHL Propagation delay time from high- to low-level output RESIN RESET tw Effective pulse duration tr tf Rise time tr tf Rise time Fall time Fall time RESIN TYP MAX See Figures 1, 2, and 3 270 500 ns See Figures 1, 2, and 3 270 500 ns See Figure 2 SENSE RESET See Figures 1 and 3 RESET See Figures 1 and 3 POST OFFICE BOX 655303 UNIT • DALLAS, TEXAS 75265 150 ns 100 75 150 200 75 150 50 ns ns 5 TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 electrical characteristics over recommended operating conditions (unless otherwise noted) VOH VOL High-level output voltage, RESET Low-level output voltage, RESET IOH = –16 mA IOL = 16 mA Vref Reference voltage, REF Iref = –500 µA, TL7702B VIT IT– Negative-going input threshold voltage input at SENSE in ut TL7705B TL7702B TA = 25°C TA = 25°C 55°C to 125°C TA = –55°C Hysteresis, y , SENSE (VIT+ – VIT–) Vres‡ Power-up reset voltage II Input current IOH IOL High-level output current, RESET VI = Vref to VCC – 1.5 V VO = 18 V Low-level output current, RESET VO = 0 TL7705B RESIN Supply current TL7702B TYP MAX VCC–1.5 Vh hys ICC MIN TL7702B TL7705B SENSE TL7705BM TEST CONDITIONS† PARAMETER VCC = 3 3.6 6 V to 18 V, V TA = 25°C IOL at RESET = 2 mA, VI = 0.4 V to VCC TA = 25°C V 0.4 V V 2.48 2.53 2.58 2.505 2.53 2.555 4.5 4.55 4.6 2.48 2.53 2.58 4.45 4.55 4.65 10 1 –10 –0.1 1.8 –2 V µA 50 µA –50 µA 3 4 VCC = 18 V, TA = –55°C to 125°C † All electrical characteristics are measured with 0.1-µF capacitors connected at REF, CT, and VCC to GND. ‡ This is the lowest value at which RESET becomes active. V mV 30 RESIN ≥ 2 V VSENSE = 15 V, UNIT mA switching characteristics, VCC = 5 V, CT open, TA = 25°C PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time from low- to high-level output RESIN RESET See Figures 1, 2, and 3 270 500* ns tPHL Propagation delay time from high- to low-level output RESIN RESET See Figures 1, 2, and 3 270 500* ns tw Effective pulse duration tr tf Rise time tr tf Rise time Fall time Fall time RESIN See Figure 2 SENSE RESET See Figures 1 and 3 RESET See Figures 1 and 3 * On products compliant to MIL-PRF-38535, these parameters are not production tested. 6 TL7705BM POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 150 ns 100 75* 150 200* 75 150* 50* ns ns TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 PARAMETER MEASUREMENT INFORMATION 5V 5V VCC RL (see Note A) DUT RESET DUT 15 pF (see Note B) RESET RL (see Note A) GND 15 pF (see Note B) RESET OUTPUT CONFIGURATION RESET OUTPUT CONFIGURATION NOTES: A. For IOL and IOH, RL = 10 kΩ. For all switching characteristics, RL = 511 Ω. B. This figure includes jig and probe capacitance. Figure 1. RESET and RESET Output Configurations tw tw VT + 2 V VT 5V 2.5 V 0V VT – 2 V RESIN SENSE WAVEFORMS Figure 2. Input Pulse Definition Voltage Fault VIT+ SENSE VIT+ VIT– 0V VIH RESIN Undefined 2V 0.8 V tf tr VIL tPLH 90% 90% RESET 90% 50% 10% tf td td VOH ÎÎ ÎÎ td 90% 50% RESET 10% 10% tr 10% 10% V OL tPHL Figure 3. Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 TYPICAL CHARACTERISTICS† DEASSERTION TIME vs LOAD RESISTANCE ASSERTION TIME vs LOAD RESISTANCE 700 20 VCC = 5 V CT = 0.1 µF CL = 10 pF TA = 25°C 600 t – Deassertion Time – ns t – Assertion Time – ns 18 16 RESET tr 14 12 10 8 6 2 4 500 RESET tf 400 300 RESET tf 200 RESET tr 6 8 0 10 0 2 RL – Load Resistance – kΩ 4 8 10 Figure 5 ASSERTION TIME vs LOAD CAPACITANCE DEASSERTION TIME vs LOAD CAPACITANCE 36 2.1 VCC = 5 V CT = 0.1 µF RL = 4.7 kΩ TA = 25°C VCC = 5 V CT = 0.1 µF RL = 4.7 kΩ TA = 25°C 1.9 t – Deassertion Time – µs t – Assertion Time – ns 6 RL – Load Resistance – kΩ Figure 4 30 RESET tr 100 RESET tf 0 VCC = 5 V CT = 0.1 µF CL = 10 pF TA = 25°C 24 RESET tr 18 RESET tf 1.7 1.5 1.3 1.1 RESET tf and RESET tr 0.9 0.7 12 0.5 6 0.3 0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200 CL – Load Capacitance – pF CL – Load Capacitance – pF Figure 6 Figure 7 † For proper operation, both RESET and RESET should be terminated with resistors of similar value. Failure to do so may cause unwanted plateauing in either output waveform during switching. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TL7702B, TL7705B, TL7733B SUPPLY-VOLTAGE SUPERVISORS The TL7705BM is obsolete and no longer is supplied. SLVS037M – SEPTEMBER 1989 – REVISED MAY 2003 APPLICATION INFORMATION VS System Supply 8 7 VCC SENSE RESET 10 kΩ 5 To System RESET 2 Reset Input (from system) RESIN 1 REF RT 3 6 CT (see text) 0.1 µF To System RESET RESET GND CT 4 10 kΩ Figure 8. System Reset Controller With Undervoltage Sensing When the TL770xB SENSE terminal is used to monitor VCC, a current-limiting resistor in series with CT is recommended. During normal operation, the timing capacitor is charged by the onboard current source to approximately VCC or an internal voltage clamp (≈7.1-V Zener), whichever is less. When the circuit then is subjected to an undervoltage condition during which VCC is rapidly slewed down, the voltage on CT exceeds that on VCC. This forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when VCC drops below V(CT), not when VSENSE falls below VT–. Texas Instruments performs a 100% electrical screen to verify that the outputs do not switch with 1 mA forced into the CT terminal. Adding the external resistor, RT, prevents false triggering. Its value is calculated as follows: * V (CT) V T – RT Where: V(CT) = VCC or 7.1 V, whichever is less VT– = 4.55 V (nom) RT = value of series resistor required For VCC = 5 V: 5 * 4.55 t 1 mA R T Therefore, RT u 450 W Using a 20%-tolerance resistor, RT should be greater than 560 Ω. Adding this series resistor changes the duration of the reset pulse by no more than 10%. RT extends the discharge of CT, but also skews the V(CT) threshold. These effects tend to cancel one another. The precise percentage change can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration of the supply-voltage fault condition. Both outputs of the TL770xB should be terminated with similar value resistors, even when only one is being used. This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an undefined state or delay system reset. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PACKAGE OPTION ADDENDUM www.ti.com 22-Aug-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-88685042A OBSOLETE LCCC FK 20 TBD Call TI Call TI 5962-8868504HA OBSOLETE CFP U 10 TBD Call TI Call TI 5962-88685052A OBSOLETE LCCC FK 20 TBD Call TI Call TI 5962-8868505HA OBSOLETE CFP U 10 TBD Call TI Call TI 5962-8868505PA OBSOLETE CDIP JG 8 TBD Call TI Call TI TL7702BCD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BCDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BCDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BCDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BCDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BCP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7702BCPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7702BID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BIDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BIDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7702BIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7702BIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7702BMFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL7702BMJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL7702BMJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI TL7702BMUB OBSOLETE CFP U 10 TBD Call TI Call TI TL7702BQD OBSOLETE SOIC D 8 TBD Call TI Call TI TL7702BQDR OBSOLETE SOIC D 8 TBD Call TI Call TI TL7702BQP OBSOLETE PDIP P 8 TBD Call TI Call TI TL7705BCD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL7705BCDE4 ACTIVE SOIC D 8 75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 22-Aug-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TL7705BCDG4 ACTIVE SOIC D 8 TL7705BCDR ACTIVE SOIC D TL7705BCDRE4 ACTIVE SOIC TL7705BCDRG4 ACTIVE TL7705BCP Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7705BCPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7705BID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL7705BIDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL7705BIDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL7705BIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL7705BIDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL7705BIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TL7705BIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7705BIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7705BMFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL7705BMJG OBSOLETE CDIP JG 8 TBD Call TI Call TI TL7705BMJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI TL7705BMUB OBSOLETE CFP U 10 TBD Call TI Call TI TL7705BQD ACTIVE SOIC D 8 75 TBD CU NIPDAU Level-1-220C-UNLIM TL7705BQDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7705BQDR ACTIVE SOIC D 8 2500 TBD CU NIPDAU Level-1-220C-UNLIM TL7705BQDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7705BQP OBSOLETE PDIP P 8 TL7733BCD ACTIVE SOIC D 8 TL7733BCDE4 ACTIVE SOIC D TL7733BCDG4 ACTIVE SOIC TL7733BCDR ACTIVE TL7733BCDRE4 ACTIVE TBD Call TI 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 Call TI PACKAGE OPTION ADDENDUM www.ti.com 22-Aug-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TL7733BCDRG4 ACTIVE SOIC D 8 TL7733BCP ACTIVE PDIP P 8 50 TL7733BCPE4 ACTIVE PDIP P 8 TL7733BID ACTIVE SOIC D TL7733BIDE4 ACTIVE SOIC TL7733BIDG4 ACTIVE TL7733BIDR 2500 Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU Level-1-260C-UNLIM Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7733BIDRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7733BIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TL7733BIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TL7733BIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TL7702BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL7702BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL7705BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL7705BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL7733BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL7733BIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL7702BCDR SOIC D 8 2500 340.5 338.1 20.6 TL7702BIDR SOIC D 8 2500 340.5 338.1 20.6 TL7705BCDR SOIC D 8 2500 340.5 338.1 20.6 TL7705BIDR SOIC D 8 2500 340.5 338.1 20.6 TL7733BCDR SOIC D 8 2500 340.5 338.1 20.6 TL7733BIDR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. 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