SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
D Qualification in Accordance With
D
D
D
D
D
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 150 V
(TLC2252/52A) and 100 V (TLC2254/54A)
Using Machine Model (C = 200 pF, R = 0)
Output Swing Includes Both Supply Rails
Low Noise . . . 19 nV/√Hz Typ at f = 1 kHz
D Low Input Bias Current . . . 1 pA Typ
D Fully Specified for Both Single-Supply and
Split-Supply Operation
D Very Low Power . . . 35 µA Per Channel Typ
D Common-Mode Input Voltage Range
D
D
D
Includes Negative Rail
Low Input Offset Voltage
850 µV Max at TA = 25°C (TLC225xA)
Macromodel Included
Performance Upgrades for the TS27L2/L4
and TLC27L2/L4
† Contact factory for details. Q100 qualification data available on
request.
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
description
60
V n − Equivalent Input Noise Voltage − nV/
VN
nv//HzHz
The TLC2252 and TLC2254 are dual and
quadruple operational amplifiers from Texas
Instruments. Both devices exhibit rail-to-rail
output performance for increased dynamic range
in single- or split-supply applications. The
TLC225x family consumes only 35 µA of supply
current per channel. This micropower operation
makes them good choices for battery-powered
applications. The noise performance has been
dramatically improved over previous generations
of CMOS amplifiers. Looking at Figure 1, the
TLC225x has a noise level of 19 nV/√Hz at 1kHz;
four times lower than competitive micropower
solutions.
50
VDD = 5 V
RS = 20 Ω
TA = 25°C
40
30
20
10
The TLC225x amplifiers, exhibiting high input
impedance and low noise, are excellent for
0
small-signal conditioning for high-impedance
101
10 2
10 3
10 4
sources, such as piezoelectric transducers.
f − Frequency − Hz
Because of the micropower dissipation levels,
Figure 1
these devices work well in hand-held monitoring
and remote-sensing applications. In addition, the
rail-to-rail output feature with single or split
supplies makes this family a great choice when interfacing with analog-to-digital converters (ADCs). For
precision applications, the TLC225xA family is available and has a maximum input offset voltage of 850 µV. This
family is fully characterized at 5 V and ± 5 V.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
Copyright 2003 − 2004 Texas Instruments Incorporated
!" ! #$%&'$ ( )%%' ( $# *)+,'$ '%$)'( $#$%& '$ (*#'$( *% '. '%&( $# ( ('%)&'(
('% /%%'0- %$)'$ *%$((1 $( $' ((%,0 ,)
'('1 $# ,, *%&'%(-
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
description (continued)
The TLC2252/4 also makes great upgrades to the TLC27L2/L4 or TS27L2/L4 in standard designs. They offer
increased output dynamic range, lower noise voltage, and lower input offset voltage. This enhanced feature set
allows them to be used in a wider range of applications. For applications that require higher output drive and
wider input voltage ranges, see the TLV2432 and TLV2442 devices. If the design requires single amplifiers,
please see the TLV2211/21/31 family. These devices are single rail-to-rail operational amplifiers in the SOT-23
package. Their small size and low power consumption, make them ideal for high density, battery-powered
equipment.
ORDERING INFORMATION
VIOmax
AT 25°C
TA
850 µV
V
V
1550 µV
−40°C to 125°C
850 µV
V
1550 µV
V
ORDERABLE
PART NUMBER
PACKAGE†
TOP-SIDE
MARKING
SOIC (D)
Tape and reel
TLC2252AQDRQ1
2252AQ
TSSOP (PW)
Tape and reel
TLC2252AQPWRQ1
2252AQ
SOIC (D)
Tape and reel
TLC2252QDRQ1
2252Q1
TSSOP (PW)
Tape and reel
TLC2252QPWRQ1
2252Q1
SOIC (D)
Tape and reel
TLC2254AQDRQ1
TLC2254AQ1
TSSOP (PW)
Tape and reel
TLC2254AQPWRQ1
2254AQ
SOIC (D)
Tape and reel
TLC2254QDRQ1
TLC2254Q1
TSSOP (PW)
Tape and reel
TLC2254QPWRQ1
2254Q1
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
TLC2254, TLC2254A
D OR PW PACKAGE
(TOP VIEW)
TLC2252, TLC2252A
D OR PW PACKAGE
(TOP VIEW)
1OUT
1IN −
1IN +
VDD − /GND
2
1
8
2
7
3
6
4
5
VDD +
2OUT
2IN −
2IN +
1OUT
1IN −
1IN +
VDD +
2IN +
2IN −
2OUT
POST OFFICE BOX 655303
1
14
2
13
3
12
4
11
5
10
6
9
7
8
• DALLAS, TEXAS 75265
4OUT
4IN −
4IN +
VDD − / GND
3IN +
3IN −
3OUT
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
equivalent schematic (each amplifier)
VDD +
Q3
Q6
Q9
Q12
Q14
Q16
R6
IN +
OUT
C1
IN −
R5
Q1
Q4
Q13
Q15
Q17
D1
Q2
Q5
R3
R4
Q7
Q8
Q10
Q11
R1
R2
VDD −/ GND
ACTUAL DEVICE COMPONENT COUNT†
TLC2252
TLC2254
Transistors
COMPONENT
38
76
Resistors
30
56
9
18
Diodes
Capacitors
3
6
† Includes both amplifiers and all ESD, bias, and trim circuitry
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Supply voltage, VDD − (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V
Input voltage, VI (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 8 V
Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current into VDD + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Total current out of VDD − . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD − .
2. Differential voltages are at IN+ with respect to IN −. Excessive current flows when input is brought below VDD − − 0.3 V.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
25 C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70
70°C
C
POWER RATING
TA = 85
85°C
C
POWER RATING
TA = 125
125°C
C
POWER RATING
D−8
724 mW
5.8 mW/°C
464 mW
377 mW
144 mW
D−14
950 mW
7.6 mW/°C
608 mW
450 mW
190 mW
PW−8
525 mW
4.2 mW/°C
336 mW
273 mW
105 mW
PW−14
700 mW
5.6 mW/°C
448 mW
364 mW
140 mW
recommended operating conditions
MIN
Supply voltage, VDD ±
± 2.2
Input voltage range, VI
VDD −
VDD −
Common-mode input voltage, VIC
Operating free-air temperature, TA
‡ Referenced to 2.5 V
4
−40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
±8
V
VDD + − 1.5
VDD + − 1.5
V
125
V
°C
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
VOH
Common-mode input
voltage range
High-level output
voltage
TEST CONDITIONS
Low-level output
voltage
Large-signal differential
voltage amplification
MAX
200
1500
VIC = 0,
RS = 50 Ω
µV/mo
25°C
0.5
1
0.5
25°C
0
to
4
60
Full range
0
to
3.5
25°C
4.9
4.8
25°C
4.8
−0.3
to
4.2
1
0
to
4
−0.3
to
4.2
4.9
4.94
4.88
0.09
Full range
4.8
4.88
0.01
0.15
0.09
0.15
0.8
Full range
Full range
10
350
0.15
0.15
1
0.7
1.2
100
V
4.8
25°C
pA
4.98
4.94
0.01
pA
V
0
to
3.5
25°C
25°C
60
1000
4.98
25°C
60
1000
1000
Full range
RL = 1 Mه
60
1000
IOH = − 75 µA
RL = 100 kه
µV
0.003
25°C
VIC = 2.5 V,
VO = 1 V to 4 V
1000
0.003
IOH = − 20 µA
IOL = 4 mA
850
25°C
|VIO | ≤ 5 mV
IOL = 500 µA
200
UNIT
µV/°C
25°C
VIC = 2.5 V,
MAX
0.5
Full range
IOL = 50 µA
TYP
0.5
Full range
RS = 50 Ω
Ω,
MIN
1750
25°C
to 125°C
VDD ± = ± 2.5 V,
VO = 0,
TLC2252A-Q1
TYP
Full range
VIC = 2.5 V,
AVD
TLC2252-Q1
MIN
25°C
IOH = − 150 µA
VIC = 2.5 V,
VOL
TA†
V
1
1.2
100
350
10
V/mV
25°C
1700
1700
rid
Differential input
resistance
25°C
1012
1012
Ω
ric
Common-mode input
resistance
25°C
1012
1012
Ω
cic
Common-mode input
capacitance
f = 10 kHz,
f = 10 kHz,
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 25 kHz,
AV = 10
25°C
200
200
Ω
CMRR
Common-mode
rejection ratio
VIC = 0 to 2.7 V,
RS = 50 Ω
VO = 2.5 V,
kSVR
Supply-voltage
rejection ratio
(∆VDD /∆VIO)
VDD = 4.4 V to 16 V,
VIC = VDD /2,
No load
IDD
Supply current
VO = 2.5 V,
Full range
No load
25°C
70
Full range
70
25°C
80
Full range
80
83
70
83
dB
70
95
80
95
dB
25°C
80
70
125
150
70
125
150
µA
† Full range is −40°C to 125°C for Q suffix.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TA†
TEST CONDITIONS
TLC2252-Q1
MIN
TYP
25°C
0.07
0.12
Full
range
0.05
MAX
TLC2252A-Q1
MIN
TYP
0.07
0.12
MAX
UNIT
SR
Slew rate at unity
gain
VO = 0.5 V to 3.5 V,
RL = 100 kه,
Equivalent input
noise voltage
f = 10 Hz
25°C
36
36
Vn
f = 1 kHz
25°C
19
19
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.1
1.1
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 10 kHz,
RL = 50 kه
AV = 1
0.2%
0.2%
THD + N
1%
1%
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF‡
RL = 50 kه,
25°C
0.2
0.2
MHz
BOM
Maximum outputswing bandwidth
VO(PP) = 2 V,
RL = 50 kه,
AV = 1,
CL = 100 pF‡
25°C
30
30
kHz
φm
Phase margin at
unity gain
RL = 50 kه,
CL = 100 pF‡
25°C
63°
63°
25°C
15
15
CL = 100 pF‡
nV/√Hz
µV
V
fA√Hz
25°C
AV = 10
Gain margin
† Full range is −40°C to 125°C for Q suffix.
‡ Referenced to 2.5 V
6
V/µs
0.05
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
PARAMETER
TA†
TEST CONDITIONS
TLC2252-Q1
MIN
25°C
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage longterm drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
Common-mode input
voltage range
25°C
to 125°C
VO = 0,
Ω
RS = 50 Ω,
IO = 4 mA
VIC = 0,
RL = 100 kΩ
850
1000
UNIT
µV
V
µV/°C
25°C
0.003
0.003
µV/mo
25°C
0.5
1
−5
to
4
Full range
−5
to
3.5
60
−5.3
to
4.2
4.9
Full range
4.7
25°C
4.8
25°C
1
−5
to
4
−4.85
Full range
−4.85
40
Full range
10
V
4.98
4.93
4.9
4.93
V
4.7
4.86
4.8
4.86
−4.99
−4.91
−4.85
−4.91
−4.85
−4.3
−4
−3.8
25°C
pA
−5.3
to
4.2
−5
to
3.5
−4
pA
60
1000
−4.99
25°C
60
1000
4.98
25°C
Full range
0.5
1000
25°C
25°C
60
1000
25°C
IO = 500 µA
A
VIC = 0,
200
MAX
0.5
|VIO | ≤ 5 mV
A
IO = − 100 µA
TYP
0.5
Full range
IO = − 200 µA
VIC = 0,
IO = 50 µA
Maximum negative
VOM −
peak output voltage
1500
Full range
IO = − 20 µA
Maximum positive peak
VOM +
output voltage
200
MIN
1750
25°C
VICR
MAX
Full range
VIC = 0,
RS = 50 Ω
TLC2252A-Q1
TYP
V
−4.3
−3.8
150
40
150
AVD
Large-signal differential
voltage amplification
25°C
3000
3000
rid
Differential input
resistance
25°C
1012
1012
Ω
ric
Common-mode input
resistance
25°C
1012
1012
Ω
cic
Common-mode input
capacitance
f = 10 kHz,
P package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 25 kHz,
AV = 10
25°C
190
190
Ω
Common-mode
rejection ratio
VIC = − 5 V to 2.7 V,
VO = 0,
RS = 50 Ω
25°C
75
CMRR
Full range
75
Supply-voltage rejection
ratio (∆VDD ± /∆VIO)
VDD = ±2.2 V to ±8 V,
VIC = 0,
No load
25°C
80
kSVR
Full range
80
IDD
Supply current
VO = 2.5 V,
Full range
VO = ± 4 V
RL = 1 MΩ
10
25°C
No load
88
75
V/mV
88
dB
75
95
80
95
dB
80
80
125
150
80
125
150
A
µA
† Full range is −40°C to 125°C for Q suffix.
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, VDD ± = ±5 V
PARAMETER
TA†
TEST CONDITIONS
VO = ± 2 V,
CL = 100 pF
RL = 100 kΩ,
TLC2252-Q1
MIN
TYP
25°C
0.07
0.12
Full
range
0.05
MAX
TLC2252A-Q1
MIN
TYP
0.07
0.12
MAX
UNIT
SR
Slew rate at unity gain
Equivalent input noise
voltage
f = 10 Hz
25°C
38
38
Vn
f = 1 kHz
25°C
19
19
Peak-to-peak equivalent
input noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.8
0.8
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.1
1.1
In
Equivalent input noise
current
25°C
0.6
0.6
Total harmonic distortion
plus noise
VO = ± 2.3 V,
RL = 50 kΩ,
kΩ
f = 10 kHz
AV = 1
0.2%
0.2%
THD + N
1%
1%
Gain-bandwidth product
f =10 kHz,
CL = 100 pF
RL = 50 kΩ,
25°C
0.21
0.21
MHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 4.6 V, AV = 1,
RL = 50 kΩ,
CL = 100 pF
25°C
14
14
kHz
φm
Phase margin at unity
gain
25°C
63°
63°
25°C
15
15
RL = 50 kΩ,
nV/√Hz
µV
V
fA√Hz
25°C
AV = 10
CL = 100 pF
Gain margin
† Full range is −40°C to 125°C for Q suffix.
8
V/µs
0.05
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
αVIO
Temperature
coefficient of input
offset voltage
Input offset voltage
long-term drift
(see Note 4)
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input
voltage range
TA†
TEST CONDITIONS
25°C
VOH
VOL
Large-signal
differential
voltage amplification
1500
VIC = 0,
RS = 50 Ω
IOL = 500 µA
IOL = 4 mA
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 100 kه
1000
µV
0.003
µV/mo
25°C
0.5
60
0.5
1000
1
60
Full range
0
to
3.5
−0.3
to
4.2
1
4.9
Full range
4.8
25°C
4.8
0
to
4
−0.3
to
4.2
4.9
4.94
4.88
0.09
Full range
4.8
4.88
0.01
0.15
0.09
0.15
25°C
0.8
Full range
Full range
10
350
0.15
0.15
1
0.7
1.2
100
V
4.8
25°C
pA
4.98
4.94
0.01
pA
V
0
to
3.5
25°C
25°C
60
1000
4.98
25°C
60
1000
1000
0
to
4
RL = 1 Mه
850
0.003
25°C
VIC = 2.5 V,
200
UNIT
25°C
25°C
IOL = 50 µA
MAX
µV/°C
|VIO | ≤ 5 mV
IOH = − 75 µA
TYP
0.5
25°C
RS = 50 Ω
Ω,
MIN
0.5
125°C
VIC = 2.5 V,
AVD
200
125°C
IOH = − 150 µA
VIC = 2.5 V,
Low-level output
voltage
MAX
1750
25°C
to 125°C
VDD ± = ± 2.5 V,
VO = 0,
TLC2254A-Q1
TYP
Full range
IOH = − 20 µA
High-level output
voltage
TLC2254-Q1
MIN
V
1
1.2
100
350
10
V/mV
25°C
1700
1700
ri(d)
Differential input
resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 25 kHz,
AV = 10
25°C
200
200
Ω
CMRR
Common-mode
rejection ratio
VIC = 0 to 2.7 V, VO = 2.5 V,
RS = 50 Ω
kSVR
Supply-voltage
rejection ratio
(∆VDD /∆VIO)
VDD = 4.4 V to 16 V,
VIC = VDD /2,
No load
IDD
Supply current
(four amplifiers)
VO = 2.5 V,
Full range
No load
25°C
70
Full range
70
25°C
80
Full range
80
83
70
83
dB
70
95
80
95
dB
25°C
80
140
250
300
140
250
300
µA
† Full range is −40°C to 125°C for Q suffix.
‡ Referenced to 2.5 V
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, VDD = 5 V
PARAMETER
TA†
TEST CONDITIONS
TLC2254-Q1
MIN
TYP
0.12
MAX
TLC2254A-Q1
MIN
TYP
0.07
0.12
MAX
UNIT
VO = 0.5 V to 3.5 V,
RL = 100 kه,
CL = 100 pF‡
25°C
0.07
Full
range
0.05
Equivalent input
noise voltage
f = 10 Hz
25°C
36
36
f = 1 kHz
25°C
19
19
Peak-to-peak
equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
25°C
0.7
0.7
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.1
1.1
In
Equivalent input
noise current
25°C
0.6
0.6
Total harmonic
distortion plus
noise
VO = 0.5 V to 2.5 V,
f = 20 kHz,
RL = 50 kه
AV = 1
0.2%
0.2%
THD + N
1%
1%
Gain-bandwidth
product
f = 50 kHz,
CL = 100 pF‡
RL = 50 kه,
25°C
0.2
0.2
MHz
BOM
Maximum outputswing bandwidth
VO(PP) = 2 V,
RL = 50 kه,
AV = 1,
CL = 100 pF‡
25°C
30
30
kHz
φm
Phase margin at
unity gain
RL = 50 kه,
CL = 100 pF‡
25°C
63°
63°
25°C
15
15
SR
Slew rate at unity
gain
Vn
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
Gain margin
† Full range is −40°C to 125°C for Q suffix.
‡ Referenced to 2.5 V
10
V/µs
0.05
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
electrical characteristics at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
PARAMETER
TA†
TEST CONDITIONS
TLC2254-Q1
MIN
25°C
VIO
Input offset voltage
αVIO
Temperature coefficient of
input offset voltage
Input offset voltage
long-term drift (see Note 4)
IIO
Input offset current
IIB
Input bias current
Common-mode input
voltage range
25°C
to 125°C
VO = 0,
RS = 50 Ω
Ω,
IO = 4 mA
VIC = 0,
RL = 100 kΩ
850
1000
UNIT
µV
V
µV/°C
25°C
0.003
0.003
µV/mo
25°C
0.5
1
−5
to
4
Full range
−5
to
3.5
60
−5.3
to
4.2
4.9
Full range
4.7
25°C
4.8
25°C
1
−5
to
4
−4.85
Full range
−4.85
40
Full range
10
V
4.98
4.93
4.9
4.93
V
4.7
4.86
4.8
4.86
−4.99
−4.91
−4.85
−4.91
−4.85
−4.3
−4
−3.8
25°C
pA
−5.3
to
4.2
−5
to
3.5
−4
pA
60
1000
−4.99
25°C
60
1000
4.98
25°C
Full range
0.5
1000
25°C
25°C
60
1000
25°C
IO = 500 µA
A
VIC = 0,
200
MAX
0.5
|VIO | ≤ 5 mV
IO = − 100 µA
A
TYP
0.5
125°C
IO = − 200 µA
VIC = 0,
IO = 50 µA
Maximum negative peak
VOM −
output voltage
1500
125°C
IO = − 20 µA
Maximum positive peak
VOM +
output voltage
200
MIN
1750
25°C
VICR
MAX
Full range
VIC = 0,
RS = 50 Ω
TLC2254A-Q1
TYP
V
−4.3
−3.8
150
40
150
AVD
Large-signal differential
voltage amplification
25°C
3000
3000
ri(d)
Differential input resistance
25°C
1012
1012
Ω
ri(c)
Common-mode input
resistance
25°C
1012
1012
Ω
ci(c)
Common-mode input
capacitance
f = 10 kHz,
N package
25°C
8
8
pF
zo
Closed-loop output
impedance
f = 25 kHz,
AV = 10
25°C
190
190
Ω
CMRR
Common-mode rejection
ratio
VIC = − 5 V to 2.7 V,
VO = 0,
RS = 50 Ω
kSVR
Supply-voltage rejection
ratio (∆VDD ± /∆VIO)
VDD± = ±ā 2.2 V to ±ā 8 V,
VIC = VDD /2, No load
IDD
Supply current
(four amplifiers)
VO = 0,
VO = ± 4 V
RL = 1 MΩ
25°C
75
Full range
75
25°C
80
Full range
80
10
25°C
No load
Full range
88
75
V/mV
88
dB
75
95
80
95
dB
80
160
250
300
160
250
300
µA
A
† Full range is −40°C to 125°C for Q suffix.
NOTE 4: Typical values are based on the input offset voltage shift observed through 500 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
operating characteristics at specified free-air temperature, VDD ± = ±5 V
PARAMETER
TA†
TEST CONDITIONS
VO = ± 2 V,
CL = 100 pF
RL = 100 kΩ,
TLC2254-Q1
MIN
TYP
25°C
0.07
0.12
Full
range
0.05
MAX
TLC2254A-Q1
MIN
TYP
0.07
0.12
MAX
UNIT
SR
Slew rate at unity gain
Equivalent input noise
voltage
f = 10 Hz
25°C
38
38
Vn
f = 1 kHz
25°C
19
19
Peak-to-peak
equivalent input noise
voltage
f = 0.1 Hz to 1 Hz
25°C
0.8
0.8
VN(PP)
f = 0.1 Hz to 10 Hz
25°C
1.1
1.1
In
Equivalent input noise
current
25°C
0.6
0.6
Total harmonic
distortion plus noise
VO = ± 2.3 V,
RL = 50 kΩ,
kΩ
f = 20 kHz
AV = 1
0.2%
0.2%
THD + N
1%
1%
Gain-bandwidth product
f =10 kHz,
CL = 100 pF
RL = 50 kΩ,
25°C
0.21
0.21
MHz
BOM
Maximum output-swing
bandwidth
VO(PP) = 4.6 V,
RL = 50 kΩ,
AV = 1,
CL = 100 pF
25°C
14
14
kHz
φm
Phase margin at unity
gain
RL = 50 kΩ,
CL = 100 pF
25°C
63°
63°
25°C
15
15
nV/√Hz
µV
V
fA /√Hz
25°C
AV = 10
Gain margin
† Full range is −40°C to 125°C for Q suffix.
12
V/µs
0.05
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dB
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Distribution
vs Common-mode input voltage
2−5
6, 7
αVIO
IIB/IIO
Input offset voltage temperature coefficient
Distribution
8 − 11
Input bias and input offset currents
vs Free-air temperature
12
VI
Input voltage range
vs Supply voltage
vs Free-air temperature
13
14
VOH
VOL
High-level output voltage
vs High-level output current
15
Low-level output voltage
vs Low-level output current
16, 17
VOM +
VOM −
Maximum positive peak output voltage
vs Output current
18
Maximum negative peak output voltage
vs Output current
19
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
20
IOS
Short-circuit output current
vs Supply voltage
vs Free-air temperature
21
22
VO
Output voltage
vs Differential input voltage
Differential gain
vs Load resistance
AVD
Large-signal differential voltage amplification
vs Frequency
vs Free-air temperature
26, 27
28, 29
zo
Output impedance
vs Frequency
30, 31
CMRR
Common-mode rejection ratio
vs Frequency
vs Free-air temperature
32
33
kSVR
Supply-voltage rejection ratio
vs Frequency
vs Free-air temperature
34, 35
36
IDD
Supply current
vs Supply voltage
vs Free-air temperature
37
38
SR
Slew rate
vs Load capacitance
vs Free-air temperature
39
40
VO
VO
Inverting large-signal pulse response
41, 42
Voltage-follower large-signal pulse response
43, 44
VO
VO
Inverting small-signal pulse response
45, 46
Vn
Equivalent input noise voltage
vs Frequency
Noise voltage (referred to input)
Over a 10-second period
51
Integrated noise voltage
vs Frequency
52
Total harmonic distortion plus noise
vs Frequency
53
Gain-bandwidth product
vs Free-air temperature
vs Supply voltage
54
55
φm
Phase margin
vs Frequency
vs Load capacitance
26, 27
56
Am
Gain margin
vs Load capacitance
57
B1
Unity-gain bandwidth
vs Load capacitance
58
Overestimation of phase margin
vs Load capacitance
59
THD + N
Voltage-follower small-signal pulse response
POST OFFICE BOX 655303
23, 24
25
47, 48
• DALLAS, TEXAS 75265
49, 50
13
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC2252
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC2252
INPUT OFFSET VOLTAGE
35
30
Percentage of Amplifiers − %
Percentage of Amplifiers − %
30
35
682 Amplifiers From 1 Wafer Lots
VDD± = ± 2.5 V
P Package
TA = 25°C
25
20
15
10
5
682 Amplifiers From 1 Wafer Lots
VDD± = ± 5 V
P Package
TA = 25°C
25
20
15
10
5
0
−1.6
−0.8
0
0.8
0
−1.6
1.6
−0.8
VIO − Input Offset Voltage − mV
Figure 2
0.8
1.6
Figure 3
DISTRIBUTION OF TLC2254
INPUT OFFSET VOLTAGE
DISTRIBUTION OF TLC2254
INPUT OFFSET VOLTAGE
20
25
Percentage of Amplifiers − %
1020 Amplifiers From 1 Wafer Lot
VDD = ± 2.5 V
TA = 25°C
Percentage of Amplifiers − %
0
VIO − Input Offset Voltage − mV
15
10
5
20
1020 Amplifiers From 1 Wafer Lot
VDD ± = ± 5 V
TA = 25°C
15
10
5
0
−1.6
−0.8
0
0.8
VIO − Input Offset Voltage − mV
1.6
0
−1.6
Figure 4
14
0
0.8
−0.8
VIO − Input Offset Voltage − mV
Figure 5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.6
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE†
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1
0.6
0.4
0.2
0
−0.2
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
−0.4
−0.6
−0.8
−1
−1
0
VDD± = ± 5 V
RS = 50 Ω
TA = 25°C
0.8
VVIO
IO − Input Offset Voltage − mV
VVIO
IO − Input Offset Voltage − mV
1
VDD = 5 V
RS = 50 Ω
TA = 25°C
0.8
1
2
3
4
5
VIC − Common-Mode Input Voltage − V
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
−6 −5 −4 −3 −2 −1 0
1
2
3
4
VIC − Common-Mode Input Voltage − V
Figure 6
Figure 7
DISTRIBUTION OF TLC2252 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLC2252 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
25
62 Amplifiers From
1 Wafer Lot
VDD = ± 2.5 V
62 Amplifiers From
1 Wafer Lot
VDD = ± 5 V
P Package
TA = 25°C to 125°C
P Package
TA = 25°C to 125°C
Percentage of Amplifiers − %
Precentage of Amplifiers − %
25
20
5
15
10
20
15
10
5
5
0
0
−1
0
1
αVIO − Temperature Coefficient − µV / °C
2
−1
0
1
αVIO − Temperature Coefficient − µV / °C
2
Figure 9
Figure 8
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC2254 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
20
25
62 Amplifiers From
1 Wafer Lot
VDD ± = ± 2.5 V
P Package
TA = 25°C to 125°C
Percentage of Amplifiers − %
Percentage of Amplifiers − %
25
15
10
5
0
−2
DISTRIBUTION OF TLC2254 INPUT OFFSET
VOLTAGE TEMPERATURE COEFFICIENT
−1
0
1
αVIO − Temperature Coefficient of
Input Offset Voltage − µV / °C
62 Amplifiers From
1 Wafer Lot
VDD ± = ± 5 V
P Package
TA = 25°C to 125°C
20
15
10
5
0
−2
2
−1
ÁÁ
ÁÁ
1
INPUT VOLTAGE RANGE
vs
SUPPLY VOLTAGE
INPUT BIAS AND INPUT OFFSET CURRENTS†
vs
FREE-AIR TEMPERATURE
10
35
VDD± = ± 2.5 V
VIC = 0
VO = 0
RS = 50 Ω
RS = 50 Ω
TA = 25°C
8
25
IIB
20
15
IIO
10
5
6
4
2
0
| VIO | ≤ 5 mV
−2
−4
−6
−8
−10
0
25
45
65
85
105
TA − Free-Air Temperature − °C
125
2
Figure 12
3
6
7
4
5
| VDD ± | − Supply Voltage − V
Figure 13
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
16
2
Figure 11
V
VII − Input Voltage Range − V
IIO − Input Bias and Input Offset Currents − pA
IIIB
IB and IIO
Figure 10
30
0
αVIO − Temperature Coefficient of
Input Offset Voltage − µV / °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
8
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE†‡
vs
HIGH-LEVEL OUTPUT CURRENT
INPUT VOLTAGE RANGE†
vs
FREE-AIR TEMPERATURE
5
5
VDD = 5 V
VOH − High-Level Output Voltage − V
VOH
VDD = 5 V
V
VII − Input Voltage Range − V
4
3
2
ÁÁ
ÁÁ
1
0
−1
−75 −55 −35 −15 5
25 45 65 85 105 125
TA − Free-Air Temperature − °C
ÁÁ
ÁÁ
ÁÁ
TA = − 55°C
4
TA = − 40°C
3
TA = 25°C
2
TA = 125°C
1
0
0
600
200
400
| IOH| − High-Level Output Current − µA
Figure 14
Figure 15
LOW-LEVEL OUTPUT VOLTAGE†‡
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE‡
vs
LOW-LEVEL OUTPUT CURRENT
1.4
VDD = 5 V
TA = 25°C
1
V
VOL
OL − Low-Level Output Voltage − V
VOL
VOL − Low-Level Output Voltage − V
1.2
VIC = 1.25 V
VIC = 0
0.8
0.6
VIC = 2.5 V
ÁÁ
ÁÁ
ÁÁ
800
ÁÁ
ÁÁ
ÁÁ
0.4
0.2
0
0
1
2
3
4
5
IOL − Low-Level Output Current − mA
VDD = 5 V
VIC = 2.5 V
1.2
TA = 125°C
1
0.8
TA = 25°C
0.6
TA = − 40°C
TA = − 55°C
0.4
0.2
0
0
1
2
3
4
5
6
IOL − Low-Level Output Current − mA
Figure 16
Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
ÁÁ
ÁÁ
ÁÁ
MAXIMUM NEGATIVE PEAK OUTPUT VOLTAGE†
vs
OUTPUT CURRENT
5
4
3
TA = 25°C
2
TA = 125°C
TA = − 40°C
TA = − 55°C
1
VDD = ± 5 V
0
0
600
200
400
IO − Output Current − µA
800
VOM −
VOM
− − Maximum Negative Peak Output Voltage − V
VVOM
OM ++ − Maximum Positive Peak Output Voltage − V
MAXIMUM POSITIVE PEAK OUTPUT VOLTAGE†
vs
OUTPUT CURRENT
−3.8
VDD± = ± 5 V
VIC = 0
−4
TA = 125°C
−4.2
TA = 25°C
TA = − 40°C
−4.4
−4.6
TA = − 55°C
ÁÁ
ÁÁ
ÁÁ
−4.8
−5
0
1
2
Figure 18
RL = 50 kΩ
TA = 25°C
VDD± = ± 5 V
8
7
6
VDD = 5 V
4
3
2
1
0
10 2
10 3
6
10 4
10 5
10
I OS − Short-Circuit Output Current − mA
IOS
VO(PP)
VO(PP) − Maximum Peak-to-Peak Output Voltage − V
ÁÁ
ÁÁ
ÁÁ
5
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
10
5
4
Figure 19
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE‡
vs
FREQUENCY
9
3
IO − Output Current − mA
9
8
VID = − 100 mV
7
VO = 0
TA = 25°C
VIC = 0
6
5
4
3
2
1
0
−1
VID = 100 mV
2
f − Frequency − Hz
3
4
5
6
7
| VDD ± | − Supply Voltage − V
Figure 20
Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
8
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT†
vs
FREE-AIR TEMPERATURE
OUTPUT VOLTAGE‡
vs
DIFFERENTIAL INPUT VOLTAGE
5
VDD = 5 V
RL = 50 kΩ
VIC = 2.5 V
TA = 25°C
VO = 0
VDD± = ± 5 V
10
9
8
4
VID = − 100 mV
VO − Output Voltage − V
IIOS
OS − Short-Circuit Output Current − mA
11
7
6
5
4
3
3
2
2
1
1
VID = 100 mV
0
−1
−75
−50
−25
0
25
50
75
100
0
0
250 500 750 1000
−1000 −750 −500 −250
VID − Differential Input Voltage − µV
125
TA − Free-Air Temperature − °C
Figure 23
Figure 22
DIFFERENTIAL GAIN‡
vs
LOAD RESISTANCE
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
VO − Output Voltage − V
3
104
VDD± = ± 5 V
VIC = 0
RL = 50 kΩ
TA = 25°C
VO (PP) = 2 V
TA = 25°C
Differential Gain − V/ mV
5
1
−1
103
VDD = ± 5 V
VDD = 5 V
102
−3
−5
0
250 500 750 1000
−1000 −750 −500 −250
VID − Differential Input Voltage − µV
10
1
101
102
RL − Load Resistance − kΩ
103
Figure 25
Figure 24
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN†
vs
FREQUENCY
AVD
AVD − Large-Signal Differential
Voltage Amplification − dB
60
180°
VDD = 5 V
RL = 50 kΩ
CL= 100 pF
TA = 25°C
135°
40
90°
Phase Margin
20
ÁÁ
ÁÁ
ÁÁ
45°
Gain
0
0°
−20
φom
m − Phase Margin
80
−45°
−40
10 3
10 4
10 5
10 6
−90°
10 7
f − Frequency − Hz
Figure 26
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE MARGIN
vs
FREQUENCY
60
180°
VDD = ± 10 V
RL= 50 kΩ
CL= 100 pF
TA = 25°C
135°
40
Phase Margin
20
ÁÁ
ÁÁ
ÁÁ
45°
Gain
0
0°
−20
−40
10 3
−45°
10 4
10 5
10 6
f − Frequency − Hz
Figure 27
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
20
90°
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
−90°
10 7
φom
m − Phase Margin
AVD
AVD − Large-Signal Differential
Voltage Amplification − dB
80
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†‡
vs
FREE-AIR TEMPERATURE
RL = 1 MΩ
10 3
ÁÁ
ÁÁ
10 4
VDD = 5 V
VIC = 2.5 V
VO = 1 V to 4 V
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/mV
AVD
AVD − Large-Signal Differential
Voltage Amplification − V/mV
10 4
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION†
vs
FREE-AIR TEMPERATURE
RL = 50 kΩ
10 2
101
−75
−50
ÁÁ
ÁÁ
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
VDD± = ± 5 V
VIC = 0
VO = ± 4 V
RL = 1 MΩ
10 3
RL = 50 kΩ
10 2
101
−75
125
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
Figure 28
Figure 29
OUTPUT IMPEDANCE‡
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
1000
VDD± = ± 5 V
TA = 25°C
z o − Output Impedance − 0
zo
Ω
VDD = 5 V
TA = 25°C
z o − Output Impedance − 0
zo
Ω
125
100
AV = 100
10
AV = 10
1
AV = 1
100
AV = 100
10
AV = 10
1
AV = 1
0.1
10 2
10 3
10 4
10 5
f − Frequency − Hz
10 6
0.1
10 2
10 3
10 4
10 5
f − Frequency − Hz
10 6
Figure 31
Figure 30
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
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21
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO†‡
vs
FREE-AIR TEMPERATURE
COMMON-MODE REJECTION RATIO†
vs
FREQUENCY
94
CMRR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
100
VDD± = ± 5 V
80
VDD = 5 V
60
40
20
0
101
10 2
10 3
10 4
10 5
VDD± = ± 5 V
92
90
86
84
82
80
−75
16 6
VDD = 5 V
88
−50
f − Frequency − Hz
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 32
Figure 33
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
100
kSVR +
VDD = 5 V
TA = 25°C
KSVR
k SVR − Supply-Voltage Rejection Ratio − dB
KSVR
k SVR − Supply-Voltage Rejection Ratio − dB
100
80
60
kSVR −
40
20
ÁÁ
ÁÁ
ÁÁ
0
−20
101
10 2
10 3
10 4
f − Frequency − Hz
10 5
10 6
ÁÁ
ÁÁ
ÁÁ
VDD± = ± 5 V
TA = 25°C
kSVR +
80
60
kSVR −
40
20
0
−20
101
Figure 34
10 2
10 3
10 4
f − Frequency − Hz
10 5
Figure 35
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
125
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10 6
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SUPPLY-VOLTAGE REJECTION RATIO†
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT†
vs
SUPPLY VOLTAGE
110
240
k
KSVR
SVR − Supply-Voltage Rejection Ratio − dB
VDD± = ± 2.2 V to ± 8 V
VO = 0
VO = 0
No Load
200
IDD
µA
I DD − Supply Current − uA
105
100
ÁÁ
ÁÁ
ÁÁ
TA = − 55°C
160
TA = 25°C
120
ÁÁ
ÁÁ
ÁÁ
95
TA = 125°C
TA = − 40°C
80
40
90
−75
−50
−25
0
25
50
75
100
0
125
0
1
TA − Free-Air Temperature − °C
2
Figure 36
5
6
7
8
SLEW RATE‡
vs
LOAD CAPACITANCE
0.2
240
0.18
VDD± = ± 5 V
VO = 0
160
VDD = 5 V
VO = 2.5 V
120
VDD = 5 V
AV = − 1
TA = 25°C
0.16
SR − Slew Rate − V/
v/us
µs
200
µA
IDD
I DD − Supply Current − uA
4
Figure 37
SUPPLY CURRENT†‡
vs
FREE-AIR TEMPERATURE
ÁÁ
ÁÁ
3
| VDD ± | − Supply Voltage − V
80
0.14
SR −
0.12
0.1
SR +
0.08
0.06
0.04
40
0.02
0
−75
−50
−25
0
25
50
75 100
TA − Free-Air Temperature − °C
125
0
101
Figure 38
10 2
10 3
CL − Load Capacitance − pF
10 4
Figure 39
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
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23
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
SLEW RATE†‡
vs
FREE-AIR TEMPERATURE
INVERTING LARGE-SIGNAL PULSE
RESPONSE‡
0.2
5
SR − Slew Rate − v/uss
V/ µ
0.16
VO
VO − Output Voltage − V
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
SR −
0.12
SR +
0.08
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
4 A = −1
V
TA = 25°C
3
2
1
0.04
0
−75
0
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
0
125
10
20
VO
VO − Output Voltage − V
2
60
70
80
90 100
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE‡
5
VO
VO − Output Voltage − V
VDD± = ± 5 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
3
50
Figure 41
INVERTING LARGE-SIGNAL PULSE
RESPONSE
4
40
t − Time − µs
Figure 40
5
30
1
0
−1
−2
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
4 A =1
V
TA = 25°C
3
2
1
−3
−4
0
−5
0
10
20
30
40 50 60
t − Time − µs
70
80
90 100
0
10
Figure 42
20
30
40 50 60 70
t − Time − µs
80
90 100
Figure 43
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
‡ For curves where VDD = 5 V, all loads are referenced to 2.5 V.
24
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TYPICAL CHARACTERISTICS
INVERTING SMALL-SIGNAL
PULSE RESPONSE†
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
2.65
5
VDD± = ± 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
VO
VO − Output Voltage − V
3
2
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
2.6
VO
VO − Output Voltage − V
4
1
0
−1
−2
−3
2.55
2.5
2.45
−4
−5
2.4
0
10
20
30
40 50 60
t − Time − µs
70
80
0
90 100
10
INVERTING SMALL-SIGNAL
PULSE RESPONSE
50
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE†
0.1
VDD± = ± 5 V
RL = 50 kΩ
CL = 100 pF
AV = − 1
TA = 25°C
0
−0.05
2.65
VDD = 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
2.6
VO
VO − Output Voltage − V
VO
VO − Output Voltage − mV
40
Figure 45
Figure 44
0.05
20
30
t − Time − µs
2.55
2.5
2.45
−0.1
0
2.4
10
20
30
40
50
0
t − Time − µs
Figure 46
10
20
30
t − Time − µs
40
50
Figure 47
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
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25
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE†
vs
FREQUENCY
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
60
VDD ± = ± 5 V
RL = 50 kΩ
CL = 100 pF
AV = 1
TA = 25°C
0.05
V n − Equivalent Input Noise Voltage − nV/
VN
nv//HzHz
VO
VO − Output Voltage − V
0.1
0
−0.05
−0.1
0
10
20
30
t − Time − µs
40
50
VDD = 5 V
RS = 20 Ω
TA = 25°C
50
40
30
20
10
0
101
10 2
10 3
f − Frequency − Hz
Figure 49
Figure 48
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
EQUIVALENT INPUT NOISE VOLTAGE OVER
A 10-SECOND PERIOD†
1000
VDD± = ± 5 V
RS = 20 Ω
TA = 25°C
VDD = 5 V
f = 0.1 Hz to 10 Hz
TA = 25°C
750
500
Noise Voltage − nV
V n − Equivalent Input Noise Voltage − nv//Hz
VN
nV/ Hz
60
50
40
30
20
250
0
−250
−500
10
−750
0
101
10 2
10 3
f − Frequency − Hz
10 4
−1000
0
Figure 50
2
4
6
t − Time − s
Figure 51
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
26
10 4
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8
10
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION PLUS NOISE†
vs
FREQUENCY
THD + N − Total Harmonic Distortion Plus Noise − %
INTEGRATED NOISE VOLTAGE
vs
FREQUENCY
Integrated Noise Voltage − µ V
100
Calculated Using Ideal Pass-Band Filter
Low Frequency = 1 Hz
TA = 25°C
10
1
0.1
1
101
10 2
10 3
f − Frequency − Hz
10 4
10 5
1
AV = 100
0.1
AV = 10
0.01
AV = 1
VDD = 5 V
RL = 50 kΩ
TA = 25°C
0.001
101
10 2
10 5
Figure 53
GAIN-BANDWIDTH PRODUCT †‡
vs
FREE-AIR TEMPERATURE
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
280
250
TA = 25°C
VDD = 5 V
f = 10 kHz
RL = 50 kΩ
CL = 100 pF
240
Gain-Bandwidth Product − kHz
Gain-Bandwidth Product − kHz
10 4
f − Frequency − Hz
Figure 52
200
160
120
80
−75
10 3
230
210
190
170
150
−50
−25
0
25
50
75
100
125
0
1
TA − Free-Air Temperature − °C
2
3
4
5
6
7
8
| VDD ± | − Supply Voltage − V
Figure 54
Figure 55
† For curves where VDD = 5 V, all loads are referenced to 2.5 V.
‡ Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
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27
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
LOAD CAPACITANCE
75°
GAIN MARGIN
vs
LOAD CAPACITANCE
20
Rnull = 200 Ω
TA = 25°C
Rnull = 500 Ω
Rnull = 500 Ω
60°
Gain Margin − dB
φom
m − Phase Margin
15
45°
Rnull = 100 Ω
Rnull = 50 Ω
30°
Rnull = 10 Ω
50 kΩ
VI
Rnull = 50 Ω
5
VDD +
Rnull
−
+
Rnull = 0
Rnull = 0
CL
TA = 25°C
VDD −
0°
101
Rnull = 100 Ω
10
Rnull = 10 Ω
50 kΩ
15°
Rnull = 200 Ω
10 4
10 2
10 3
CL − Load Capacitance − pF
0
101
10 5
10 2
10 3
Figure 57
OVERESTIMATION OF PHASE MARGIN†
vs
LOAD CAPACITANCE
UNITY-GAIN BANDWIDTH†
vs
LOAD CAPACITANCE
25
200
TA = 25°C
TA = 25°C
Rnull = 500 Ω
Overestimation of Phase Margin
B1 − Unity-Gain Bandwidth − kHz
175
150
125
100
75
50
20
15
Rnull = 100 Ω
10
Rnull = 200 Ω
Rnull = 50 Ω
Rnull = 10 Ω
5
25
0
101
10 2
10 3
10 4
10 5
0
101
CL − Load Capacitance − pF
Figure 58
10 2
10 3
10 4
CL − Load Capacitance − pF
Figure 59
† See application information
28
10 5
CL − Load Capacitance − pF
Figure 56
ÁÁ
ÁÁ
10 4
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10 5
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
driving large capacitive loads
The TLC225x is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 56
and Figure 57 illustrate its ability to drive loads up to 1000 pF while maintaining good gain and phase margins
(Rnull = 0).
A smaller series resistor (Rnull) at the output of the device (see Figure 60) improves the gain and phase margins
when driving large capacitive loads. Figure 56 and Figure 57 show the effects of adding series resistances of
10 Ω, 50 Ω, 100 Ω, 200 Ω, and 500 Ω. The addition of this series resistor has two effects: the first is that it adds
a zero to the transfer function and the second is that it reduces the frequency of the pole associated with the
output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the improvement in phase margin, equation 1 can be used.
ǒ
∆φ m1 + tan –1 2 × π × UGBW × R
null
×C
Ǔ
(1)
L
Where :
∆φ m1 + Improvement in phase margin
UGBW + Unity-gain bandwidth frequency
R null + Output series resistance
C L + Load capacitance
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (see Figure 58). To
use equation 1, UGBW must be approximated from Figure 58.
Using equation 1 alone overestimates the improvement in phase margin, as illustrated in Figure 59. The
overestimation is caused by the decrease in the frequency of the pole associated with the load, thus providing
additional phase shift and reducing the overall improvement in phase margin.
Using Figure 60, with equation 1 enables the designer to choose the appropriate output series resistance to
optimize the design of circuits driving large capacitance loads.
50 kΩ
VDD +
50 kΩ
VI
Rnull
−
+
CL
VDD −/ GND
Figure 60. Series-Resistance Circuit
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29
SGLS188A − OCTOBER 2003 − REVISED FEBRUARY 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using MicroSim Parts, the model generation software used
with MicroSim PSpice. The Boyle macromodel (see Note 5) and subcircuit in Figure 61 are generated using
the TLC225x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
99
3
VCC +
9
RSS
10
J1
DP
VC
J2
IN +
11
RD1
VAD
DC
12
C1
R2
−
53
HLIM
−
+
C2
6
−
−
+
+
GCM
GA
−
RD2
−
RO1
DE
5
+
VE
.SUBCKT TLC225x 1 2 3 4 5
C1
11
12
6.369E−12
C2
6
7
25.00E−12
DC
5
53
DX
DE
54
5
DX
DLP
90
91
DX
DLN
92
90
DX
DP
4
3
DX
EGND
99
0
POLY (2) (3,0) (4,0) 0 .5 .5
FB
7
99
POLY (5) VB VC VE VLP
+ VLN 0 57.62E6 −60E6 60E6 60E6 −60E6
GA
6
0
11
12 26.86E−6
GCM
0
6
10
99 2.686E−9
ISS
3
10
DC 3.1E−6
HLIM
90
0
VLIM 1K
J1
11
2
10 JX
J2
12
1
10 JX
R2
6
9
100.0E3
OUT
RD1
60
11
37.23E3
RD2
60
12
37.23E3
R01
8
5
84
R02
7
99
84
RP
3
4
71.43E3
RSS
10
99
64.52E6
VAD
60
4
−.5
VB
9
0
DC 0
VC
3
53
DC .605
VE
54
4
DC .605
VLIM
7
8
DC 0
VLP
91
0
DC −.235
VLN
0
92
DC 7.5
.MODEL DX D (IS=800.0E−18)
.MODEL JX PJF (IS=500.0E−15 BETA=139E−6
+ VTO=−.05)
.ENDS
Figure 61. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
30
−
VLIM
8
54
4
91
+
VLP
7
60
+
−
+ DLP
90
RO2
VB
IN −
VCC −
92
FB
−
+
ISS
RP
2
1
DLN
EGND +
POST OFFICE BOX 655303
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VLN
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TLC2252AQDRQ1
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLC2252AQPWRQ1
ACTIVE
TSSOP
PW
8
TLC2252QDRQ1
ACTIVE
SOIC
D
8
2000
None
CU NIPDAU
Level-1-250C-UNLIM
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLC2252QPWRQ1
ACTIVE
TSSOP
PW
8
TLC2254AQDRQ1
ACTIVE
SOIC
D
14
2000
None
CU NIPDAU
Level-1-220C-UNLIM
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLC2254AQPWRQ1
ACTIVE
TSSOP
PW
14
TLC2254QDRQ1
ACTIVE
SOIC
D
14
2000
None
CU NIPDAU
Level-1-250C-UNLIM
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLC2254QPWRQ1
ACTIVE
TSSOP
PW
14
2000
None
CU NIPDAU
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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IMPORTANT NOTICE
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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