SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
D Controlled Baseline
D
D
D
D
D
D
D
D Temperature-Compensated Voltage
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−40°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree†
Power-On Reset Generator
Automatic Reset Generation After
Voltage Drop
Precision Voltage Sensor
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D
D
D
D
D
D
Reference
Programmable Delay Time by External
Capacitor
Supply Voltage Range . . . 2 V to 6 V
Defined RESET Output from VDD ≥ 1 V
Power-Down Control Support for Static
RAM With Battery Backup
Maximum Supply Current of 16 µA
Power Saving Totem-Pole Outputs
PW PACKAGE
(TOP VIEW)
CONTROL
RESIN
CT
GND
1
8
2
7
3
6
4
5
VDD
SENSE
RESET
RESET
description
The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer
and microprocessor systems.
During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD (≥ 2 V) is established, the
circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE))
remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure
proper system reset. The delay time, td, is determined by an external capacitor:
td = 2.1 × 104 × CT
Where
CT is in farads
td is in seconds
Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed
SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold
voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage
and the delay time, td, has expired.
In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control
support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor
contains additional logic intended for control of static memories with battery backup during power failure. By
driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL
driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is
automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the
battery.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
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1
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
ORDERING INFORMATION†
ORDERABLE
PART NUMBER
PACKAGE‡
TA
−40°C
−40
C to 125
125°C
C
TOP-SIDE
MARKING
TSSOP − PW
Tape and reel
TLC7701QPWREP
7701QE
TSSOP − PW
Tape and reel
TLC7705QPWREP
7705QE
TSSOP − PW
Tape and reel
TLC7733QPWREP
7733QE
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
‡ The PW package is only available left-end taped and reeled (indicated by the R suffix on the device type;
e.g., TLC7701QPWREP).
FUNCTION TABLE
logic symbol¶
CONTROL
RESIN
VI(SENSE)>VIT+
RESET
RESET
L
L
False
H
L
L
L
True
H
L
L
H
False
L
H
True
H
L§
L
H§
H
L
False
H
L
SENSE
RESIN
S
S<VIT
VIT
2
1
CT
3
×
L
True
H
L
1
H
H
False
H
L
H§
2
CONTROL
1
Z1
Z2
CX
H
H
H
True
H
§ RESET and RESET states shown are valid for t > td.
≥1
COMP
7
≥1
5
Z3
≥1
6
RESET
RESET
3
¶ This symbol is in accordance with ANSI/IEEE Std 91−1984 and
IEC Publication 617-12.
functional block diagram
8
CONTROL
1
6
RESET†
5
RESET†
50 µA
RESIN
SENSE
2
7
R1‡
R2‡
1 MΩ
1.1 V
4
3
CT
† Outputs are totem-pole configuration. External pullup or pulldown resistors are not required.
‡ Nominal values:
TLC7701
2
VDD
R1 (Typ)
R2 (Typ)
0
∞
TLC7705
910 kΩ
290 kΩ
TLC7733
750 kΩ
450 kΩ
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GND
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
timing diagram
VDD and VI(SENSE)
VIT+
Threshold Voltages
VIT+
VIT−
Vres
RESET
Output
t
ÎÎ
td
td
Output
Undefined
t
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range, CONTROL, RESIN, SENSE (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 mA
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: TL77xxQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
PW
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
525 mW
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
273 mW
105 mW
4.2 mW/°C
recommended operating conditions at specified temperature range
Supply voltage, VDD
Input voltage, VI
High-level input voltage at RESIN and CONTROL‡, VIH
MIN
MAX
UNIT
2
6
V
0
VDD
V
0.7×VDD
Low-level input voltage at RESIN and CONTROL‡, VIL
High-level output current, IOH
Low-level output current, IOL
0.2×VDD
−2
VDD ≥ 2.7 V
Input transition rise and fall rate at RESIN and CONTROL, ∆t/∆V
Operating free-air temperature range, TA
‡ To ensure a low supply current, VIL should be kept < 0.3 V and VIH > VDD − 0.3 V.
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V
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−40
V
mA
2
mA
100
ns/V
125
°C
3
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating conditions (see Note 2) (unless otherwise
noted)
TLC77xx
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
IOH = − 20 µA
4.3
IOH = − 2 mA
VDD = 4.5 V
VDD = 4.5 V
VDD = 2 V
VDD = 2.7 V
0.2
IOL = 20 µA
0.2
IOL = 2 mA
VDD = 4.5 V
VDD = 4.5 V
Negative-going input threshold voltage,
SENSE (see Note 3)
TLC7705
TLC7705
Hysteresis voltage, SENSE
II
Input current
V
3.7
0.2
V
0.5
VDD = 2 V to 6 V
1.04
1.1
1.16
4.43
4.5
4.63
2.855
2.93
3.03
V
30
VDD = 2 V to 6 V
mV
70
TLC7733
IOL = 20 µA
1
RESIN
VI = 0 V to VDD
2
CONTROL
SENSE
VI = VDD
VI = 5 V
SENSE, TLC7701 only
VI = 5 V
Power-up reset voltage‡
UNIT
2.5
TLC7701
Vres
MAX
1.8
TLC7733
Vhys
TYP†
VDD = 2 V
VDD = 2.7 V
TLC7701
VIT −
MIN
7
15
5
10
V
µA
2
IDD
Supply current
RESIN = VDD,
SENSE = VDD ≥ VITmax + 0.2 V
CONTROL = 0 V, Outputs open
IDD(d)
Supply current during td
VDD = 5 V,
RESIN = VDD,
CONTROL = 0 V,
VCT = 0 ,
SENSE = VDD,
Outputs open
9
16
µA
120
150
µA
CI
Input capacitance, SENSE
VI = 0 V to VDD
50
pF
† Typical values apply at TA = 25°C.
‡ The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEDEC standards for
semiconductor symbology. Rise time of VDD ≥ 15 µs/V.
NOTES: 2. All characteristics are measured with CT = 0.1 µF.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be connected near the supply terminals.
4
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SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
switching characteristics at VDD = 5 V, RL = 2 kΩ, CL = 50 pF, TA = Full Range (unless otherwise
noted)
MEASURED
PARAMETER
td
Delay time
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
FROM
(INPUT)
VI(SENSE) ≥ VIT+
RESET
and
RESET
tr
Rise time
tf
Fall time
TEST CONDITIONS
RESIN = 0.7 × VDD,
CONTROL = 0.2 × VDD,
CT = 100 nF,
TA = Full range,
See timing diagram
MIN
TYP
MAX
1.1
2.1
4.2
UNIT
ms
20
RESET
SENSE
RESET
VIH = VIT+max + 0.2 V,
VIL = VIT−min − 0.2 V,
RESIN = 0.7 × VDD,
CONTROL = 0.2 × VDD,
CT = NC†
5
µss
5
20
20
RESET
RESIN
RESET
CONTROL
Low-level minimum pulse
duration to switch RESET
and RESET
TLC77xx
TO
(OUTPUT)
RESET
VIH = 0.7 × VDD,
VIL = 0.2 × VDD,
SENSE = VIT+max + 0.2 V,
CONTROL = 0.2 × VDD,
CT = NC†
60
ns
65
VIH = 0.7 × VDD,
VIL = 0.2 × VDD,
SENSE = VIT+max + 0.2 V,
RESIN = 0.7 × VDD,
CT = NC†
VIH = VIT+max + 0.2 V,
VIL = VIT−min − 0.2 V,
VIL = 0.2 × VDD,
VIH = 0.7 × VDD
SENSE
RESIN
RESET
and
RESET
µs
20
µs
58
ns
58
ns
3
µss
1
10% to 90%
8
90% to 10%
4
ns/V
† NC = No capacitor, and includes up to 100-pF probe and jig capacitance.
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5
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
5V
DUT
RL
(see Note A)
CL
(see Note B)
NOTES: A. For switching characteristics, RL = 2 kΩ .
B. CL = 50 pF includes jig and probe capacitance.
Figure 1. RESET AND RESET Output Configurations
I, Q, and Y suffixed devices
tw(L)
0.7 × VDD
0.5 × VDD
0.2 × VDD
M suffixed devices
tw(L)
tw(L)
2.7 V
1.5 V
0.4 V
(a) RESIN
VIT+max + 200 mV
VIT+
VIT−min − 200 mV
VIT−
(b) SENSE
Figure 2. Input Pulse Definition Waveforms
6
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SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10
1.005
9
1.004
8
I DD − Supply Current − µ A
Normalized Input Threshold Voltage − VIT− (TA )/V IT− (25 °C)
TYPICAL CHARACTERISTICS
1.003
1.002
1.001
1
0.999
7
6
5
4
3
RESIN = VDD = −1 V to 6.5 V
SENSE = GND
CONTROL = GND
CT = Open = 100 pF
TA = 25°C
2
1
0.998
0.997
−40
0
−20
0
20
40
60
80
100
−1
−0.5
120
0.5
TA − Temperature − °C
1.5
4
0°C
3.5
−55°C
125°C
3
2.5
85°C
2
25°C
1.5
−40°C
1
VDD = 4.5 V
RESIN = 4.5 V
SENSE = 0.5 V
CONTROL = 0 V
CT = Open = 100 pF
−1
0
−5
−10 −15
−20 −25 −30 −35 −40
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
4.5
5
5.5
6.5
6
5
−0.5
4.5
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0
3.5
Figure 4
Figure 3
0.5
2.5
VDD − Supply Voltage − V
5
4
VDD = 4.5 V
RESIN = 4.5 V
SENSE = 5 V
CONTROL = 0 V
CT = Open = 100 pF
125°C
85°C
25°C
0°C
3
2
−40°C
1
−55°C
0
−1
−5
0
5
10
15
20
25
30
IOL − Low-Level Output Current − mA
IOH − High-Level Output Current − mA
Figure 6
Figure 5
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7
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE AT SENSE
8
VDD = 4.5 V
CT = Open = 100 pF
6
125°C
4
I I − Input Current − µ A
−55°C
2
0
−2
125°C
−4
−55°C
−6
−8
−10
−1
0
1
2
3
4
5
6
VI − Input Voltage at SENSE − V
Figure 7
MINIMUM PULSE DURATION AT SENSE
vs
SENSE THRESHOLD OVERDRIVE
t w − Minimum Pulse Duration at SENSE − µ s
7
VDD = 2 V
Control = 0.4 V
RESIN = 1.4 V
CT = Open = 100 pF
6
5
4
3
2
1
0
0
50
100
150
200
250
300
Sense Threshold Overdrive − mV
Figure 8
8
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350
400
SGLS013A − MARCH 2003 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
VDD
0.1 µF
100 kΩ
0.1 µF
VDD
VDD
TLC77xx
RESIN RESET
SENSE RESET
CT
RESET
RESET
TMS70C20
NC
CONTROL
GND
GND
Figure 9. Reset Controller in a Microcomputer System
VDD
0.1 µF
VDD
TLC77xx
RESIN
0.1 µF
0.1 µF
SENSE
RESET
CONTROL
VDD
CT
RESET
CSH1
CS
RESET
32K 8
CMOS RAM
GND
TMS370
ADD0 −15
DATA0 −7
16
8
A0 −A15
D0 −D7
R/W
R/W
GND
GND
Figure 10. Data Retention During Power Down Using Static CMOS RAMs
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9
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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