TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 D D D D D D D Micro-Power Operation . . . < 1 µA/Channel Input Common-Mode Range Exceeds the Rails . . . –0.1 V to VCC + 5 V Reverse Battery Protection Up To 18 V Rail-to-Rail Input/Output Gain Bandwidth Product . . . 5.5 kHz Supply Voltage Range . . . 2.5 V to 16 V Specified Temperature Range – TA = 0°C to 70°C . . . Commercial Grade – TA = –40°C to 125°C . . . Industrial Grade Ultrasmall Packaging – 5-Pin SOT-23 (TLV2401) – 8-Pin MSOP (TLV2402) Universal OpAmp EVM (Refer to the EVM Selection Guide SLOU060) Operational Amplifier – + SUPPLY CURRENT vs SUPPLY VOLTAGE 1.4 I CC – Supply Current – µ A/Ch D D description The TLV240x family of single-supply operational amplifiers has the lowest supply current available today at only 880 nA per channel. Reverse battery protection guards the amplifier from an overcurrent condition due to improper battery installation. For harsh environments, the inputs can be taken 5 V above the positive supply rail without damage to the device. AV = 1 VIN = VCC / 2 TA = 25 °C 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 VCC – Supply Voltage – V The low supply current is coupled with extremely low input bias currents enabling them to be used with mega-Ω resistors making them ideal for portable, long active life, applications. DC accuracy is ensured with a low typical offset voltage as low as 390 µV, CMRR of 120 dB and minimum open loop gain of 130 V/mV at 2.7 V. The maximum recommended supply voltage is as high as 16 V and ensured operation down to 2.5 V, with electrical characteristics specified at 2.7 V, 5 V and 15 V. The 2.5-V operation makes it compatible with Li-Ion battery-powered systems and many micro-power microcontrollers available today including TI’s MSP430. All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP, and quads in TSSOP. SELECTION OF SINGLE SUPPLY OPERATIONAL AMPLIFIER PRODUCTS† DEVICE VCC (V) VIO (mV) BW (MHz) SLEW RATE (V/µs) ICC/ch (µA) RAIL-TO-RAIL TLV240x‡ 2.5–16 0.390 0.005 0.002 0.880 I/O TLV224x 2.5–12 0.600 0.005 0.002 1 I/O TLV2211 2.7–10 0.450 0.065 0.025 13 O TLV245x 2.7–6 0.020 0.22 0.110 23 I/O TLV225x 2.7–8 0.200 0.2 0.12 35 O † All specifications are typical values measured at 5 V. ‡ This device also offers 18-V reverse battery protection and 5-V over-the-rail operation on the inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TLV2401 AVAILABLE OPTIONS VIOmax AT 25°C TA 0°C to 70°C - 40°C to 125°C 1500 µV PACKAGED DEVICES SOT-23† SYMBOLS (DBV) SMALL OUTLINE† (D) TLV2401CD TLV2401CDBV VAWC TLV2401ID TLV2401IDBV VAWI PLASTIC DIP (P) — TLV2401IP † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2401CDR). TLV2402 AVAILABLE OPTIONS VIOmax AT 25°C TA 0°C to 70°C – 40°C to 125°C 1500 µV PACKAGED DEVICES MSOP† SYMBOLS (DGK) SMALL OUTLINE† (D) PLASTIC DIP (P) TLV2402CD TLV2402CDGK xxTIAIX — TLV2402ID TLV2402IDGK xxTIAIY TLV2402IP † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2402CDR). TLV2404 AVAILABLE OPTIONS PACKAGED DEVICES † SMALL OUTLINE PLASTIC DIP (N) (D) VIOmax AT 25°C TA 0°C to 70°C – 40°C to 125°C 1500 µV TLV2404CD TLV2404CN TLV2404ID TLV2404IN TSSOP (PW) TLV2404CPW TLV2404IPW † This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2404CDR). TLV240x PACKAGE PINOUTS TLV2401 D OR P PACKAGE (TOP VIEW) TLV2401 DBV PACKAGE (TOP VIEW) OUT GND IN+ 1 5 VCC 2 3 4 IN – NC IN – IN + GND 1 8 2 7 3 6 4 5 TLV2402 D, DGK, OR P PACKAGE (TOP VIEW) NC VCC OUT NC TLV2404 D, N, OR PW PACKAGE (TOP VIEW) 1OUT 1IN – 1IN+ VCC 2IN+ 2IN – 2OUT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 4OUT 4IN – 4IN+ GND 3IN+ 3IN – 3OUT NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1OUT 1IN – 1IN + GND 1 8 2 7 3 6 4 5 VCC 2OUT 2IN – 2IN+ TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V Differential input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V Input current range, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND DISSIPATION RATING TABLE PACKAGE ΘJC (°C/W) ΘJA (°C/W) TA ≤ 25°C POWER RATING D (8) 38.3 176 710 mW 142 mW D (14) 26.9 122.6 1022 mW 204.4 mW TA = 125°C POWER RATING DBV (5) 55 324.1 385 mW 77.1 mW DGK (8) 54.2 259.9 481 mW 96.2 mW N (14) 32 78 1600 mW 320.5 mW P (8) 41 104 1200 mW 240.4 mW PW (14) 29.3 173.6 720 mW 144 mW recommended operating conditions Single supply Supply voltage voltage, VCC Split supply Common-mode input voltage range, VICR C-suffix free air temperature, temperature TA Operating free-air I-suffix POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX 2.5 16 ±1.25 ±8 –0.1 0 VCC+5 70 – 40 125 UNIT V V °C 3 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 electrical characteristics at recommended operating conditions, VCC = 2.7, 5 V, and 15 V (unless otherwise noted) dc performance PARAMETER VIO Input offset voltage αVIO Offset voltage draft TEST CONDITIONS VIC = 0 to VCC, RS = 50 Ω MAX 390 1200 1500 25°C VCC = 5 V 7V VCC = 2 2.7 V, VO( V, RL = 500 kΩ O(pp)) = 1 V AVD TYP Full range VCC = 15 V Large-signal g g differential voltage g amplification MIN 25°C VO = VCC/2 V, VIC = VCC/2 V, RS = 50 Ω VCC = 2 2.7 7V CMRR Common-mode Common mode rejection ratio TA† VCC = 5 V V, VO( V, RL = 500 kΩ O(pp)) = 3 V VCC = 15 V V, VO( V, RL = 500 kΩ O(pp)) = 6 V 63 Full range 60 25°C 70 Full range 63 25°C 80 Full range 75 25°C 130 Full range 30 25°C 300 Full range 100 25°C 1000 Full range 120 µV µV/°C 3 25°C UNIT 120 120 dB 120 400 1000 V/mV 1800 † Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is – 40°C to 125°C. input characteristics PARAMETER IIO TEST CONDITIONS Input offset current TLV240xC VO = VCC/2 V, VIC = VCC/2 V V, RS = 50 Ω IIB Input bias current TLV240xI TYP MAX 25 250 300 pA 400 100 300 350 Full range 25°C UNIT pA 900 300 MΩ Ci(c) Common-mode input capacitance f = 100 kHz 25°C 3 † Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is – 40°C to 125°C. pF 4 Differential input resistance MIN Full range 25°C TLV240xC TLV240xI ri(d) TA† 25°C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 electrical characteristics at recommended operating conditions, VCC = 2.7, 5 V, and 15 V (unless otherwise noted) (continued) output characteristics PARAMETER TEST CONDITIONS VCC = 2 2.7 7V VIC = VCC/2,, IOH = –2 µA VCC = 5 V VCC = 15 V VOH High level output voltage High-level VCC = 2 2.7 7V VIC = VCC/2,, IOH = –50 µA VCC = 5 V VCC = 15 V /2 IOL = 2 µA VIC = VCC/2, VOL Low level output voltage Low-level VIC = VCC/2, /2 IOL = 50 µA TA† 25°C MIN TYP 2.65 2.68 Full range 2.63 25°C 4.95 Full range 4.93 25°C 14.95 Full range 14.93 25°C 2.62 Full range 2.6 25°C 4.92 Full range 4.9 25°C 14.92 Full range 14.9 25°C MAX 4.98 14.98 V 2.65 4.95 14.95 90 Full range 150 180 25°C UNIT 180 Full range 230 mV 260 IO Output current VO = 0.5 V from rail 25°C ±200 † Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is – 40°C to 125°C. µA power supply PARAMETER TEST CONDITIONS VCC = 2.7 2 7 V or 5 V ICC Supply current (per channel) VO = VCC/2 VCC = 15 V Reverse supply current PSRR Power supply rejection ratio (∆VCC/∆VIO) VCC = –18 V, VIN = 0 V, VO = Open circuit TA† 25°C TLV240xC VCC = 5 to 15 V, No load VIC = VCC/2 V, TLV240xI TYP MAX 880 950 Full range 1290 25°C 900 Full range Full range 990 UNIT nA 1350 25°C 25°C VCC = 2.7 to 5 V, VIC = VCC/2 V, No load, MIN 50 100 120 96 85 25°C 100 Full range 100 nA dB dB 120 dB † Full range is 0°C to 70°C for the C suffix and –40°C to 125°C for the I suffix. If not specified, full range is – 40°C to 125°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 electrical characteristics at recommended operating conditions, VCC = 2.7, 5 V, and 15 V (unless otherwise noted) (continued) dynamic performance PARAMETER TEST CONDITIONS UGBW Unity gain bandwidth RL = 500 kΩ, SR Slew rate at unity gain VO(pp) = 0.8 V, RL = 500 kΩ, φM Phase margin RL = 500 kΩ kΩ, CL = 100 pF Gain margin ts VCC = 2.7 or 5 V, V(STEP)PP = 1 V, AV = –1, VCC = 15 V, V(STEP)PP = 1 V V, AV = –1, Settling time CL = 100 pF, RL = 100 kΩ CL = 100 pF F, RL = 100 kΩ CL = 100 pF TA 25°C CL = 100 pF 25°C MIN TYP MAX UNIT 5.5 kHz 2.5 V/ms 60° 25°C 15 0.1% dB 1.84 25°C ms 0.1% 6.1 0.01% 32 noise/distortion performance PARAMETER Vn Equivalent input noise voltage In Equivalent input noise current 6 TEST CONDITIONS TA f = 10 Hz f = 100 Hz f = 100 Hz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP 800 25°C 500 8 MAX UNIT nV/√Hz fA/√Hz TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input Offset Voltage vs Common-mode input voltage 1, 2, 3 vs Free-air temperature 4, 6, 8 vs Common-mode input voltage 5, 7, 9 vs Free-air temperature 4, 6, 8 vs Common-mode input voltage 5, 7, 9 IIB Input Bias Current IIO Input Offset Current CMRR Common-mode rejection ratio vs Frequency VOH VOL High-level output voltage vs High-level output current 11, 13, 15 Low-level output voltage vs Low-level output current 12, 14, 16 VO(PP) Zo Output voltage peak-to-peak vs Frequency 17 Output impedance vs Frequency 18 ICC PSRR Supply current vs Supply voltage 19 Power supply rejection ratio vs Frequency 20 AVD Differential voltage gain vs Frequency 21 Phase vs Frequency 21 Gain-bandwidth product vs Supply voltage 22 SR Slew rate vs Free-air temperature 23 φm Phase margin vs Capacitive load 24 Gain margin vs Capacitive load 25 Supply current vs Reverse voltage 26 Voltage noise over a 10 Second Period 10 27 Large signal follower pulse response 28, 29, 30 Small signal follower pulse response 31 Large signal inverting pulse response 32, 33, 34 Small signal inverting pulse response 35 Crosstalk vs Frequency POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 36 7 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 800 600 400 200 0 0 –100 –200 –300 VCC = 5 V TA = 25 °C –400 –0.2 –0.1 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2 –200 –0.20 –0.1 0.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9 Figure 1 200 100 IIO 0 IIB –100 –200 –40 –25 –10 5 I IB / I IO – Input Bias / Offset Current – pA 20 35 50 65 80 95 110 125 350 300 IIO 0 –50 IIB –100 –150 –0.2 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2 –0.1 VICR – Common Mode Input Voltage – V Figure 7 8 4.2 200 150 100 50 IIO 0 –50 IIB –100 –150 –0.2 –0.1 0.2 8.6 10.8 13.0 15.2 0.6 1.0 1.4 1.8 2.2 2.6 2.9 400 300 200 100 IIO 0 IIB –100 –200 –40 –25 –10 5 20 35 50 65 80 95 110 125 TA – Free-Air Temperature – °C Figure 6 Figure 5 INPUT BIAS / OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE INPUT BIAS / OFFSET CURRENT vs FREE-AIR TEMPERATURE 600 6.4 VCC = 5 V VIC = 2.5 V 500 VICR – Common Mode Input Voltage – V I IB / I IO – Input Bias / Offset Current – pA I IB / I IO – Input Bias / Offset Current – pA 50 2.0 INPUT BIAS / OFFSET CURRENT vs FREE-AIR TEMPERATURE 700 100 –300 600 VCC = 2.7 V TA = 25 °C Figure 4 150 –200 Figure 3 250 INPUT BIAS / OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE VCC = 5 V TA = 25 °C –100 VICR – Common-Mode Input Voltage –V 400 TA – Free-Air Temperature – °C 200 0 –400 –0.2 –0.1 250 VCC = 15 V VIC = 7.5 V 500 400 300 200 100 IIO 0 –100 –200 –40 –25 –10 5 IIB 20 35 50 65 80 95 110 125 TA – Free-Air Temperature – °C Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I IB / I IO – Input Bias / Offset Current – pA I IB / I IO – Input Bias / Offset Current – pA 300 100 INPUT BIAS / OFFSET CURRENT vs COMMON MODE INPUT VOLTAGE 600 400 200 Figure 2 INPUT BIAS / OFFSET CURRENT vs FREE-AIR TEMPERATURE 500 VCC = 15 V TA = 25 °C 300 VICR – Common-Mode Input Voltage – V VICR – Common-Mode Input Voltage – V VCC = 2.7 V VIC = 1.35 V V IO – Input Offset Voltage – µV 1000 I IB / I IO – Input Bias / Offset Current – pA VCC = 2.7 V TA = 25°C V IO – Input Offset Voltage – µV V IO – Input Offset Voltage – µV 400 100 1400 1200 INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE VCC = 15 V TA = 25 °C 200 150 100 50 IIO 0 –50 IIB –100 –150 –0.2 –0.1 2.0 4.2 6.4 8.6 10.8 13.0 15.2 VICR – Common-Mode Input Voltage –V Figure 9 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 1.50 100 RF=100 kΩ RI=1 kΩ 80 60 40 20 VCC = 2.7 V 2.4 TA = –40°C 2.1 TA = –0°C TA = 25 °C TA = 70 °C TA = 125 °C 1.8 1.5 1.2 0 10 100 1k f – Frequency – Hz HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 50 100 150 VOL – Low-Level Output Voltage – V TA = –0°C TA = 25 °C TA = 70 °C TA = 125 °C 4.0 3.5 150 TA = 0 °C TA = –40°C 1.00 0.75 TA = 25 °C TA = 70 °C TA = 125 °C 0.50 0.25 0 50 100 150 Figure 14 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT OUTPUT VOLTAGE PEAK-TO-PEAK vs FREQUENCY V O(PP) – Output voltage Peak–to–Peak – V TA = –40°C TA = –0°C TA = 25 °C TA = 70 °C TA = 125 °C 0.75 0.50 0.25 0 0 50 100 150 14.5 TA = –0°C TA = 25 °C TA = 70 °C TA = 125 °C 14.0 13.5 TA = –40°C VCC = 15 V 13 Figure 13 1.00 200 200 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 0 200 IOL – Low-Level Output Current – µA 1.25 150 Figure 12 1.25 200 VCC = 15 V 100 15.0 IOH – High-Level Output Current – µA 1.50 50 Figure 11 150 200 OUTPUT IMPEDANCE vs FREQUENCY 10k 14 VCC = 15 V 12 10 8 6 RL = 100 kΩ CL = 100 pF TA = 25°C VCC = 5 V 2 VCC = 2.7 V AV = 10 1k AV = 1 100 0 VCC = 2.7, 5, & 15 V TA = 25°C –2 10 100 Figure 15 16 4 50 IOH – High-Level Output Current – µA Z o – Output Impedance – Ω 100 0.25 0 0 50 TA = 70 °C TA = 125 °C 0.50 IOL – Low-Level Output Current – µA VCC = 5 V 3.0 0 0.75 IOH – High-Level Output Current – µA V OH – High-Level Output Voltage – V TA = –40°C 1.00 200 1.50 4.5 TA = 25 °C TA = 0 °C TA = –40°C 1.25 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 5.0 VCC = 5 V VCC = 2.7 V 0 0 10k Figure 10 V OH – High-Level Output Voltage – V VOL – Low-Level Output Voltage – V VCC=2.7, 5, 15 V 1 VOL – Low-Level Output Voltage – V LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 2.7 120 V OH – High-Level Output Voltage – V CMRR – Common-Mode Rejection Ratio – dB COMMON-MODE REJECTION RATIO vs FREQUENCY IOL – Low-Level Output Current – µA 100 f – Frequency – Hz Figure 16 Figure 17 POST OFFICE BOX 655303 1k • DALLAS, TEXAS 75265 10 100 1k f – Frequency – Hz 10k Figure 18 9 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE POWER SUPPLY REJECTION RATIO vs FREQUENCY PSRR – Power Supply Rejection Ratio – dB I CC – Supply Current – µ A/Ch 1.4 1.2 1.0 0.8 0.6 TA = 125°C TA = 70 °C TA = 25 °C TA = 0 °C TA = –40°C 0.4 0.2 AV = 1 VIN = VCC / 2 0 0 2 4 6 8 10 12 14 16 VCC = 2.7, 5, & 15 V TA = 25°C 110 100 90 80 70 60 50 40 VCC – Supply Voltage – V 100 1k f – Frequency – Hz Figure 19 Figure 20 DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 10 90 30 45 20 10 0 0 VCC = 2.7, 5, & 15 V RL = 500 kΩ CL = 100 pF TA = 25°C –10 100 1k f – Frequency – Hz 4 3 2 1 VCC – Supply Voltage –V Figure 22 SLEW RATE vs FREE-AIR TEMPERATURE PHASE MARGIN vs CAPACITIVE LOAD 80 3.0 70 SR+ VCC = 5, 15 V 60 VCC = 2.7 V 2.0 1.5 SR– 1.0 VCC = 2.7, 5, & 15 V Phase Margin – ° SR – Slew Rate – V/ ms 5 TA = 25°C RL = 100 kΩ CL = 100 pF f = 1 kHz Figure 21 3.5 2.5 6 0 2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0 –45 10k –20 10 GBWP –Gain Bandwidth Product – kHz 50 40 10k 7 135 Phase – ° AVD – Differential Voltage Gain – dB 60 50 40 30 20 0.5 10 0 –40 –25 –10 5 10 120 VCC = 2.7, 5, & 15 V RL = 500 kΩ TA = 25°C 0 20 35 50 65 80 95 110 125 TA – Free-Air Temperature – °C 100 1k CL – Capacitive Load – pF Figure 23 Figure 24 POST OFFICE BOX 655303 10 • DALLAS, TEXAS 75265 10k TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS GAIN MARGIN vs CAPACITIVE LOAD SUPPLY CURRENT vs REVERSE VOLTAGE 25 60 RL= 500 kΩ TA = 25°C 55 I CC – Supply Current – nA Gain Margin – dB TA = 25°C 50 20 VCC = 15 V 15 10 VCC = 2.7 & 5 V 5 45 40 35 30 25 20 15 10 5 0 100 1k CL – Capacitive Load – pF 0 –18 –16 –14 –12 –10 10k –4 –6 –2 Figure 25 Figure 26 VOLTAGE NOISE OVER A 10 SECOND PERIOD LARGE SIGNAL FOLLOWER PULSE RESPONSE 0 2 5 4 VCC = 5 V f = 0.1 Hz to 10 Hz TA = 25°C 3 Input Referred Voltage Noise – µV –8 VCC – Reverse Voltage – V 4 V – Output Voltage – V O 2 1 0 –1 –2 1 VIN 3 0 VCC = 2.7 V AV = 1 RL = 100 kΩ CL = 100 pF TA = 25°C 2 1 VO –1 V IN – Input Voltage – V 10 0 –3 –1 –4 2 3 4 5 6 7 8 9 –1 10 3 4 Figure 28 3 VIN 0 3 –1 IN VO V 1 20 10 5 15 0 10 –5 VO 5 V 4 V – Output Voltage – V O 1 15 VCC = 15 V AV = 1 RL = 100 kΩ CL = 100 pF TA = 25°C 25 2 – Input Voltage – V 5 6 30 4 VIN 5 LARGE SIGNAL FOLLOWER PULSE RESPONSE VCC = 5 V AV = 1 RL = 100 kΩ CL = 100 pF TA = 25°C 7 V – Output Voltage – V O 2 Figure 27 8 2 1 t – Time – ms LARGE SIGNAL FOLLOWER PULSE RESPONSE 6 0 t – Time – s – Input Voltage – V 1 IN 0 0 0 –5 –1 –1 0 1 2 3 4 5 6 –2 0 2 4 6 8 10 t – Time – ms t – Time – ms Figure 29 Figure 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12 14 16 11 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 TYPICAL CHARACTERISTICS SMALL SIGNAL FOLLOWER PULSE RESPONSE LARGE SIGNAL INVERTING PULSE RESPONSE 2.0 150 1.5 100 80 60 VO –150 40 20 1 VCC = 2.7 V AV = –1 RL = 100 kΩ CL = 100 pF TA = 25°C 0.5 0.0 –0.5 –1.0 VO –1.5 0 –20 –50 0 –2 –1 50 100 150 200 250 300 350 400 450 500 0 1 t – Time – µs 4 5 6 LARGE SIGNAL INVERTING PULSE RESPONSE LARGE SIGNAL INVERTING PULSE RESPONSE 4 12 2.0 3 10 2 8 1 6 0 VCC = 5 V AV = –1 RL = 100 kΩ CL = 100 pF TA = 25°C 0.0 –0.5 –1.0 IN –1.5 –1 –2.0 12 9 VIN 4 –3.0 0 VCC = 15 V AV = –1 RL = 100 kΩ CL = 100 pF TA = 25°C 2 0 –2 –4 –3 –6 –8 VO 6 3 IN 0.5 7 V 1.0 – Input Voltage – V VIN V – Output Voltage – V O 2.5 V V – Output Voltage – V O 3 Figure 32 –2.5 VO –10 –3.5 –12 –1 0 1 2 3 4 5 6 7 –5 20 200 0 100 –20 –100 30 35 IN –60 VCC = 2.7, 5, & 15 V All Channels RL = 100 kΩ CL = 100 pF VIN = 1 VPP VCC = 15 V –80 –100 VCC = 2.7, 5 V V VO –40 Crosstalk –dB 0 – Input Voltage – mV VCC = 2.7, 5, & 15 V AV = –1 RL = 100 kΩ CL = 100 pF TA = 25°C 25 CROSSTALK vs FREQUENCY –50 –100 –150 –200 15 Figure 34 150 0 10 Figure 33 VIN 50 5 t – Time – ms 200 100 0 t – Time – ms SMALL SIGNAL INVERTING PULSE RESPONSE VO – Output Voltage – mV 2 t – Time – ms Figure 31 1.5 12 0 –1 IN VCC = 2.7, 5, & 15 V AV = 1 RL = 100 kΩ CL = 100 pF TA = 25°C 120 2 1.0 V 0 –120 –140 0 200 400 600 800 1000 1200 t – Time – ms 100 1k f – Frequency –Hz Figure 35 Figure 36 POST OFFICE BOX 655303 – Input Voltage – V V – Output Voltage – mV O 140 3 VIN – Input Voltage – V 300 V – Output Voltage – V O VIN 160 V IN – Input Voltage – mV 180 10 • DALLAS, TEXAS 75265 10k TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION reverse battery protection The TLV2401/2/4 are protected against reverse battery voltage up to 18 V. When subjected to reverse battery condition the supply current is typically less than 100 nA at 25°C (inputs grounded and outputs open). This current is determined by the leakage of 6 Schottky diodes and will therefore increase as the ambient temperature increases. When subjected to reverse battery conditions and negative voltages applied to the inputs or outputs, the input ESD structure will turn on—this current should be limited to less than 10 mA. If the inputs or outputs are referred to ground, rather than midrail, no extra precautions need be taken. common-mode input range The TLV2401/2/4 has rail-to-rail input and outputs. For common-mode inputs from –0.1 V to VCC – 0.8 V a PNP differential pair will provide the gain. For inputs between VCC – 0.8 V and VCC, two NPN emitter followers buffering a second PNP differential pair provide the gain. This special combination of NPN/PNP differential pair enables the inputs to be taken 5 V above the rails, because as the inputs go above VCC, the NPNs switch from functioning as transistors to functioning as diodes. This will lead to an increase in input bias current. The second PNP differential pair continues to function normally as the inputs exceed VCC. The TLV2401/2/4 has a negative common-input range that exceeds ground by 100 mV. If the inputs are taken much below this, reduced open loop gain will be observed with the ultimate possibility of phase inversion. offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB– RG + – VI VO + RS ǒ ǒ ǓǓ ǒ ǒ ǓǓ IIB+ V OO + VIO 1 ) R R F G " IIB) RS 1 ) R R F G " IIB– RF Figure 37. Output Offset Voltage Model POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 38). RG RF – VO + VI R1 V O V I C1 ǒ Ǔǒ + 1 ) RRF G 1 f –3dB Ǔ 1 + 2pR1C1 ) sR1C1 1 Figure 38. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 RG RF RG = Figure 39. 2-Pole Low-Pass Sallen-Key Filter 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 –3dB + 2p1RC ( RF 1 2– Q ) TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION circuit layout considerations To achieve the levels of high performance of the TLV240x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. D D D D D Ground planes – It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. Short trace runs/compact part placements – Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. Surface-mount passive components – Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION general power dissipation considerations ǒ Ǔ For a given θJA, the maximum power dissipation is shown in Figure 40 and is calculated by the following formula: P Where: + D T –T MAX A q JA PD = Maximum power dissipation of THS240x IC (watts) TMAX = Absolute maximum junction temperature (150°C) TA = Free-ambient air temperature (°C) θJA = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 2 Maximum Power Dissipation – W 1.75 PDIP Package Low-K Test PCB θJA = 104°C/W 1.5 1.25 SOIC Package Low-K Test PCB θJA = 176°C/W TJ = 150°C MSOP Package Low-K Test PCB θJA = 260°C/W 1 0.75 0.5 0.25 SOT-23 Package Low-K Test PCB θJA = 324°C/W 0 –55 –40 –25 –10 5 20 35 50 65 80 95 110 125 TA – Free-Air Temperature – °C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 40. Maximum Power Dissipation vs Free-Air Temperature 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV2401, TLV2402, TLV2404 FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice . The Boyle macromodel (see Note 2) and subcircuit in Figure 41 are generated using the TLV240x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D D D D D D D D D D D D Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 3 99 VCC+ + egnd ree ro2 cee fb rp rc1 rc2 – c1 7 11 12 + 1 c2 vlim IN+ r2 + 9 6 – vc 2 8 + q1 q2 IN– – vb ga – ro1 gcm ioff 53 dp 13 14 re1 VOUT re2 91 10 iee VCC– 4 + vlp + 54 5 92 – hlim – ve dln 90 + dc – dlp – vln + de .subckt 240X_5V–X 1 2 3 4 5 * c1 11 12 9.8944E–12 c2 6 7 30.000E–12 cee 10 99 8.8738E–12 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 61.404E6 –1E3 1E3 61E6 –61E6 ga 6 0 11 12 1.0216E–6 gcm 0 6 10 99 10.216E–12 iee 10 4 dc 54.540E–9 ioff 0 6 dc 5e–12 hlim 90 0 vlim 1K q1 11 2 13 qx1 q2 12 1 14 qx2 r2 6 9 100.00E3 rc1 rc2 re1 re2 ree ro1 ro2 rp vb vc ve vlim vlp vln .model .model .model .model .ends 3 3 13 14 10 8 7 3 9 3 54 7 91 0 dx dy qx1 qx2 11 978.81E3 12 978.81E3 10 30.364E3 10 30.364E3 99 3.6670E9 5 10 99 10 4 1.4183E6 0 dc 0 53 dc .88315 4 dc .88315 8 dc 0 0 dc 540 92 dc 540 D(Is=800.00E–18) D(Is=800.00E–18 Rs=1m Cjo=10p) NPN(Is=800.00E–18 Bf=27.270E21) NPN(Is=800.0000E–18 Bf=27.270E21) Figure 41. Boyle Macromodels and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV2401CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2401IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2401IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2402IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2402IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2404AIN OBSOLETE PDIP N 14 Addendum-Page 2 Call TI Samples (Requires Login) TLV2402CD TBD (3) Call TI PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV2404CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404CPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2404INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2404IPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2404IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 3 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV2402 : • Automotive: TLV2402-Q1 NOTE: Qualified Version Definitions: • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 21-Sep-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TLV2401CDBVR SOT-23 DBV 5 3000 180.0 TLV2401CDBVT SOT-23 DBV 5 250 TLV2401CDR SOIC D 8 2500 TLV2401IDBVR SOT-23 DBV 5 TLV2401IDBVT SOT-23 DBV TLV2401IDR SOIC TLV2401IDR SOIC TLV2402CDGKR VSSOP B0 (mm) K0 (mm) P1 (mm) 9.0 3.15 3.2 1.4 4.0 180.0 9.0 3.15 3.2 1.4 330.0 12.4 6.4 5.2 2.1 3000 180.0 9.0 3.15 3.2 5 250 180.0 9.0 3.15 D 8 2500 330.0 12.4 D 8 2500 330.0 12.4 DGK 8 2500 330.0 W Pin1 (mm) Quadrant 8.0 Q3 4.0 8.0 Q3 8.0 12.0 Q1 1.4 4.0 8.0 Q3 3.2 1.4 4.0 8.0 Q3 6.4 5.2 2.1 8.0 12.0 Q1 6.4 5.2 2.1 8.0 12.0 Q1 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2402CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2402IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2402IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2404CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2404IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2404IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Sep-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2401CDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2401CDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2401CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2401IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2401IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2401IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2401IDR SOIC D 8 2500 367.0 367.0 35.0 TLV2402CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2402CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2402IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2402IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2404CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2404IDR SOIC D 14 2500 367.0 367.0 38.0 TLV2404IPWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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