TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN FEATURES 7 3 6 4 5 VDD OUTB REF AGND NC V DD 3 2 1 20 19 NC DIN NC 4 18 NC SCLK 5 17 OUTB NC 6 16 NC CS 7 15 REF NC 8 14 NC NC 10 11 12 13 AGND 9 NC Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices 8 2 FK PACKAGE (TOP VIEW) APPLICATIONS • • • • • 1 OUTA • • DIN SCLK CS OUTA NC • D, JG PACKAGE (TOP VIEW) Dual 12-Bit Voltage Output DAC Programmable Internal Reference Programmable Settling Time: – 1 µs in Fast Mode, – 3.5 µs in Slow Mode Compatible With TMS320 and SPI™ Serial Ports Differential Nonlinearity <0.5 LSB Typ Monotonic Over Temperature NC • • • DESCRIPTION The TLV5638 is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface allows glueless interface to TMS320, SPI™, QSPI™, and Microwire™ serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5638 simplifies overall system design. Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space in standard commercial, industrial, and automotive temperature ranges. It is also available in JG and FK packages in the military temperature range. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2004, Texas Instruments Incorporated TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS PACKAGE TA SOIC (D) CERAMIC DIP (JG) 20 PAD LCCC (FK) 0°C to 70°C TLV5638CD — — 40°C to 85°C TLV5638ID — — 40°C to 125°C TLV5638QD TLV5638QDR — — 55°C to 125°C — TLV5638MJG TLV5638MFK FUNCTIONAL BLOCK DIAGRAM REF AGND VDD PGA With Output Enable Voltage Bandgap Power-On Reset Power and Speed Control 2 2 2-Bit Control Latch x2 OUTA x2 OUTB DIN 12 SCLK CS Serial Interface and Control 12 12 Buffer 12 2 12-Bit DAC A Latch 12-Bit DAC B Latch 12 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 Terminal Functions TERMINAL I/O/P DESCRIPTION NAME NO. AGND 5 P Ground CS 3 I Chip select. Digital input active low, used to enable/disable inputs DIN 1 I Digital serial data input OUT A 4 O DAC A analog voltage output OUT B 7 O DAC B analog voltage output REF 6 I/O Analog reference voltage input/output SCLK 2 I Digital serial clock input VDD 8 P Positive power supply ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage (VDD to AGND) 7V Reference input voltage range -0.3 V to VDD + 0.3 V Digital input voltage range -0.3 V to VDD + 0.3 V Operating free-air temperature range, TA TLV5638C 0°C to 70°C TLV5638I -40°C to 85°C TLV5638Q -40°C to 125°C TLV5638M -55°C to 125°C Storage temperature range, Tstg -65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) 260°C Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE (1) PACKAGE TA≤ 25°C POWER RATING DERATING FACTOR ABOVE TA= 25°C (1) TA= 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 635 mW 5.08 mW/°C 407 mW 330 mW 127 mW FK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mW JG 1050 mW 8.40 mW/°C 672 mW 546 mW 210 mW This is the inverse of the traditional Junction-to-Ambient thermal Resistance (RθJA). Thermal Resistances are not production tested and are for informational purposes only. 3 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 RECOMMENDED OPERATING CONDITIONS Supply voltage, VDD MIN NOM MAX VDD = 5 V 4.5 5 5.5 V VDD = 3 V 2.7 3 3.3 V 2 (1) V 0.55 (1) Power on reset, POR High-level digital input voltage, VIH VDD = 2.7 V 2 VDD = 5.5 V 2.4 V VDD = 2.7 V Low-level digital input voltage, VIL VDD = 5.5 V UNIT 0.6 TLV5638C and TLV5638I 1 TLV5638Q and TLV5638M 0.8 V V Reference voltage, Vref to REF terminal VDD = 5 V (2) AGND 2.048 VDD-1.5 V Reference voltage, Vref to REF terminal VDD = 3 V (2) AGND 1.024 VDD-1.5 V Load resistance, RL 2 kΩ Load capacitance, CL 100 pF Clock frequency, fCLK 20 MHz Operating free-air temperature, TA (1) (2) TLV5638C 0 TLV5638I 40 70 85 TLV5638Q 40 125 TLV5638M 55 125 °C This parameter is not tested for Q and M suffix devices. Due to the x2 output buffer, a reference input voltage ≥ (VDD-0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used. ELECTRICAL CHARACTERISTICS over recommended operating conditions, Vref = 2.048 V, Vref= 1.024 V (unless otherwise noted) POWER SUPPLY PARAMETER TLV5638C, I TLV5638M TEST CONDITIONS MIN IDD Power supply current No load, All inputs = AGND or VDD, DAC latch = 0x800 Power-down supply current PSRR (1) (2) 4 Power supply rejection ratio Zero scale, Full scale, (1) (2) UNIT TYP MAX VDD= 5 V, Int. ref. Fast 4.3 7 Slow 2.2 3.6 VDD = 3 V, Int. ref. Fast 3.8 6.3 Slow 1.8 3.0 VDD = 5 V, Ext. ref. Fast 3.9 6.3 Slow 1.8 3.0 VDD = 3 V, Ext. ref. Fast 3.5 5.7 Slow 1.5 2.6 0.01 10 65 65 Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) EZS(VDDmin))/VDDmax] Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) EG(VDDmin))/VDDmax] mA mA mA mA µA dB TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS (Continued) over recommended operating conditions, Vref = 2.048 V, Vref= 1.024 V (unless otherwise noted) STATIC DAC SPECIFICATIONS PARAMETER TEST CONDITIONS MIN Resolution Integral nonlinearity, end point adjusted See DNL Differential nonlinearity See (2) EZS Zero-scale error (offset error at zero scale) See (3) EZSTC Zero-scale-error temperature coefficient See (4) EG Gain error See (5) EGTC Gain error temperature coefficient See INL TYP MAX 12 (1) UNIT bits C and I suffixes ±1.7 ±4 LSB Q and M suffixes ±1.7 ±6 LSB ±0.4 ±1 LSB ±24 mV 10 ppm/°C ±0.6 (6) 10 % full scale V ppm/°C OUTPUT SPECIFICATIONS VO Output voltage RL= 10 kΩ Output load regulation accuracy VO = 4.096 V, 2.048 V, RL= 2 kΩ 0 VDD-0.4 V ±0.25 % full scale V V REFERENCE PIN CONFIGURED AS OUTPUT (REF) Vref(OUTL) Low reference voltage Vref(OUTH) High reference voltage Iref(source) Output source current Iref(sink) Output sink current VDD > 4.75 V 1.003 1.024 1.045 2.027 2.048 2.069 1 -1 mA Load capacitance PSRR 100 Power supply rejection ratio V mA -65 pF dB REFERENCE PIN CONFIGURED AS INPUT (REF) VI Input voltage RI Input resistance CI Input capacitance 0 Reference input bandwidth REF = 0.2 Vpp + 1.024 V dc Reference feedthrough REF = 1 Vpp at 1.024 V dc (7) VDD-1.5 V 10 MΩ 5 pF Fast 1.3 MHz Slow 525 kHz -80 dB DIGITAL INPUTS IIH HIgh-level digital input current VI = VDD IIL Low-level digital input current VI = 0 V Ci Input capacitance (1) (2) (3) (4) (5) (6) (7) 1 -1 µA µA 8 pF The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) - EZS (Tmin)]/Vref× 106/(Tmax - Tmin). Gain error is the deviation from the ideal output (2Vref - 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. Gain temperature coefficient is given by: EG TC = [EG(Tmax) - EG (Tmin)]/Vref× 106/(Tmax - Tmin). Reference feedthrough is measured at the DAC output with an input code = 0x000. 5 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 ELECTRICAL CHARACTERISTICS (Continued) over recommended operating conditions, Vref = 2.048 V, Vref= 1.024 V (unless otherwise noted) ANALOG OUTPUT DYNAMIC PERFORMANCE PARAMETER TEST CONDITIONS ts(FS) Output settling time, full scale RL = 10 kΩ, CL = 100 pF, See (1) ts(CC) Output settling time, code to code RL = 10 kΩ, CL = 100 pF, See (2) SR Slew rate RL = 10 kΩ, CL = 100 pF, See (3) Glitch energy DIN = 0 to 1, FCLK = 100 kHz, CS = VDD SNR MIN 1 3 Slow 3.5 7 Fast 0.5 1.5 Slow 1 2 Fast 12 Slow 1.8 THD fs = 480 kSPS, fout = 1 kHz, RL = 10 kΩ, CL = 100 pF Total harmonic distortion (2) (3) 74 58 67 69 Spurious free dynamic range (1) 69 57 UNIT µs µs V/µs 5 Signal-to-noise ratio S/(N+D) Signal-to-noise + distortion TYP MAX Fast nV-s dB 57 72 Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. DIGITAL INPUT TIMING REQUIREMENTS MIN NOM MAX UNIT tsu(CS-CK) Setup time, CS low before first negative SCLK edge 10 ns tsu(C16-CS) Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns twH SCLK pulse width high 25 ns twL SCLK pulse width low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 10 ns th(D) Hold time, data held valid after SCLK falling edge 5 ns PARAMETER MEASURMENT INFORMATION twL SCLK X 1 2 tsu(D) DIN X D15 twH 3 4 5 15 X 16 th(D) D14 D13 D12 D1 D0 X tsu(C16-CS) tsu(CS-CK) CS Figure 1. Timing Diagram 6 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE POWER DOWN SUPPLY CURRENT vs TIME 4.5 2.4 4 2.2 I DD – Supply Current – mA I DD – Power Down Supply Current – mA 2.6 2 1.8 1.6 1.4 1.2 1 0.8 Fast Mode 3.5 3 2.5 2 Slow Mode 1.5 0.6 0.4 VDD = 5 V Vref = Int. 2 V Input Code = Full Scale (Both DACs) 1 0.2 0 0 10 20 30 40 50 t – Time – µs 60 70 0.5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TA – Free-Air Temperature – °C 80 Figure 2. Figure 3. SUPPLY CURRENT vs FREE-AIR TEMPERATURE OUTPUT VOLTAGE vs LOAD CURRENT 4.5 3.5 Fast Mode 3 2.5 2 Slow Mode 1.5 VDD = 3 V Vref = Int. 1 V Input Code = 4095 Fast Mode 2.062 VO – Output Voltage – V I DD – Supply Current – mA 4 2.064 VDD = 3 V Vref = Int. 1 V Input Code = Full Scale (Both DACs) 2.06 Slow Mode 2.058 2.056 2.054 2.052 1 0.5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TA – Free-Air Temperature – °C Figure 4. 2.05 0 0.5 1 1.5 2 2.5 3 3.5 4 Source Current – mA Figure 5. 7 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 3 4.128 VDD = 5 V Vref = Int. 2 V Input Code = 4095 Fast Mode 2.5 VO – Output Voltage – V VO – Output Voltage – V 4.126 VDD = 3 V Vref = Int. 1 V Input Code = 0 4.124 Slow Mode 4.122 4.12 4.118 Fast Mode 2 1.5 1 0.5 4.116 Slow Mode 0 4.114 0 0.5 1 1.5 2 2.5 3 3.5 0 4 Source Current – mA 0.5 1 1.5 Figure 6. THD+N – Total Harmonic Distortion and Noise – dB VDD = 5 V Vref = Int. 2 V Input Code = 0 VO – Output Voltage – V 4 3.5 Fast Mode 3 2.5 2 1.5 1 0.5 Slow Mode 0 0.5 1 1.5 2 2.5 Sink Current – mA Figure 8. 8 3 3.5 4 TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY 5 0 2.5 Figure 7. OUTPUT VOLTAGE vs LOAD CURRENT 4.5 2 Sink Current – mA 3 3.5 4 0 –10 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale –20 –30 –40 –50 –60 Slow Mode –70 Fast Mode –80 –90 –100 100 1000 10000 f – Frequency – Hz Figure 9. 100000 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs FREQUENCY 0 VDD = 5 V Vref = 1 V dc + 1 V p/p Sinewave Output Full Scale THD – Total Harmonic Distortion – dB –10 –20 –30 –40 –50 –60 –70 Slow Mode –80 Fast Mode –90 –100 100 1000 10000 100000 f – Frequency – Hz INL – Integral Nonlinearity Error – LSB Figure 10. INTEGRAL NONLINEARITY ERROR 4 3 2 1 0 –1 –2 –3 –4 0 1024 2048 3072 4096 DNL – Differential Nonlinearily Error – LSB Digital Code Figure 11. DIFFERENTIAL NONLINEARITY ERROR 1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 1024 2048 Digital Code 3072 4096 Figure 12. 9 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 APPLICATION INFORMATION GENERAL FUNCTION The TLV5638 is a dual 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power on reset initially puts the internal latches to a defined state (all bits zero). SERIAL INTERFACE A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI™, and Microwire™. TMS320 DSP FSX DX CLKX TLV5638 CS DIN SCLK SPI TLV5638 CS DIN SCLK I/O MOSI SCK Microwire I/O SO SK TLV5638 CS DIN SCLK Figure 13. Three-Wire Interface Notes on SPI™ and Microwire™: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to CS. If the word width is 8 bits (SPI™ and Microwire™), two write operations must be performed to program the TLV5638. After the write operation(s), the holding registers or the control register are updated automatically on the 16th positive clock edge. SERIAL CLOCK FREQUENCY AND UPDATE RATE The maximum serial clock frequency is given by: f sclkmax 1 20 MHz t whmin t wlmin The maximum update rate is: f updatemax 1 16 t whmin t wlmin 1.25 MHz Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5638 has to be considered, too. 10 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 APPLICATION INFORMATION (continued) DATA FORMAT The 16-bit data word for the TLV5638 consists of two parts: • Program bits (D15..D12) • New data (D11..D0) D15 D14 D13 D12 R1 SPD PWR R0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 12 Data bits SPD: Speed control bit 1 → fast mode 0 → slow mode PWR: Power control bit 1 → power down 0 → normal operation The following table lists the possible combination of the register select bits: REGISTERED SELECT BITS R1 R0 REGISTER 0 0 Write data to DAC B and BUFFER 0 1 Write data to BUFFER 1 0 Write data to DAC A and update DAC B with BUFFER content 1 1 Write data to control register The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected, then the 12 data bits determine the new DAC value: DATA BITS: DAC A, DAC B and BUFFER D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New DAC Value If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage: DATA BITS: CONTROL D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X X X REF1 REF0 REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage. REFERENCE BITS REF1 REF0 REFERENCE 0 0 External 0 1 1.024 V 1 0 2.048 V 1 1 External CAUTION: If external reference voltage is applied to the REF pin, external reference MUST be selected. 11 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 EXAMPLES OF OPERATION: 1. Set DAC A output, select fast mode, select internal reference at 2.048 V: a. Set reference voltage to 2.048 V (CONTROL register) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 b. Write new DAC A value and update DAC A output: D15 D14 D13 D12 1 1 0 0 D11 D10 D9 D8 New DAC A output value The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. 2. Set DAC B output, select fast mode, select external reference: a. Select external reference (CONTROL register): D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 b. Write new DAC B value to BUFFER and update DAC B output: D15 D14 D13 D12 0 1 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 New BUFFER content and DAC B output value The DAC A output is updated on the rising clock edge after D0 is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. 3. Set DAC A value, set DAC B value, update both simultaneously, select slow mode, select internal reference at 1.024 V: a. Set reference voltage to 1.024 V (CONTROL register) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 D9 D8 D7 b. Write data for DAC B to BUFFER: D15 D14 D13 D12 0 0 0 1 c. D11 D10 D6 D5 D4 D3 D2 D1 D0 D4 D3 D2 D1 D0 New DAC B value Write new DAC A value and update DAC A and B simultaneously: D15 D14 D13 D12 1 0 0 0 D11 D10 D9 D8 D7 D6 D5 New DAC A value Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled. To output data consecutively using the same DAC configuration, it is not necessary to program the CONTROL register again. 1. Set power-down mode: D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1 X X X X X X X X X X X X X X = Don't care 12 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 LINEARITY, OFFSET, AND GAIN ERROR USING SINGLE ENDED SUPPLIES When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 14. Output Voltage 0V Negative Offset DAC Code Figure 14. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. 13 TLV5638 www.ti.com SLAS225C – JUNE 1999 – REVISED JANUARY 2004 DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY Integral Nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Differential Nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. Zero-Scale Error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. Gain Error (EG) Gain error is the error in slope of the DAC transfer function. Total Harmonic Distortion (THD) THD is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. The value for THD is expressed in decibels. Signal-to-Noise Ratio + Distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. 14 PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE LCCC FK 20 1 TBD Call TI Call TI 5962-9957601QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI TLV5638CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638MFKB ACTIVE LCCC FK 20 1 TBD TLV5638MJGB ACTIVE CDIP JG 8 1 TBD TLV5638QD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638QDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638QDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV5638QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) POST-PLATE N / A for Pkg Type N / A for Pkg Type The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1 Samples (Requires Login) 5962-9957601Q2A A42 (3) PACKAGE OPTION ADDENDUM www.ti.com 27-Apr-2012 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF TLV5638, TLV5638M : • Catalog: TLV5638 • Enhanced Product: TLV5638-EP, TLV5638-EP • Military: TLV5638M NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV5638CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5638IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV5638QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5638CDR SOIC D 8 2500 367.0 367.0 35.0 TLV5638IDR SOIC D 8 2500 367.0 367.0 35.0 TLV5638QDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 0.063 (1,60) 0.015 (0,38) 4 0.065 (1,65) 0.045 (1,14) 0.310 (7,87) 0.290 (7,37) 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP1-T8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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