TLV717xx TLV717xxP www.ti.com SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 150-mA, Low-Dropout Regulator with Foldback Current Limit for Portable Devices Check for Samples: TLV717xx, TLV717xxP FEATURES DESCRIPTION • • • • The TLV717xx series of low-dropout (LDO) linear regulators are low quiescent current LDOs with excellent line and load transient performance and are designed for power-sensitive applications. These devices provide a typical accuracy of 0.5%. 1 2 • • • • Very Low Dropout: 215 mV at 150 mA Accuracy: 0.5% (typical) Low IQ: 35 µA Available in Fixed-Output Voltages: 1.2 V to 5.0 V(1) High PSRR: – 70 dB at 1 kHz – 50 dB at 1 MHz Stable with Effective Output Capacitance: 0.1 µF(2) Foldback Current Limit Package: 1-mm × 1-mm DQN (1) See the Package Option Addendum at the end of this document for a complete list of available voltage options. (2) See the Input and Output Capacitor Requirements section in the Application Information for more details. APPLICATIONS • • • Wireless Handsets, Smart Phones, PDAs MP3 Players Other Hand-Held Products TLV717xx 1-mm x 1-mm DQN (Bottom View) The TLV717xx series offer current foldback that throttles down the output current with a decrease in load resistance. The typical value at which current foldback initiates is 350 mA; the typical value of the output short current limit value is 40 mA. Furthermore, these devices are stable with an effective output capacitance of only 0.1 µF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices regulate to specified accuracy with no output load. The TLV717xx series is available in a 1-mm × 1-mm DQN package that makes them ideal for hand-held applications. The TLV717xxP provides an active pulldown circuit to quickly discharge output loads. Typical Application Circuit VIN IN IN GND OUT COUT VOUT 1 mF Ceramic TLV717xx Series On Off EN OUT CIN EN GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2012, Texas Instruments Incorporated TLV717xx TLV717xxP SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT TLV717xx(x)Pyyyz (1) XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 475 = 4.75 V). P is optional; devices with P have an LDO regulator with an active output discharge. YYY is the package designator. Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –25°C, unless otherwise noted. All voltages are with respect to GND. VALUE Voltage Current MIN MAX Input range, VIN –0.3 6.0 V Enable range, VEN –0.3 VIN + 0.3 V Output range, VOUT –0.3 6.0 V Maximum output, IOUT Internally limited Output short-circuit duration Indefinite Continuous total power dissipation, PDISS Temperature Electrostatic discharge (ESD) ratings (1) UNIT See Thermal Information table Junction range, TJ –55 +150 °C Storage junction range, Tstg –55 +150 °C 2000 V 500 V Human body model (HBM) Charged device model (CDM) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TLV717xx TLV717xxP THERMAL METRIC (1) DQN UNITS 4 PINS θJA Junction-to-ambient thermal resistance 393.3 θJC(top) Junction-to-case(top) thermal resistance 140.3 θJB Junction-to-board thermal resistance 330 ψJT Junction-to-top characterization parameter 6.5 ψJB Junction-to-board characterization parameter 329 θJC(bottom) Junction-to-case(bottom) thermal resistance 147.5 (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP TLV717xx TLV717xxP www.ti.com SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted. TLV717 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range 1.7 5.5 V VOUT Output voltage range 1.2 5.0 V IOUT Output current 150 TA = +25°C DC output accuracy mA 0.5 VOUT ≥ 1.2 V, –40°C ≤ TA ≤ +85°C –1.5 VOUT ≤ 1.2 V 25 mV 5 mV 10 20 mV 1.2 V ≤ VOUT < 1.5 V 330 500 mV 1.5 V ≤ VOUT < 1.8 V 330 450 mV 1.8 V ≤ VOUT ≤ 5.0 V 215 350 mV 35 55 µA 0.1 0.5 µA Line regulation VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V ΔVO/IOUT Load regulation 0 mA ≤ IOUT ≤ 150 mA VDO Dropout voltage IGND Ground pin current IOUT = 0 mA ISHDN Shutdown current VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V PSRR Power-supply rejection ratio VIN = 3.3 V, VOUT = 2.8 V, IOUT = 30 mA % 1 ΔVO/VIN VIN = 0.98 × VOUT(NOM), IOUT = 150 mA % +1.5 f = 10 Hz 70 dB f = 100 Hz 70 dB f = 1 kHz 65 dB f = 10 kHz 60 dB f = 100 kHz 43 dB 55 µVRMS VNOISE Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA tSTR Startup time COUT = 1.0 μF, IOUT = 150 mA ISC Short current limit VIN = min (VOUT(NOM) + 1 V, 5.5 V), VOUT = 0 V VHI Enable high (enabled) 0.9 VIN VLO Enable low (disabled) 0 0.4 IEN EN pin current RPULLDOWN Pull-down resistor (TLV717xxP only) UVLO Undervoltage lockout EN = 5.5 V VIN rising Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP 100 µs 40 mA V V 0.01 µA 120 Ω 1.6 V Submit Documentation Feedback 3 TLV717xx TLV717xxP SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com PIN CONFIGURATION DQN PACKAGE 1-mm × 1-mm TBD (Top View) IN EN 4 3 1 2 OUT GND DQN PACKAGE 1-mm × 1-mm TBD (Bottom View) EN IN 3 4 2 1 GND OUT PIN DESCRIPTIONS PIN NAME 4 NO. DESCRIPTION EN 3 Enable pin. Driving EN over 1.2 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode. GND 2 Ground pin IN 4 Input pin. A small capacitor is recommended from this pin to ground to assure stability. See the Input and Output Capacitor Requirements section in the Application Information for more details. OUT 1 Regulated output voltage pin. A small 1-μF ceramic capacitor is recommended from this pin to ground to assure stability. See the Input and Output Capacitor Requirements section in the Application Information for more details. Thermal pad — It is recommended to connect this pin to GND for improved thermal performance. Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP TLV717xx TLV717xxP www.ti.com SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 FUNCTIONAL BLOCK DIAGRAMS IN OUT Foldback Current Limit UVLO EN Bandgap LOGIC TLV717xx GND Figure 1. TLV717xx Block Diagram IN OUT Foldback Current Limit UVLO EN 120 W Bandgap LOGIC TLV717xxP GND Figure 2. TLV717xxP Block Diagram Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP Submit Documentation Feedback 5 TLV717xx TLV717xxP SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted. LOAD REGULATION LINE REGULATION 2.9 2.88 2.88 2.86 2.86 Output Voltage (V) 2.9 VOUT (V) 2.84 2.82 2.8 2.78 2.76 +85°C +25°C -40°C 2.74 2.72 2.84 2.82 2.8 2.78 2.76 +85°C +25°C -40°C 2.74 2.72 2.7 2.7 20 0 40 60 80 100 120 140 160 180 200 IOUT (mA) 2.9 3.5 3 4 5.5 G002 Figure 4. LINE REGULATION DROPOUT VOLTAGE vs FIXED OUTPUT VOLTAGE VERSIONS 0.3 Dropout Voltage (V) 2.84 2.82 2.8 2.78 2.76 +85°C +25°C -40°C 2.74 2.72 0.25 0.2 0.15 +85°C +25°C -40°C 0.1 2.7 3.5 3 4 4.5 5 5.5 Input Voltage (V) 1.5 2 2.5 3 3.5 4 5 4.5 Fixed Output Voltage Versions (V) G003 Figure 5. G004 Figure 6. DROPOUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs TEMPERATURE 0.3 2.838 2.828 Output Voltage (V) 0.25 Dropout Voltage (V) 5 Figure 3. 2.86 0.2 0.15 0.1 0 2.818 2.808 2.798 2.788 2.778 +85°C +25°C -40°C 0.05 10 mA 150 mA 2.768 2.758 50 60 70 80 90 100 110 120 130 140 150 Output Current (mA) -40 -27.5 -15 -2.5 Submit Documentation Feedback 10 22.5 35 Temperature (°C) G005 Figure 7. 6 4.5 Input Voltage (V) G001 IOUT = 150 mA 2.88 Output Voltage (V) IOUT = 10 mA 47.5 60 72.5 85 G006 Figure 8. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP TLV717xx TLV717xxP www.ti.com SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted. GROUND PIN CURRENT vs INPUT VOLTAGE 45 Ground Pin Current (mA) IOUT = 0 mA 40 Ground Pin Current (mA) GROUND PIN CURRENT vs OUTPUT CURRENT 3000 35 30 25 20 15 10 +85°C +25°C -40°C 5 2500 2000 1500 1000 +85°C +25°C -40°C 500 0 0 3 3.5 4 4.5 5.5 5 Input Voltage (V) 0 25 50 G007 Figure 9. G008 2.5 35 30 25 20 15 10 2 1.5 1 +85°C +25°C -40°C 0.5 5 0 0 -40 -27.5 -15 -2.5 10 22.5 35 47.5 60 85 72.5 Temperature (°C) 0 50 100 150 200 250 300 350 Output Current (mA) G009 G010 Figure 11. Figure 12. TLV71728 PSRR vs FREQUENCY TLV71728 PSRR vs FREQUENCY 80 80 Power-Supply Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 150 OUTPUT VOLTAGE vs OUTPUT CURRENT Output Voltage (V) Ground Pin Current (mA) 125 3 IOUT = 0 mA 40 100 Figure 10. GROUND PIN CURRENT vs TEMPERATURE 45 75 Output Current (mA) 70 60 50 40 30 20 IOUT = 30 mA IOUT = 150 mA 10 VIN - VOUT = 0.5 V 0 70 60 50 40 30 20 IOUT = 30 mA IOUT = 150 mA 10 VIN - VOUT = 1 V 0 10 100 1k 10k 100k Frequency (Hz) 1M 10M 10 100 G011 Figure 13. 1k 10k 100k 1M 10M Frequency (Hz) G012 Figure 14. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP Submit Documentation Feedback 7 TLV717xx TLV717xxP SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At operating temperature range (TA = –40°C to +85°C), TA = +25°C, VIN = VOUT(NOM) + 0.5 V or 1.7 V (whichever is greater), IOUT = 10 mA, VEN = VIN, and COUT = 1 µF, unless otherwise noted. PSRR vs INPUT VOLTAGE OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 80 Noise Spectral Density (mV/ÖHz) Power-Supply Rejection Ratio (dB) 90 70 60 50 40 30 1 kHz 10 kHz 100 kHz 20 10 1 0.1 0.01 1.2 2.8 5 0 0 3.6 3.7 3.8 3.9 4 Input Voltage (V) 4.1 4.2 4.3 10 100 Figure 15. 8 Submit Documentation Feedback 1k 10k 100k Frequency (Hz) G013 1M 10M G014 Figure 16. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP TLV717xx TLV717xxP www.ti.com SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 APPLICATION INFORMATION The TLV717xx belongs to a new family of next-generation value low-dropout (LDO) regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for RF portable applications. This family of regulators offers current foldback. Device operating junction temperature is –40°C to +125°C. INPUT AND OUTPUT CAPACITOR REQUIREMENTS X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. The TLV717xx is designed to be stable with an effective capacitance of 0.1 µF or larger at the output, though a 1-µF ceramic capacitor is recommended for typical applications. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 µF. This effective capacitance refers to the capacitance that the LDO detects under operating bias voltage and temperature conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of cheaper dielectrics, this capability of being stable with 0.1-µF effective capacitance also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications. Note that using a 0.1-µF rated capacitor at the LDO output does not ensure stability because the effective capacitance under the specified operating conditions would be less than 0.1 µF. Maximum ESR should be less than 200 mΩ. Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to 1.0-µF, low ESR capacitor across the IN and GND pins of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast, rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-µF input capacitor may be necessary to ensure stability. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance (such as PSRR, output noise, and transient response), it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the output capacitor ground connection should be connected directly to the device GND pin. High ESR capacitors may degrade PSRR performance. INTERNAL CURRENT LIMIT The TLV717xx has an internal foldback current limit that helps to protect the regulator during fault conditions. The current supplied by the device is gradually throttled down as the output voltage decreases. When the output is shorted, the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in current limit, and is VOUT = ILIMIT × RLOAD. The advantage of foldback current limit is that the ILIMIT value is less than the fixed current limit. Therefore, the power that the PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] is much less. The TLV717xx PMOS pass element has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. SHUTDOWN The enable pin (EN) is active high. The device is enabled when the voltage at the EN pin goes above 0.9 V. This relatively lower voltage value required to turn the LDO on can be exploited to power the LDO with a GPIO of recent processors whose GPIO logic 1 voltage level is lower than traditional microcontrollers. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the IN pin. Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP Submit Documentation Feedback 9 TLV717xx TLV717xxP SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 www.ti.com DROPOUT VOLTAGE The TLV717xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but increases the duration of the transient response. UNDERVOLTAGE LOCKOUT (UVLO) The TLV717xx uses an undervoltage lockout circuit (UVLO = 1.6 V) to keep the output shut off until the internal circuitry operates properly. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to ambient air. Performance data for JEDEC-low and high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition, plated through-holes to heat-dissipating layers also improves heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 1. PD = (VIN – VOUT) × IOUT 10 Submit Documentation Feedback (1) Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP TLV717xx TLV717xxP www.ti.com SBVS176A – OCTOBER 2011 – REVISED APRIL 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October 2011) to Revision A • Page Changed document status from Product Preview to Production Data ................................................................................. 1 Copyright © 2011–2012, Texas Instruments Incorporated Product Folder Link(s): TLV717xx TLV717xxP Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 6-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71712PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71713PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71713PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71715PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71715PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71718PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71718PDBVT PREVIEW SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71718PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71718PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71725PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71725PDBVT PREVIEW SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71725PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71725PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV717285PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV717285PQNR PREVIEW X2SON DQN 5 3000 TBD TLV71728PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) Addendum-Page 1 Samples (Requires Login) TLV71712PDQNR Call TI (3) Call TI CU NIPDAU Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 6-Jun-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV71728PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71730PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71730PDBVT PREVIEW SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71730PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71730PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71733PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71733PDBVT PREVIEW SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71733PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71733PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71736PDBVR PREVIEW SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71736PDBVT PREVIEW SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71736PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV71736PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 6-Jun-2012 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV71712PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71712PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71712PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71712PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71713PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71713PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71713PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71713PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71715PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71715PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71715PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71715PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71718PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71718PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71718PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71718PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71725PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71725PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV71725PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71725PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV717285PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV717285PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71728PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71728PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71728PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71728PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71730PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71730PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71730PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71730PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71733PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71733PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71733PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV71733PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71736PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV71736PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 *All dimensions are nominal Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2012 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV71712PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71712PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV71712PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV71712PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71713PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV71713PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71713PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV71713PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71715PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71715PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV71715PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71715PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV71718PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71718PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV71718PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71718PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV71725PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV71725PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71725PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71725PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV717285PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV717285PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71728PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71728PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV71728PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71728PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV71730PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71730PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV71730PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71730PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV71733PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV71733PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71733PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV71733PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV71736PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV71736PDQNT X2SON DQN 4 250 180.0 180.0 30.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at 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