TOSHIBA TMP86CH22UG

8 Bit Microcontroller
TLCS-870/C Series
TMP86CH22UG
TMP86CH22UG
The information contained herein is subject to change without notice. 021023 _ D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
The Toshiba products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic
appliances, etc.).
These Toshiba products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended
Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B
The products described in this document shall not be used or embedded to any downstream products
of which manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of TOSHIBA or others. 021023_C
The products described in this document may include products subject to the foreign exchange and
foreign trade laws. 021023_F
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
© 2006 TOSHIBA CORPORATION
All Rights Reserved
Page 2
Revision History
Date
Revision
2005/12/8
1
First Release
2006/9/8
2
Contents Revised
Table of Contents
TMP86CH22UG
1.1
1.2
1.3
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
4
5
2. Operational Description
2.1
CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
2.1.2
2.1.3
Memory Address Map............................................................................................................................... 9
Program Memory (MaskROM).................................................................................................................. 9
Data Memory (RAM) ............................................................................................................................... 10
2.2.1
2.2.2
Clock Generator...................................................................................................................................... 10
Timing Generator .................................................................................................................................... 12
2.2
System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2.1
2.2.2.2
Configuration of timing generator
Machine cycle
2.2.3.1
2.2.3.2
2.2.3.3
Single-clock mode
Dual-clock mode
STOP mode
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
STOP mode
IDLE1/2 mode and SLEEP1/2 mode
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
SLOW mode
2.2.3
2.2.4
2.3
Operation Mode Control Circuit .............................................................................................................. 13
Operating Mode Control ......................................................................................................................... 18
Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.1
2.3.2
2.3.3
2.3.4
External Reset Input ............................................................................................................................... 31
Address trap reset .................................................................................................................................. 32
Watchdog timer reset.............................................................................................................................. 32
System clock reset.................................................................................................................................. 32
3. Interrupt Control Circuit
3.1
3.2
Interrupt latches (IL19 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.1
3.2.2
Interrupt master enable flag (IMF) .......................................................................................................... 36
Individual interrupt enable flags (EF19 to EF4) ...................................................................................... 37
3.3.1
3.3.2
Interrupt acceptance processing is packaged as follows........................................................................ 39
Saving/restoring general-purpose registers ............................................................................................ 40
Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.2.1
3.3.2.2
Using PUSH and POP instructions
Using data transfer instructions
3.3.3
Interrupt return ........................................................................................................................................ 41
3.4.1
3.4.2
Address error detection .......................................................................................................................... 42
Debugging .............................................................................................................................................. 42
3.4
Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
i
3.5
3.6
3.7
Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4. Special Function Register (SFR)
4.1
4.2
SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5. I/O Ports
5.1
5.2
5.3
5.4
5.5
5.6
Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P3 (P37, P34 to P33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P6 (P64 to P61) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P7 (P76 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
53
54
56
58
60
6. Watchdog Timer (WDT)
6.1
6.2
Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Malfunction Detection Methods Using the Watchdog Timer ...................................................................
Watchdog Timer Enable .........................................................................................................................
Watchdog Timer Disable ........................................................................................................................
Watchdog Timer Interrupt (INTWDT)......................................................................................................
Watchdog Timer Reset ...........................................................................................................................
64
65
66
66
67
6.3.1
6.3.2
6.3.3
6.3.4
Selection of Address Trap in Internal RAM (ATAS) ................................................................................
Selection of Operation at Address Trap (ATOUT) ..................................................................................
Address Trap Interrupt (INTATRAP).......................................................................................................
Address Trap Reset ................................................................................................................................
68
68
68
69
6.3
Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7. Time Base Timer (TBT)
7.1
Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.1.1
7.1.2
7.1.3
Configuration .......................................................................................................................................... 71
Control .................................................................................................................................................... 71
Function .................................................................................................................................................. 72
7.2.1
7.2.2
Configuration .......................................................................................................................................... 73
Control .................................................................................................................................................... 73
7.2
Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8. 18-Bit Timer/Counter (TC1)
8.1
8.2
8.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.3.1
ii
Timer mode............................................................................................................................................. 79
8.3.2
8.3.3
8.3.4
Event Counter mode ............................................................................................................................... 80
Pulse Width Measurement mode............................................................................................................ 81
Frequency Measurement mode .............................................................................................................. 82
9. 8-Bit TimerCounter (TC5, TC6)
9.1
9.2
9.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
8-Bit Timer Mode (TC5 and 6) ................................................................................................................ 91
8-Bit Event Counter Mode (TC5, 6) ........................................................................................................ 92
8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)..................................................................... 92
8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6).................................................................. 95
16-Bit Timer Mode (TC5 and 6) .............................................................................................................. 97
16-Bit Event Counter Mode (TC5 and 6) ................................................................................................ 98
16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6).......................................................... 98
16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) ............................................. 101
Warm-Up Counter Mode....................................................................................................................... 103
9.3.9.1
9.3.9.2
Low-Frequency Warm-up Counter Mode
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
High-Frequency Warm-Up Counter Mode
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)
10. Real-Time Clock
10.1
10.2
10.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Control of the RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11. Asynchronous Serial interface (UART )
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8.1
11.8.2
Data Transmit Operation .................................................................................................................... 112
Data Receive Operation ..................................................................................................................... 112
11.9.1
11.9.2
11.9.3
11.9.4
11.9.5
11.9.6
Parity Error..........................................................................................................................................
Framing Error......................................................................................................................................
Overrun Error ......................................................................................................................................
Receive Data Buffer Full.....................................................................................................................
Transmit Data Buffer Empty ...............................................................................................................
Transmit End Flag ..............................................................................................................................
11.9
107
108
110
111
111
112
112
112
Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
113
113
113
114
114
115
12. Synchronous Serial Interface (SIO)
12.1
12.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
iii
12.3
Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.3.1
Internal clock
External clock
12.3.2.1
12.3.2.2
Leading edge
Trailing edge
12.3.2
12.4
12.5
12.6
Clock source ....................................................................................................................................... 119
12.3.1.1
12.3.1.2
Shift edge............................................................................................................................................ 121
Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.6.1
12.6.2
12.6.3
4-bit and 8-bit transfer modes ............................................................................................................. 122
4-bit and 8-bit receive modes ............................................................................................................. 124
8-bit transfer / receive mode ............................................................................................................... 125
13. 8-Bit AD Converter (ADC)
13.1
13.2
13.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.3.1
13.3.2
13.3.3
13.3.4
AD Conveter Operation ......................................................................................................................
AD Converter Operation .....................................................................................................................
STOP and SLOW Mode during AD Conversion .................................................................................
Analog Input Voltage and AD Conversion Result ...............................................................................
130
130
131
132
13.4.1
13.4.2
13.4.3
13.4.4
Restrictions for AD Conversion interrupt (INTADC) usage .................................................................
Analog input pin voltage range ...........................................................................................................
Analog input shared pins ....................................................................................................................
Noise countermeasure........................................................................................................................
133
133
133
133
13.4
Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
14. Key-on Wakeup (KWU)
14.1
14.2
14.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
15. LCD Driver
15.1
15.2
15.2.1
15.2.2
15.2.3
15.2.4
LCD driving methods ..........................................................................................................................
Frame frequency.................................................................................................................................
LCD drive voltage ...............................................................................................................................
Adjusting the LCD panel drive capability ............................................................................................
15.3.1
15.3.2
Display data setting ............................................................................................................................ 142
Blanking .............................................................................................................................................. 142
15.4.1
15.4.2
15.4.3
Initial setting ........................................................................................................................................ 143
Store of display data ........................................................................................................................... 143
Example of LCD driver output............................................................................................................. 145
15.3
15.4
16.
iv
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
139
140
141
141
LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Input/Output Circuit
16.1
16.2
Control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
17. Electrical Characteristics
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCD Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Counter 1 input (ECIN) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
155
156
157
158
159
160
161
162
162
18. Package Dimension
This is a technical document that describes the operating functions and electrical
specifications of the 8-bit microcontroller series TLCS-870/C (LSI).
v
vi
TMP86CH22UG
CMOS 8-Bit Microcontroller
TMP86CH22UG
Product No.
ROM
(MaskROM)
RAM
Package
OTP MCU
Emulation Chip
TMP86CH22UG
16384
bytes
512
bytes
P-LQFP44-1010-0.80B
TMP86PH22UG
TMP86C923XB
1.1 Features
1. 8-bit single chip microcomputer TLCS-870/C series
- Instruction execution time :
0.25 µs (at 16 MHz)
122 µs (at 32.768 kHz)
- 132 types & 731 basic instructions
2. 18interrupt sources (External : 5 Internal : 13)
3. Input / Output ports (I/O : 32 pins
Output : 1 pin)
Large current output: 3pins (Typ. 20mA), LED direct drive
4. Watchdog Timer
5. Prescaler
- Time base timer
- Divider output function
6. 18-bit Timer/Counter : 1ch
- Timer Mode
- Event Counter Mode
- Pulse Width Measurement Mode
- Frequency Measurement Mode
7. 8-bit timer counter : 2 ch
- Timer, Event counter, Programmable divider output (PDO),
Pulse width modulation (PWM) output,
060116EBP
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's
own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or
sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C
• The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance/Handling Precautions. 030619_S
Page 1
1.1 Features
TMP86CH22UG
Programmable pulse generation (PPG) modes
8. 8-bit UART : 1 ch
9. 8-bit SIO: 1 ch
10. 8-bit successive approximation type AD converter (with sample hold)
Analog inputs: 4ch
11. Key-on wakeup : 1 ch
12. LCD driver/controller
- LCD direct drive capability (MAX 23 seg × 4 com)
- 1/4,1/3,1/2duties or static drive are programmably selectable
13. Clock operation
Single clock mode
Dual clock mode
14. Low power consumption operation
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
stop.)
SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
oscillate.)
IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interruputs(CPU restarts).
IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts).
SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts).
SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock.
interruput.
15. Wide operation voltage:
4.5 V to 5.5 V at 16MHz /32.768 kHz
2.7 V to 5.5 V at 8 MHz /32.768 kHz
1.8 V to 5.5 V at 4.2MHz /32.768 kHz
Page 2
Release by
TMP86CH22UG
RESET
22
21
20
19
18
17
16
15
14
13
12
P50(SEG23)
P17(SEG24/SCK)
P16(SEG25/SO)
P15(SEG26/SI)
P14(SEG27/INT3)
P13(SEG28/INT2)
P12(SEG29/INT1)
P11(SEG30/TXD)
P10(SEG31/RXD)
P64(AIN4/STOP2)
P63(AIN3/INT0)
(INT5/STOP) P20
(ECIN/AIN1) P61
(ECNT/AIN2) P62
1
2
3
4
5
6
7
8
9
10
11
34
35
36
37
38
39
40
41
42
43
44
VSS
XIN
XOUT
TEST
VDD
(XTIN) P21
(XTOUT) P22
(SEG11) P74
(SEG10) P75
(SEG9) P76
COM3
COM2
COM1
COM0
VLC
(PDO6/PWM6/PPG6/TC6) P33
(PDO5/PWM5/TC5) P34
(DVO) P37
33
32
31
30
29
28
27
26
25
24
23
P73 (SEG12)
P72 (SEG13)
P71 (SEG14)
P70 (SEG15)
P57 (SEG16)
P56 (SEG17)
P55 (SEG18)
P54 (SEG19)
P53 (SEG20)
P52 (SEG21)
P51 (SEG22)
1.2 Pin Assignment
Figure 1-1 Pin Assignment
Page 3
1.3 Block Diagram
TMP86CH22UG
1.3 Block Diagram
Figure 1-2 Block Diagram
Page 4
TMP86CH22UG
1.4 Pin Names and Functions
Table 1-1 Pin Names and Functions(1/3)
Pin Name
Pin Number
Input/Output
Functions
21
IO
O
IO
PORT17
LCD segment output 24
Serial Clock I/O
P16
SEG25
SO
20
IO
O
O
PORT16
LCD segment output 25
Serial Data Output
P15
SEG26
SI
19
IO
O
I
PORT15
LCD segment output 26
Serial Data Input
P14
SEG27
INT3
18
IO
O
I
PORT14
LCD segment output 27
External interrupt 3 input
P13
SEG28
INT2
17
IO
O
I
PORT13
LCD segment output 28
External interrupt 2 input
P12
SEG29
INT1
16
IO
O
I
PORT12
LCD segment output 29
External interrupt 1 input
P11
SEG30
TXD
15
IO
O
I
PORT11
LCD segment output 30
UART data output
P10
SEG31
RXD
14
IO
O
I
PORT10
LCD segment output 31
UART data input
P22
XTOUT
7
IO
O
PORT22
Resonator connecting pins(32.768kHz) for inputting external
clock
P21
XTIN
6
IO
I
PORT21
Resonator connecting pins(32.768kHz) for inputting external
clock
9
IO
I
I
PORT20
STOP mode release signal input
External interrupt 5 input
44
O
O
PORT37
Divider Output
43
IO
I
O
PORT34
TC5 input
PDO5/PWM5 output
42
IO
I
O
PORT33
TC6 input
PDO6/PWM6/PPG6 output
P57
SEG16
29
IO
O
PORT57
LCD segment output 16
P56
SEG17
28
IO
O
PORT56
LCD segment output 17
P55
SEG18
27
IO
O
PORT55
LCD segment output 18
P17
SEG24
SCK
P20
STOP
INT5
P37
DVO
P34
TC5
PDO5/PWM5
P33
TC6
PDO6/PWM6/PPG6
Page 5
1.4 Pin Names and Functions
TMP86CH22UG
Table 1-1 Pin Names and Functions(2/3)
Pin Name
Pin Number
Input/Output
Functions
P54
SEG19
26
IO
O
PORT54
LCD segment output 19
P53
SEG20
25
IO
O
PORT53
LCD segment output 20
P52
SEG21
24
IO
O
PORT52
LCD segment output 21
P51
SEG22
23
IO
O
PORT51
LCD segment output 22
P50
SEG23
22
IO
O
PORT50
LCD segment output 23
P64
AIN4
STOP2
13
IO
I
I
PORT64
AD converter analog input 4
STOP2 input
12
IO
I
I
PORT63
AD converter analog input 3
External interrupt 0 input
P62
AIN2
ECNT
11
IO
I
I
PORT62
AD converter analog input 2
ECNT input
P61
AIN1
ECIN
10
IO
I
I
PORT61
AD converter analog input 1
ECIN input
P76
SEG9
36
IO
O
PORT76
LCD segment output 9
P75
SEG10
35
IO
O
PORT75
LCD segment output 10
P74
SEG11
34
IO
O
PORT74
LCD segment output 11
P73
SEG12
33
IO
O
PORT73
LCD segment output 12
P72
SEG13
32
IO
I
PORT72
LCD segment output 13
P71
SEG14
31
IO
O
PORT71
LCD segment output 14
P70
SEG15
30
IO
O
PORT70
LCD segment output 15
COM3
37
O
LCD common output 3
COM2
38
O
LCD common output 2
COM1
39
O
LCD common output 1
COM0
40
O
LCD common output 0
XIN
2
I
P63
AIN3
INT0
Page 6
Resonator connecting pins for high-frequency clock
TMP86CH22UG
Table 1-1 Pin Names and Functions(3/3)
Pin Name
Pin Number
Input/Output
Functions
XOUT
3
O
RESET
8
I
Reset signal
TEST
4
I
Test pin for out-going test. Normally, be fixed to low.
VDD
5
I
+5V
VSS
1
I
0(GND)
Page 7
Resonator connecting pins for high-frequency clock
1.4 Pin Names and Functions
TMP86CH22UG
Page 8
TMP86CH22UG
2. Operational Description
2.1 CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1
Memory Address Map
The TMP86CH22UG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special
function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the
memory address map.
0000H
SFR
SFR:
64 bytes
003FH
0040H
512
bytes
RAM
RAM:
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
023FH
0F80H
DBR:
128
bytes
DBR
TMP86CH22UG
0FFFH
C000H
MaskROM:
Data buffer register includes:
Peripheral control registers
Peripheral status registers
LCD display memory
Program memory
16384
bytes
MaskROM
FFB0H
Vector table for interrupts
(16 bytes)
FFBFH
FFC0H
Vector table for vector call instructions
(32 bytes)
FFDFH
FFE0H
Vector table for interrupts
FFFFH
(32 bytes)
Figure 2-1 Memory Address Map
2.1.2
Program Memory (MaskROM)
The TMP86CH22UG has a 16384 bytes (Address C000H to FFFFH) of program memory (MaskROM ).
Page 9
2. Operational Description
2.2 System Clock Controller
2.1.3
TMP86CH22UG
Data Memory (RAM)
The TMP86CH22UG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H
to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available
against such an area.
The data memory contents become unstable when the power supply is turned on; therefore, the data memory
should be initialized by an initialization routine.
Example :Clears RAM to “00H”. (TMP86CH22UG)
SRAMCLR:
LD
HL, 0040H
; Start address setup
LD
A, H
; Initial value (00H) setup
LD
BC, 01FFH
LD
(HL), A
INC
HL
DEC
BC
JRS
F, SRAMCLR
2.2 System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a standby controller.
Timing generator control register
TBTCR
0036H
Clock
generator
XIN
fc
High-frequency
clock oscillator
Timing
generator
XOUT
Standby controller
0038H
XTIN
Low-frequency
clock oscillator
SYSCR1
fs
System clocks
0039H
SYSCR2
System control registers
XTOUT
Clock generator control
Figure 2-2 System Colck Control
2.2.1
Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied to the CPU core
and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the
low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power
operation based on the low-frequency clock.
The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator
between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also
possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.
Page 10
TMP86CH22UG
Low-frequency clock
High-frequency clock
XIN
XOUT
XIN
XOUT
XTIN
XTOUT
(Open)
(a) Crystal/Ceramic
resonator
XTIN
XTOUT
(Open)
(c) Crystal
(b) External oscillator
(d) External oscillator
Figure 2-3 Examples of Resonator Connection
Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse
which the fixed frequency is outputted to the port by the program.
The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance.
Page 11
2. Operational Description
2.2 System Clock Controller
2.2.2
TMP86CH22UG
Timing Generator
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
1. Generation of main system clock
2. Generation of divider output (DVO) pulses
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
7. LCD
2.2.2.1
Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
and machine cycle counters.
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
fc or fs
Main system clock generator
Machine cycle counters
SYSCK
DV7CK
High-frequency
clock fc
Low-frequency
clock fs
1 2
fc/4
S
A
Divider
Y
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
B
Multiplexer
S
B0
B1
A0 Y0
A1 Y1
Multiplexer
Warm-up
controller
Watchdog
timer
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
Figure 2-4 Configuration of Timing Generator
Page 12
TMP86CH22UG
Timing Generator Control Register
TBTCR
(0036H)
7
6
(DVOEN)
5
(DVOCK)
DV7CK
4
3
DV7CK
(TBTEN)
Selection of input to the 7th stage
of the divider
2
1
0
(TBTCK)
(Initial value: 0000 0000)
0: fc/28 [Hz]
1: fs
R/W
Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after
release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
2.2.2.2
Machine cycle
Instruction execution and peripheral hardware operation are synchronized with the main system clock.
The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
1/fc or 1/fs [s]
Main system clock
State
S0
S1
S2
S3
S0
S1
S2
S3
Machine cycle
Figure 2-5 Machine Cycle
2.2.3
Operation Mode Control Circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). Figure 2-6 shows the operating mode transition diagram.
2.2.3.1
Single-clock mode
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].
(1)
NORMAL1 mode
In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.
The TMP86CH22UG is placed in this mode after reset.
Page 13
2. Operational Description
2.2 System Clock Controller
TMP86CH22UG
(2)
IDLE1 mode
In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are
halted; however on-chip peripherals remain active (Operate using the high-frequency clock).
IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1
mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF
(Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance
of the interrupt, and the operation will return to normal after the interrupt service is completed. When
the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the
IDLE1 mode start instruction.
(3)
IDLE0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.
This mode is enabled by SYSCR2<TGHALT> = "1".
When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back
again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =
“1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.
2.2.3.2
Dual-clock mode
Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and
P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the
high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in
SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and
4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.
The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program.
(1)
NORMAL2 mode
In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate
using the high-frequency clock and/or low-frequency clock.
(2)
SLOW2 mode
In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency
clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hardware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes
into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1
mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.
(3)
SLOW1 mode
This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.
Page 14
TMP86CH22UG
Switching back and forth between SLOW1 and SLOW2 modes are performed by
SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is
stopped; output from the 1st to 6th stages is also stopped.
(4)
IDLE2 mode
In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are
halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or
the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode,
except that operation returns to NORMAL2 mode.
(5)
SLEEP1 mode
In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU,
the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode.
In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from
the 1st to 6th stages is also stopped.
(6)
SLEEP2 mode
The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the
SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock.
(7)
SLEEP0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode
is enabled by setting “1” on bit SYSCR2<TGHALT>.
When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back
again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF
= “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to SLOW1 mode.
2.2.3.3
STOP mode
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The
internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a
inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After
the warm-up period is completed, the execution resumes with the instruction which follows the STOP
mode start instruction.
Page 15
2. Operational Description
2.2 System Clock Controller
TMP86CH22UG
IDLE0
mode
RESET
Reset release
Note 2
SYSCR2<TGHALT> = "1"
SYSCR1<STOP> = "1"
SYSCR2<IDLE> = "1"
NORMAL1
mode
Interrupt
STOP pin input
IDLE1
mode
(a) Single-clock mode
SYSCR2<XTEN> = "0"
SYSCR2<XTEN> = "1"
SYSCR2<IDLE> = "1"
IDLE2
mode
NORMAL2
mode
Interrupt
SYSCR1<STOP> = "1"
STOP pin input
SYSCR2<SYSCK> = "0"
SYSCR2<SYSCK> = "1"
STOP
SYSCR2<IDLE> = "1"
SLEEP2
mode
SLOW2
mode
Interrupt
SYSCR2<XEN> = "0"
SYSCR2<XEN> = "1"
SYSCR2<IDLE> = "1"
SLEEP1
mode
Interrupt
(b) Dual-clock mode
SYSCR1<STOP> = "1"
SLOW1
mode
STOP pin input
SYSCR2<TGHALT> = "1"
Note 2
SLEEP0
mode
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1
and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
Table 2-1 Operating Mode and Conditions
Oscillator
Operating Mode
High
Frequency
Low
Frequency
RESET
NORMAL1
Single clock
IDLE1
Oscillation
Reset
Operate
Halt
Operate
Halt
Operate with
high frequency
Machine Cycle
Time
4/fc [s]
–
4/fc [s]
Halt
Oscillation
Operate with
low frequency
Oscillation
Halt
Operate
Operate
Operate with
low frequency
SLOW1
4/fs [s]
Stop
SLEEP0
STOP
Reset
Stop
SLEEP2
SLEEP1
Reset
Halt
SLOW2
Dual clock
Other
Peripherals
Stop
NORMAL2
IDLE2
TBT
Operate
IDLE0
STOP
CPU Core
Halt
Stop
Halt
Page 16
Halt
–
TMP86CH22UG
System Control Register 1
SYSCR1
7
6
5
4
(0038H)
STOP
RELM
RETM
OUTEN
3
2
1
0
WUT
(Initial value: 0000 00**)
STOP
STOP mode start
0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)
R/W
RELM
Release method for STOP
mode
0: Edge-sensitive release
1: Level-sensitive release
R/W
RETM
Operating mode after STOP
mode
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode
R/W
Port output during STOP mode
0: High impedance
1: Output kept
R/W
OUTEN
WUT
Warm-up time at releasing
STOP mode
Return to NORMAL mode
Return to SLOW mode
00
3 x 216/fc
3 x 213/fs
01
216/fc
213/fs
10
3 x 214/fc
3 x 26/fs
11
214/fc
26/fs
R/W
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting
from SLOW mode to STOP mode.
Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external
interrupt request on account of falling edge.
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Note 8: The warmig-up time should be set correctly for using oscillator.
System Control Register 2
SYSCR2
(0039H)
7
6
5
4
XEN
XTEN
SYSCK
IDLE
3
2
1
TGHALT
0
(Initial value: 1000 *0**)
XEN
High-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
XTEN
Low-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
SYSCK
Main system clock select
(Write)/main system clock monitor (Read)
0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
IDLE
CPU and watchdog timer control
(IDLE1/2 and SLEEP1/2 modes)
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)
TGHALT
TG control (IDLE0 and SLEEP0
modes)
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
(Start IDLE0 and SLEEP0 modes)
R/W
R/W
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared
to “0” when SYSCK = “1”.
Note 2: *: Don’t care, TG: Timing generator, *; Don’t care
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals
may be set after IDLE0 or SLEEP0 mode is released.
Page 17
2. Operational Description
2.2 System Clock Controller
2.2.4
TMP86CH22UG
Operating Mode Control
2.2.4.1
STOP mode
STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input
(STOP2) which is controlled by the STOP mode release control register (STOPCR).
The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
status in effect before STOP mode was entered.
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
which started STOP mode.
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP2) for releasing STOP
mode in edge-sensitive mode.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP2). However,
because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the
STOP pin must be used for releasing STOP mode.
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external
interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.
(1)
Level-sensitive release mode (RELM = “1”)
In this mode, STOP mode is released by setting the STOP pin high or setting the STOP2 pin input
which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply
is cut off and long term battery backup.
Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP2
input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus,
to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP2 input is high. The following two methods can be used
for confirmation.
1. Testing a port.
2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).
Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
SSTOPH:
LD
(SYSCR1), 01010000B
; Sets up the level-sensitive release mode
TEST
(P2PRD). 0
; Wait until the STOP pin input goes low level
JRS
F, SSTOPH
; IMF ← 0
DI
SET
(SYSCR1). 7
; Starts STOP mode
Page 18
TMP86CH22UG
Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.
PINT5:
TEST
(P2PRD). 0
; To reject noise, STOP mode does not start if
JRS
F, SINT5
LD
(SYSCR1), 01010000B
port P20 is at high
; Sets up the level-sensitive release mode.
; IMF ← 0
DI
SET
SINT5:
(SYSCR1). 7
; Starts STOP mode
RETI
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Warm up
Confirm by program that the
STOP pin input is low and start
STOP mode.
NORMAL
operation
STOP mode is released by the hardware.
Always released if the STOP
pin input is high.
Figure 2-7 Level-sensitive Release Mode
Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted.
Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release
mode is not switched until a rising edge of the STOP pin input is detected.
(2)
Edge-sensitive release mode (RELM = “0”)
In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic
signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In
the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level.
Do not use any STOP2 pin input for releasing STOP mode in edge-sensitive release mode.
Example :Starting STOP mode from NORMAL mode
; IMF ← 0
DI
LD
(SYSCR1), 10010000B
; Starts after specified to the edge-sensitive release mode
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Warm up
NORMAL
operation
STOP mode started
by the program.
STOP
operation
STOP mode is released by the hardware at the rising
edge of STOP pin input.
Figure 2-8 Edge-sensitive Release Mode
Page 19
2. Operational Description
2.2 System Clock Controller
TMP86CH22UG
STOP mode is released by the following sequence.
1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency
clock oscillator is turned on.
2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all
internal operations remain halted. Four different warm-up times can be selected with the
SYSCR1<WUT> in accordance with the resonator characteristics.
3. When the warm-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction.
Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the
timing generator are cleared to "0".
Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately
performs the normal reset operation.
Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed.
The power supply voltage must be at the operating voltage level before releasing STOP mode.
The RESET pin input must also be “H” level, rising together with the power supply voltage. In this
case, if an external time constant circuit has been connected, the RESET pin input voltage will
increase at a slower pace than the power supply voltage. At this time, there is a danger that a
reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level
input voltage (Hysteresis input).
Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz)
Warm-up Time [ms]
WUT
00
01
10
11
Return to NORMAL Mode
Return to SLOW Mode
12.288
4.096
3.072
1.024
750
250
5.85
1.95
Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up
time may include a certain amount of error if there is any fluctuation of the oscillation frequency
when STOP mode is released. Thus, the warm-up time must be considered as an approximate
value.
Page 20
Page 21
Figure 2-9 STOP Mode Start/Release
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
STOP pin
input
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
0
Halt
Turn off
Turn on
Turn on
n
Count up
a+3
Warm up
a+2
n+2
n+3
n+4
0
(b) STOP mode release
1
Instruction address a + 2
a+4
2
Instruction address a + 3
a+5
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
n+1
SET (SYSCR1). 7
a+3
3
Instruction address a + 4
a+6
0
Halt
Turn off
TMP86CH22UG
2. Operational Description
2.2 System Clock Controller
2.2.4.2
TMP86CH22UG
IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
interrupts. The following status is maintained during these modes.
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
operate.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before these modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
Starting IDLE1/2 and
SLEEP1/2 modes by
instruction
CPU and WDT are halted
Yes
Reset input
Reset
No
No
Interrupt request
Yes
“0”
IMF
“1” (Interrupt release mode)
Normal
release mode
Interrupt processing
Execution of the instruction which follows the
IDLE1/2 and SLEEP1/2
modes start instruction
Figure 2-10 IDLE1/2 and SLEEP1/2 Modes
Page 22
TMP86CH22UG
• Start the IDLE1/2 and SLEEP1/2 modes
After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2
and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”.
• Release the IDLE1/2 and SLEEP1/2 modes
IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and
SLEEP1/2 modes, the SYSCR2<IDLE> is automatically cleared to “0” and the operation mode
is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes.
IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
(1)
Normal release mode (IMF = “0”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual
interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the
instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt
latches (IL) of the interrupt source used for releasing must be cleared to “0” by load instructions.
(2)
Interrupt release mode (IMF = “1”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual
interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the
program operation is resumed from the instruction following the instruction, which starts IDLE1/2
and SLEEP1/2 modes.
Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2
modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2
modes will not be started.
Page 23
Page 24
Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Halt
Halt
Halt
Halt
Operate
Operate
Operate
Acceptance of interrupt
Instruction address a + 2
a+4
(b) IDLE1/2 and SLEEP1/2 modes release
㽳㩷Interrupt release mode
a+3
㽲㩷Normal release mode
a+3
(a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a)
Operate
SET (SYSCR2). 4
a+2
Halt
a+3
2.2 System Clock Controller
2. Operational Description
TMP86CH22UG
TMP86CH22UG
2.2.4.3
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base
timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes.
1. Timing generator stops feeding clock to peripherals except TBT.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before IDLE0 and SLEEP0 modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
SLEEP0 modes.
Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
Stopping peripherals
by instruction
Starting IDLE0, SLEEP0
modes by instruction
CPU and WDT are halted
Reset input
Yes
Reset
No
No
TBT
source clock
falling
edge
Yes
No
TBTCR<TBTEN>
= "1"
Yes
No
TBT interrupt
enable
Yes
(Normal release mode)
No
IMF = "1"
Yes (Interrupt release mode)
Interrupt processing
Execution of the instruction
which follows the IDLE0,
SLEEP0 modes start
instruction
Figure 2-12 IDLE0 and SLEEP0 Modes
Page 25
2. Operational Description
2.2 System Clock Controller
TMP86CH22UG
• Start the IDLE0 and SLEEP0 modes
Stop (Disable) peripherals such as a timer counter.
To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”.
• Release the IDLE0 and SLEEP0 modes
IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag
of TBT and TBTCR<TBTEN>.
After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is automatically
cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0
modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”,
INTTBT interrupt latch is set to “1”.
IDLE0 and SLEEP0 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR<TBTEN> setting.
(1)
Normal release mode (IMF•EF6•TBTCR<TBTEN> = “0”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK>. After the falling edge is detected, the program operation is resumed from the
instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or
SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”.
(2)
Interrupt release mode (IMF•EF6•TBTCR<TBTEN> = “1”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK> and INTTBT interrupt processing is started.
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR<TBTCK>.
Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is
started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be
started.
Page 26
Page 27
Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release
Watchdog
timer
Instruction
execution
Program
counter
TBT clock
Halt
Halt
Halt
Watchdog
timer
Main
system
clock
Halt
Instruction
execution
Program
counter
TBT clock
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
a+3
Halt
Operate
Operate
(b) IDLE and SLEEP0 modes release
㽳㩷Interrupt release mode
a+3
㽲㩷Normal release mode
a+3
Acceptance of interrupt
Instruction address a + 2
a+4
(a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a
Operate
SET (SYSCR2). 2
a+2
TMP86CH22UG
2. Operational Description
2.2 System Clock Controller
2.2.4.4
TMP86CH22UG
SLOW mode
SLOW mode is controlled by the system control register 2 (SYSCR2).
The following is the methods to switch the mode with the warm-up counter.
(1)
Switching from NORMAL2 mode to SLOW1 mode
First, set SYSCR2<SYSCK> to switch the main system clock to the low-frequency clock for
SLOW2 mode. Next, clear SYSCR2<XEN> to turn off high-frequency oscillation.
Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from
SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from
SLOW mode to stop mode.
Example 1 :Switching from NORMAL2 mode to SLOW1 mode.
SET
(SYSCR2). 5
; SYSCR2<SYSCK> ← 1
(Switches the main system clock to the low-frequency
clock for SLOW2)
CLR
(SYSCR2). 7
; SYSCR2<XEN> ← 0
(Turns off high-frequency oscillation)
Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized.
SET
(SYSCR2). 6
; SYSCR2<XTEN> ← 1
LD
(TC5CR), 43H
; Sets mode for TC6, 5 (16-bit mode, fs for source)
LD
(TC6CR), 05H
; Sets warming-up counter mode
LDW
(TTREG5), 8000H
; Sets warm-up time (Depend on oscillator accompanied)
; IMF ← 0
DI
SET
(EIRH). 5
; IMF ← 1
EI
SET
; Enables INTTC6
(TC6CR). 3
; Starts TC6, 5
CLR
(TC6CR). 3
; Stops TC6, 5
SET
(SYSCR2). 5
; SYSCR2<SYSCK> ← 1
:
PINTTC6:
(Switches the main system clock to the low-frequency clock)
CLR
(SYSCR2). 7
; SYSCR2<XEN> ← 0
(Turns off high-frequency oscillation)
RETI
:
VINTTC6:
DW
PINTTC6
; INTTC6 vector table
Page 28
TMP86CH22UG
(2)
Switching from SLOW1 mode to NORMAL2 mode
First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization
(Warm up) has been taken by the timer/counter (TC6,TC5), clear SYSCR2<SYSCK> to switch the
main system clock to the high-frequency clock.
SLOW mode can also be released by inputting low level on the RESET pin. After releasing reset, the
operation mode is started from NORMAL1 mode.
Note: After SYSCK is cleared to “0”, executing the instructions is continiued by the low-frequency clock
for the period synchronized with low-frequency and high-frequency clocks.
High-frequency clock
Low-frequency clock
Main system clock
SYSCK
Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms).
SET
(SYSCR2). 7
; SYSCR2<XEN> ← 1 (Starts high-frequency oscillation)
LD
(TC5CR), 63H
; Sets mode for TC6, 5 (16-bit mode, fc for source)
LD
(TC6CR), 05H
; Sets warming-up counter mode
LD
(TTREG6), 0F8H
; Sets warm-up time
; IMF ← 0
DI
SET
(EIRH). 5
; IMF ← 1
EI
SET
; Enables INTTC6
(TC6CR). 3
; Starts TC6, 5
CLR
(TC6CR). 3
; Stops TC6, 5
CLR
(SYSCR2). 5
; SYSCR2<SYSCK> ← 0
:
PINTTC6:
(Switches the main system clock to the high-frequency clock)
RETI
:
VINTTC6:
DW
PINTTC6
; INTTC6 vector table
Page 29
Page 30
Figure 2-14 Switching between the NORMAL2 and SLOW Modes
SET (SYSCR2). 7
SET (SYSCR2). 5
SLOW1 mode
Instruction
execution
XEN
SYSCK
Highfrequency
clock
Lowfrequency
clock
Main
system
clock
NORMAL2
mode
Instruction
execution
XEN
SYSCK
Highfrequency
clock
Lowfrequency
clock
Main
system
clock
(b) Switching to the NORMAL2 mode
Warm up during SLOW2 mode
CLR (SYSCR2). 5
(a) Switching to the SLOW mode
SLOW2 mode
CLR (SYSCR2). 7
NORMAL2
mode
SLOW1 mode
Turn off
2.2 System Clock Controller
2. Operational Description
TMP86CH22UG
TMP86CH22UG
2.3 Reset Circuit
The TMP86CH22UG has four types of reset generation procedures: An external reset input, an address trap reset,
a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the
system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the
maximum 24/fc[s].
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when
power is turned on.
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
On-chip Hardware
Initial Value
Program counter
(PC)
(FFFEH)
Stack pointer
(SP)
Not initialized
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
(JF)
Not initialized
Zero flag
(ZF)
Not initialized
Carry flag
(CF)
Not initialized
Half carry flag
(HF)
Not initialized
Sign flag
(SF)
Not initialized
Overflow flag
(VF)
Not initialized
(IMF)
0
(EF)
0
(IL)
0
Interrupt individual enable flags
Interrupt latches
2.3.1
Initial Value
Prescaler and divider of timing generator
0
Not initialized
Jump status flag
Interrupt master enable flag
On-chip Hardware
Watchdog timer
Enable
Output latches of I/O ports
Refer to I/O port circuitry
Control registers
Refer to each of control
register
LCD data buffer
Not initialized
RAM
Not initialized
External Reset Input
The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized.
When the RESET pin input goes high, the reset operation is released and the program execution starts at the
vector address stored at addresses FFFEH to FFFFH.
VDD
RESET
Internal reset
Watchdog timer reset
Malfunction
reset output
circuit
Address trap reset
System clock reset
Figure 2-15 Reset Circuit
Page 31
2. Operational Description
2.3 Reset Circuit
TMP86CH22UG
2.3.2
Address trap reset
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be
generated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz).
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative.
Instruction
execution
Reset release
JP a
Instruction at address r
Address trap is occurred
Internal reset
maximum 24/fc [s]
4/fc to 12/fc [s]
16/fc [s]
Note 1: Address “a” is in the SFR, DBR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Figure 2-16 Address Trap Reset
2.3.3
Watchdog timer reset
Refer to Section “Watchdog Timer”.
2.3.4
System clock reset
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
CPU. (The oscillation is continued without stopping.)
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
The reset time is maximum 24/fc (1.5 µs at 16.0 MHz).
Page 32
TMP86CH22UG
Page 33
2. Operational Description
2.3 Reset Circuit
TMP86CH22UG
Page 34
TMP86CH22UG
3. Interrupt Control Circuit
The TMP86CH22UG has a total of 18 interrupt sources excluding reset. Interrupts can be nested with priorities.
Four of the internal interrupt sources are non-maskable while the rest are maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Interrupt Factors
Internal/External
Enable Condition
Interrupt
Latch
Vector
Address
Priority
(Reset)
Non-maskable
–
FFFE
1
Internal
INTSWI (Software interrupt)
Non-maskable
–
FFFC
2
Internal
INTUNDEF (Executed the undefined instruction
interrupt)
Non-maskable
–
FFFC
2
Internal
INTATRAP (Address trap interrupt)
Non-maskable
IL2
FFFA
2
Internal
INTWDT (Watchdog timer interrupt)
Non-maskable
IL3
FFF8
2
External
INT0
IMF• EF4 = 1, INT0EN = 1
IL4
FFF6
5
External
INT1
IMF• EF5 = 1
IL5
FFF4
6
Internal
INTTBT
IMF• EF6 = 1
IL6
FFF2
7
Internal
INTTC1
IMF• EF7 = 1
IL7
FFF0
8
Internal
INTSIO
IMF• EF8 = 1
IL8
FFEE
9
External
INT2
IMF• EF9 = 1
IL9
FFEC
10
Internal
INTRXD
IMF• EF10 = 1
IL10
FFEA
11
Internal
INTTXD
IMF• EF11 = 1
IL11
FFE8
12
-
Reserved
IMF• EF12 = 1
IL12
FFE6
13
INTTC6
IMF• EF13 = 1
IL13
FFE4
14
Internal
INTRTC
IMF• EF14 = 1
IL14
FFE2
15
Internal
INTADC
IMF• EF15 = 1
IL15
FFE0
16
Internal
Reserved
IMF• EF16 = 1
IL16
FFBE
17
External
-
INT3
IMF• EF17 = 1
IL17
FFBC
18
Internal
INTTC5
IMF• EF18 = 1
IL18
FFBA
19
External
INT5
IMF• EF19 = 1
IL19
FFB8
20
-
Reserved
IMF• EF20 = 1
IL20
FFB6
21
-
Reserved
IMF• EF21 = 1
IL21
FFB4
22
-
Reserved
IMF• EF22 = 1
IL22
FFB2
23
-
Reserved
IMF• EF23 = 1
IL23
FFB0
24
Note 1: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is
cancelled). For details, see “Address Trap”.
Note 2: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
Note 3: If an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15 (INTADC) is
being accepted, the INTADC interrupt latch may be cleared without the INTADC interrupt being processed. For details,
refer to the corresponding notes in the chapter on the AD converter.
3.1 Interrupt latches (IL19 to IL2)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to “0” during reset.
Page 35
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86CH22UG
The interrupt latches are located on address 002EH, 003CH and 003DH in SFR area. Each latch can be cleared to
"0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the
interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write
instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed.
Interrupt latches are not set to “1” by an instruction.
Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
Example 1 :Clears interrupt latches
; IMF ← 0
DI
LDW
(ILL), 1110100000111111B
; IL12, IL10 to IL6 ← 0
; IMF ← 1
EI
Example 2 :Reads interrupt latchess
WA, (ILL)
; W ← ILH, A ← ILL
TEST
(ILL). 7
; if IL7 = 1 then jump
JR
F, SSET
LD
Example 3 :Tests interrupt latches
3.2 Interrupt enable register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR.
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
registers are located on address 002CH, 003AH and 003BH in SFR area, and they can be read and written by an
instructions (Including read-modify-write instructions such as bit manipulation or operation instructions).
3.2.1
Interrupt master enable flag (IMF)
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When
an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,
which was the status before interrupt acceptance, is loaded on IMF again.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to “0”.
Page 36
TMP86CH22UG
3.2.2
Individual interrupt enable flags (EF19 to EF4)
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” disables acceptance. During reset, all the individual interrupt enable flags (EF19 to EF4) are initialized to “0” and
all maskable interrupts are not accepted until they are set to “1”.
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Example 1 :Enables interrupts individually and sets IMF
; IMF ← 0
DI
LDW
:
(EIRL), 1110100010100000B
; EF15 to EF13, EF11, EF7, EF5 ← 1
Note: IMF should not be set.
:
; IMF ← 1
EI
Example 2 :C compiler description example
unsigned int _io (3AH) EIRL;
/* 3AH shows EIRL address */
_DI();
EIRL = 10100000B;
:
_EI();
Page 37
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86CH22UG
Interrupt Latches
(Initial value: 00000000 000000**)
ILH,ILL
(003DH, 003CH)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
IL15
IL14
IL13
IL12
IL11
IL10
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
ILH (003DH)
1
0
ILL (003CH)
(Initial value: ****0000)
ILE
(002EH)
7
6
5
4
3
2
1
0
−
−
−
−
IL19
IL18
IL17
IL16
ILE (002EH)
IL19 to IL2
at RD
0: No interrupt request
Interrupt latches
at WR
0: Clears the interrupt request
1: (Interrupt latch is not set.)
1: Interrupt request
R/W
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Interrupt Enable Registers
(Initial value: 00000000 0000***0)
EIRH,EIRL
(003BH, 003AH)
15
14
13
EF15
EF14
EF13
12
11
10
9
8
7
6
5
EF12
EF11
EF10
EF9
EF8
EF7
EF6
EF5
EIRH (003BH)
4
3
2
1
EF4
0
IMF
EIRL (003AH)
(Initial value: ****0000)
EIRE
(002CH)
7
6
5
−
−
−
4
3
2
1
0
−
EF19
EF18
EF17
EF16
EIRE (002CH)
EF19 to EF4
IMF
Individual-interrupt enable flag
(Specified for each bit)
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Interrupt master enable flag
0:
1:
Disables the acceptance of all maskable interrupts
Enables the acceptance of all maskable interrupts
R/W
Note 1: *: Don’t care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Page 38
TMP86CH22UG
3.3 Interrupt Sequence
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
“0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the
completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
3.3.1
Interrupt acceptance processing is packaged as follows.
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any following interrupt.
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3.
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter.
e. The instruction stored at the entry address of the interrupt service program is executed.
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
Interrupt service task
1-machine cycle
Interrupt
request
Interrupt
latch (IL)
IMF
Execute
instruction
PC
SP
Execute
instruction
a−1
a
Execute
instruction
Interrupt acceptance
a+1
b
a
b+1 b+2 b + 3
n−1 n−2
n
Execute RETI instruction
c+2
c+1
a
n−2 n−1
n-3
a+1 a+2
n
Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first
machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
service program
Vector table address
FFF2H
03H
FFF3H
D2H
Entry address
Vector
D203H
0FH
D204H
06H
Figure 3-2 Vector table address,Entry address
Page 39
Interrupt
service
program
3. Interrupt Control Circuit
3.3 Interrupt Sequence
TMP86CH22UG
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the
level of current servicing interrupt is requested.
In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,
acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,
before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length
between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply
nested.
3.3.2
Saving/restoring general-purpose registers
During interrupt acceptance processing, the program counter (PC) and the program status word (PSW,
includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are
saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using
the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers.
3.3.2.1
Using PUSH and POP instructions
If only a specific register is saved or interrupts of the same source are nested, general-purpose registers
can be saved/restored using the PUSH/POP instructions.
Example :Save/store register using PUSH and POP instructions
PINTxx:
PUSH
WA
; Save WA register
(interrupt processing)
POP
WA
; Restore WA register
RETI
; RETURN
Address
(Example)
SP
b-5
A
SP
b-4
SP
b-3
PCL
W
PCL
PCH
PCH
PCH
PSW
PSW
PSW
At acceptance of
an interrupt
At execution of
PUSH instruction
PCL
At execution of
POP instruction
b-2
b-1
SP
b
At execution of
RETI instruction
Figure 3-3 Save/store register using PUSH and POP instructions
3.3.2.2
Using data transfer instructions
To save only a specific register without nested interrupts, data transfer instructions are available.
Page 40
TMP86CH22UG
Example :Save/store register using data transfer instructions
PINTxx:
LD
(GSAVA), A
; Save A register
(interrupt processing)
LD
A, (GSAVA)
; Restore A register
RETI
; RETURN
Main task
Interrupt
service task
Interrupt
acceptance
Saving
registers
Restoring
registers
Interrupt return
Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction
Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing
3.3.3
Interrupt return
Interrupt return instructions [RETI]/[RETN] perform as follows.
[RETI]/[RETN] Interrupt Return
1. Program counter (PC) and program status word
(PSW, includes IMF) are restored from the stack.
2. Stack pointer (SP) is incremented by 3.
As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to
restarting address, during interrupt service program.
Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and
INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and
PCH are located on address (SP + 1) and (SP + 2) respectively.
Example 1 :Returning from address trap interrupt (INTATRAP) service program
PINTxx:
POP
WA
; Recover SP by 2
LD
WA, Return Address
;
PUSH
WA
; Alter stacked data
(interrupt processing)
RETN
; RETURN
Page 41
3. Interrupt Control Circuit
3.4 Software Interrupt (INTSW)
TMP86CH22UG
Example 2 :Restarting without returning interrupt
(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
PINTxx:
INC
SP
; Recover SP by 3
INC
SP
;
INC
SP
;
(interrupt processing)
LD
EIRL, data
; Set IMF to “1” or clear it to “0”
JP
Restart Address
; Jump into restarting address
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed.
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
task is performed but not the main task.
3.4 Software Interrupt (INTSW)
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
is highest prioritized interrupt).
Use the SWI instruction only for detection of the address error or for debugging.
3.4.1
Address error detection
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM, DBR or SFR areas.
3.4.2
Debugging
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
address.
3.5 Undefined Instruction Interrupt (INTUNDEF)
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt
(SWI) does.
3.6 Address Trap Interrupt (INTATRAP)
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address
trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested.
Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on
watchdog timer control register (WDTCR).
Page 42
TMP86CH22UG
3.7 External Interrupts
The TMP86CH22UG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits
(Pulse inputs of less than a certain time are eliminated as noise).
Edge selection is also possible with INT1 to INT3. The INT0/P63 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset.
Edge selection, noise reject control and INT0/P63 pin function selection are performed by the external interrupt
control register (EINTCR).
Source
INT0
INT1
INT2
INT3
INT5
Pin
INT0
INT1
INT2
INT3
INT5
Enable Conditions
Release Edge
Digital Noise Reject
IMF ΠEF4 ΠINT0EN=1
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
IMF ΠEF5 = 1
Falling edge
or
Rising edge
Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or
more are considered to be signals. In the SLOW
or the SLEEP mode, pulses of less than 1/fs [s]
are eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
IMF ΠEF9 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
IMF ΠEF17 = 1
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
IMF ΠEF19 = 1
Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch.
Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input.
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such
as disabling the interrupt enable flag.
Page 43
3. Interrupt Control Circuit
3.7 External Interrupts
TMP86CH22UG
External Interrupt Control Register
EINTCR
7
6
5
4
3
2
1
(0037H)
INT1NC
INT0EN
-
-
INT3ES
INT2ES
INT1ES
0
(Initial value: 00** 000*)
INT1NC
Noise reject time select
0: Pulses of less than 63/fc [s] are eliminated as noise
1: Pulses of less than 15/fc [s] are eliminated as noise
R/W
INT0EN
P63/INT0 pin configuration
0: P63 input/output port
1: INT0 pin (Port P63 should be set to an input mode)
R/W
INT3 ES
INT3 edge select
0: Rising edge
1: Falling edge
R/W
INT2 ES
INT2 edge select
0: Rising edge
1: Falling edge
R/W
INT1 ES
INT1 edge select
0: Rising edge
1: Falling edge
R/W
Note 1: fc: High-frequency clock [Hz], *: Don’t care
Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register
(EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR).
Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc.
Page 44
TMP86CH22UG
4. Special Function Register (SFR)
The TMP86CH22UG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address
0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for
TMP86CH22UG.
4.1 SFR
Address
Read
Write
0000H
Reserved
0001H
P1DR
0002H
P2DR
0003H
P3DR
0004H
P3OUTCR
0005H
P5DR
0006H
P6DR
0007H
P7DR
0008H
Reserved
0009H
P1CR
000AH
P5CR
000BH
P6CR1
000CH
P6CR2
000DH
P7CR
000EH
ADCCR1
000FH
ADCCR2
0010H
TREG1AL
0011H
TREG1AM
0012H
TREG1AH
0013H
TREG1B
0014H
TC1CR1
0015H
0016H
TC1CR2
TC1SR
-
0017H
RTCCR
0018H
Reserved
0019H
Reserved
001AH
TC5CR
001BH
TC6CR
001CH
Reserved
001DH
Reserved
001EH
TTREG5
001FH
TTREG6
0020H
ADCDR2
0021H
ADCDR1
-
0022H
Reserved
0023H
Reserved
0024H
Reserved
0025H
UARTSR
Page 45
UARTCR1
4. Special Function Register (SFR)
4.1 SFR
TMP86CH22UG
Address
Read
0026H
-
Write
UARTCR2
0027H
LCDCR
0028H
Reserved
0029H
Reserved
002AH
PWREG5
002BH
PWREG6
002CH
EIRE
002DH
Reserved
002EH
ILE
002FH
Reserved
0030H
Reserved
0031H
Reserved
0032H
Reserved
0033H
Reserved
0034H
-
WDTCR1
0035H
-
WDTCR2
0036H
TBTCR
0037H
EINTCR
0038H
SYSCR1
0039H
SYSCR2
003AH
EIRL
003BH
EIRH
003CH
ILL
003DH
ILH
003EH
Reserved
003FH
PSW
Note 1: Do not access reserved areas by the program.
Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 46
TMP86CH22UG
4.2 DBR
Address
Read
Write
0F80H
Reserved
0F81H
Reserved
0F82H
Reserved
0F83H
Reserved
0F84H
SEG9
0F85H
SEG11/10
0F86H
SEG13/12
0F87H
SEG15/14
0F88H
SEG17/16
0F89H
SEG19/18
0F8AH
SEG21/20
0F8BH
SEG23/22
0F8CH
SEG25/24
0F8DH
SEG27/26
0F8EH
SEG29/28
0F8FH
SEG31/30
0F90H
SIOBR0
0F91H
SIOBR1
0F92H
SIOBR2
0F93H
SIOBR3
0F94H
SIOBR4
0F95H
SIOBR5
0F96H
SIOBR6
0F97H
SIOBR7
0F98H
-
SIOCR1
0F99H
SIOSR
SIOCR2
0F9AH
-
STOPCR
0F9BH
RDBUF
TDBUF
0F9CH
P2PRD
-
0F9DH
P3PRD
-
0F9EH
P1LCR
0F9FH
P5LCR
Page 47
4. Special Function Register (SFR)
4.2 DBR
TMP86CH22UG
Address
Read
Write
0FA0H
P7LCR
0FA1H
Reserved
0FA2H
Reserved
0FA3H
Reserved
0FA4H
Reserved
0FA5H
Reserved
0FA6H
Reserved
0FA7H
Reserved
0FA8H
Reserved
0FA9H
Reserved
0FAAH
Reserved
0FABH
Reserved
0FACH
Reserved
0FADH
Reserved
0FAEH
Reserved
0FAFH
Reserved
0FB0H
Reserved
0FB1H
Reserved
0FB2H
Reserved
0FB3H
Reserved
0FB4H
Reserved
0FB5H
Reserved
0FB6H
Reserved
0FB7H
Reserved
0FB8H
Reserved
0FB9H
Reserved
0FBAH
Reserved
0FBBH
Reserved
0FBCH
Reserved
0FBDH
Reserved
0FBEH
Reserved
0FBFH
Reserved
Address
Read
0FC0H
Write
Reserved
: :
: :
0FDFH
Reserved
Address
Read
0FE0H
Write
Reserved
: :
: :
0FFFH
Reserved
Note 1: Do not access reserved areas by the program.
Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 48
TMP86CH22UG
5. I/O Ports
The TMP86CH22UG have 6 parallel input/output ports (33 pins) as follows.
Primary Function
Secondary Functions
Port P1
8-bit I/O port
External interrupt input, UART input/output, serial interface input/output and
segment output.
Port P2
3-bit I/O port
Low-frequency resonator connections, external interrupt input, STOP mode
release signal input.
Port P3
2-bit I/O port
1-bit output port
Port P5
8-bit I/O port
LCD Segment output.
Port P6
4-bit I/O port
Analog input, external interrupt input, timer/counter input and STOP mode
release signal input.
Port P7
7-bit I/O port
LCD Segment output.
Timer/counter input/output and divider output.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 5-1 shows input/output timing examples.
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
port.
Fetch cycle
Fetch cycle
Read cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Ex: LD A, (x)
Instruction execution cycle
Input strobe
Data input
(a) Input timing
Fetch cycle
Fetch cycle
Write cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Instruction execution cycle
Ex: LD (x), A
Output strobe
Old
Data output
(b) Output timing
Note: The positions of the read and write cycles may vary, depending on the instruction.
Figure 5-1 Input/Output Timing (Example)
Page 49
New
5. I/O Ports
5.1 Port P1 (P17 to P10)
TMP86CH22UG
5.1 Port P1 (P17 to P10)
Port P1 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Input/output
mode is specified by the P1 control register (P1CR).
During reset, the P1DR, P1CR and P1LCR are initialized to “0”.
Port P1 is also used as UART input/output, an external interrupt input, serial interface input/output and segment
output of LCD. It is necessary to set registers for using each function. The following table shows register programming for multi function ports. When the port P16 is used, set not only P16 port registers but also P31 port register.
Also set not only port P17 registers but also P32 register similarly. Though the TMP86CH22UG do not have P31 and
P32 ports, it is necessary to set P3 port registers for keeping software compatibility with TMP86C923XB. For detail,
refer to Table 5-2 and Table 5-3 and then refer to description of P3OUTCR and P3DR registers.
Table 5-1 Register programming for P15 to P10
Programmed Value
Function (Port P15 to P10)
P1DR[5:0]
P1CR[5:0]
P1LCR[5:0]
*
"0"
"0"
Port "0" output
"0"
"1"
"0"
Port "1" output and UART output
"1"
"1"
"0"
*
"1"
Port input, UART input, SIO input or
external interrupt input
*
LCD segment output
Note: Asterisk (*) indicates "1" or "0" either of which can be selected.
Table 5-2 Register programming for P16
Programmed Value
Function (Port P16)
P1DR[6]
P1CR[6]
P1LCR[6]
SIO output
*
"0"
"0"
Port input
*
"0"
"0"
Port "0" output
"0"
"1"
"0"
Port "1" output
"1"
"1"
"0"
*
*
"1"
P3DR[1]
P3OUTCR[1]
(SIOEN1)
"1"
"1"
"0"
LCD segment output
Note 1: When P16 is used as port output, set in order each registers as follows. If it is not set appropriately, an overcurrent may
flow causing damage to the emulation chip (86C923XB).
STEP 1. P3OUTCR<SIOEN1> = “0”
STEP 2 P1LCR[6] = “0”
STEP 3. P1CR[6] = “1”
Note 2: When P16 is used as SO output, set in order each registers as follows. If it is not set appropriately, an overcurrent may
flow causing damage to the emulation chip (86C923XB).
STEP 1. P1LCR[6]="0"
STEP 2. P1CR[6]="0"
STEP 3. P3OUTCR<SIOEN1>="1"
Note 3: Asterisk (*) indicates "1" or "0" either of which can be selected.
Page 50
TMP86CH22UG
Table 5-3 Register programming for P17
Programmed Value
Function (Port P17)
P1DR[7]
P1CR[7]
P1LCR[7]
SIO output
*
"0"
"0"
Port input or SIO input
*
"0"
"0"
Port "0" output
"0"
"1"
"0"
Port "1" output
"1"
"1"
"0"
*
*
"1"
P3DR[2]
P3OUTCR[2]
(SIOEN2)
"1"
"1"
"0"
LCD segment output
Note 1: When P17 is used as port output, set in order each registers as follows. If it is not set appropriately, an overcurrent may
flow causing damage to the emulation chip (86C923XB).
STEP 1. P3OUTCR<SIOEN2> = “0”
STEP 2 P1LCR[7] = “0”
STEP 3. P1CR[7] = “1”
Note 2: When P17 is used as SCK output, set in order each registers as follows. If it is not set appropriately, an overcurrent may
flow causing damage to the emulation chip (86C923XB).
STEP 1. P1LCR[7]="0"
STEP 2. P1CR[7]="0"
STEP 3. P3OUTCR<SIOEN2>="1"
Note 3: Asterisk (*) indicates "1" or "0" either of which can be selected.
Table 5-4 Values Read from P1DR and register programming
Conditions
Values Read from P1DR
P1CR
P1LCR
"0"
"0"
Terminal input data
"0"
"1"
"0"
"0"
"1"
Output latch contents
"1"
Page 51
5. I/O Ports
5.1 Port P1 (P17 to P10)
TMP86CH22UG
P3DR[1]
P3OUTCR<SIOEN1>
(In case of P16)
P3DR[1]
P3OUTCR<SIOEN1>
(In case of P17)
(Others)
STOP
OUTEN
P1LCRi input
P1LCR[i]
D
Q
D
Q
D
Q
P1CR[i] input
P1CR[i]
Data input (P1DR[i])
Data output (P1DR[i])
P1i
Output latch
LCD data output
(P1DR[1])
Note1 : i = 7 to 0
Note2 : STOP is bit7 in SYSCR1
Note3 : OUTEN is bit4 in SYSCR1
TXD output
(In case of P11)
(P1DR[6])
0
Y
1 S
P3OUTCR<SIOEN1>
SO output
(In case of P16)
(P1DR[7])
0
Y
1 S
P3OUTCR<SIOEN2>
SCK output
(In case of P17)
(Others)
Figure 5-2 Port 1
P1DR
(0001H)
R/W
P1LCR
(0F9EH)
7
6
5
4
3
2
1
0
P17
SEG24
SCK
P16
SEG25
SO
P15
SEG26
SI
P14
SEG27
INT3
P13
SEG28
INT2
P12
SEG29
INT1
P11
SEG30
TXD
P10
SEG31
RXD
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
P1LCR
P1CR
(0009H)
(Initial value: 0000 0000)
7
Port P1/segment output control
(set for each bit individually)
0: P1 input/output port or secondary function (expect for segment)
1: Segment output
6
3
5
4
2
1
R/W
0
(Initial value: 0000 0000)
P1CR
P1 port input/output control
(set for each bit individually)
0: Input mode, SO output or SCK output
1: Output mode
R/W
Note 1: When P16 and P17 is used as port output or SIO output, set in order each registers according to notes of Table 5-2 and
Table 5-3.
Note 2: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together,
the output latch (P1DR) contents for the port in input mode might be changed by executing a bit manipulation instruction.
Page 52
TMP86CH22UG
5.2 Port P2 (P22 to P20)
Port P2 is a 3-bit input/output port.
It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set
to “1”.
During reset, the output latch is initialized to “1”.
A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dualclock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports.
It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or
an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse.
P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address.
When read the output latch data, the P2DR register should be read and when read the terminal input data, the
P2PRD register should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable.
Data input (P2PRD[0])
Data input
D
Data output (P2DR[0])
Q
P20 (INT5, STOP)
Output latch
Second function input
Data input (P2PRD[1])
Osc. enable
Data input
Data output (P2DR[1])
D
Q
P21 (XTIN)
Output latch
Data input (P2PRD[2])
Data input
Data output (P2DR[2])
D
Q
P22 (XTOUT)
Output latch
STOP
OUTEN
XTEN
Note1 : STOP is bit7 in SYSCR1.
Note2 : OUTEN is bit4 in SYSCR1.
fs
Figure 5-3 Port 2
P2DR
(0002H)
R/W
P2PRD
(0F9CH)
Read only
7
6
5
4
3
2
P22
XTOUT
7
6
5
4
3
1
P21
XTIN
0
P20
INT5
(Initial value: **** *111)
STOP
2
1
0
P22
P21
P20
Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Page 53
5. I/O Ports
5.3 Port P3 (P37, P34 to P33)
TMP86CH22UG
5.3 Port P3 (P37, P34 to P33)
Port P3 is a 1-bit output and a 2-bit input/output port. It can be selected whether output circuit of P34 to P33 port is
C-MOS output or a sink open drain individually, by setting P3OUTCR. When a corresponding bit of P3OUTCR is
“0”, the output circuit is selected to a sink open drain and when a corresponding bit of P3OUTCR is “1”, the output
circuit is selected to a C-MOS output.
During reset, the P3DR is initialized to "1", and the P3OUTCR is initialized to "0".
Port P3 is also used as a timer/counter input/output, divider output. It is necessary to set registers for using each
function. The following table shows register programming for multi function ports.
P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address. When
read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD register
should be read. If a read instruction is executed for each registers of P3 port, read data of reserved bits are unstable.
Table 5-5 Register programming for P34 to P33
Programmed Value
Function (Port P34 to P33)
P3DR[4:3]
P3OUTCR[4:3]
Port input or timer counter input
"1"
"0"
Port "0" output
"0"
Programming
Port "1" output or timer counter output
"1"
applications
for each
Table 5-6 Register programming for P37
Function (Port P37)
Programmed
Value
P3DR[7]
Port "0" output
"0"
Port "1" output or divider output
"1"
STOP
OUTEN
P3OUTCR[i]
D
Q
P3OUTCR[i] input
Data input (P3PRD[i])
Output latch read (P3DR[i])
Data output (P3DR[i])
Second function output
D
Q
P3i
Output latch
Second function input
a) P34, P33
Note1 : i = 4,3
Note2 : STOP is bit7 in SYSCR1.
Note3 : OUTEN is bit4 in SYSCR1.
STOP
OUTEN
P3OUTCR[7]
Data output (P3DR[7])
Second function output
D
Q
P37
Output latch
b) P37
Figure 5-4 Port 3
Page 54
TMP86CH22UG
7
P3DR
(0003H)
R/W
6
5
4
3
P37
P34
P33
DVO
PWM5
PWM6
PDO5
PDO6
TC5
PPG6
2
1
0
"1"
"1"
"1"
(Initial value: 1**1 1***)
TC6
Note 1: Make sure to write "1" to bit2 to bit0 in P3DR.
Note 2: If a read instruction is executed for P3DR, read data of bits 6 to 5 and bit 2 to 0 are unstable.
P3OUTCR
(0004H)
7
6
5
4
3
2
1
0
P34
P33
SIOEN2
SIOEN1
"0"
(Initial value: **** 0000)
P34, P33
Port P3 output circuit control
(set for each bit individually)
0: Sink open-drain output
1: C-MOS output
SIOEN2
Port P17 control
0: SCK input, Port input, Port output or LCD output
1: SCK output
SIOEN1
Port P16 control
0: Port input, Port output or LCD output
1: SO output
R/W
Note 1: When P16 and P17 is used as port output or SIO output, set in order each registers according to notes of Table 1-2 and
Table 1-3.
Note 2: If a read instruction is executed for P3OUTCR, read data of bits 7 to 5 and bit 0 are unstable.
Note 3: Make sure to write "0" to bit 0 in P3OUTCR.
P3PRD
(0F9DH)
Read only
7
6
5
4
3
P34
P33
2
1
0
Note 1: If a read instruction is executed for P3PRD, read data of bits 7 to 5 and bits 2 to 0 are unstable.
Page 55
5. I/O Ports
5.4 Port P5 (P57 to P50)
TMP86CH22UG
5.4 Port P5 (P57 to P50)
Port P5 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Input/output
mode is spedified by the P5 control register (P5CR).
During reset, the P5DR, P5CR and P5LCR are initialized to “0”.
Port P5 is also used as a segment output of LCD. It is necessary to set registers for using each function. The following table shows register programming for multi function ports.
Table 5-7 Register programming for P57 to P50
Programmed Value
Function (Port P57 to P50)
P5DR[7:0]
P5CR[7:0]
P5LCR[7:0]
*
"0"
"0"
Port "0" output
"0"
"1"
"0"
Port "1" output and UART output
"1"
"1"
"0"
*
*
"1"
Port input
LCD segment output
Note: Asterisk (*) indicates "1" or "0" either of which can be selected.
Table 5-8 Values Read from P5DR and register programming
Conditions
Values Read from P5DR
P5CR
P5LCR
"0"
"0"
Terminal input data
"0"
"1"
"0"
"0"
"1"
Output latch contents
"1"
STOP
OUTEN
P5LCR[i] input
P5LCR[i]
D
Q
D
Q
D
Q
P5CR[i] input
P5CR[i]
Data input (P5DR[i])
Data output (P5DR[i])
P5i
Output latch
LCD data output
Note1 : i = 7 to 0
Note2 : STOP is bit7 in SYSCR1
Note3 : OUTEN is bit4 in SYSCR1
Figure 5-5 Port 5
Page 56
TMP86CH22UG
P5DR
(0005H)
R/W
P5LCR
(0F9FH)
7
6
5
4
3
2
1
0
P57
SEG16
P56
SEG17
P55
SEG18
P54
SEG19
P53
SEG20
P52
SEG21
P51
SEG22
P50
SEG23
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
P5LCR
P5CR
(000AH)
(Initial value: 0000 0000)
7
Port P5/segment output control
(set for each bit individually)
0: P5 input/output port
1: LCD segment output
6
3
5
4
2
1
R/W
0
(Initial value: 0000 0000)
P5CR
P5 port input/output control
(set for each bit individually)
0: Input mode
1: Output mode
R/W
Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the
output latch (P5DR) contents for the port in input mode might be changed by executing a bit manipulation instruction.
Page 57
5. I/O Ports
5.5 Port P6 (P64 to P61)
TMP86CH22UG
5.5 Port P6 (P64 to P61)
Port P6 is an 4-bit input/output port which can be configured as an input or an output in one-bit unit. Input/output
mode is specified by the P6 control register (P6CR1) and input control register (P6CR2).
During reset, the output latch (P6DR) and P6CR1 are initialized to "0", P6CR2 is initialized to "1".
Port P6 is also used as an analog input, Key on Wake up input, timer/counter input and external interrupt input. It
is necessary to set registers for using each function. The following table shows register programming for multi function ports.
Table 5-9 Register programming for P64 to P61
Programmed Value
Function (Port P64 to P61)
P6DR[4:1]
P6CR1[4:1]
P6CR2[4:1]
Port input, external interrupt input or timer counter
input
*
"0"
"1"
Analog input or Key on wake up input
*
"0"
"0"
Port "0" output
"0"
"1"
*
Port "1" output
"1"
"1"
*
Note: Asterisk (*) indicates "1" or "0" either of which can be selected.
Table 5-10 Values Read from P6DR and register programming
Conditions
Values Read from P6DR
P6CR1
P6CR2
"0"
"0"
"0"
"0"
"1"
Terminal input data
"0"
"1"
Output latch contents
"1"
Page 58
TMP86CH22UG
P6CR2[i]
D
Q
D
Q
D
Q
P6CR2[i] input
P6CR1[i]
P6CR1[i] input
Second function input
Data input (P6DR[i])
Data output (P6DR[i])
P6i
STOP
OUTEN
Analog input
AINDS
SAIN
Note1 : i = 3 to 1
Note2 : STOP is bit 7 in SYSCR1.
Note3 : SAIN is AD input select signal.
Note4 : STOP2EN is bit4 in STOPCR.
a) P63 to P61
STOP2
Key-on wakeup
P6CR2[4]
D
Q
D
Q
D
Q
P6CR2[4] input
P6CR1[4]
P6CR1[4] input
Data input (P6DR[4])
Data output (P6DR[4])
P64
STOP
OUTEN
Analog input
AINDS
SAIN
b) P64
Figure 5-6 Port 6 and P6CR
P6DR
(0006H)
R/W
P6CR1
(000BH)
7
6
5
7
6
5
"0"
"0"
"0"
P6CR1
4
3
2
1
P64
AIN4
STOP2
P63
AIN3
INT0
P62
AIN2
ECNT
P61
AIN1
ECIN
4
3
2
1
0
(Initial value: ***0 000*)
0
"0"
(Initial value: ***0 000*)
0: Port input, Key on wake up input, Analog input, external input
or timer counter input
1: Port output
I/O control for port P6
(Specified for each bit)
R/W
Note 1: Make sure to write "0" to bit7 to bit5, bit0 in P6CR1.
P6CR2
(000CH)
7
6
5
4
3
2
1
0
(Initial value: ***1 111*)
P6CR2
P6 port input control
(Specified for each bit)
0: Analog input or Key on wake up input
1: Port input, external interrupt input or timer counter input
Page 59
R/W
5. I/O Ports
5.6 Port P7 (P76 to P70)
TMP86CH22UG
5.6 Port P7 (P76 to P70)
Port P7 is a 7-bit input/output port which can be configured as an input or an output in one-bit unit. Input/output
mode is spedified by the P7 control register (P7CR).
During reset, the P7DR, P7CR and P7LCR are initialized to “0”.
Port P7 is also used as a segment output of LCD. It is necessary to set registers for using each function. The following table shows register programming for multi function ports.
Table 5-11 Register programming for P76 to P70
Programmed Value
Function (Port P76 to P70)
P7DR[6:0]
P7CR[6:0]
P7LCR[6:0]
*
"0"
"0"
Port "0" output
"0"
"1"
"0"
Port "1" output and UART output
"1"
"1"
"0"
*
*
"1"
Port input
LCD segment output
Note: Asterisk (*) indicates "1" or "0" either of which can be selected.
Table 5-12 Values Read from P7DR and register programming
Conditions
Values Read from P7DR
P7CR
P7LCR
"0"
"0"
Terminal input data
"0"
"1"
"0"
"0"
"1"
Output latch contents
"1"
STOP
OUTEN
P7LCR[i] input
P7LCR[i]
D
Q
D
Q
D
Q
P7CR[i] input
P7CR[i]
Data input (P7DR[i])
Data output (P7DR[i])
P7i
Output latch
LCD data output
Note1 : i = 6 to 0
Note2 : STOP is bit7 in SYSCR1.
Note3 : OUTEN is bit4 in SYSCR1.
Figure 5-7 Port 7
Page 60
TMP86CH22UG
P7DR
(0007H)
R/W
P7LCR
(0FA0H)
7
7
6
5
4
3
2
1
0
P76
SEG9
P75
SEG10
P74
SEG11
P73
SEG12
P72
SEG13
P71
SEG14
P70
SEG15
6
5
4
3
2
1
0
"0"
P7LCR
(Initial value: 0000 0000)
(Initial value: 0000 0000)
Port P7/segment output control
(set for each bit individually)
0: P7 input/output port
1: LCD segment output
R/W
Note: Because the LCD driver does not operate correctly, always set "0" to bit7 of P7LCR.
P7CR
(000DH)
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
P7CR
P7 port input/output control
(set for each bit individually)
0: Input mode
1: Output mode
R/W
Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the
output latch (P7DR) contents for the port in input mode might be changed by executing a bit manipulation instruction.
Page 61
5. I/O Ports
5.6 Port P7 (P76 to P70)
TMP86CH22UG
Page 62
TMP86CH22UG
6. Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine.
The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “interrupt request”. Upon the reset release, this signal is initialized to “reset request”.
When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt.
Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to
effect of disturbing noise.
6.1 Watchdog Timer Configuration
Reset release
23
15
Binary counters
Selector
fc/2 or fs/2
fc/221 or fs/213
fc/219 or fs/211
fc/217 or fs/29
Clock
Clear
R
Overflow
1
WDT output
2
S
2
Q
Interrupt request
Internal reset
Q
S R
WDTEN
WDTT
Writing
disable code
Writing
clear code
WDTOUT
Controller
0034H
WDTCR1
0035H
WDTCR2
Watchdog timer control registers
Figure 6-1 Watchdog Timer Configuration
Page 63
Reset
request
INTWDT
interrupt
request
6. Watchdog Timer (WDT)
6.2 Watchdog Timer Control
TMP86CH22UG
6.2 Watchdog Timer Control
The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release.
6.2.1
Malfunction Detection Methods Using the Watchdog Timer
The CPU malfunction is detected, as shown below.
1. Set the detection time, select the output, and clear the binary counter.
2. Clear the binary counter repeatedly within the specified detection time.
If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When
WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and then internal hardware is
initialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog timer interrupt (INTWDT) is generated.
The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/SLEEP
mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated.
Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH
is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow
time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/
4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter than 3/4 of the
time set to WDTCR1<WDTT>.
Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection
Within 3/4 of WDT
detection time
LD
(WDTCR2), 4EH
: Clears the binary counters.
LD
(WDTCR1), 00001101B
: WDTT ← 10, WDTOUT ← 1
LD
(WDTCR2), 4EH
: Clears the binary counters (always clears immediately before and
after changing WDTT).
(WDTCR2), 4EH
: Clears the binary counters.
(WDTCR2), 4EH
: Clears the binary counters.
:
:
LD
Within 3/4 of WDT
detection time
:
:
LD
Page 64
TMP86CH22UG
Watchdog Timer Control Register 1
WDTCR1
(0034H)
7
WDTEN
6
5
4
3
(ATAS)
(ATOUT)
WDTEN
Watchdog timer enable/disable
2
1
0
WDTT
WDTOUT
(Initial value: **11 1001)
0: Disable (Writing the disable code to WDTCR2 is required.)
1: Enable
NORMAL1/2 mode
WDTT
WDTOUT
Watchdog timer detection time
[s]
Watchdog timer output select
DV7CK = 0
DV7CK = 1
SLOW1/2
mode
00
225/fc
217/fs
217/fs
01
223/fc
215/fs
215fs
10
221fc
213/fs
213fs
11
219/fc
211/fs
211/fs
0: Interrupt request
1: Reset request
Write
only
Write
only
Write
only
Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”.
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
don’t care is read.
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
Note 5: To clear WDTEN, set the register in accordance with the procedures shown in “1.2.3 Watchdog Timer Disable”.
Watchdog Timer Control Register 2
WDTCR2
(0035H)
7
6
5
4
3
2
1
0
(Initial value: **** ****)
WDTCR2
Write
Watchdog timer control code
4EH: Clear the watchdog timer binary counter (Clear code)
B1H: Disable the watchdog timer (Disable code)
D2H: Enable assigning address trap area
Others: Invalid
Write
only
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.
Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
6.2.2
Watchdog Timer Enable
Setting WDTCR1<WDTEN> to “1” enables the watchdog timer. Since WDTCR1<WDTEN> is initialized
to “1” during reset, the watchdog timer is enabled automatically after the reset release.
Page 65
6. Watchdog Timer (WDT)
6.2 Watchdog Timer Control
6.2.3
TMP86CH22UG
Watchdog Timer Disable
To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller.
1. Set the interrupt master flag (IMF) to “0”.
2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to “0”.
4. Set WDTCR2 to the disable code (B1H).
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
Example :Disabling the watchdog timer
: IMF ← 0
DI
LD
(WDTCR2), 04EH
: Clears the binary coutner
LDW
(WDTCR1), 0B101H
: WDTEN ← 0, WDTCR2 ← Disable code
Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)
Watchdog Timer Detection Time[s]
WDTT
6.2.4
NORMAL1/2 mode
DV7CK = 0
DV7CK = 1
SLOW
mode
00
2.097
4
4
01
524.288 m
1
1
10
131.072 m
250 m
250 m
11
32.768 m
62.5 m
62.5 m
Watchdog Timer Interrupt (INTWDT)
When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated
by the binary-counter overflow.
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
master flag (IMF).
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt
is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is
held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the
RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
Example :Setting watchdog timer interrupt
LD
SP, 023FH
: Sets the stack pointer
LD
(WDTCR1), 00001000B
: WDTOUT ← 0
Page 66
TMP86CH22UG
6.2.5
Watchdog Timer Reset
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset
time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
219/fc [s]
217/fc
Clock
Binary counter
(WDTT=11)
1
2
3
0
1
2
3
0
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
A reset occurs
(WDTCR1<WDTOUT>= "1")
Write 4EH to WDTCR2
Figure 6-2 Watchdog Timer Interrupt
Page 67
6. Watchdog Timer (WDT)
6.3 Address Trap
TMP86CH22UG
6.3 Address Trap
The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address
traps.
Watchdog Timer Control Register 1
7
WDTCR1
(0034H)
6
ATAS
ATOUT
5
4
3
ATAS
ATOUT
(WDTEN)
2
1
(WDTT)
0
(WDTOUT)
(Initial value: **11 1001)
Select address trap generation in
the internal RAM area
0: Generate no address trap
1: Generate address traps (After setting ATAS to “1”, writing the control code
D2H to WDTCR2 is reguired)
Select opertion at address trap
0: Interrupt request
1: Reset request
Write
only
Watchdog Timer Control Register 2
WDTCR2
(0035H)
7
5
4
3
2
1
0
(Initial value: **** ****)
WDTCR2
6.3.1
6
Write
Watchdog timer control code
and address trap area control
code
D2H: Enable address trap area selection (ATRAP control code)
4EH: Clear the watchdog timer binary counter (WDT clear code)
B1H: Disable the watchdog timer (WDT disable code)
Others: Invalid
Write
only
Selection of Address Trap in Internal RAM (ATAS)
WDTCR1<ATAS> specifies whether or not to generate address traps in the internal RAM area. To execute
an instruction in the internal RAM area, clear WDTCR1<ATAS> to “0”. To enable the WDTCR1<ATAS> setting, set WDTCR1<ATAS> and then write D2H to WDTCR2.
Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of the
setting in WDTCR1<ATAS>.
6.3.2
Selection of Operation at Address Trap (ATOUT)
When an address trap is generated, either the interrupt request or the reset request can be selected by
WDTCR1<ATOUT>.
6.3.3
Address Trap Interrupt (INTATRAP)
While WDTCR1<ATOUT> is “0”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap interrupt (INTATRAP) will be generated.
An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt master flag (IMF).
When an address trap interrupt is generated while the other interrupt including a watchdog timer interrupt is
already accepted, the new address trap is processed immediately and the previous interrupt is held pending.
Therefore, if address trap interrupts are generated continuously without execution of the RETN instruction, too
many levels of nesting may cause a malfunction of the microcontroller.
To generate address trap interrupts, set the stack pointer beforehand.
Page 68
TMP86CH22UG
6.3.4
Address Trap Reset
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap reset will be generated.
When an address trap reset request is generated, the internal hardware is reset. The reset time is maximum
24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Page 69
6. Watchdog Timer (WDT)
6.3 Address Trap
TMP86CH22UG
Page 70
TMP86CH22UG
7. Time Base Timer (TBT)
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base
timer interrupt (INTTBT).
7.1 Time Base Timer
7.1.1
Configuration
MPX
fc/223 or fs/215
fc/221 or fs/213
fc/216 or fs/28
fc/214 or fs/26
fc/213 or fs/25
fc/212 or fs/24
fc/211 or fs/23
fc/29 or fs/2
Source clock
IDLE0, SLEEP0
release request
Falling edge
detector
INTTBT
interrupt request
3
TBTCK
TBTEN
TBTCR
Time base timer control register
Figure 7-1 Time Base Timer configuration
7.1.2
Control
Time Base Timer is controled by Time Base Timer control register (TBTCR).
Time Base Timer Control Register
7
TBTCR
(0036H)
6
(DVOEN)
TBTEN
5
(DVOCK)
Time Base Timer
enable / disable
4
3
(DV7CK)
TBTEN
2
1
0
TBTCK
(Initial Value: 0000 0000)
0: Disable
1: Enable
NORMAL1/2, IDLE1/2 Mode
TBTCK
Time Base Timer interrupt
Frequency select : [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
Mode
000
fc/223
fs/215
fs/215
001
fc/221
fs/213
fs/213
010
fc/216
fs/28
–
011
fc/2
14
6
–
100
fc/213
fs/25
–
101
fc/2
12
4
–
110
fc/211
fs/23
–
111
9
fs/2
–
fc/2
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care
Page 71
fs/2
fs/2
R/W
7. Time Base Timer (TBT)
7.1 Time Base Timer
TMP86CH22UG
Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously.
Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt.
LD
(TBTCR) , 00000010B
; TBTCK ← 010
LD
(TBTCR) , 00001010B
; TBTEN ← 1
; IMF ← 0
DI
SET
(EIRL) . 6
Table 7-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Time Base Timer Interrupt Frequency [Hz]
TBTCK
7.1.3
NORMAL1/2, IDLE1/2 Mode
NORMAL1/2, IDLE1/2 Mode
SLOW1/2, SLEEP1/2 Mode
DV7CK = 0
DV7CK = 1
000
1.91
1
1
001
7.63
4
4
010
244.14
128
–
011
976.56
512
–
100
1953.13
1024
–
101
3906.25
2048
–
110
7812.5
4096
–
111
31250
16384
–
Function
An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider
output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled.
The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set
interrupt period ( Figure 7-2 ).
Source clock
TBTCR<TBTEN>
INTTBT
Interrupt period
Enable TBT
Figure 7-2 Time Base Timer Interrupt
Page 72
TMP86CH22UG
7.2 Divider Output (DVO)
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
buzzer drive. Divider output is from DVO pin.
7.2.1
Configuration
Output latch
D
Data output
Q
DVO pin
MPX
A
B
C Y
D
S
2
fc/213 or fs/25
fc/212 or fs/24
fc/211 or fs/23
fc/210 or fs/22
Port output latch
TBTCR<DVOEN>
DVOCK
DVOEN
TBTCR
DVO pin output
Divider output control register
(a) configuration
(b) Timing chart
Figure 7-3 Divider Output
7.2.2
Control
The Divider Output is controlled by the Time Base Timer Control Register.
Time Base Timer Control Register
7
TBTCR
(0036H)
DVOEN
DVOEN
6
5
DVOCK
4
3
(DV7CK)
(TBTEN)
Divider output
enable / disable
2
1
0
(TBTCK)
(Initial value: 0000 0000)
0: Disable
1: Enable
R/W
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
Mode
00
fc/213
fs/25
fs/25
01
fc/212
fs/24
fs/24
10
fc/211
fs/23
fs/23
11
fc/210
fs/22
fs/22
NORMAL1/2, IDLE1/2 Mode
DVOCK
Divider Output (DVO)
frequency selection: [Hz]
R/W
Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not
change the setting of the divider output frequency.
Page 73
7. Time Base Timer (TBT)
7.2 Divider Output (DVO)
TMP86CH22UG
Example :1.95 kHz pulse output (fc = 16.0 MHz)
LD
(TBTCR) , 00000000B
; DVOCK ← "00"
LD
(TBTCR) , 10000000B
; DVOEN ← "1"
Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Divider Output Frequency [Hz]
DVOCK
NORMAL1/2, IDLE1/2 Mode
DV7CK = 0
DV7CK = 1
SLOW1/2, SLEEP1/2
Mode
00
1.953 k
1.024 k
1.024 k
01
3.906 k
2.048 k
2.048 k
10
7.813 k
4.096 k
4.096 k
11
15.625 k
8.192 k
8.192 k
Page 74
ECIN Pin
ECNT Pin
P33 Pin
2
SEG
1
1
WGPSCK
S
Y
fs/215 or fc/223
fs/25 or fc/213
fs/23 or fc/211
fc/27
fc/23
fs
fc
Edge detector
TC6OUT
PWM6/PDO6/PPG6
fc/214 or fs/26
fc/213 or fs/25
C
D
E
F
G
B
A
H
C
B
A
1
TC1CR1
Frequency
measurement mode
Pulse width
measurement mode
TC1CR2
1 2 1 2 1
Timer/Event count modes
2 2
Y
3
S
Y
Window pulse
generator
TREG1B
TC1CK
TC1S
A
B
C
TC1M
Page 75
TC1C
Figure 8-1 Timer/Counter1
00 S
11
10
SEG
SGP
SGEDG
WGPSCK
TC6OUT
fc/212 or fs/24
Y
2
CMP
TREG1AL TREG1AM TREG1AH
18- bit up-counter
CLEAR signal
Edge detector
SGEDG
1
TC1M
1
TC1SR
1
F/F
INTTC1
TMP86CH22UG
8. 18-Bit Timer/Counter (TC1)
8.1 Configuration
8. 18-Bit Timer/Counter (TC1)
8.2 Control
TMP86CH22UG
8.2 Control
The Timer/counter 1 is controlled by timer/counter 1 control registers (TC1CR1/TC1CR2), an 18-bit timer register
(TREG1A), and an 8-bit internal window gate pulse setting register (TREG1B).
Timer register
TREG1AH
(0012H)
R/W
7
6
5
4
3
2
−
−
−
−
−
−
7
6
5
4
3
2
TREG1AM
(0011H)
R/W
0
(Initial value: ∗∗∗∗ ∗∗00)
TREG1AH
1
0
TREG1AM
7
6
5
TREG1AL
(0010H)
R/W
4
(Initial value: 0000 0000)
3
2
1
0
TREG1AL
7
TREG1B
(0013H)
1
6
5
4
(Initial value: 0000 0000)
3
2
Ta
1
0
Tb
(Initial value: 0000 0000)
NORMAL1/2,IDLE1/2 modes
DV7CK=0
DV7CK=1
SLOW1/2,
SLEEP1/2 modes
(16 - Ta) × 212/fc
(16 - Ta) × 24/fs
(16 - Ta) × 24/fs
WGPSCK
Ta
Tb
Setting "H" level period of the window
gate pulse
00
01
10
Setting "L" level period of the window
gate pulse
00
01
10
13
(16 - Ta) × 2 /fc
(16 - Ta) × 2 /fs
(16 - Ta) × 25/fs
214/fc
26/fs
(16 - Ta) × 26/fs
(16 - Ta) ×
5
(16 - Ta) ×
(16 - Tb) × 212/fc
(16 - Tb) × 24/fs
(16 - Tb) × 24/fs
(16 - Tb) × 213/fc
(16 - Tb) × 25/fs
(16 - Tb) × 25/fs
(16 - Tb) × 214/fc
(16 - Tb) × 26/fs
(16 - Tb) × 26/fs
Page 76
R/W
TMP86CH22UG
Timer/counter 1 control register 1
7
TC1CR1
(0014H)
6
TC1C
5
4
3
TC1S
2
1
TC1CK
0
TC1M
(Initial value: 1000 1000)
TC1C
Counter/overfow flag
controll
0:
1:
Clear Counter/overflow flag ( “1” is automatically set after clearing.)
Not clear Counter/overflow flag
R/W
TC1S
TC1 start control
00:
10:
*1:
Stop and counter clear and overflow flag clear
Start
Reserved
R/W
NORMAL1/2,IDLE1/2 modes
TC1CK
TC1 source clock select
DV7CK="0"
DV7CK="1"
SLOW1/2
mode
SLEEP1/2
mode
fc
fs
fc
fs
fc
-
fc
-
fc/223
fs/215
fs/215
fs/215
13
fs/25
fs/25
fs/25
fc/211
fs/23
7
fc/2
fc/27
fc/23
fc/23
fs/23
-
fs/23
-
000:
001:
010:
011:
100:
101:
110:
fc/2
111:
TC1M
TC1 mode select
00:
01:
10:
11:
R/W
External clock (ECIN pin input)
Timer/Event counter mode
Reserved
Pulse width measurement mode
Frequency measurement mode
R/W
Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] * ; Don’t care
Note 2: Writing to the low-byte of the timer register 1A (TREG1AL, TREG1AM), the compare function is inhibited until the highbyte (TREG1AH) is written.
Note 3: Set the mode and source clock, and edge (selection) when the TC1 stops (TC1S=00).
Note 4: “fc” can be selected as the source clock only in the timer mode during SLOW mode and in the pulse width measurement
mode during NORMAL 1/2 or IDLE 1/2 mode.
Note 5: When a read instruction is executed to the timer register (TREG1A), the counter immediate value, not the register set
value, is read out. Therefore it is impossible to read out the written value of TREG1A. To read the counter value, the read
instruction should be executed when the counter stops to avoid reading unstable value.
Note 6: Set the timer register (TREG1A) to ≥1.
Note 7: When using the timer mode and pulse width measurement mode, set TC1CK (TC1 source clock select) to internal clock.
Note 8: When using the event counter mode, set TC1CK (TC1 source clock select) to external clock.
Note 9: Because the read value is different from the written value, do not use read-modify-write instructions to TREG1A.
Note 10:fc/27, fc/23can not be used as source clock in SLOW/SLEEP mode.
Note 11:The read data of bits 7 to 2 in TREG1AH are always “0”. (Data “1” can not be written.)
Page 77
8. 18-Bit Timer/Counter (TC1)
8.2 Control
TMP86CH22UG
Timer/Counter 1 control register 2
7
TC1CR2
(0015H)
SEG
SEG
SGP
SGEDG
6
5
SGP
4
3
SGEDG
2
WGPSCK
1
0
TC6OUT
"0"
External input clock (ECIN) edge
select
0:
1:
Counts at the falling edge
Counts at the both (falling/rising) edges
Window gate pulse select
00:
01:
10:
11:
ECNT input
Internal window gate pulse (TREG1B)
PWM6/PDO6/PPG6 (TC6)output
Reserved
0:
1:
Interrupts at the falling edge
Interrupts at the falling/rising edges
Window gate pulse interrupt edge
select
NORMAL1/2,IDLE1/2 modes
WGPSCK
TC6OUT
Window gate pulse source clock
select
TC6 output (PWM6/PDO6/PPG6)
external output select
00:
01:
10:
11:
0:
1:
(Initial value: 0000 000*)
R/W
R/W
DV7CK="0"
DV7CK="1"
SLOW1/2
mode
SLEEP1/2
mode
212/fc
24/fs
24/fs
24/fs
13
5
5
2 /fc
2 /fs
2 /fs
25/fs
214/fc
Reserved
26/fs
Reserved
26/fs
Reserved
26/fs
Reserved
Output to P33
No output to P33
R/W
R/W
Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] *; Don't care
Note 2: Set the mode, source clock, and edge (selection) when the TC1 stops (TC1S = 00).
Note 3: If there is no need to use PWM6/PDO6/PPG6 as window gate pulse of TC1 always write "0" to TC6OUT.
Note 4: Make sure to write TC1CR2 "0" to bit 0 in TC1CR2.
Note 5: When using the event counter mode or pulse width measurement mode, set SEG to "0".
Page 78
TMP86CH22UG
TC1 status register
TC1SR
(0016H)
7
6
5
4
3
2
1
0
HECF
HEOVF
"0"
"0"
"0"
"0"
"0"
"0"
HECF
HEOVF
Operating Status monitor
0:
1:
Stop (during Tb) or disable
Under counting (during Ta)
Counter overflow monitor
0:
1:
No overflow
Overflow status
(Initial value: 0000 0000)
Read
only
8.3 Function
TC1 has four operating modes. The timer mode of the TC1 is used at warm-up when switching form SLOW mode
to NORMAL2 mode.
8.3.1
Timer mode
In this mode, counting up is performed using the internal clock. The contents of TREGIA are compared with
the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared.
Counting up resumes after the counter is cleared.
Table 8-1 Source clock (internal clock) of Timer/Counter 1
Source Clock
Resolution
NORMAL1/2, IDLE1/2 Mode
Maximum Time Setting
SLOW Mode
SLEEP Mode
fc = 16 MHz
fs =32.768
kHz
fc = 16 MHz
fs =32.768
kHz
fs/215 [Hz]
fs/215 [Hz]
fs/215 [Hz]
0.52 s
1s
38.2 h
72.8 h
fc/213
fs/25
fs/25
fs/25
512 ms
0.98 ms
2.2 min
4.3 min
fc/211
fs/23
fs/23
fs/23
128 ms
244 ms
0.6 min
1.07 min
fc/27
fc/27
-
-
8 ms
-
2.1 s
-
fc/23
fc/23
-
-
0.5 ms
-
131.1 ms
-
fc
fc
fc (Note)
-
62.5 ns
-
16.4 ms
-
fs
fs
-
-
-
30.5 ms
-
8s
DV7CK = 0
DV7CK = 1
fc/223 [Hz]
Note: When fc is selected for the source clock in SLOW mode, the lower bits 11 of TREG1A is invalid, and a match of the upper
bits 7 makes interrupts.
Page 79
8. 18-Bit Timer/Counter (TC1)
8.3 Function
TMP86CH22UG
Command Start
Internal clock
Up counter
0
TREG1A
1
2
3
4
n-1
n 0
1
2
3
4
5
6
n
Match detect
Counter clear
INTTC1 interrupt
Figure 8-2 Timing chart for timer mode
8.3.2
Event Counter mode
It is a mode to count up at the falling edge of the ECIN pin input. When using this mode, set
TC1CR1<TC1CK> to the external clock and then set TC1CR2<SEG> to “0” (Both edges can not be used).
The countents of TREG1A are compared with the contents of up-counter. If a match is found, an INTTC1
interrupt is generated, and the counter is cleared. Counting up resumes for ECIN pin input edge each after the
counter is cleared.
The maximum applied frequency is fc/24 [Hz] in NORMAL 1/2 or IDLE 1/2 mode and fs/24[Hz] in SLOW
or SLEEP mode . Two or more machine cycles are required for both the “H” and “L” levels of the pulse width.
Start
ECIN pin input
Up counter
TREG1A
0
1
2
n-1
n
0
1
n
Match Detect
Counter clear
INTTC1 interrupt
Figure 8-3 Event counter mode timing chart
Page 80
2
TMP86CH22UG
8.3.3
Pulse Width Measurement mode
In this mode, pulse widths are counted on the falling edge of logical AND-ed pulse between ECIN pin input
(window pulse) and the internal clock. When using this mode, set TC1CR1<TC1CK> to suitable internal clock
and then set TC1CR2<SEG> to “0” (Both edges can not be used).
An INTTC1 interrupt is generated when the ECIN input detects the falling edge of the window pulse or both
rising and falling edges of the window pulse, that can be selected by TC1CR2<SGEDG>.
The contents of TREG1A should be read while the count is stopped (ECIN pin is low), then clear the counter
using TC1CR1<TC1C> (Normally, execute these process in the interrupt program).
When the counter is not cleared by TC1CR1<TC1C>, counting-up resumes from previous stopping value.
When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time, TC1SR<HEOVF>
is set to “1”. TC1SR<HEOVF> remains the previous data until the counter is required to be cleared by
TC1CR1<TC1C>.
Note:In pulse width measurement mode, if TC1CR1<TC1S> is written to "00" while ECIN input is "1", INTTC1 interrupt occurs. According to the following step, when timer counter is stopped, INTTC1 interrupt latch should be
cleared to "0".
Example :
TC1STOP :
¦
¦
DI
; Clear IMF
CLR
(EIRL). 7
; Clear bit7 of EIRL
LD
(TC1CR1), 00011010B
; Stop timer couter 1
LD
(ILL), 01111111B
; Clear bit7 of ILL
SET
(EIRL). 7
; Set bit7 of EIRL
EI
; Set IMF
¦
¦
Note 1: When SGEDG (window gate pulse interrupt edge select) is set to both edges and ECIN pin input is "1" in
the pulse width measurement mode, an INTTC1 interrupt is generated by setting TC1S (TC1 start control)
to "10" (start).
Note 2: In the pulse width measurement mode, HECF (operating status monitor) cannot used.
Note 3: Because the up counter is counted on the falling edge of logical AND-ed pulse (between ECIN pin input and
the internal clock), if ECIN input becomes falling edge while internal source clock is "H" level, the up
counter stops plus "1".
Count Start
Count Stop
Count Start
ECIN pin input
Internal clock
AND-ed pulse
(Internal signal)
Up counter
0
1
2
3
n-2
n-1
n
n+1
0
Read Clear
INTTC1 interrupt
Interrupt
TC1CR1<TC1C>
Figure 8-4 Pulse width measurement mode timing chart
Page 81
1
2
8. 18-Bit Timer/Counter (TC1)
8.3 Function
TMP86CH22UG
8.3.4
Frequency Measurement mode
In this mode, the frequency of ECIN pin input pulse is measured. When using this mode, set
TC1CR1<TC1CK> to the external clock.
The edge of the ECIN input pulse is counted during “H” level of the window gate pulse selected by
TC1CR2<SGP>. To use ECNT input as a window gate pulse, TC1CR2<SGP> should be set to “00”.
An INTTC1 interrupt is generated on the falling edge or both the rising/falling edges of the window gate
pulse, that can be selected by TC1CR2<SGEDG>. In the interrupt service program, read the contents of
TREG1A while the count is stopped (window gate pulse is low), then clear the counter using
TC1CR1<TC1C>. When the counter is not cleared, counting up resumes from previous stopping value.
The window pulse status can be monitored by TC1SR<HECF>.
When up counter is counted up from 3FFFFH to 00000H, an overflow occurs. At that time,
TC1SR<HEOVF> is set to “1”. TC1SR<HEOVF> remains the previous data until the counter is required to be
cleared by TC1CR1<TC1C>.
Using TC6 output (PWM6/PDO6/PPG6) for the window gate pulse, external output of PWM6/PDO6/PPG6 to
P33 can be controlled using TC1CR2<TC6OUT>. Zero-clearing TC1CR2<TC6OUT> outputs PWM6/
PDO6/PPG6 to P33; setting 1 in TC1CR2<TC6OUT> does not output PWM6/PDO6/PPG6 to P33.
(TC1CR2<TC6OUT> is used to control output to P33 only. Thus, use the timer counter 6 control register to
operate/stop PWM6/PDO6/PPG6.)
When the internal window gate pulse is selected, the window gate pulse is set as follows.
Table 8-2 Internal window gate pulse setting time
NORMAL1/2,IDLE1/2 modes
DV7CK=1
SLOW1/2,
SLEEP1/2 modes
(16 - Ta) ×
212/fc
(16 - Ta) × 24/fs
(16 - Ta) × 24/fs
(16 - Ta) ×
213/fc
25/fs
(16 - Ta) × 25/fs
WGPSCK
DV7CK=0
Ta
Tb
Setting "H" level period of the window
gate pulse
00
01
10
Setting "L" level period of the window
gate pulse
00
01
10
14
(16 - Ta) × 2 /fc
(16 - Ta) ×
6
(16 - Ta) × 2 /fs
(16 - Ta) × 26/fs
(16 - Tb) × 212/fc
(16 - Tb) × 24/fs
(16 - Tb) × 24/fs
(16 - Tb) × 213/fc
(16 - Tb) × 25/fs
(16 - Tb) × 25/fs
(16 - Tb) × 214/fc
(16 - Tb) × 26/fs
(16 - Tb) × 26/fs
R/W
The internal window gate pulse consists of “H” level period (Ta) that is counting time and “L” level period
(Tb) that is counting stop time. Ta or Tb can be individually set by TREG1B. One cycle contains Ta + Tb.
Note 1: Because the internal window gate pulse is generated in synchronization with the internal divider, it may be
delayed for a maximum of one cycle of the source clock (WGPSCK) immediately after start of the timer.
Note 2: Set the internal window gate pulse when the timer counter is not operating or during the Tb period. When
Tb is overwritten during the Tb period, the update is valid from the next Tb period.
Note 3: In case of TC1CR2<SEG> = "1", if window gate pulse becomes falling edge, the up counter stops plus "1"
regardless of ECIN input level. Therefore, if ECIN is always "H" or "L" level, count value becomes "1".
Note 4: In case of TC1CR2<SEG> = "0", because the up counter is counted on the falling edge of logical AND-ed
pulse (between ECIN pin input and window gate pulse), if window gate pulse becomes falling edge while
ECIN input is "H" level, the up counter stops plus "1". Therefore, if ECIN input is always "H" level, count
value becomes "1".
Page 82
TMP86CH22UG
Table 8-3 Table Setting Ta and Tb (WGPSCK = 10, fc = 16 MHz)
Setting Value
Setting time
Setting Value
Setting time
0
16.38ms
8
8.19ms
1
15.36ms
9
7.17ms
2
14.34ms
A
6.14ms
3
13.31ms
B
5.12ms
4
12.29ms
C
4.10ms
5
11.26ms
D
3.07ms
6
10.24ms
E
2.05ms
7
9.22ms
F
1.02ms
Table 8-4 Table Setting Ta and Tb (WGPSCK = 10, fs = 32.768 kHz)
Setting Valuen
Setting time
Setting Value
Setting time
0
31.25ms
8
15.63ms
1
29.30ms
9
13.67ms
2
27.34ms
A
11.72ms
3
25.39ms
B
9.77ms
4
23.44ms
C
7.81ms
5
21.48ms
D
5.86ms
6
19.53ms
E
3.91ms
7
17.58ms
F
1.95ms
Page 83
8. 18-Bit Timer/Counter (TC1)
8.3 Function
TMP86CH22UG
ECIN pin input
Window gate
pulse
Ta
Ta
Tb
AND-ed pulse
(Internal signal)
Up counter
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Read Clear
INTTC1 interrupt
TC1CR1<TC1C>
a) TC1CR2<SEG> = "0"
TC1CR2<SEG>
ECIN pin input
Window gate
pulse
Up counter
INTTC1 interrupt
Ta
0
Ta
Tb
1 2 3 4 5 6 7 8 9 10 11 12
13
0
1 2 3 4 5 6 7 8 9 10 11
12
Read Clear
TC1CR1<TC1C>
a) TC1CR2<SEG> = "1"
Figure 8-5 Timing chart for the frequency measurement mode (Window gate pulse falling
interrupt)
Page 84
TMP86CH22UG
9. 8-Bit TimerCounter (TC5, TC6)
9.1 Configuration
PWM mode
Overflow
fc/211 or fs/23
7
fc/2
5
fc/2
fc/23
fs
fc/2
fc
TC6 pin
A
B
C
D
E
F
G
H
Y
A
B
INTTC6
interrupt request
Clear
Y
8-bit up-counter
TC6S
S
PDO, PPG mode
A
B
S
16-bit
mode
S
TC6M
TC6S
TFF6
Toggle
Q
Set
Clear
Y
16-bit mode
Timer, Event
Counter mode
S
TC6CK
PDO6/PWM6/
PPG6 pin
Timer F/F6
A
Y
TC6CR
B
TTREG6
PWREG6
PWM, PPG mode
DecodeEN
PDO, PWM,
PPG mode
TFF6
16-bit
mode
TC5S
PWM mode
fc/211 or fs/23
fc/27
5
fc/2
3
fc/2
fs
fc/2
fc
TC5 pin
Y
8-bit up-counter
Overflow
16-bit mode
PDO mode
16-bit mode
Timer,
Event Couter mode
S
TC5M
TC5S
TFF5
INTTC5
interrupt request
Clear
A
B
C
D
E
F
G
H
Toggle
Q
Set
Clear
PDO5/PWM5/
pin
Timer F/F5
TC5CK
TC5CR
PWM mode
TTREG5
PWREG5
DecodeEN
TFF5
Figure 9-1 8-Bit TimerCouter 5, 6
Page 85
PDO, PWM mode
16-bit mode
9. 8-Bit TimerCounter (TC5, TC6)
9.1 Configuration
TMP86CH22UG
9.2 TimerCounter Control
The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers
(TTREG5, PWREG5).
TimerCounter 5 Timer Register
TTREG5
(001EH)
R/W
7
PWREG5
(002AH)
R/W
7
6
5
4
3
2
1
0
(Initial value: 1111 1111)
6
5
4
3
2
1
0
(Initial value: 1111 1111)
Note 1: Do not change the timer register (TTREG5) setting while the timer is running.
Note 2: Do not change the timer register (PWREG5) setting in the operating mode except the 8-bit and 16-bit PWM modes while
the timer is running.
TimerCounter 5 Control Register
TC5CR
(001AH)
TFF5
7
TFF5
6
5
4
TC5CK
Time F/F5 control
3
2
TC5S
0:
1:
1
0
TC5M
(Initial value: 0000 0000)
Clear
Set
R/W
NORMAL1/2, IDLE1/2 mode
TC5CK
Operating clock selection [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/211
fs/23
fs/23
001
fc/27
fc/27
–
010
fc/25
fc/25
–
011
fc/23
fc/23
–
100
fs
fs
fs
101
fc/2
fc/2
–
110
fc
fc
fc (Note 8)
111
TC5S
TC5 start control
0:
1:
000:
001:
TC5M
TC5M operating mode select
010:
011:
1**:
R/W
TC5 pin input
Operation stop and counter clear
Operation start
R/W
8-bit timer/event counter mode
8-bit programmable divider output (PDO) mode
8-bit pulse width modulation (PWM) output mode
16-bit mode
(Each mode is selectable with TC6M.)
Reserved
R/W
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz]
Note 2: Do not change the TC5M, TC5CK and TFF5 settings while the timer is running.
Note 3: To stop the timer operation (TC5S= 1 → 0), do not change the TC5M, TC5CK and TFF5 settings. To start the timer operation (TC5S= 0 → 1), TC5M, TC5CK and TFF5 can be programmed.
Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC6CR<TC6M>, where TC5M must
be fixed to 011.
Note 5: To use the TimerCounter in the 16-bit mode, select the source clock by programming TC5CK. Set the timer start control
and timer F/F control by programming TC6CR<TC6S> and TC6CR<TFF6>, respectively.
Note 6: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table
9-1 and Table 9-2.
Page 86
TMP86CH22UG
Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93.
Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode.
Page 87
9. 8-Bit TimerCounter (TC5, TC6)
9.1 Configuration
TMP86CH22UG
The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers
(TTREG6 and PWREG6).
TimerCounter 6 Timer Register
TTREG6
(001FH)
R/W
7
PWREG6
(002BH)
R/W
7
6
5
4
3
2
1
0
(Initial value: 1111 1111)
6
5
4
3
2
1
0
(Initial value: 1111 1111)
Note 1: Do not change the timer register (TTREG6) setting while the timer is running.
Note 2: Do not change the timer register (PWREG6) setting in the operating mode except the 8-bit and 16-bit PWM modes while
the timer is running.
TimerCounter 6 Control Register
TC6CR
(001BH)
TFF6
7
TFF6
6
5
4
TC6CK
Timer F/F6 control
3
2
TC6S
0:
1:
1
0
TC6M
(Initial value: 0000 0000)
Clear
Set
R/W
NORMAL1/2, IDLE1/2 mode
TC6CK
Operating clock selection [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/211
fs/23
fs/23
001
fc/27
fc/27
–
010
fc/25
fc/25
–
011
fc/2
3
3
–
100
fs
fs
fs
101
fc/2
fc/2
–
110
fc
fc
–
111
TC6S
TC6 start control
0:
1:
000:
001:
010:
TC6M
TC6M operating mode select
011:
100:
101:
110:
111:
fc/2
R/W
TC6 pin input
Operation stop and counter clear
Operation start
R/W
8-bit timer/event counter mode
8-bit programmable divider output (PDO) mode
8-bit pulse width modulation (PWM) output mode
Reserved
16-bit timer/event counter mode
Warm-up counter mode
16-bit pulse width modulation (PWM) output mode
16-bit PPG mode
R/W
Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz]
Note 2: Do not change the TC6M, TC6CK and TFF6 settings while the timer is running.
Note 3: To stop the timer operation (TC6S= 1 → 0), do not change the TC6M, TC6CK and TFF6 settings.
To start the timer operation (TC6S= 0 → 1), TC6M, TC6CK and TFF6 can be programmed.
Note 4: When TC6M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC6 overflow signal regardless of the
TC5CK setting.
Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC6M, where TC5CR<TC5 M>
must be set to 011.
Page 88
TMP86CH22UG
Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR<TC5CK>. Set the timer start
control and timer F/F control by programming TC6S and TFF6, respectively.
Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table
9-1 and Table 9-2.
Note 8: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93.
Note 9: To use the PDO, PWM or PPG mode, a pulse is not output from the timer output pin when TC1CR2<TC6OUT> is set to 1.
To output a pulse from the timer output pin, clear TC1CR2<TC6OUT> to 0.
Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes)
Operating mode
fc/211
or
fs/2
fc/27
fc/25
fc/23
fs
fc/2
fc
TC5
pin input
TC6
pin input
3
8-bit timer
Ο
Ο
Ο
Ο
–
–
–
–
–
8-bit event counter
–
–
–
–
–
–
–
Ο
Ο
8-bit PDO
Ο
Ο
Ο
Ο
–
–
–
–
–
8-bit PWM
Ο
Ο
Ο
Ο
Ο
Ο
Ο
–
–
16-bit timer
Ο
Ο
Ο
Ο
–
–
–
–
–
16-bit event counter
–
–
–
–
–
–
–
Ο
–
Warm-up counter
–
–
–
–
Ο
–
–
–
–
16-bit PWM
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
–
16-bit PPG
Ο
Ο
Ο
Ο
–
–
–
Ο
–
Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on
lower bit (TC5CK).
Note 2: Ο : Available source clock
Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes)
Operating mode
fc/211
or
fc/27
fc/25
fc/23
fs
fc/2
fc
TC5
pin input
TC6
pin input
fs/23
8-bit timer
Ο
–
–
–
–
–
–
–
–
8-bit event counter
–
–
–
–
–
–
–
Ο
Ο
8-bit PDO
Ο
–
–
–
–
–
–
–
–
8-bit PWM
Ο
–
–
–
Ο
–
–
–
–
16-bit timer
Ο
–
–
–
–
–
–
–
–
16-bit event counter
–
–
–
–
–
–
–
Ο
–
Warm-up counter
–
–
–
–
–
–
Ο
–
–
16-bit PWM
Ο
–
–
–
Ο
–
–
Ο
–
16-bit PPG
Ο
–
–
–
–
–
–
Ο
–
Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on
lower bit (TC5CK).
Note2: Ο : Available source clock
Page 89
9. 8-Bit TimerCounter (TC5, TC6)
9.1 Configuration
TMP86CH22UG
Table 9-3 Constraints on Register Values Being Compared
Operating mode
Register Value
8-bit timer/event counter
1≤ (TTREGn) ≤255
8-bit PDO
1≤ (TTREGn) ≤255
8-bit PWM
2≤ (PWREGn) ≤254
16-bit timer/event counter
1≤ (TTREG6, 5) ≤65535
Warm-up counter
256≤ (TTREG6, 5) ≤65535
16-bit PWM
2≤ (PWREG6, 5) ≤65534
16-bit PPG
and
(PWREG6, 5) + 1 < (TTREG6, 5)
1≤ (PWREG6, 5) < (TTREG6, 5) ≤65535
Note: n = 5 to 6
Page 90
TMP86CH22UG
9.3 Function
The TimerCounter 5 and 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter,
16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes.
9.3.1
8-Bit Timer Mode (TC5 and 6)
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting.
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after the programming. Therefore, if TTREGi is changed while the timer is running, an expected operation
may not be obtained.
Note 3: j = 5, 6
Table 9-4 Source Clock for TimerCounter 5, 6 (Internal Clock)
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211 [Hz]
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
32.6 ms
62.3 ms
fc/27
fc/27
–
8 µs
–
2.0 ms
–
fc/25
fc/25
–
2 µs
–
510 µs
–
fc/23
fc/23
–
500 ns
–
127.5 µs
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 µs later
(TimerCounter6, fc = 16.0 MHz)
(TTREG6), 0AH
: Sets the timer register (80 µs÷27/fc = 0AH).
(EIRH). 5
: Enables INTTC6 interrupt.
LD
(TC6CR), 00010000B
: Sets the operating cock to fc/27, and 8-bit timer mode.
LD
(TC6CR), 00011000B
: Starts TC6.
LD
DI
SET
EI
Page 91
9. 8-Bit TimerCounter (TC5, TC6)
9.1 Configuration
TMP86CH22UG
TC6CR<TC6S>
Internal
Source Clock
1
Counter
TTREG6
?
2
3
n-1
n 0
1
2
n-1
n 0
1
2
0
n
Match detect
Counter clear
INTTC6 interrupt request
Counter clear
Match detect
Figure 9-2 8-Bit Timer Mode Timing Chart (TC6)
9.3.2
8-Bit Event Counter Mode (TC5, 6)
In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.
When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and
the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input
pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24
Hz in the SLOW1/2 or SLEEP1/2 mode.
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output
pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is
not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in
effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an
expected operation may not be obtained.
Note 3: j = 5, 6
TC6CR<TC6S>
TC6 pin input
0
Counter
TTREG6
?
1
2
n-1
n 0
1
2
n-1
n 0
1
2
0
n
Match detect
INTTC6 interrupt request
Counter
clear
Match detect
Counter
clear
Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC6)
9.3.3
8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)
This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin.
In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and
the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the
timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by
TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.
To use the programmable divider output, set the output latch of the I/O port to 1.
Page 92
TMP86CH22UG
Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz)
Setting port
LD
(TTREG6), 3DH
: 1/1024÷27/fc÷2 = 3DH
LD
(TC6CR), 00010001B
: Sets the operating clock to fc/27, and 8-bit PDO mode.
LD
(TC6CR), 00011001B
: Starts TC6.
Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running.
Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new
value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed
while the timer is running, an expected operation may not be obtained.
Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> setting upon stopping of the timer.
Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the PDOj pin to the high level.
Note 3: j = 5, 6
Page 93
Page 94
?
INTTC6 interrupt request
PDO6 pin
Timer F/F6
TTREG6
Counter
Internal
source clock
TC6CR<TFF6>
TC6CR<TC6S>
0
n
1
Match detect
2
n 0
1
Match detect
2
n 0
1
Match detect
2
n 0
1
Match detect
2
n 0
1
2
3
Set F/F
Held at the level when the timer
is stopped
0
Write of "1"
9.1 Configuration
9. 8-Bit TimerCounter (TC5, TC6)
TMP86CH22UG
Figure 9-4 8-Bit PDO Mode Timing Chart (TC6)
TMP86CH22UG
9.3.4
8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6)
This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The
up-counter counts up using the internal clock.
When a match between the up-counter and the PWREGj value is detected, the logic level output from the
timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the
timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The
INTTCj interrupt request is generated at this time.
Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be generated. Upon reset, the timer F/Fj is cleared to 0.
(The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.)
Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be
changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the
INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immediately after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output,
the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the
reading data of PWREGj is previous value until INTTCj is generated.
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is
generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse
different from the programmed value until the next INTTCj interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is
stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the
TCjCR<TFFj> upon stopping of the timer.
Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped
CLR (TCjCR).3: Stops the timer.
CLR (TCjCR).7: Sets the PWMj pin to the high level.
Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP
mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWMj pin during the warm-up period time after exiting the STOP mode.
Note 4: j = 5, 6
Table 9-5 PWM Output Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211 [Hz]
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
32.8 ms
62.5 ms
fc/2
7
–
8 µs
–
2.05 ms
–
fc/2
5
–
2 µs
–
512 µs
–
fc/2
7
fc/2
5
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
fc/23
fc/23
–
500 ns
–
128 µs
–
fs
fs
fs
30.5 µs
30.5 µs
7.81 ms
7.81 ms
fc/2
fc/2
–
125 ns
–
32 µs
–
fc
fc
–
62.5 ns
–
16 µs
–
Page 95
Page 96
?
Shift registar
0
Shift
INTTC6 interrupt request
PWM6 pin
Timer F/F6
?
PWREG6
Counter
Internal
source clock
TC6CR<TFF6>
TC6CR<TC6S>
n
n
n
Match detect
1
n
n+1
Shift
FF
0
n
n
n+1
m
One cycle period
Write to PWREG4
Match detect
1
Shift
FF
0
m
m
m+1
p
Write to PWREG4
Match detect
m
1
Shift
FF
0
p
p
Match detect
1
p
9.1 Configuration
9. 8-Bit TimerCounter (TC5, TC6)
TMP86CH22UG
Figure 9-5 8-Bit PWM Mode Timing Chart (TC6)
TMP86CH22UG
9.3.5
16-Bit Timer Mode (TC5 and 6)
In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascadable to form a 16-bit timer.
When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the
timer is started by setting TC6CR<TC6S> to 1, an INTTC6 interrupt is generated and the up-counter is cleared.
After being cleared, the up-counter continues counting. Program the upper byte and lower byte in this order in
the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the timer mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj, and PPGj pins may output a pulse.
Note 2: In the timer mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the
shift register configuration in the timer mode, the new value programmed in TTREGj is in effect immediately
after programming of TTREGj. Therefore, if TTREGj is changed while the timer is running, an expected
operation may not be obtained.
Note 3: j = 5, 6
Table 9-6 Source Clock for 16-Bit Timer Mode
Source Clock
Resolution
NORMAL1/2, IDLE1/2 mode
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211
fs/23
fs/23
128 µs
244.14 µs
8.39 s
16 s
fc/27
fc/27
–
8 µs
–
524.3 ms
–
fc/25
fc/25
–
2 µs
–
131.1 ms
–
fc/23
fc/23
–
500 ns
–
32.8 ms
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later
(fc = 16.0 MHz)
(TTREG5), 927CH
: Sets the timer register (300 ms÷27/fc = 927CH).
(EIRH). 5
: Enables INTTC6 interrupt.
LD
(TC5CR), 13H
:Sets the operating cock to fc/27, and 16-bit timer mode
(lower byte).
LD
(TC6CR), 04H
: Sets the 16-bit timer mode (upper byte).
LD
(TC6CR), 0CH
: Starts the timer.
LDW
DI
SET
EI
TC6CR<TC6S>
Internal
source clock
0
Counter
TTREG5
(Lower byte)
TTREG6
(Upper byte)
?
?
INTTC6 interrupt request
1
2
3
mn-1 mn 0
1
2
mn-1 mn 0
1
n
m
Match
detect
Counter
clear
Match
detect
Counter
clear
Figure 9-6 16-Bit Timer Mode Timing Chart (TC5 and TC6)
Page 97
2
0
9. 8-Bit TimerCounter (TC5, TC6)
9.1 Configuration
9.3.6
TMP86CH22UG
16-Bit Event Counter Mode (TC5 and 6)
In the event counter mode, the up-counter counts up at the falling edge to the TC5 pin. The TimerCounter 5
and 6 are cascadable to form a 16-bit event counter.
When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after
the timer is started by setting TC6CR<TC6S> to 1, an INTTC6 interrupt is generated and the up-counter is
cleared.
After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC5 pin.
Two machine cycles are required for the low- or high-level pulse input to the TC5 pin.
Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 in
the SLOW1/2 or SLEEP1/2 mode. Program the lower byte (TTREG5), and upper byte (TTREG6) in this
order in the timer register. (Programming only the upper or lower byte should not be attempted.)
Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.
Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in
the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect immediately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation
may not be obtained.
Note 3: j = 5, 6
9.3.7
16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)
This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The
TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator.
The counter counts up using the internal clock or external clock.
When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the
logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The
logic level output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the
counter is cleared. The INTTC6 interrupt is generated at this time.
Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or
SLEEP1/2 mode.
Since the initial value can be set to the timer F/F6 by TC6CR<TFF6>, positive and negative pulses can be
generated. Upon reset, the timer F/F6 is cleared to 0.
(The logic level output from the PWM6 pin is the opposite to the timer F/F6 logic level.)
Since PWREG6 and 5 in the PWM mode are serially connected to the shift register, the values set to
PWREG6 and 5 can be changed while the timer is running. The values set to PWREG6 and 5 during a run of
the timer are shifted by the INTTCj interrupt request and loaded into PWREG6 and 5. While the timer is
stopped, the values are shifted immediately after the programming of PWREG6 and 5. Set the lower byte
(PWREG5) and upper byte (PWREG5) in this order to program PWREG6 and 5. (Programming only the lower
or upper byte of the register should not be attempted.)
If executing the read instruction to PWREG6 and 5 during PWM output, the values set in the shift register is
read, but not the values set in PWREG6 and 5. Therefore, after writing to the PWREG6 and 5, reading data of
PWREG6 and 5 is previous value until INTTC6 is generated.
For the pin used for PWM output, the output latch of the I/O port must be set to 1.
Note 1: In the PWM mode, program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt
request is generated (normally in the INTTC6 interrupt service routine.) If the programming of PWREGj and
the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of
pulse different from the programmed value until the next INTTC6 interrupt request is generated.
Note 2: When the timer is stopped during PWM output, the PWM6 pin holds the output status when the timer is
stopped. To change the output status, program TC6CR<TFF6> after the timer is stopped. Do not program
TC6CR<TFF6> upon stopping of the timer.
Example: Fixing thePWM6 pin to the high level when the TimerCounter is stopped
Page 98
TMP86CH22UG
CLR (TC6CR).3: Stops the timer.
CLR (TC6CR).7 : Sets the PWM6 pin to the high level.
Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM6
pin during the warm-up period time after exiting the STOP mode.
Table 9-7 16-Bit PWM Output Mode
Source Clock
NORMAL1/2, IDLE1/2 mode
Resolution
Repeated Cycle
DV7CK = 0
DV7CK = 1
SLOW1/2,
SLEEP1/2
mode
fc/211
fs/23 [Hz]
fs/23 [Hz]
128 µs
244.14 µs
8.39 s
16 s
fc/27
fc/27
–
8 µs
–
524.3 ms
–
fc/25
fc/25
–
2 µs
–
131.1 ms
–
fc/23
fc/23
–
500ns
–
32.8 ms
–
fc = 16 MHz
fs = 32.768 kHz
fc = 16 MHz
fs = 32.768 kHz
fs
fs
fs
30.5 µs
30.5 µs
fc/2
fc/2
–
125 ns
–
8.2 ms
–
fc
fc
–
62.5 ns
–
4.1 ms
–
2
s
Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz)
Setting ports
LDW
(PWREG5), 07D0H
: Sets the pulse width.
LD
(TC5CR), 33H
: Sets the operating clock to fc/23, and 16-bit PWM output
mode (lower byte).
LD
(TC6CR), 056H
: Sets TFF6 to the initial value 0, and 16-bit PWM signal
generation mode (upper byte).
LD
(TC6CR), 05EH
: Starts the timer.
Page 99
2s
Page 100
?
?
PWREG6
(Upper byte)
16-bit
shift register
0
a
Shift
INTTC6 interrupt request
PWM6 pin
Timer F/F6
?
PWREG5
(Lower byte)
Counter
Internal
source clock
TC6CR<TFF6>
TC6CR<TC6S>
an
n
an
Match detect
1
an
an+1
Shift
FFFF
0
an
an
an+1
m
b
One cycle period
Write to PWREG6
Write to PWREG5
Match detect
1
Shift
FFFF
0
bm
bm bm+1
p
c
Write to PWREG6
Write to PWREG5
Match detect
bm
1
Shift
FFFF
0
cp
Match detect
cp
1
cp
9.1 Configuration
9. 8-Bit TimerCounter (TC5, TC6)
TMP86CH22UG
Figure 9-7 16-Bit PWM Mode Timing Chart (TC5 and TC6)
TMP86CH22UG
9.3.8
16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6)
This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascadable to enter the 16-bit PPG mode.
The counter counts up using the internal clock or external clock. When a match between the up-counter and
the timer register (PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is
switched to the opposite state. The counter continues counting. The logic level output from the timer F/F6 is
switched to the opposite state again when a match between the up-counter and the timer register (TTREG5,
TTREG6) value is detected, and the counter is cleared. The INTTC6 interrupt is generated at this time.
Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or
SLEEP1/2 mode.
Since the initial value can be set to the timer F/F6 by TC6CR<TFF6>, positive and negative pulses can be
generated. Upon reset, the timer F/F6 is cleared to 0.
(The logic level output from the PPG6 pin is the opposite to the timer F/F6.)
Set the lower byte and upper byte in this order to program the timer register. (TTREG5 → TTREG6,
PWREG5 → PWREG6) (Programming only the upper or lower byte should not be attempted.)
For PPG output, set the output latch of the I/O port to 1.
Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz)
Setting ports
LDW
(PWREG5), 07D0H
: Sets the pulse width.
LDW
(TTREG5), 8002H
: Sets the cycle period.
LD
(TC5CR), 33H
: Sets the operating clock to fc/23, and16-bit PPG mode
(lower byte).
LD
(TC6CR), 057H
: Sets TFF6 to the initial value 0, and 16-bit
PPG mode (upper byte).
LD
(TC6CR), 05FH
: Starts the timer.
Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since
PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi.
Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not
be obtained.
Note 2: When the timer is stopped during PPG output, the PPG6 pin holds the output status when the timer is
stopped. To change the output status, program TC6CR<TFF6> after the timer is stopped. Do not change
TC6CR<TFF6> upon stopping of the timer.
Example: Fixing the PPG6 pin to the high level when the TimerCounter is stopped
CLR (TC6CR).3: Stops the timer
CLR (TC6CR).7: Sets the PPG6 pin to the high level
Note 3: i = 5, 6
Page 101
Page 102
?
TTREG6
(Upper byte)
INTTC6 interrupt request
PPG6 pin
Timer F/F6
?
?
TTREG5
(Lower byte)
PWREG6
(Upper byte)
n
PWREG5
(Lower byte)
?
0
Counter
Internal
source clock
TC6CR<TFF6>
TC6CR<TC6S>
m
r
q
mn
Match detect
1
mn mn+1
Match detect
qr-1 qr 0
mn
Match detect
1
mn mn+1
Match detect
qr-1 qr 0
mn
Match detect
1
F/F clear
0
Held at the level when the timer
stops
mn mn+1
Write of "0"
9.1 Configuration
9. 8-Bit TimerCounter (TC5, TC6)
TMP86CH22UG
Figure 9-8 16-Bit PPG Mode Timing Chart (TC5 and TC60)
TMP86CH22UG
9.3.9
Warm-Up Counter Mode
In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is
switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a
16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to
low-frequency, and vice-versa.
Note 1: In the warm-up counter mode, fix TCiCR<TFFi> to 0. If not fixed, the PDOi, PWMi and PPGi pins may output
pulses.
Note 2: In the warm-up counter mode, only upper 8 bits of the timer register TTREG6 and 5 are used for match
detection and lower 8 bits are not used.
Note 3: i = 5, 6
9.3.9.1
Low-Frequency Warm-up Counter Mode
(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability
is obtained. Before starting the timer, set SYSCR2<XTEN> to 1 to oscillate the low-frequency clock.
When a match between the up-counter and the timer register (TTREG6, 5) value is detected after the timer
is started by setting TC6CR<TC6S> to 1, the counter is cleared by generating the INTTC6 interrupt
request. After stopping the timer in the INTTC6 interrupt service routine, set SYSCR2<SYSCK> to 1 to
switch the system clock from the high-frequency to low-frequency, and then clear of SYSCR2<XTEN> to
0 to stop the high-frequency clock.
Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz)
Maximum Time Setting
(TTREG6, 5 = 0100H)
Maximum Time Setting
(TTREG6, 5 = FF00H)
7.81 ms
1.99 s
Example :After checking low-frequency clock oscillation stability with TC6 and 5, switching to the SLOW1 mode
SET
(SYSCR2).6
: SYSCR2<XTEN> ← 1
LD
(TC5CR), 43H
: Sets TFF5=0, source clock fs, and 16-bit mode.
LD
(TC6CR), 05H
: Sets TFF6=0, and warm-up counter mode.
LD
(TTREG5), 8000H
: Sets the warm-up time.
(The warm-up time depends on the oscillator characteristic.)
: IMF ← 0
DI
SET
(EIRH). 5
: IMF ← 1
EI
SET
:
PINTTC6:
: Enables the INTTC6.
(TC6CR).3
: Starts TC6 and 5.
:
CLR
(TC6CR).3
: Stops TC6 and 5.
SET
(SYSCR2).5
: SYSCR2<SYSCK> ← 1
(Switches the system clock to the low-frequency clock.)
CLR
(SYSCR2).7
: SYSCR2<XEN> ← 0 (Stops the high-frequency clock.)
RETI
:
VINTTC6:
DW
:
PINTTC6
: INTTC6 vector table
Page 103
9. 8-Bit TimerCounter (TC5, TC6)
9.1 Configuration
TMP86CH22UG
9.3.9.2
High-Frequency Warm-Up Counter Mode
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)
In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock.
When a match between the up-counter and the timer register (TTREG6, 5) value is detected after the timer
is started by setting TC6CR<TC6S> to 1, the counter is cleared by generating the INTTC6 interrupt
request. After stopping the timer in the INTTC6 interrupt service routine, clear SYSCR2<SYSCK> to 0 to
switch the system clock from the low-frequency to high-frequency, and then SYSCR2<XTEN> to 0 to
stop the low-frequency clock.
Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode
Minimum time (TTREG6, 5 = 0100H)
Maximum time (TTREG6, 5 = FF00H)
16 µs
4.08 ms
Example :After checking high-frequency clock oscillation stability with TC6 and 5, switching to the NORMAL1 mode
SET
(SYSCR2).7
: SYSCR2<XEN> ← 1
LD
(TC5CR), 63H
: Sets TFF5=0, source clock fs, and 16-bit mode.
LD
(TC6CR), 05H
: Sets TFF6=0, and warm-up counter mode.
LD
(TTREG5), 0F800H
: Sets the warm-up time.
(The warm-up time depends on the oscillator characteristic.)
: IMF ← 0
DI
SET
(EIRH). 5
: Enables the INTTC6.
(TC6CR).3
: Starts the TC6 and 5.
: IMF ← 1
EI
SET
:
PINTTC6:
:
CLR
(TC6CR).3
: Stops the TC6 and 5.
CLR
(SYSCR2).5
: SYSCR2<SYSCK> ← 0
(Switches the system clock to the high-frequency clock.)
CLR
(SYSCR2).6
: SYSCR2<XTEN> ← 0
(Stops the low-frequency clock.)
RETI
VINTTC6:
:
:
DW
PINTTC6
: INTTC6 vector table
Page 104
TMP86CH22UG
10. Real-Time Clock
The TMP86CH22UG include a real time counter (RTC). A low-frequency clock can be used to provide a periodic
interrupt (0.0625[s],0.125[s],0.25[s],0.50[s]) at a programmed interval, implement the clock function. The RTC can
be used in the mode in which the low-frequency oscillator is active (except for the SLEEP0 mode).
10.1 Configuration
RTCCR
Interrupt request
INTRTC
Selector
RTCSEL
RTCRUN
211/fs 212/fs 213/fs 214/fs
fs
(32.768 kHz)
Binary counter
Figure 10-1 Configuration of the RTC
10.2 Control of the RTC
The RTC is controlled by the RTC control register (RTCCR).
RTC Control Register
RTCCR
(0017H)
7
6
5
4
3
2
1
RTCSEL
RTCSEL
RTCRUN
0
RTCRUN
Interrupt generation period
(fs = 32.768 kHz)
00: 0.50 [s]
01: 0.25 [s]
10: 0.125 [s]
11: 0.0625 [s]
RTC control
0: Stops and clears the binary counter.
1: Starts counting
(Initial value: **** *000)
R/W
Note 1: Program the RTCCR during low-frequency oscillation (when SYSCR2<XTEN> = “1”). For selecting an interrupt generation period, program the RTCSEL when the timer is inactive (RTCRUN = “0”). During the timer operation, do not change
the RTCSEL programming at the same moment the timer stops.
Note 2: The timer automatically stops, and this register is initialized (the timer's binary counter is also initialized) if one of the following operations is performed while the timer is active:
1. Stopping the low-frequency oscillation (with SYSCR2<XTEN> = “0”)
2. When the TMP86CH22UG are put in STOP or SLEEP0 mode
Therefore, before activating the timer after releasing from STOP or SLEEP0 mode, reprogram the registers again.
Note 3: If a read instruction for RTCCR is executed, undefined value is set to bits 7 to 3.
Note 4: If break processing is performed on the debugger for the development tool during the timer operation, the timer stops
counting (contents of the RTCCR isn't altered). When the break is cancelled, processing is restarted from the point at
which it was suspended.
Page 105
10. Real-Time Clock
10.3 Function
TMP86CH22UG
10.3 Function
The RTC counts up on the internal low-frequency clock. When RTCCR<RTCRUN> is set to “1”, the binary
counter starts counting up. Each time the end of the period specified with RTCCR<RTCSEL> is detected, an
INTRTC interrupt is generated, and the binary counter is cleared. The timer continues counting up even after the
binary counter is cleared.
Page 106
TMP86CH22UG
11. Asynchronous Serial interface (UART )
11.1 Configuration
UART control register 1
Transmit data buffer
UARTCR1
TDBUF
3
Receive data buffer
RDBUF
2
INTTXD
Receive control circuit
Transmit control circuit
2
Shift register
Shift register
Parity bit
Stop bit
Noise rejection
circuit
RXD
TXD
INTRXD
Transmit/receive clock
Y
M
P
X
S
fc/13
fc/26
fc/52
fc/104
fc/208
fc/416
INTTC5
fc/96
A
B
C
D
E
F
G
H
A
B
C
6
fc/2
fc/27
8
fc/2
S
2
Y
4
2
Counter
UARTSR
UARTCR2
UART status register
UART control register 2
MPX: Multiplexer
Baud rate generator
Figure 11-1 UART (Asynchronous Serial Interface)
Page 107
11. Asynchronous Serial interface (UART )
11.2 Control
TMP86CH22UG
11.2 Control
UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR).
UART Control Register1
UARTCR1
(0025H)
7
6
5
4
3
TXE
RXE
STBT
EVEN
PE
2
1
0
BRG
(Initial value: 0000 0000)
TXE
Transfer operation
0:
1:
Disable
Enable
RXE
Receive operation
0:
1:
Disable
Enable
STBT
Transmit stop bit length
0:
1:
1 bit
2 bits
EVEN
Even-numbered parity
0:
1:
Odd-numbered parity
Even-numbered parity
Parity addition
0:
1:
No parity
Parity
PE
BRG
000:
001:
010:
011:
100:
101:
110:
111:
Transmit clock select
Write
only
fc/13 [Hz]
fc/26
fc/52
fc/104
fc/208
fc/416
TC5 ( Input INTTC5)
fc/96
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is
enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UARTCR1<RXE> and UARTCR1<TXE> should be set to “0” before UARTCR1<BRG> is changed.
UART Control Register2
UARTCR2
(0026H)
7
6
5
4
3
2
1
0
RXDNC
RXDNC
Selection of RXD input noise
rejectio time
STOPBR
Receive stop bit length
00:
01:
10:
11:
0:
1:
STOPBR
(Initial value: **** *000)
No noise rejection (Hysteresis input)
Rejects pulses shorter than 31/fc [s] as noise
Rejects pulses shorter than 63/fc [s] as noise
Rejects pulses shorter than 127/fc [s] as noise
Write
only
1 bit
2 bits
Note: When UARTCR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when UARTCR2<RXDNC>
= “10”, longer than 192/fc [s]; and when UARTCR2<RXDNC> = “11”, longer than 384/fc [s].
Page 108
TMP86CH22UG
UART Status Register
UARTSR
(0025H)
7
6
5
4
3
2
1
PERR
FERR
OERR
RBFL
TEND
TBEP
0
(Initial value: 0000 11**)
PERR
Parity error flag
0:
1:
No parity error
Parity error
FERR
Framing error flag
0:
1:
No framing error
Framing error
OERR
Overrun error flag
0:
1:
No overrun error
Overrun error
RBFL
Receive data buffer full flag
0:
1:
Receive data buffer empty
Receive data buffer full
TEND
Transmit end flag
0:
1:
On transmitting
Transmit end
TBEP
Transmit data buffer empty flag
0:
1:
Transmit data buffer full (Transmit data writing is finished)
Transmit data buffer empty
Note: When an INTTXD is generated, TBEP flag is set to "1" automatically.
UART Receive Data Buffer
RDBUF
(0F9BH)
7
6
5
4
3
2
1
0
Read only
(Initial value: 0000 0000)
UART Transmit Data Buffer
TDBUF
(0F9BH)
7
6
5
4
3
2
1
0
Write only
(Initial value: 0000 0000)
Page 109
Read
only
11. Asynchronous Serial interface (UART )
11.3 Transfer Data Format
TMP86CH22UG
11.3 Transfer Data Format
In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and
parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added to the
transfer data. The transfer data formats are shown as follows.
PE
STBT
0
Frame Length
8
1
2
3
9
10
0
Start
Bit 0
Bit 1
0
1
Start
Bit 0
1
0
Start
1
1
Start
11
Bit 6
Bit 7
Stop 1
Bit 1
Bit 6
Bit 7
Stop 1
Stop 2
Bit 0
Bit 1
Bit 6
Bit 7
Parity
Stop 1
Bit 0
Bit 1
Bit 6
Bit 7
Parity
Stop 1
12
Stop 2
Figure 11-2 Transfer Data Format
Without parity / 1 STOP bit
With parity / 1 STOP bit
Without parity / 2 STOP bit
With parity / 2 STOP bit
Figure 11-3 Caution on Changing Transfer Data Format
Note: In order to switch the transfer data format, perform transmit operations in the above Figure 11-3 sequence except
for the initial setting.
Page 110
TMP86CH22UG
11.4 Transfer Rate
The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows.
Table 11-1 Transfer Rate (Example)
Source Clock
BRG
16 MHz
8 MHz
4 MHz
000
76800 [baud]
38400 [baud]
19200 [baud]
001
38400
19200
9600
010
19200
9600
4800
011
9600
4800
2400
100
4800
2400
1200
101
2400
1200
600
When TC5 is used as the UART transfer rate (when UARTCR1<BRG> = “110”), the transfer clock and transfer
rate are determined as follows:
Transfer clock [Hz] = TC5 source clock [Hz] / TTREG5 setting value
Transfer Rate [baud] = Transfer clock [Hz] / 16
11.5 Data Sampling Method
The UART receiver keeps sampling input using the clock selected by UARTCR1<BRG> until a start bit is
detected in RXD pin input. RT clock starts detecting “L” level of the RXD pin. Once a start bit is detected, the start
bit, data bits, stop bit(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock
interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to majority
rule (The data are the same twice or more out of three samplings).
RXD pin
Start bit
RT0
1
2
3
Bit 0
4
5
6
7
8
9 10 11 12 13 14 15 0
1
2
3
4
5
6
7
8
9 10 11
2
3
4
5
6
7
8
9 10 11
RT clock
Start bit
Internal receive data
Bit 0
(a) Without noise rejection circuit
RXD pin
Start bit
RT0
1
2
3
Bit 0
4
5
6
7
8
9 10 11 12 13 14 15 0
1
RT clock
Internal receive data
Start bit
Bit 0
(b) With noise rejection circuit
Figure 11-4 Data Sampling Method
Page 111
11. Asynchronous Serial interface (UART )
11.6 STOP Bit Length
TMP86CH22UG
11.6 STOP Bit Length
Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>.
11.7 Parity
Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>.
11.8 Transmit/Receive Operation
11.8.1 Data Transmit Operation
Set UARTCR1<TXE> to “1”. Read UARTSR to check UARTSR<TBEP> = “1”, then write data in TDBUF
(Transmit data buffer). Writing data in TDBUF zero-clears UARTSR<TBEP>, transfers the data to the transmit
shift register and the data are sequentially output from the TXD pin. The data output include a one-bit start bit,
stop bits whose number is specified in UARTCR1<STBT> and a parity bit if parity addition is specified.
Select the data transfer baud rate using UARTCR1<BRG>. When data transmit starts, transmit buffer empty
flag UARTSR<TBEP> is set to “1” and an INTTXD interrupt is generated.
While UARTCR1<TXE> = “0” and from when “1” is written to UARTCR1<TXE> to when send data are
written to TDBUF, the TXD pin is fixed at high level.
When transmitting data, first read UARTSR, then write data in TDBUF. Otherwise, UARTSR<TBEP> is not
zero-cleared and transmit does not start.
11.8.2 Data Receive Operation
Set UARTCR1<RXE> to “1”. When data are received via the RXD pin, the receive data are transferred to
RDBUF (Receive data buffer). At this time, the data transmitted includes a start bit and stop bit(s) and a parity
bit if parity addition is specified. When stop bit(s) are received, data only are extracted and transferred to
RDBUF (Receive data buffer). Then the receive buffer full flag UARTSR<RBFL> is set and an INTRXD
interrupt is generated. Select the data transfer baud rate using UARTCR1<BRG>.
If an overrun error (OERR) occurs when data are received, the data are not transferred to RDBUF (Receive
data buffer) but discarded; data in the RDBUF are not affected.
Note:When a receive operation is disabled by setting UARTCR1<RXE> bit to “0”, the setting becomes valid when
data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting
may not become valid. If a framing error occurs, be sure to perform a re-receive operation.
Page 112
TMP86CH22UG
11.9 Status Flag
11.9.1 Parity Error
When parity determined using the receive data bits differs from the received parity bit, the parity error flag
UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RXD pin
Shift register
Parity
Stop
pxxxx0*
xxxx0**
1pxxxx0
UARTSR<PERR>
After reading UARTSR then
RDBUF clears PERR.
INTRXD interrupt
Figure 11-5 Generation of Parity Error
11.9.2 Framing Error
When “0” is sampled as the stop bit in the receive data, framing error flag UARTSR<FERR> is set to “1”.
The UARTSR<FERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RXD pin
Shift register
Stop
Final bit
xxxx0*
xxx0**
0xxxx0
After reading UARTSR then
RDBUF clears FERR.
UARTSR<FERR>
INTRXD interrupt
Figure 11-6 Generation of Framing Error
11.9.3 Overrun Error
When all bits in the next data are received while unread data are still in RDBUF, overrun error flag
UARTSR<OERR> is set to “1”. In this case, the receive data is discarded; data in RDBUF are not affected.
The UARTSR<OERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
Page 113
11. Asynchronous Serial interface (UART )
11.9 Status Flag
TMP86CH22UG
UARTSR<RBFL>
RXD pin
Stop
Final bit
Shift register
xxx0**
RDBUF
yyyy
xxxx0*
1xxxx0
UARTSR<OERR>
After reading UARTSR then
RDBUF clears OERR.
INTRXD interrupt
Figure 11-7 Generation of Overrun Error
Note:Receive operations are disabled until the overrun error flag UARTSR<OERR> is cleared.
11.9.4 Receive Data Buffer Full
Loading the received data in RDBUF sets receive data buffer full flag UARTSR<RBFL> to "1". The
UARTSR<RBFL> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RXD pin
Stop
Final bit
Shift register
xxx0**
RDBUF
yyyy
xxxx0*
1xxxx0
xxxx
After reading UARTSR then
RDBUF clears RBFL.
UARTSR<RBFL>
INTRXD interrupt
Figure 11-8 Generation of Receive Data Buffer Full
Note:If the overrun error flag UARTSR<OERR> is set during the period between reading the UARTSR and reading
the RDBUF, it cannot be cleared by only reading the RDBUF. Therefore, after reading the RDBUF, read the
UARTSR again to check whether or not the overrun error flag which should have been cleared still remains
set.
11.9.5 Transmit Data Buffer Empty
When no data is in the transmit buffer TDBUF, UARTSR<TBEP> is set to “1”, that is, when data in TDBUF
are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag
UARTSR<TBEP> is set to “1”. The UARTSR<TBEP> is cleared to “0” when the TDBUF is written after
reading the UARTSR.
Page 114
TMP86CH22UG
Data write
TDBUF
xxxx
*****1
Shift register
TXD pin
Data write
zzzz
yyyy
1xxxx0
*1xxxx
****1x
*****1
Start
Bit 0
Final bit
Stop
1yyyy0
UARTSR<TBEP>
After reading UARTSR writing TDBUF
clears TBEP.
INTTXD interrupt
Figure 11-9 Generation of Transmit Data Buffer Empty
11.9.6 Transmit End Flag
When data are transmitted and no data is in TDBUF (UARTSR<TBEP> = “1”), transmit end flag
UARTSR<TEND> is set to “1”. The UARTSR<TEND> is cleared to “0” when the data transmit is stated after
writing the TDBUF.
Shift register
TXD pin
***1xx
****1x
*****1
1yyyy0
Stop
Start
*1yyyy
Bit 0
Data write for TDBUF
UARTSR<TBEP>
UARTSR<TEND>
INTTXD interrupt
Figure 11-10 Generation of Transmit End Flag and Transmit Data Buffer Empty
Page 115
11. Asynchronous Serial interface (UART )
11.9 Status Flag
TMP86CH22UG
Page 116
TMP86CH22UG
12. Synchronous Serial Interface (SIO)
The TMP86CH22UG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and
receive data buffer that can automatically and continuously transfer up to 64 bits of data.
Serial interface is connected to outside peripherl devices via SO, SI, SCK port.
12.1 Configuration
SIO control / status register
SIOSR
SIOCR1
SIOCR2
CPU
Transmit and
receive data buffer
(8 bytes in DBR)
Buffer control
circuit
Control circuit
Shift register
Shift
clock
7
6
5
4
3
2
1
0
SO
Serial data output
8-bit transfer
4-bit transfer
SI
Serial data input
INTSIO interrupt request
Serial clock
SCK
Serial clock I/O
Figure 12-1 Serial Interface
Page 117
12. Synchronous Serial Interface (SIO)
12.2 Control
TMP86CH22UG
12.2 Control
The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be
determined by reading SIO status register (SIOSR).
The transmit and receive data buffer is controlled by the SIOCR2<BUF>. The data buffer is assigned to address
0F90H to 0F97H for SIO in the DBR area, and can continuously transfer up to 8 words (bytes or nibbles) at one time.
When the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full (in
the receive mode or transmit/receive mode) interrupt (INTSIO) is generated.
When the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a
fixed interval wait can be applied to the serial clock for each word transferred. Four different wait times can be
selected with SIOCR2<WAIT>.
SIO Control Register 1
SIOCR1
7
6
(0F98H)
SIOS
SIOINH
SIOS
5
4
Continue / abort transfer
SIOM
2
1
SIOM
Indicate transfer start / stop
SIOINH
3
Transfer mode select
0
SCK
0:
Stop
1:
Start
(Initial value: 0000 0000)
0:
Continuously transfer
1:
Abort transfer (Automatically cleared after abort)
000:
8-bit transmit mode
010:
4-bit transmit mode
100:
8-bit transmit / receive mode
101:
8-bit receive mode
110:
4-bit receive mode
Write
only
Except the above: Reserved
NORMAL1/2, IDLE1/2 mode
SCK
Serial clock select
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
mode
000
fc/213
fs/25
fs/25
001
fc/28
fc/28
-
010
fc/27
fc/27
-
011
fc/26
fc/26
-
100
fc/25
fc/25
-
101
fc/24
fc/24
-
110
Reserved
111
External clock ( Input from SCK pin )
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz]
Note 2: Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock.
Note 3: SIOCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.
SIO Control Register 2
SIOCR2
(0F99H)
7
6
5
4
3
WAIT
Page 118
2
1
BUF
0
(Initial value: ***0 0000)
Write
only
TMP86CH22UG
Always sets "00" except 8-bit transmit / receive mode.
WAIT
Wait control
Number of transfer words
(Buffer address in use)
BUF
00:
Tf = TD(Non wait)
01:
Tf = 2TD(Wait)
10:
Tf = 4TD(Wait)
11:
Tf = 8TD (Wait)
000:
1 word transfer
0F90H
001:
2 words transfer
0F90H ~ 0F91H
010:
3 words transfer
0F90H ~ 0F92H
011:
4 words transfer
0F90H ~ 0F93H
100:
5 words transfer
0F90H ~ 0F94H
101:
6 words transfer
0F90H ~ 0F95H
110:
7 words transfer
0F90H ~ 0F96H
111:
8 words transfer
0F90H ~ 0F97H
Write
only
Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving.
Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest
address. ( The first buffer address transmitted is 0F90H ).
Note 3: The value to be loaded to BUF is held after transfer is completed.
Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0).
Note 5: *: Don't care
Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.
SIO Status Register
SIOSR
7
6
(0F99H)
SIOF
SEF
SIOF
SEF
5
4
3
2
1
Serial transfer operating status monitor
0:
1:
Transfer terminated
Transfer in process
Shift operating status monitor
0:
1:
Shift operation terminated
Shift operation in process
0
Note 1: Tf; Frame time, TD; Data transfer time
Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1".
(output)
SCK output
TD
Tf
Figure 12-2 Frame time (Tf) and Data transfer time (TD)
12.3 Serial clock
12.3.1 Clock source
Internal clock or external clock for the source clock is selected by SIOCR1<SCK>.
Page 119
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only
12. Synchronous Serial Interface (SIO)
12.3 Serial clock
TMP86CH22UG
12.3.1.1 Internal clock
Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The
SCK pin goes high when transfer starts.
When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode)
cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock
and holds the next shift operation until the read/write processing is completed.
Table 12-1 Serial Clock Rate
NORMAL1/2, IDLE1/2 mode
DV7CK = 0
SLOW1/2,
SLEEP1/2 mode
DV7CK = 1
SCK
Clock
Baud Rate
Clock
Baud Rate
Clock
Baud Rate
000
fc/213
1.91 Kbps
fs/25
1024 bps
fs/25
1024 bps
001
fc/28
61.04 Kbps
fc/28
61.04 Kbps
-
-
010
fc/27
122.07 Kbps
fc/27
122.07 Kbps
-
-
011
fc/26
244.14 Kbps
fc/26
244.14 Kbps
-
-
100
fc/25
488.28 Kbps
fc/25
488.28 Kbps
-
-
101
fc/24
976.56 Kbps
fc/24
976.56 Kbps
-
-
110
-
-
-
-
-
-
111
External
External
External
External
External
External
Note: 1 Kbit = 1024 bit (fc = 16 MHz, fs = 32.768 kHz)
Automatically
wait function
SCK
pin (output)
SO
a0
pin (output)
Written transmit
data
a1
a2
a3
a
b0
b
b1
b2
b3
c0
c1
c
Figure 12-3 Automatic Wait Function (at 4-bit transmit mode)
12.3.1.2 External clock
An external clock connected to the SCK pin is used as the serial clock. In this case, output latch of this
port should be set to "1". To ensure shifting, a pulse width of at least 4 machine cycles is required. This
pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for
interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. Therfore, maximum transfer frequency will be 488.3K bit/sec (at fc=16MHz).
SCK
pin (Output)
tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes)
4/fs (In the SLOW1/2, SLEEP1/2 modes)
tSCKL, tSCKH > 4tcyc
tSCKL tSCKH
Figure 12-4 External clock pulse width
Page 120
TMP86CH22UG
12.3.2 Shift edge
The leading edge is used to transmit, and the trailing edge is used to receive.
12.3.2.1 Leading edge
Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/
output).
12.3.2.2 Trailing edge
Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output).
SCK pin
SO pin
Bit 0
Bit 1
Bit 2
Bit 3
Shift register
3210
*321
**32
***3
Bit 2
Bit 3
(a) Leading edge
SCK pin
SI pin
Shift register
Bit 0
Bit 1
0***
****
10**
210*
3210
*; Don’t care
(b) Trailing edge
Figure 12-5 Shift edge
12.4 Number of bits to transfer
Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of
the transmit/receive data buffer register are used. The upper 4 bits are cleared to “0” when receiving.
The data is transferred in sequence starting at the least significant bit (LSB).
12.5 Number of words to transfer
Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIOCR2<BUF>.
An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of
words is to be changed during transfer, the serial interface must be stopped before making the change. The number of
words can be changed during automatic-wait operation of an internal clock. In this case, the serial interface is not
required to be stopped.
Page 121
12. Synchronous Serial Interface (SIO)
12.6 Transfer Mode
TMP86CH22UG
SCK pin
SO pin
a0
a1
a2
a3
INTSIO interrupt
(a) 1 word transmit
SCK pin
SO pin
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
c2
c3
b3
c0
c1
c2
c3
INTSIO interrupt
(b) 3 words transmit
SCK pin
SI pin
a0
a1
a2
a3
b0
b1
b2
INTSIO interrupt
(c) 3 words receive
Figure 12-6 Number of words to transfer (Example: 1word = 4bit)
12.6 Transfer Mode
SIOCR1<SIOM> is used to select the transmit, receive, or transmit/receive mode.
12.6.1 4-bit and 8-bit transfer modes
In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data
(number of transfer words to be transferred) to the data buffer registers (DBR).
After the data are written, the transmission is started by setting SIOCR1<SIOS> to “1”. The data are then
output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit
(LSB). As soon as the LSB has been output, the data are transferred from the data buffer register to the shift
register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO (Buffer
empty) interrupt is generated to request the next transmitted data.
When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next
transmitted data are not loaded to the data buffer register by the time the number of data words specified with
the SIOCR2<BUF> has been transmitted. Writing even one word of data cancels the automatic-wait; therefore,
when transmitting two or more words, always write the next word before transmission of the previous word is
completed.
Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do
not use the DBR of the remained 5 words.
When an external clock is used, the data must be written to the data buffer register before shifting next data.
Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request
to writing of the data to the data buffer register by the interrupt service program.
The transmission is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer
empty interrupt service program.
Page 122
TMP86CH22UG
SIOCR1<SIOS> is cleared, the operation will end after all bits of words are transmitted.
That the transmission has ended can be determined from the status of SIOSR<SIOF> because SIOSR<SIOF>
is cleared to “0” when a transfer is completed.
When SIOCR1<SIOINH> is set, the transmission is immediately ended and SIOSR<SIOF> is cleared to
“0”.
When an external clock is used, it is also necessary to clear SIOCR1<SIOS> to “0” before shifting the next
data; If SIOCR1<SIOS> is not cleared before shift out, dummy data will be transmitted and the operation will
end.
If it is necessary to change the number of words, SIOCR1<SIOS> should be cleared to “0”, then
SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to “0”.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO interrupt
a
DBR
b
Write Write
(a)
(b)
Figure 12-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock)
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Input)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO interrupt
DBR
a
b
Write Write
(a)
(b)
Figure 12-8 Transfer Mode (Example: 8bit, 1word transfer, External clock)
Page 123
12. Synchronous Serial Interface (SIO)
12.6 Transfer Mode
TMP86CH22UG
SCK pin
SIOSR<SIOF>
SO pin
MSB of last word
tSODH = min 3.5/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)
tSODH = min 3.5/fs [s] (In the SLOW1/2, SLEEP1/2 modes)
Figure 12-9 Transmiiied Data Hold Time at End of Transfer
12.6.2 4-bit and 8-bit receive modes
After setting the control registers to the receive mode, set SIOCR1<SIOS> to “1” to enable receiving. The
data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word
of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the
number of words specified with the SIOCR2<BUF> has been received, an INTSIO (Buffer full) interrupt is
generated to request that these data be read out. The data are then read from the data buffer registers by the
interrupt service program.
When the internal clock is used, and the previous data are not read from the data buffer register before the
next data are received, the serial clock will stop and an automatic-wait will be initiated until the data are read.
A wait will not be initiated if even one data word has been read.
Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore,
during SIO do not use such DBR for other applications.
When an external clock is used, the shift operation is synchronized with the external clock; therefore, the
previous data are read before the next data are transferred to the data buffer register. If the previous data have
not been read, the next data will not be transferred to the data buffer register and the receiving of any more data
will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay
between the time when the interrupt request is generated and when the data received have been read.
The receiving is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to “1” in buffer full
interrupt service program.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
cleared, the receiving is ended at the time that the final bit of the data has been received. That the receiving has
ended can be determined from the status of SIOSR<SIOF>. SIOSR<SIOF> is cleared to “0” when the receiving is ended. After confirmed the receiving termination, the final receiving data is read. When SIOCR1<SIOINH> is set, the receiving is immediately ended and SIOSR<SIOF> is cleared to “0”. (The received data is
ignored, and it is not required to be read out.)
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
cleared to “0” then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”. If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of data receiving, SIOCR2<BUF> must be rewritten before the received data is read
out.
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the transfer mode.
Page 124
TMP86CH22UG
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(Output)
SI pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
INTSIO Interrupt
DBR
a
b
Read out
Read out
Figure 12-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock)
12.6.3 8-bit transfer / receive mode
After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first
to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIOCR1<SIOS> to “1”.
When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving,
the data are input to the SI pin at the trailing edges of the serial clock. When the all receive is enabled, 8-bit
data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when
the number of data words specified with the SIOCR2<BUF> has been transferred. Usually, read the receive
data from the buffer register in the interrupt service. The data buffer register is used for both transmitting and
receiving; therefore, always write the data to be transmitted after reading the all received data.
When the internal clock is used, a wait is initiated until the received data are read and the next transfer data
are written. A wait will not be initiated if even one transfer data word has been written.
When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is
necessary to read the received data and write the data to be transmitted next before starting the next shift operation. When an external clock is used, the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written.
The transmit/receive operation is ended by clearing SIOCR1<SIOS> to “0” or setting SIOCR1<SIOINH> to
“1” in INTSIO interrupt service program.
When SIOCR1<SIOS> is cleared, the current data are transferred to the buffer. After SIOCR1<SIOS>
cleared, the transmitting/receiving is ended at the time that the final bit of the data has been transmitted.
That the transmitting/receiving has ended can be determined from the status of SIOSR<SIOF>.
SIOSR<SIOF> is cleared to “0” when the transmitting/receiving is ended.
When SIOCR1<SIOINH> is set, the transmit/receive operation is immediately ended and SIOSR<SIOF> is
cleared to “0”.
If it is necessary to change the number of words in external clock operation, SIOCR1<SIOS> should be
cleared to “0”, then SIOCR2<BUF> must be rewritten after confirming that SIOSR<SIOF> has been cleared to
“0”.
If it is necessary to change the number of words in internal clock, during automatic-wait operation which
occurs after completion of transmit/receive operation, SIOCR2<BUF> must be rewritten before reading and
writing of the receive/transmit data.
Page 125
12. Synchronous Serial Interface (SIO)
12.6 Transfer Mode
TMP86CH22UG
Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the
transfer mode, end receiving by clearing SIOCR1<SIOS> to “0”, read the last data and then switch the transfer mode.
Clear SIOS
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK pin
(output)
SO pin
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
SI pin
c0
c1
c2
c3
c4
c5
c6
c7
d0
d1
d2
d3
d4
d5
d6
d7
INTSIO interrupt
c
a
DBR
Write (a)
Read out (c)
b
Write (b)
d
Read out (d)
Figure 12-11 Transfer / Receive Mode (Example: 8bit, 1word transfer, Internal clock)
SCK pin
SIOSR<SIOF>
SO pin
Bit 6
Bit 7 of last word
tSODH = min 4/fc [s] ( In the NORMAL1/2, IDLE1/2 modes)
tSODH = min 4/fs [s] (In the SLOW1/2, SLEEP1/2 modes)
Figure 12-12 Transmitted Data Hold Time at End of Transfer / Receive
Page 126
TMP86CH22UG
13. 8-Bit AD Converter (ADC)
The TMP86CH22UG have a 8-bit successive approximation type AD converter.
13.1 Configuration
The circuit configuration of the 8-bit AD converter is shown in Figure 13-1.
It consists of control registers ADCCR1 and ADCCR2, converted value registers ADCDR1 and ADCDR2, a DA
converter, a sample-and-hold circuit, a comparator, and a successive comparison circuit.
DA converter
VSS
VDD
R/2
Analog input
multiplexer
AIN1
0
R
R/2
Reference
voltage
Sample hold
circuit
Y
8
to
n
Successive approximate circuit
Shift clock
S EN
AINDS
ADCCR1
IREFON
SAIN
INTADC interrupt
Control circuit
4
ADRS
AIN4
Analog
comparator
3
8
ACK
ADCCR2
AD converter control register 1,2
ADCDR1
ADBF
ADCDR2
AD conversion result register1,2
Figure 13-1 8-bit AD Converter (ADC)
Page 127
EOCF
13. 8-Bit AD Converter (ADC)
13.1 Configuration
TMP86CH22UG
13.2 Control
The AD converter consists of the following four registers:
1. AD converter control register 1 (ADCCR1)
This register selects the analog channels in which to perform AD conversion and controls the AD converter as it starts operating.
2. AD converter control register 2 (ADCCR2)
This register selects the AD conversion time and controls the connection of the DA converter (ladder
resistor network).
3. AD converted value register (ADCDR1)
This register is used to store the digital value after being converted by the AD converter.
4. AD converted value register (ADCDR2)
This register monitors the operating status of the AD converter.
AD Converter Control Register 1
ADCCR1
(000EH)
7
6
5
4
ADRS
"0"
"1"
AINDS
3
2
1
SAIN
ADRS
AD conversion start
0:
1:
−
Start
AINDS
Analog input control
0:
1:
Analog input enable
Analog input disable
Analog input channel select
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
Reserved
AIN1
AIN2
AIN3
AIN4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SAIN
0
(Initial value: 0001 0000)
R/W
Note 1: Select analog input when AD converter stops (ADCDR2<ADBF> = “0”).
Note 2: When the analog input is all use disabling, the ADCCR1<AINDS> should be set to “1”.
Note 3: During conversion, do not perform output instruction to maintain a precision for all of the pins. And port near to analog
input, do not input intense signaling of change.
Note 4: The ADRS is automatically cleared to “0” after starting conversion.
Note 5: Do not set ADCCR1<ADRS> newly again during AD conversion. Before setting ADCCR1<ADRS> newly again, check
ADCDR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g.,
interrupt handling routine).
Note 6: After STOP or SLOW/SLEEP mode are started, AD converter control register 1 (ADCCR1) is all initialized and no data
can be written in this register. Therefore, to use AD converter again, set the ADCCR1 newly after returning to NORMAL1
or NORMAL2 mode.
Note 7: Although ADCCR1<SAIN> is initialized to "Reserved value" after reset, set the suitable analog input channel when using
AD converter.
Note 8: Always set bit 5 in ADCCR1 to “1” and set bit 6 in ADCCR1 to “0”.
Page 128
TMP86CH22UG
AD Converter Control Register 2
7
ADCCR2
(000FH)
6
IREFON
ACK
5
4
3
IREFON
“1”
2
1
0
ACK
“0”
(Initial value: **0* 000*)
DA converter (ladder resistor)
connection control
0:
1:
Connected only during AD conversion
Always connected
R/W
AD conversion time select
000:
001:
010:
011:
100:
101:
110:
111:
39/fc
Reserved
78/fc
156/fc
312/fc
624/fc
1248/fc
Reserved
R/W
Note 1: Always set bit 0 in ADCCR2 to “0” and set bit 4 in ADCCR2 to “1”.
Note 2: When a read instruction for ADCCR2, bit 6 to 7 in ADCCR2 read in as undefined data.
Note 3: After STOP or SLOW/SLEEP mode are started, AD converter control register 2 (ADCCR2) is all initialized and no data
can be written in this register. Therefore, to use AD converter again, set the ADCCR2 newly after returning to NORMAL1
or NORMAL2 mode.
Table 13-1 Conversion Time according to ACK Setting and Frequency
Condition
Conbersion
time‘
16MHz
8MHz
4 MHz
2 MHz
10MHz
5 MHz
2.5 MHz
39/fc
-
-
-
19.5 µs
-
-
15.6 µs
010
78/fc
-
-
19.5 µs
39.0 µs
-
15.6 µs
31.2 µs
011
156/fc
-
19.5 µs
39.0 µs
78.0 µs
15.6 µs
31.2 µs
62.4 µs
100
312/fc
19.5 µs
39.0 µs
78.0 µs
156.0 µs
31.2 µs
62.4 µs
124.8 µs
ACK
000
001
Reserved
101
624/fc
39.0 µs
78.0 µs
156.0 µs
-
62.4 µs
124.8 µs
-
110
1248/fc
78.0 µs
156.0 µs
-
-
124.8 µs
-
-
111
Reserved
Note 1: Settings for “−” in the above table are inhibited.
Note 2: Set conversion time by Supply Voltage(VDD) as follows.
-
VDD = 4.5 to 5.5 V
(15.6 µs or more)
-
VDD = 2.7 to 5.5 V
(31.2 µs or more)
-
VDD = 1.8 to 5.5 V
(124.8 µs or more)
AD Conversion Result Register
ADCDR1
(0021H)
7
6
5
4
3
2
1
0
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
5
4
3
2
1
0
EOCF
ADBF
(Initial value: 0000 0000)
AD Conversion Result Register
ADCDR2
(0020H)
7
EOCF
ADBF
6
(Initial value: **00 ****)
AD conversion end flag
0: Before or during conversion
1: Conversion completed
AD conversion busy flag
0: During stop of AD conversion
1: During AD conversion
Note 1: The ADCDR2<EOCF> is cleared to “0” when reading the ADCDR1.
Therefore, the AD conversion result should be read to ADCDR2 more first than ADCDR1.
Note 2: ADCDR2<ADBF> is set to “1” when AD conversion starts and cleared to “0” when the AD conversion is finished. It
also is cleared upon entering STOP or SLOW mode.
Note 3: If a read instruction is executed for ADCDR2, read data of bits 7, 6 and 3 to 0 are unstable.
Page 129
Read
only
13. 8-Bit AD Converter (ADC)
13.3 Function
TMP86CH22UG
13.3 Function
13.3.1 AD Conveter Operation
When ADCCR1<ADRS> is set to "1", AD conversion of the voltage at the analog input pin specified by
ADCCR1<SAIN> is thereby started.
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDR1) and at the same time ADCDR2<EOCF> is set to “1”, the AD conversion finished interrupt
(INTADC) is generated.
ADCCR1<ADRS> is automatically cleared after AD conversion has started. Do not set ADCCR1<ADRS>
newly again (restart) during AD conversion. Before setting ADRS newly again, check ADCDR<EOCF> to see
that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine).
AD conversion start
AD conversion start
ADCCR1<ADRS>
ADCDR2<ADBF>
ADCDR1 status
Indeterminate
First conversion result
Second conversion result
EOCF cleared by reading
conversion result
ADCDR2<EOCF>
INTADC interrupt
Conversion
result read
Reading ADCDR1
Conversion
result read
Reading ADCDR2
Figure 13-2 AD Converter Operation
13.3.2 AD Converter Operation
1. Set up the AD converter control register 1 (ADCCR1) as follows:
• Choose the channel to AD convert using AD input channel select (SAIN).
• Specify analog input enable for analog input control (AINDS).
2. Set up the AD converter control register 2 (ADCCR2) as follows:
• Set the AD conversion time using AD conversion time (ACK). For details on how to set the conversion time, refer to Table 13-1.
• Choose IREFON for DA converter control.
3. After setting up 1. and 2. above, set AD conversion start (ADRS) of AD converter control register 1
(ADCCR1) to “1”.
4. After an elapse of the specified AD conversion time, the AD converted value is stored in AD converted value register 1 (ADCDR1) and the AD conversion finished flag (EOCF) of AD converted
value register 2 (ADCDR2) is set to “1”, upon which time AD conversion interrupt INTADC is generated.
5. EOCF is cleared to “0” by a read of the conversion result. However, if reconverted before a register
read, although EOCF is cleared the previous conversion result is retained until the next conversion is
completed.
Page 130
TMP86CH22UG
Example :After selecting the conversion time of 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD
conversion once. After checking EOCF, read the converted value and store the 8-bit data in address 009FH on
RAM.
; AIN SELECT
:
:
:
:
; Before setting the AD converter register, set each port register suitably (For detail, see chapter of I/O port.)
LD
(ADCCR1), 00100011B
; Select AIN3
LD
(ADCCR2), 11011000B
; Select conversion time (312/fc) and operation mode
SET
(ADCCR1). 7
; ADRS = 1
TEST
(ADCDR2). 5
; EOCF = 1 ?
JRS
T, SLOOP
; AD CONVERT START
SLOOP:
; RESULT DATA READ
LD
A, (ADCDR1)
LD
(9FH), A
13.3.3 STOP and SLOW Mode during AD Conversion
When the STOP or SLOW mode is entered forcibly during AD conversion, the AD convert operation is suspended and the AD converter is initialized (ADCCR1 and ADCCR2 are initialized to initial value.). Also, the
conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to
read the conversion results before entering STOP or SLOW mode.) When restored from STOP or SLOW
mode, AD conversion is not automatically restarted, so it is necessary to restart AD conversion. Note that since
the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the
analog reference voltage.
Page 131
13. 8-Bit AD Converter (ADC)
13.3 Function
TMP86CH22UG
13.3.4 Analog Input Voltage and AD Conversion Result
The analog input voltage is corresponded to the 8-bit digital value converted by the AD as shown in Figure
13-3.
AD conversion result
FFH
FEH
FDH
03H
02H
01H
×
0
1
2
3
253
254
Analog input voltage
255
256
VDD
VSS
256
Figure 13-3 Analog Input Voltage and AD Conversion Result (typ.)
Page 132
TMP86CH22UG
13.4 Precautions about AD Converter
13.4.1 Restrictions for AD Conversion interrupt (INTADC) usage
When an AD interrupt is used, it may not be processed depending on program composition. For example, if
an INTADC interrupt request is generated while an interrupt with priority lower than the interrupt latch IL15
(INTADC) is being accepted, the INTADC interrupt latch may be cleared without the INTADC interrupt being
processed.
The completion of AD conversion can be detected by the following methods:
(1) Method not using the AD conversion end interrupt
Whether or not AD conversion is completed can be detected by monitoring the AD conversion end flag
(EOCF) by software. This can be done by polling EOCF or monitoring EOCF at regular intervals after start of
AD conversion.
(2) Method for detecting AD conversion end while a lower-priority interrupt is being processed
While an interrupt with priority lower than INTADC is being processed, check the AD conversion end flag
(EOCF) and interrupt latch IL15. If IL15 = 0 and EOCF = 1, call the AD conversion end interrupt processing
routine with consideration given to PUSH/POP operations. At this time, if an interrupt request with priority
higher than INTADC has been set, the AD conversion end interrupt processing routine will be executed first
against the specified priority. If necessary, we recommend that the AD conversion end interrupt processing routine be called after checking whether or not an interrupt request with priority higher than INTADC has been
set.
13.4.2 Analog input pin voltage range
Make sure the analog input pins (AIN1 to AIN4) are used at voltages within VSS below VDD. If any voltage
outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain.
The other analog input pins also are affected by that.
13.4.3 Analog input shared pins
The analog input pins (AIN1 to AIN4) are shared with input/output ports. When using any of the analog
inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary
to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other
pins may also be affected by noise arising from input/output to and from adjacent pins.
13.4.4 Noise countermeasure
The internal equivalent circuit of the analog input pins is shown in Figure 13-4. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output
impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capacitor
external to the chip.
Page 133
13. 8-Bit AD Converter (ADC)
13.4 Precautions about AD Converter
TMP86CH22UG
AINx
Allowable signal
source impedance
Internal resistance
5 kΩ (typ)
Analog comparator
Internal capacitance
C = 22 pF (typ.)
5 kΩ (max)
DA converter
Note) i = 4~1
Figure 13-4 Analog Input Equivalent Circuit and Example of Input Pin Processing
Page 134
TMP86CH22UG
14. Key-on Wakeup (KWU)
In the TMP86CH22UG, the STOP mode is released by not only P20(INT5/STOP) pin but also STOP2 pin.
When the STOP mode is released by STOP2 pin, the STOP pin needs to be used.
In details, refer to the following section " 14.2 Control ".
14.1 Configuration
INT5
STOP
STOP mode
release signal
(1:Release)
STOP2
STOP2
STOPCR
(0F9AH)
Figure 14-1 Key-on Wakeup Circuit
14.2 Control
STOP2 pin can controlled by Key-on Wakeup Control Register (STOPCR). It can be configured as enable/disable
in 1-bit unit. When this pin is used for STOP mode release, configure corresponding I/O pin to input mode by I/O
port register beforehand.
Key-on Wakeup Control Register
STOPCR
7
(0F9AH)
6
5
4
3
2
1
STOP2
STOP2
0
(Initial value: ***0 ****)
0:Disable
1:Enable
STOP mode released by STOP2
Write
only
14.3 Function
Stop mode can be entered by setting up the System Control Register (SYSCR1), and can be exited by detecting the
"L" level on STOP2 pin, which are enabled by STOPCR, for releasing STOP mode (Note1).
Also, the level of the STOP2 pin can be confirmed by reading corresponding I/O port data register, check STOP2
pin "H" that is enabled by STOPCR before the STOP mode is startd (Note2).
Note 1: When the STOP mode released by the edge release mode (SYSCR1<RELM> = “0”), inhibit input from STOP2
pin by Key-on Wakeup Control Register (STOPCR) or must be set "H" level into STOP2 pin that is available input
during STOP mode.
Note 2: When the STOP pin input is high or STOP2 pin inputwhich is enabled by STOPCR is low, executing an instruction
which starts STOP mode will not place in STOP mode but instead will immediately start the release sequence
(Warm up).
Page 135
14. Key-on Wakeup (KWU)
14.3 Function
TMP86CH22UG
Note 3: STOP pin doesn’t have the control register such as STOPCR, so when STOP mode is released by STOP2 pin,
STOP pin also should be used as STOP mode release function.
Note 4: In STOP mode, Key-on Wakeup pin which is enabled as input mode (for releasing STOP mode) by Key-on
Wakeup Control Register (STOPCR) may genarate the penetration current, so the said pin must be disabled AD
conversion input (analog voltage input).
Note 5: When the STOP mode is released by STOP2 pin, the level of STOP pin should hold "L" level (Figure 14-2).
b) In case of STOP2
a) STOP
STOP pin
STOP pin "L"
STOP mode
Release
STOP mode
STOP2 pin
STOP mode
Figure 14-2 Priority of STOP pin and STOP2 pin
Table 14-1 Release level (edge) of STOP mode
Release level (edge)
Pin name
SYSCR1<RELM>="1"
(Note2)
SYSCR1<RELM>="0"
STOP
"H" level
Rising edge
STOP2
"L" level
Don’t use (Note1)
Page 136
Release
STOP mode
TMP86CH22UG
15. LCD Driver
The TMP86CH22UG has a driver and control circuit to directly drive the liquid crystal device (LCD). The pins to
be connected to LCD are as follows:
1. Segment output port
23 pins
(SEG31 to SEG9)
2. Common output port
4 pins
(COM3 to COM0)
In addition, VLC pin is provided for the LCD power supply.
The devices that can be directly driven is selectable from LCD of the following drive methods:
1. 1/4 Duty (1/3 Bias) LCD
Max 92 Segments
(8 segments × 11 digits)
2. 1/3 Duty (1/3 Bias) LCD
Max 69 Segments
(8 segments × 8 digits)
3. 1/3 Duty (1/2 Bias) LCD
Max 69 Segments
(8 segments × 8 digits)
4. 1/2 Duty (1/2 Bias) LCD
Max 46 Segments
(8 segments × 5 digits)
5. Static LCD
Max 23 Segments
(8 segments × 2 digits)
15.1 Configuration
LCDCR
7
EDSP
6
5
LRSE
4
3
DUTY
2
1
0
SLF
DBR
fc/217, fs/29
display data area
fc/216, fs/28
fc/215
fc/214
Timing
control
Duty
control
Display data select control
Blanking
control
Power Switch and
Bias, Bleeder
resistance
VLC
Display data buffer register
Common driver
COM0
to
COM3
Segment driver
SEG9
Figure 15-1 LCD Driver
Page 137
to
SEG31
15. LCD Driver
15.1 Configuration
TMP86CH22UG
15.2 Control
The LCD control register (LCDCR) controls the LCD driver. EDSP specifies whether to enable the LCD display.
If EDSP is cleared to “0” for blanking, the power switch for the VLC pin is turned off. So, the COM pin and pin output selected with SEG enter GND level.
LCD Driver Control Register
LCDCR
(0027H)
7
EDSP
EDSP
6
5
4
LRSEL
LCD display control
3
2
1
DUTY
0
SLF
(Initial value: 0000 0000)
0: Blanking
1: Enables LCD display (Blanking is released)
NORMAL1/2, IDLE/1/2 mode
SLOW1/2, SLEEP1/2 mode
SLF Setting
LRSE
DUTY
Period selection of enabling
(turn on) of the low bleeder
resistor (for implementing
appropriate LCD panel drive
capability)
Selection of driving methods
00:
01:
SLF Setting
11
10
01
00
01
00
26/fc
27/fc
28/fc
29/fc
1/fs
2/fs
9
10
2 /fc
2 /fc
11
2 /fc
12
2 /fc
Selection of LCD frame frequency
2 /fs
10:
Always enabling
11:
Reserved
24/fs
000: 1/4 Duty (1/3 Bias)
001: 1/3 Duty (1/3 Bias)
010: 1/3 Duty (1/2 Bias)
011: 1/2 Duty (1/2 Bias)
100: Static
101: Reserved
110: Reserved
111: Reserved
NORMAL1/2, IDLE0/1/2 mode
SLF
3
00:
01:
10:
11:
fc/217
fc/2
[Hz]
16
fc/215
fc/213
R/W
SLOW1/2, SLEEP1/2 mode
fs/29 [Hz]
fs/28
Reserved
Reserved
Note 1: The base-frequency (SLF) source clock is switched between high and low frequencies by the SYSCR2<SYSCK> programming. The base frequency does not depend on the TBTCR<DV7CK> programming.
Note 2: If the setting of SYSCR2<SYSCK>is changed, be sure to turn off the LCD (clear EDSP to “0”) to avoid the output of incorrect waveform.
Note 3: Programming LRSE properly according to the LCD panel used. As the LRSE programming increases (lengthen the period
of enabling of the low resistor), the drive capability becomes higher while the power dissipation increases. Reversely, as
the LRSE programming decreases shorten the period of enabling of the low resistor, the drive capability becomes lower
while the power consumption decreases.
Note 4: If the IDLE0, SLEEP0, or STOP mode is activated when the display is enabled, LCDCR<EDSP> is automatically changed
to “0” to blank the display.
Page 138
TMP86CH22UG
15.2.1 LCD driving methods
As for LCD driving method, 5 types can be selected by LCDCR<DUTY>. The driving method is initialized
in the initial program according to the LCD used.
VLCD
VLCD
1/fF
0
0
−VLCD
Data "1"
Data "0"
−VLCD
Data "1"
Data "0"
(b) 1/3 Duty (1/3 Bias)
(a) 1/4 Duty (1/3 Bias)
VLCD
1/fF
VLCD
1/fF
0
1/fF
0
−VLCD
−VLCD
Data "1"
Data "1"
Data "0"
(c) 1/3 Duty (1/2 Bias)
VLCD
Data "0"
(d) 1/2 Duty (1/2 Bias)
1/fF
0
−VLCD
Data "1"
Data "0"
(e) Static
Note 1: fF: Frame frequency
Note 2: VLCD: LCD drive voltage (= VDD − VLC)
Figure 15-2 LCD Drive Waveform (COM - SEG pins)
Page 139
15. LCD Driver
15.1 Configuration
TMP86CH22UG
15.2.2 Frame frequency
Frame frequency (fF) is set according to driving method and base frequency as shown in the following Table
15-1. The base frequency is selected by LCDCR<SLF> according to the frequency fc and fs of the basic clock
to be used.
Table 15-1 Setting of LCD Frame Frequency for high frequency clock
(a) At the SYSCR2<SYSCK> = “0”.
Frame Frequency [Hz]
SLF
Base Frequency [Hz]
1/4 Duty
1/3 Duty
4 fc
--- • -------3 2 17
1/2 Duty
Static
4 fc
--- • -------2 2 17
fc
-------17
2
fc
-------17
2
fc
-------17
2
(fc = 16 MHz)
122
163
244
122
(fc = 8 MHz)
61
81
122
61
fc
-------16
2
fc
-------16
2
4 fc
--- • -------2 2 16
fc
-------16
2
(fc = 8 MHz)
122
163
244
122
(fc = 4 MHz)
61
81
122
61
fc
-------15
2
fc
-------15
2
4 fc
--- • -------2 2 15
fc
-------15
2
(fc = 4 MHz)
122
163
244
122
(fc = 2 MHz)
61
81
122
61
fc
-------14
2
fc
-------14
2
4 fc
--- • -------2 2 14
fc
-------14
2
(fc = 2 MHz)
122
162
244
122
(fc = 1 MHz)
61
81
122
61
00
4 fc
--- • -------3 2 16
01
4 fc
--- • -------3 2 15
10
4 fc
--- • -------3 2 14
11
Note: fc: High-frequency clock [Hz]
Table 15-2 Setting of LCD Frame Frequency for low frequency clock
(b) At the SYSCR2<SYSCK> = “1”.
Frame Frequency [Hz]
SLF
00
01
Base Frequency [Hz]
1/4 Duty
1/3 Duty
1/2 Duty
Static
fs
-----9
2
fs
-----9
2
4 fs
--- • -----3 29
4 fs
--- • -----2 29
fs
-----9
2
(fs = 32.768 kHz)
64
85
128
64
fs
-----8
2
fs
-----8
2
4 fs
--- • -----3 28
4 fs
--- • -----2 28
fs
-----8
2
(fs = 32.768 kHz)
128
171
256
128
1*
Reserved
Note: fs: Low-frequency clock [Hz]
Page 140
TMP86CH22UG
15.2.3 LCD drive voltage
LCD driving voltage VLCD is given as potential difference VDD − VLC between pins VDD and VLC.
Therefore, when the CPU voltage and LCD drive voltage are the same, VLC pin will be connected to VSS pin.
The LCD lights when the potential difference between segment output and common output is ±VLCD. Otherwise it turns off.
During reset, the power switch of LCD driver is automatically turned off, shutting off the VLC voltage.
After reset, if the P*LCR register (*; Port No.) for each port is set to “1” with LCDCR<EDSP> = “0”, a
GND level is output from the pin which can be used as segment.
The power switch is turned on to supply VLC voltage to LCD driver by setting with LCDCR<EDSP> to “1”.
If the IDLE0, SLEEP0, or STOP mode is activated, LCDCR<EDSP> is automatically changed to “0” to
blank the display. To turn the display back on after releasing from the previous mode, set LCDCR<EDSP> to
“1” again.
Note:During reset, the LCD common outputs (COM3 to COM0) are fixed “0” level. However, the multiplex port
(input/output port or SEG output is selectable) becomes high impedance. Therefore, when the reset input is
long remarkably, ghost problem may appear in LCD display.
15.2.4 Adjusting the LCD panel drive capability
The LCD panel drive capability can be adjusted by programming LCDCR<LRSE>. When the period of
enabling of the low bleeder resistor is lengthened, the drive capability becomes higher while the power consumption increases. Reversely, when the period of enabling of the low bleeder resistor is shortened, the drive
capability becomes lower while the power consumption decreases. If the drive capability is not enough, the
LCD display might present a ghost problem. So, implement the optimum drive capability for the LCD panel
used. The figure below shows the bleeder resistance timing and equivalent circuit for 1/4 duty and 1/3 bias.
Frame frequency
VDD
High/low
resistance
switching
signal
VM1
VM2
VDD
RH
RL
RH
RL
RH
RL
VLCD
When LCDCR
<LRSE> "10B"
When LCDCR
<LRSE> =
"00B" or "01B"
RLt
RLt
RLt
RLt
VM
RLt
VM2
RLt RHt RLt RHt RLt RHt RLt RHt RLt RHt
(a) ON Timing for Low Bleeder Resistance
RH: High resistance
RL: Low resistance
RLt: Period during which resistance RL is selected (Time specified with LCDCR<LRSE>)
RHt: Period during which resistance RH is selected
(Time specified with LCDCR<SLF> ÷ 4 − Time specified with LCDCR<LRSE>)
VLC
VLC
(b) Equivalent Circuit for
Bleeder Resistance
Figure 15-3 Bleeder Resistance Selection with LCDCR<LRSE> (for 1/4 duty and 1/3 bias)
Page 141
15. LCD Driver
15.3 LCD Display Operation
TMP86CH22UG
15.3 LCD Display Operation
15.3.1 Display data setting
Display data is stored to the display data area (address 0F84H to 0F8FH,12 bytes) in the DBR. The display
data stored in the display data area is automatically read out and sent to the LCD driver by the hardware. The
LCD driver generates the segment signal and common signal according to the display data and driving method.
Therefore, display patterns can be changed by only over writing the contents of display data area by the program. Table 15-4 shows the correspondence between the display data area and SEG/COM pins.
LCD light when display data is “1” and turn off when “0”. According to the driving method of LCD, the
number of pixels which can be driven becomes different, and the number of bits in the display data area which
is used to store display data also becomes different.
Therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the
addresses not connected to LCD can be used to store general user process data (see Table 15-3).
Table 15-3 Driving Method and Bit for Display Data
Driving methods
Bit 7/3
Bit 6/2
Bit 5/1
Bit 4/0
1/4 Duty
COM3
COM2
COM1
COM0
1/3 Duty
–
COM2
COM1
COM0
1/2 Duty
–
–
COM1
COM0
Static
–
–
–
COM0
Note: –: This bit is not used for display data
Table 15-4 LCD Display Data Area (DBR)
Address
Bit 7
Bit 6
Bit 5
0F84H
Bit 4
Bit 3
Bit 2
Bit 1
SEG9
Reserved
0F85H
SEG11
SEG10
0F86H
SEG13
SEG12
0F87H
SEG15
SEG14
0F88H
SEG17
SEG16
0F89H
SEG19
SEG18
0F8AH
SEG21
SEG20
0F8BH
SEG23
SEG22
0F8CH
SEG25
SEG24
0F8DH
SEG27
SEG26
0F8EH
SEG29
SEG28
0F8FH
SEG31
COM3
COM2
COM1
Bit 0
SEG30
COM0
COM3
COM2
COM1
COM0
15.3.2 Blanking
Blanking is enabled when LCDCR<EDSP> is cleared to “0”.
To blank the LCD display and turn it off, a GND-level signal is output to the COM pin and the port which
can be used as the segment by setting of P*LCR register (*; Port No.). At this time, the power switch of VLC
pin is turned off.
Page 142
TMP86CH22UG
15.4 Control Method of LCD Driver
15.4.1 Initial setting
Figure 15-4 shows the flowchart of initialization.
Example :To operate a 1/4 duty LCD of 32 segments × 4 com-mons at frame frequency fc/216 [Hz],
The period of enabling of the low bleeder resistor: 28/fc
LD
(LCDCR), 00000001B
; Sets LCD driving method, The period of enabling of low bleeder
resistor and frame frequency.
LD
(P*LCR), 0FFH
; Sets segment output control register. (*; Port No.)
:
:
:
:
LD
; Sets the initial value of display data.
(LCDCR), 10000001B
; Display enable
Sets LCD driving method (DUTY).
Sets frame frequency (SLF).
Selects period of enabling
of low resistor (LRSE).
Sets segment output control registers
(P*LCR (*; Port No.))
Initialization of display data area.
Display enable (EDSP)
(Releases from blanking.)
Figure 15-4 Initial Setting of LCD Driver
15.4.2 Store of display data
Generally, display data are prepared as fixed data in program memory (ROM) and stored in display data area
by load command.
Example :(1) To display using 1/4 duty LCD a numerical value which corresponds to the LCD data stored in data memory
at address 80H (when pins COM and SEG are connected to LCD as in Figure 15-5), display data become as
shown in Table 15-5.
LD
A, (80H)
ADD
A, TABLE-$-7
LD
HL, 0F85H
LD
W, (PC + A)
LD
(HL), W
RET
TABLE:
DB
11011111B, 00000110B,
11100011B, 10100111B,
00110110B, 10110101B,
11110101B, 00010111B,
11110111B, 10110111B
Note:DB is a byte data definition instruction.
Page 143
15. LCD Driver
15.3 LCD Display Operation
TMP86CH22UG
COM0
COM1
COM2
COM3
SEG10
SEG11
Figure 15-5 Example of COM, SEG Pin Connection (1/4 duty)
Table 15-5 Example of Display Data (1/4 duty)
No.
Display
Display data
No.
Display
Display data
0
11011111
5
10110101
1
00000110
6
11110101
2
11100011
7
00000111
3
10100111
8
11110111
4
00110110
9
10110111
Example: (2) Table 15-6 shows an example of display data which are displayed using 1/2 duty LCD in the
same way as Table 15-5. The connection between pins COM and SEG are the same as shown in Figure 15-6.
COM0
SEG13
SEG10
SEG12
COM1
SEG11
Figure 15-6 Example of COM, SEG Pin Connection
Page 144
TMP86CH22UG
Table 15-6 Example of Display Data (1/2 duty)
Display data
Display data
Number
Number
High order address
Low order address
High order address
Low order address
0
**01**11
**01**11
5
**11**10
**01**01
1
**00**10
**00**10
6
**11**11
**01**01
2
**10**01
**01**11
7
**01**10
**00**11
3
**10**10
**01**11
8
**11**11
**01**11
4
**11**10
**00**10
9
**11**10
**01**11
Note: *: Don’t care
15.4.3 Example of LCD driver output
COM0
COM1
COM2
COM3
SEG10
SEG11
EDSP
VLC
SEG10
0
VLC
SEG11
Display data area
0
VLC
COM0
0
Address
0F85H
VLC
1011 0101
COM1
0
VLC
COM2
0
VLC
COM3
0
VLCD
0
COM0-SEG10
(Selected)
-VLCD
VLCD
0
COM2-SEG11
(Non selected)
-VLCD
Figure 15-7 1/4 Duty (1/3 Bias) Drive
Page 145
15. LCD Driver
15.3 LCD Display Operation
TMP86CH22UG
SEG11
SEG10
SEG12
COM0
COM1
COM2
EDSP
VLC
SEG10
0
VLC
Display data area
SEG11
0
VLC
Address
SEG12
0F85H
*111 *010
0F86H
**** *001
0
VLC
COM0
0
VLC
*: Don’t care
COM1
0
VLC
COM2
0
VLCD
COM0-SEG11
(Selected)
0
-VLCD
VLCD
COM1-SEG12
(Non selected)
0
-VLCD
Figure 15-8 1/3 Duty (1/3 Bias) Drive
Page 146
TMP86CH22UG
SEG11
SEG10
SEG12
COM0
COM1
COM2
EDSP
VDD
SEG10
VLC
Display data area
Address
VLC
VDD
SEG12
0F85H
*111 *010
0F86H
**** *001
*: Don’t care
VDD
SEG11
VLC
VDD
COM0
VLC
VDD
COM1
VLC
VDD
COM2
VLC
VLCD
COM0-SEG11
(Selected)
0
-VLCD
VLCD
0
-VLCD
COM1-SEG12
(Non selected)
Figure 15-9 1/3 Duty (1/2 Bias) Drive
Page 147
15. LCD Driver
15.3 LCD Display Operation
TMP86CH22UG
COM0
SEG10
SEG13
SEG12
COM1
SEG11
EDSP
VDD
SEG10
VLC
VDD
Display data area
SEG11
Address
SEG12
0F85H
**01 **01
0F86H
**11 **10
*: Don’t care
VLC
VDD
VLC
VDD
SEG13
VLC
VDD
COM0
VLC
VDD
COM1
VLC
VLCD
0
COM0-SEG11
(Selected)
-VLCD
COM1-SEG12
(Non selected)
VLCD
0
-VLCD
Figure 15-10 1/2 Duty (1/2 Bias) Drive
Page 148
TMP86CH22UG
SEG10
SEG11
SEG15
SEG16
SEG14
SEG12
SEG13
SEG17
COM0
Display data area
EDSP
Address
0F85H
***0 ***1
0F86H
***1 ***1
0F87H
***1 ***0
0F88H
***0 ***1
VDD
SEG10
VLC
VDD
SEG14
VLC
VDD
*: Don’t care
SEG17
VLC
VDD
COM0
VLC
VLCD
COM0-SEG10
(Selected)
0
-VLCD
VLCD
COM0-SEG14
0
(Non selected)
-VLCD
Figure 15-11 Static Drive
Page 149
15. LCD Driver
15.3 LCD Display Operation
TMP86CH22UG
Page 150
TMP86CH22UG
16. Input/Output Circuit
16.1 Control pins
The input/output circuitries of the TMP86CH22UG control pins are shown below.
Control Pin
I/O
Input/Output Circuitry
Remarks
Osc.enable
fc
VDD
XIN
XOUT
Resonator connecting pins
(high frequency)
VDD
Rf
Input
Output
RO
Rf = 1.2 MΩ (typ.)
RO =0.5 kΩ (typ.)
XIN
XOUT
XTEN
Osc.enable
XTIN
XTOUT
Input
Output
fs
VDD
VDD
Rf
RO
Resonator connecting pins
(Low frequency)
Rf = 6 MΩ (typ.)
RO = 220 kΩ (typ.)
XTIN
XTOUT
VDD
R RIN
RESET
Input
Address-trap-reset
Hysteresis input
Pull-up resistor
RIN = 220 kΩ (typ.)
R = 100 Ω (typ.)
Watchdog-timer-reset
System-clock-reset
VDD
TEST
Input
Pull-down resistor
RIN = 70 kΩ (typ.)
R
RIN
R = 100 Ω (typ.)
Note: The TEST pin of TMP86PH22UG does not have a pull-down resistor. Fix the TEST pin at Low level.
Page 151
16. Input/Output Circuit
16.2 Input/Output Ports
TMP86CH22UG
16.2 Input/Output Ports
Port
I/O
Input/Output Circuitry
Remarks
Initial "High-Z"
SEG output
VDD
Data output
P1
I/O
Output latch input
Disable
R
Tri-stateo I/O
Hysteresis input
R = 100 Ω (typ.)
LCD segment output
Pin input
Initial "High-Z"
SEG output
P5
P70
to
P76
VDD
Data output
I/O
Tri-stateo I/O
R = 100 Ω (typ.)
LCD segment output
Output latch input
Disable
R
Pin input
Initial "High-Z"
VDD
Output latch input
P20
I/O
Data output
Disable
R
Sink open drain output
Hysteresis input
R = 100 Ω (typ.)
Pin input
Initial "High-Z"
P21
P22
VDD
Output latch input
I/O
Data output
Disable
R
Sink open drain output
Hysteresis input
R = 100 Ω (typ.)
Pin input
Initial "High-Z"
VDD
Data output
P33
P34
I/O
Output latch input
Disable
R
Pin input
Page 152
Tri-stateo I/O
Hysteresis input
High current output (Nch)
R = 100 Ω (typ.)
TMP86CH22UG
Port
I/O
Input/Output Circuitry
Remarks
Initial "High-Z"
P37
Output
VDD
Sink open drain output
High current output (Nch)
Output latch input
Data output
Disable
Initial "High-Z"
Analog input
VDD
Data output
P61
to
P64
Output latch input
I/O
Disable
R
Pin input
Key-on Wakeup
Page 153
Tri-stateo I/O
Hysteresis input
R = 100 Ω (typ.)
Analog input
Key on wake up input (P64 only)
16. Input/Output Circuit
16.2 Input/Output Ports
TMP86CH22UG
Page 154
TMP86CH22UG
17. Electrical Characteristics
17.1 Absolute Maximum Ratings
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant.
Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down
or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when
designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
(VSS = 0 V)
Parameter
Symbol
Pins
Rating
Unit
Supply Voltage
VDD
−0.3 to 6.5
V
Input Voltage
VIN
−0.3 to VDD + 0.3
V
VOUT1
−0.3 to VDD + 0.3
V
Output Voltage
Output Current (Per 1 pin)
Output Current (Total)
Power Dissipation [Topr = 85°C]
IOUT1
P1, P33, P34, P5, P6, P7 Port
−1.8
IOUT2
P1, P2, P5, P6, P7 Port
3.2
IOUT3
P33, P34, P37 Port
30
Σ IOUT1
P1, P33, P34, P5, P6, P7 Port
−30
Σ IOUT2
P1, P2, P5, P6, P7 Port
60
Σ IOUT3
P33, P34, P37 Port
PD
mA
60
350
Soldering Temperature (Time)
Tsld
260 (10 s)
Storage Temperature
Tstg
−55 to 125
Operating Temperature
Topr
−40 to 85
Page 155
°C
17. Electrical Characteristics
17.2 Recommended Operating Condition
TMP86CH22UG
17.2 Recommended Operating Condition
The recommended operating conditions for a device are operating conditions under which it can be guaranteed that
the device will operate as specified. If the device is used under operating conditions other than the recommended
operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may
occur. Thus, when designing products which include this device, ensure that the recommended operating conditions
for the device are always adhered to.
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Pins
Condition
fc = 16 MHz
fc = 8 MHz
Supply Voltage
VDD
fc = 4.2MHz
fs = 32.768
kHz
NORMAL1, 2 mode
IDLE0, 1, 2 mode
NORMAL1, 2 mode
IDLE0, 1, 2 mode
Min
Max
Unit
4.5
2.7
NORMAL1, 2 mode
5.5
IDLE0, 1, 2 mode
SLOW1, 2 mode
1.8
(Note1)
SLEEP0, 1, 2 mode
V
STOP mode
Input High Level
VIH1
Except Hysteresis input
VIH2
Hysteresis input
VDD < 4.5 V
VIH3
Input Low Level
VDD ≥ 4.5 V
VIL1
Except Hysteresis input
VIL2
Hysteresis input
VDD ≥ 4.5 V
VDD × 0.70
VDD × 0.75
VDD × 0.90
VDD × 0.30
0
VDD = 1.8 V to 5.5 V
Clock Frequency
fc
XIN, XOUT
fs
XTIN, XTOUT
VDD = 2.7 V to 5.5 V
4.2
1.0
8.0
30.0
34.0
VDD = 4.5 V to 5.5 V
MHz
16.0
Note 1: When the supply voltage is 1.8 V ≤VDD < 2.0 V, the operating temperature is Topr = −20 to 85°C.
Page 156
VDD × 0.25
VDD × 0.10
VDD < 4.5 V
VIL3
VDD
kHz
TMP86CH22UG
17.3 DC Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Pins
Condition
Min
Typ.
Max
Unit
–
0.9
–
V
VHS
Hysteresis input
IIN1
TEST
VDD = 5.5 V, VIN = 0 V
–
–
−2
IIN2
Sink Open Drain,
Tri-state
VDD = 5.5 V, VIN = 5.5 V/0 V
–
–
±2
IIN3
RESET
VDD = 5.5 V, VIN = 5.5 V
–
–
+2
RIN1
TEST Pull-Down
VDD = 5.5 V, VIN = 5.5 V
–
70
–
RIN2
RESET Pull-Up
VDD = 5.5 V, VIN = 0 V
100
220
450
ILO1
Sink Open Drain Port
VDD = 5.5 V, VOUT = 5.5 V
–
–
2
ILO2
Tri-state Port
VDD = 5.5 V, VOUT = 5.5 V/0 V
–
–
±2
VOH
C-MOS, Tri-state Port
VDD = 4.5 V, IOH = −0.7 mA
4.1
–
–
Output Low Voltage
VOL
Except XOUT, P33, P34
and P37 Port
VDD = 4.5 V, IOL = 1.6 mA
–
–
0.4
Output Low Current
IOL
High Current Port (P33,
P34 and P37 Port)
VDD = 4.5 V, VOL = 1.0 V
–
20
–
–
11.1
16.0
–
7.1
11.0
Hysteresis Voltage
Input Current
Input Resistance
Output leakage current
Output High Voltage
VDD = 5.5 V
Supply Current in
NORMAL1, 2 mode
VIN = 5.3 V/0.2 V
fc = 16 MHz
fs = 32.768 kHz
(Except LCD current, Include AD
current)
Supply Current in
IDLE0, 1, 2 mode
VDD = 5.5 V
Supply Current in
NORMAL1, 2 mode
Supply Current in
IDLE0, 1, 2 mode
Supply Current in
SLOW1 mode
Supply Current in
SLEEP1 mode
Supply Current in
SLEEP0 mode
Supply Current in
STOP mode
VIN = 5.3 V/0.2 V
IDD
fc = 16 MHz
fs = 32.768 kHz
(Except LCD and AD current)
VDD = 3.0 V
VIN = 2.8 V/0.2 V
fs = 32.768 kHz
(Except LCD current)
VDD = 5.5 V
VIN = 5.3 V/0.2 V
µA
kΩ
µA
V
mA
mA
–
10.5
15.0
–
6.5
10.0
–
10
21
–
7.5
16
–
5
12
–
0.5
10
µA
Note 1: Typical values show those at Topr = 25°C, VDD = 5 V
Note 2: Input current (IIN1, IIN3): The current through pull-up or pull-down resistor is not included.
Note 3: When the LCD driver is enable, ILCD current is added to IDD. Refer to the LCD characteristics about ILCD. When the AD
converter is enable, ladder resistance current is added to IDD.
Note 4: The supply currents of SLOW2 and SLEEP2 modes are equivalent to IDLE0, 1, 2.
Page 157
17. Electrical Characteristics
17.4 LCD Characteristics
TMP86CH22UG
17.4 LCD Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
Symbol
Pins
Condition
Min
Typ.
Max
–
92
–
–
9.2
–
Unit
VDD = 5.5 V, VLC = 0 V
ROS1 = ROC1 = 20kΩ
1/4 Duty, 1/3 Bias
VDD = 5.5 V, VLC = 0 V
ROS1 = ROC1 = 200kΩ
LCD resistor current
(VDD - VLC)
1/4 Duty, 1/3 Bias
ILCD
µA
VDD = 3.0 V, VLC = 0 V
ROS1 = ROC1 = 20kΩ
–
50
–
–
5
–
1/4 Duty, 1/3 Bias
VDD = 3.0 V, VLC = 0 V
ROS1 = ROC1 = 200kΩ
1/4 Duty, 1/3 Bias
Segment Output Low
Resistance
ROS1
SEG pin
–
20
–
Common Output Low
Resistance
ROC1
COM pin
–
20
–
Segment Output
High Resistance
ROS2
SEG pin
–
200
–
Common Output
High Resistance
ROC2
COM pin
–
200
–
3.8
–
4.2
3.3
–
3.7
2.8
–
3.2
kΩ
VO2/3
Segment/Common
Output Voltage
VO1/2
SEG/COM pin
VDD = 5.0 V, VLC = 2.0 V
VO1/3
Note 1: Output resistors ROS and ROC indicate "ON" when swiching levels.
Note 2: VO2/3 indicates the output voltage at 2/3 level when operating in the 1/4 or 1/3 duty mode.
Note 3: VO1/2 indicates the output voltage at 1/2 level when operating in the 1/2 or static duty mode.
Note 4: VO1/3 indicates the output voltage at 1/3 level when operating in the 1/4 or 1/3 duty mode.
Note 5: When using LCD, it is necessary to consider values of ROS1/2 and ROC1/2.
Page 158
V
TMP86CH22UG
17.5 AD Conversion Characteristics
(VSS = 0.0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −40 to 85°C)
Parameter
Analog Input Voltage
Symbol
Condition
VAIN
Min
Typ.
Max
Unit
VSS
–
VDD
V
–
–
±1
Zero Point Error
VDD = 5.0 V
–
–
±1
Full Scale Error
VSS = 0.0 V
–
–
±1
–
–
±2
Non linearity Error
Total Error
LSB
(VSS = 0.0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −40 to 85°C)
Parameter
Analog Input Voltage
Symbol
Condition
VAIN
Min
Typ.
Max
Unit
VSS
–
VDD
V
–
–
±1
Zero Point Error
VDD = 2.7 V
–
–
±1
Full Scale Error
VSS = 0.0 V
–
–
±1
–
–
±2
Non linearity Error
Total Error
LSB
(VSS = 0.0 V, 2.0 V ≤ VDD < 2.7 V, Topr = −40 to 85°C) (Note 4)
(VSS = 0.0 V, 1.8 V ≤ VDD < 2.0 V, Topr = −10 to 85°C) (Note 4)
Parameter
Analog Input Voltage
Symbol
Condition
VAIN
Min
Typ.
Max
Unit
VSS
–
VDD
V
–
–
±2
Zero Point Error
VDD = 1.8 V
–
–
±2
Full Scale Error
VSS = 0.0 V
–
–
±2
–
–
±4
Non linearity Error
Total Error
LSB
Note 1: The total error includes all errors except a quantization error, and is defined as maximum deviation from the ideal
conversion line.
Note 2: Conversion time is different in recommended value by power supply voltage.
About conversion time, please refer to “8-bit AD converter (ADC)”.
Note 3: Please use input voltage to AIN input Pin in limit of VDD − VSS.
When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel
conversion value.
Note 4: When AD is used with VDD < 2.0 V, the guaranteed temperature range varies with the operating voltage.
Page 159
17. Electrical Characteristics
17.6 AC Characteristics
TMP86CH22UG
17.6 AC Characteristics
(VSS = 0 V, VDD = 4.5 to 5.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.25
–
4
117.6
–
133.3
For external clock operation
(XIN input)
fc = 16 MHz
–
31.25
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
NORMAL1, 2 mode
Machine Cycle Time
tcy
IDLE1, 2 mode
SLOW1, 2 mode
SLEEP1, 2 mode
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
Unit
µs
(VSS = 0 V, VDD = 2.7 to 4.5 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
NORMAL1, 2 mode
Machine Cycle Time
tcy
IDLE1, 2 mode
SLOW1, 2 mode
tWCH
Low Level Clock Pulse Width
tWCL
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
Typ.
Max
0.5
–
4
Unit
µs
117.6
–
133.3
For external clock operation
(XIN input)
fc = 8 MHz
–
62.5
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
SLEEP1, 2 mode
High Level Clock Pulse Width
Min
(VSS = 0 V, VDD = 1.8 to 2.7 V, Topr = −40 to 85°C)
Parameter
Symbol
Condition
Min
Typ.
Max
0.95
–
4
117.6
–
133.3
For external clock operation
(XIN input)
fc = 4.2 MHz
–
119.05
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
NORMAL1, 2 mode
Machine Cycle Time
tcy
IDLE1, 2 mode
SLOW1, 2 mode
SLEEP1, 2 mode
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
High Level Clock Pulse Width
tWCH
Low Level Clock Pulse Width
tWCL
µs
Note 1: When the supply voltage is 1.8 V ≤VDD < 2.0 V, the operating temperature is Topr = −20 to 85°C.
Page 160
Unit
TMP86CH22UG
17.7 Timer Counter 1 input (ECIN) Characteristics
(VSS = 0 V, Topr = −40 to 85°C)
Parameter
TC1 input (ECIN input)
Symbol
tTC1
Condition
Min
Typ.
Max
Frequency measurement mode
VDD = 4.5 to 5.5 V
Single edge count
–
–
16
Both edge count
–
–
16
Frequency measurement mode
VDD = 2.7 to 4.5 V
Single edge count
–
–
8
Both edge count
–
–
8
Frequency measurement mode
VDD = 1.8 to 2.7 V
Single edge count
–
–
4.2
Both edge count
–
–
4.2
Page 161
Unit
MHz
17. Electrical Characteristics
17.8 Recommended Oscillating Conditions
TMP86CH22UG
17.8 Recommended Oscillating Conditions
XIN
C1
XOUT
XTIN
C2
XTOUT
C1
(1) High-frequency Oscillation
C2
(2) Low-frequency Oscillation
Note 1: A quartz resonator can be used for high-frequency oscillation only when VDD is 2.7 V or above. If VDD is below 2.7
V, use a ceramic resonator.
Note 2: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these
factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the
device will actually be mounted.
Note 3: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by
Murata Manufacturing Co., Ltd.
For details, please visit the website of Murata at the following URL:
http://www.murata.com
17.9 Handling Precaution
- The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown
below.
1. When using the Sn-37Pb solder bath
Solder bath temperature = 230 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
2. When using the Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature = 245 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
Note: The pass criteron of the above test is as follows:
Solderability rate until forming ≥ 95 %
- When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we
recommend electrically shielding the package in order to maintain normal operating condition.
Page 162
TMP86CH22UG
18. Package Dimension
P-LQFP44-1010-0.80B
Unit: mm
12.0 0.2
0.08
0.07
0.2
0.25
0.145
0.055
0.1 0.05 1.4 0.05
0.8
0.6 0.15
Page 163
1.6MAX
0.37
1.0TYP
12.0 0.2
10.0 0.2
10.0 0.2
18. Package Dimension
TMP86CH22UG
Page 164
This is a technical document that describes the operating functions and electrical specifications of the 8-bit
microcontroller series TLCS-870/C (LSI).
Toshiba provides a variety of development tools and basic software to enable efficient software
development.
These development tools have specifications that support advances in microcomputer hardware (LSI) and
can be used extensively. Both the hardware and software are supported continuously with version updates.
The recent advances in CMOS LSI production technology have been phenomenal and microcomputer
systems for LSI design are constantly being improved. The products described in this document may also
be revised in the future. Be sure to check the latest specifications before using.
Toshiba is developing highly integrated, high-performance microcomputers using advanced MOS
production technology and especially well proven CMOS technology.
We are prepared to meet the requests for custom packaging for a variety of application areas.
We are confident that our products can satisfy your application needs now and in the future.