TOSHIBA TMP86CH72FG

8 Bit Microcontroller
TLCS-870/C Series
TMP86CH72FG
The information contained herein is subject to change without notice. 021023_D
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.
Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
The TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.).
These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of
human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended
Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.
021023_B
The products described in this document shall not be used or embedded to any downstream products of
which manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patents or other rights of TOSHIBA or the third parties. 070122_C
The products described in this document are subject to foreign exchange and foreign trade control
laws. 060925_E
For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
© 2007 TOSHIBA CORPORATION
All Rights Reserved
Revision History
Date
Revision
2007/10/4
1
First Release
Table of Contents
TMP86CH72FG
1.1
1.2
1.3
1.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
3
4
5
2. Operational Description
2.1
CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
2.1.2
2.1.3
Memory Address Map............................................................................................................................... 9
Program Memory (MaskROM).................................................................................................................. 9
Data Memory (RAM) ................................................................................................................................. 9
2.2.1
2.2.2
Clock Generator...................................................................................................................................... 10
Timing Generator .................................................................................................................................... 12
2.2
System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2.1
2.2.2.2
Configuration of timing generator
Machine cycle
2.2.3.1
2.2.3.2
2.2.3.3
Single-clock mode
Dual-clock mode
STOP mode
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
STOP mode
IDLE1/2 mode and SLEEP1/2 mode
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
SLOW mode
2.2.3
2.2.4
2.3
Operation Mode Control Circuit .............................................................................................................. 13
Operating Mode Control ......................................................................................................................... 18
Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.1
2.3.2
2.3.3
2.3.4
External Reset Input ............................................................................................................................... 31
Address trap reset .................................................................................................................................. 32
Watchdog timer reset.............................................................................................................................. 32
System clock reset.................................................................................................................................. 32
3. Interrupt Control Circuit
3.1
3.2
Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.1
3.2.2
Interrupt master enable flag (IMF) .......................................................................................................... 36
Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 36
3.4.1
3.4.2
Interrupt acceptance processing is packaged as follows........................................................................ 39
Saving/restoring general-purpose registers ............................................................................................ 40
3.3
3.4
Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4.2.1
3.4.2.2
Using PUSH and POP instructions
Using data transfer instructions
3.4.3
Interrupt return ........................................................................................................................................ 42
3.5.1
3.5.2
Address error detection .......................................................................................................................... 43
Debugging .............................................................................................................................................. 43
3.5
Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
i
3.6
3.7
3.8
Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4. Program Patch Logic
4.1
4.2
4.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.1
Address jump mode ................................................................................................................................ 50
4.3.1.1
Setting the registers
4.3.2.1
Setting the registers
4.3.3.1
Setting the registers
4.3.2
4.3.3
1-byte data replacement mode ............................................................................................................... 52
2-byte data replacement mode ............................................................................................................... 53
5. Special Function Register (SFR)
5.1
5.2
SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6. I/O Ports
6.1
6.2
6.3
6.4
6.5
Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port P5 (P52 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ports P6 (P67 to P60), P7 (P77 to P70), P8 (P87 to P80),
and P9 (P97 to P90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
66
67
69
70
7. Watchdog Timer (WDT)
7.1
7.2
Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Malfunction Detection Methods Using the Watchdog Timer ...................................................................
Watchdog Timer Enable .........................................................................................................................
Watchdog Timer Disable ........................................................................................................................
Watchdog Timer Interrupt (INTWDT)......................................................................................................
Watchdog Timer Reset ...........................................................................................................................
72
73
74
74
75
7.3.1
7.3.2
7.3.3
7.3.4
Selection of Address Trap in Internal RAM (ATAS) ................................................................................
Selection of Operation at Address Trap (ATOUT) ..................................................................................
Address Trap Interrupt (INTATRAP).......................................................................................................
Address Trap Reset ................................................................................................................................
76
76
76
77
7.3
Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8. Time Base Timer (TBT)
8.1
Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.1.1
8.1.2
ii
Configuration .......................................................................................................................................... 79
Control .................................................................................................................................................... 79
8.1.3
Function .................................................................................................................................................. 80
8.2.1
8.2.2
Configuration .......................................................................................................................................... 81
Control .................................................................................................................................................... 81
8.2
Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9. 16-Bit Timer/Counter2 (TC2)
9.1
9.2
9.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.3.1
9.3.2
9.3.3
Timer mode............................................................................................................................................. 85
Event counter mode................................................................................................................................ 87
Window mode ......................................................................................................................................... 87
10. 8-Bit TimerCounter 3 (TC3)
10.1
10.2
10.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.3.1 Timer mode........................................................................................................................................... 92
Figure 10-3 ...................................................................................................................................................... 94
10.3.3 Capture Mode ....................................................................................................................................... 95
11. 8-Bit TimerCounter 4 (TC4)
11.1
11.2
11.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.3.1
11.3.2
11.3.3
11.3.4
Timer Mode........................................................................................................................................... 99
Event Counter Mode ........................................................................................................................... 100
Programmable Divider Output (PDO) Mode ....................................................................................... 101
Pulse Width Modulation (PWM) Output Mode .................................................................................... 102
12. Synchronous Serial Interface (SIO)
12.1
12.2
12.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
12.3.1
Clock source
Shift edges
12.3.2.1
12.3.2.2
MSB transfer
LSB transfer
12.3.3.1
12.3.3.2
12.3.3.3
12.3.3.4
12.3.3.5
12.3.3.6
Transmit mode
Transmit error
Receive mode
Receive error
Transmit/receive mode
Transmit/receive error
12.3.2
12.3.3
12.4
Serial clock ......................................................................................................................................... 108
12.3.1.1
12.3.1.2
Transfer bit direction ........................................................................................................................... 110
Transfer modes................................................................................................................................... 110
Chip selection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
iii
13. Asynchronous Serial interface (UART )
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.8.1
13.8.2
Data Transmit Operation .................................................................................................................... 130
Data Receive Operation ..................................................................................................................... 130
13.9.1
13.9.2
13.9.3
13.9.4
13.9.5
13.9.6
Parity Error..........................................................................................................................................
Framing Error......................................................................................................................................
Overrun Error ......................................................................................................................................
Receive Data Buffer Full.....................................................................................................................
Transmit Data Buffer Empty ...............................................................................................................
Transmit End Flag ..............................................................................................................................
13.9
125
126
128
129
129
130
130
130
Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
131
131
131
132
132
133
14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.1
14.2
14.3
14.4
14.5
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Data Format in the I2C Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.5.1
Acknowledgement mode specification................................................................................................ 139
14.5.1.1
14.5.1.2
Acknowledgment mode (ACK = “1”)
Non-acknowledgment mode (ACK = “0”)
14.5.3.1
14.5.3.2
Clock source
Clock synchronization
14.5.2
14.5.3
Number of transfer bits ....................................................................................................................... 140
Serial clock ......................................................................................................................................... 140
14.5.4
14.5.5
14.5.6
14.5.7
14.5.8
14.5.9
14.5.10
14.5.11
14.5.12
14.5.13
Slave address and address recognition mode specification ...............................................................
Master/slave selection ........................................................................................................................
Transmitter/receiver selection.............................................................................................................
Start/stop condition generation ...........................................................................................................
Interrupt service request and cancel...................................................................................................
Setting of I2C bus mode .....................................................................................................................
Arbitration lost detection monitor ......................................................................................................
Slave address match detection monitor............................................................................................
GENERAL CALL detection monitor ..................................................................................................
Last received bit monitor...................................................................................................................
14.6.1
14.6.2
14.6.3
Device initialization ............................................................................................................................. 145
Start condition and slave address generation..................................................................................... 145
1-word data transfer............................................................................................................................ 145
14.6
135
135
135
136
137
141
141
141
142
142
143
143
144
144
144
Data Transfer of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
14.6.3.1
14.6.3.2
14.6.4
14.6.5
When the MST is “1” (Master mode)
When the MST is “0” (Slave mode)
Stop condition generation ................................................................................................................... 148
Restart ................................................................................................................................................ 149
15. 8-Bit AD Converter (ADC)
15.1
iv
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
15.2
15.3
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
15.3.1
15.3.2
15.3.3
15.3.4
AD Conveter Operation ......................................................................................................................
AD Converter Operation .....................................................................................................................
STOP and SLOW Mode during AD Conversion .................................................................................
Analog Input Voltage and AD Conversion Result ...............................................................................
15.4.1
15.4.2
15.4.3
Analog input pin voltage range ........................................................................................................... 157
Analog input shared pins .................................................................................................................... 157
Noise countermeasure........................................................................................................................ 157
15.4
154
154
155
156
Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
16. Key-on Wakeup (KWU)
16.1
16.2
16.3
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
17. Vacuum Fluorescent Tube (VFT) Driver Circuit
17.1
17.2
17.3
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
17.3.1
17.3.2
Setting of Display mode ...................................................................................................................... 166
Display data setting ............................................................................................................................ 166
17.5.1
17.5.2
For Conventional type VFT ................................................................................................................. 168
For Grid scan type VFT ...................................................................................................................... 169
17.6.1
High-breakdown voltage buffer ........................................................................................................... 170
17.4
17.5
17.6
Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Example of Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Port Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
17.6.1.1
Ports P6 to P9
17.6.2.1
17.6.2.2
When outputting
When inputting
17.6.2
Caution ............................................................................................................................................... 170
18. Input/Output Circuitry
18.1
18.2
Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Input/Output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
19. Electrical Characteristics
19.1
19.2
19.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
How to Calculate Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
19.3.1 Power consumption Pmax = Operating power consumption
+ Normal output port loss + VFT driver loss. ............................................................................................ 177
19.4
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
19.4.1
19.4.2
19.5
19.6
DC Characteristics (1) (VDD = 5 V) .................................................................................................... 178
DC Characteristics (2) (VDD = 3 V) .................................................................................................... 179
AD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
v
19.7 HSIO AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Note 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Note 2:
Note 2:
19.8
19.9
........................................................................................................................................................... 182
........................................................................................................................................................... 182
Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
20. Package Dimensions
This is a technical document that describes the operating functions and electrical
specifications of the 8-bit microcontroller series TLCS-870/C (LSI).
vi
TMP86CH72FG
CMOS 8-Bit Microcontroller
TMP86CH72FG
Product No.
ROM
(MaskROM)
RAM
Package
OTP MCU
Emulation Chip
TMP86CH72FG
16384
bytes
1024
bytes
QFP64-P-1414-0.80C
TMP86PM72FG
TMP86C972XB
1.1 Features
1. 8-bit single chip microcomputer TLCS-870/C series
- Instruction execution time :
0.25 µs (at 16 MHz)
122 µs (at 32.768 kHz)
- 132 types & 731 basic instructions
2. 19interrupt sources (External : 6 Internal : 13)
3. Input / Output ports (54 pins)
Large current output: 2pins (Typ. 20mA), LED direct drive
4. Watchdog Timer
5. Prescaler
- Time base timer
- Divider output function
6. 16-bit timer counter: 1 ch
- Timer, Event counter, Window modes
7. 8-bit timer counter : 1 ch
- Timer, Event counter, Capture modes
8. 8-bit timer counter : 1 ch
- Timer, Event counter, Pulse width modulation (PWM) output,
Programmable divider output (PDO) modes
9. Serial Interface
- 8-bit SIO :1 channel (32 bytes Buffer)
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's
own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or
sale are prohibited under any applicable laws and regulations. 060106_Q
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C
• The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance/Handling Precautions. 030619_S
Page 1
1.1 Features
TMP86CH72FG
10. 8-bit UART : 1 ch
11. Serial Bus Interface(I2C Bus): 1ch
12. 8-bit successive approximation type AD converter (with sample hold)
Analog inputs: 6ch
13. Key-on wakeup : 4 ch
14. Vacuum flouorescent tube driver (automatic display)
- Programmable grid scan
- High breakdown voltage ports(MAX 40 V × 37 bits)
15. Clock operation
Single clock mode
Dual clock mode
16. Low power consumption operation
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
stop.)
SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock
oscillate.)
IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interruputs(CPU restarts).
IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts).
SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.
SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts).
SLEEP2 mode: CPU stops and peripherals operate using high and low frequency clock.
interruput.
17. Wide operation voltage:
4.5 V to 5.5 V at 16MHz /32.768 kHz
2.7 V to 5.5 V at 8 MHz /32.768 kHz
Page 2
Release by
TMP86CH72FG
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
RESET
(TC2/INT5/STOP) P20
(TC3/INT3) P10
(TC4/PWM4/PDO4) P11
(TXD) P12
(RXD/INT2) P13
(SDA/SI) P14
(SCL/SO) P15
(SCK) P16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VSS
XIN
XOUT
TEST
VDD
(XTIN) P21
(XTOUT) P22
(V14) P76
(V13) P75
(V12) P74
(V11) P73
(V10) P72
(V9) P71
(V8) P70
(V7) P67
(V6) P66
(V5) P65
(V4) P64
(V3) P63
(V2) P62
(V1) P61
(V0) P60
VDD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P77 (V15)
P80 (V16)
P81 (V17)
P82 (V18)
P83 (V19)
P84 (V20)
P85 (V21)
P86 (V22)
P87 (V23)
P90 (V24)
P91 (V25)
P92 (V26)
P93 (V27)
P94 (V28)
P95 (V29)
P96 (V30)
1.2 Pin Assignment
Figure 1-1 Pin Assignment
Page 3
P97(V31)
VKK
VAREF
P47(AIN5/STOP5)
P46(AIN4/STOP4)
P45(AIN3/STOP3)
P44(AIN2/STOP2)
P43(AIN1)
P42(AIN0)
AVSS
P41
P40
P52(INT1)
P51(INT0)
P50(DVO)
P17(CS/INT4)
1.3 Block Diagram
TMP86CH72FG
1.3 Block Diagram
Figure 1-2 Block Diagram
Page 4
TMP86CH72FG
1.4 Pin Names and Functions
Table 1-1 Pin Names and Functions(1/3)
Pin Name
Pin Number
Input/Output
Functions
17
IO
I
I
PORT17
SIO chip select input
External interrupt 4 input
16
IO
IO
PORT16
Serial clock input/output
P15
SO
SCL
15
IO
O
O
PORT15
Serial data output
I2C bus clock
P14
SI
SDA
14
IO
I
I
PORT14
Serial data input
I2C bus data
P13
INT2
RXD
13
IO
I
I
PORT13
External interrupt 2 input
UART data input
P12
TXD
12
IO
O
PORT12
UART data output
11
IO
O
I
PORT11
PWM4/PDO4 output
TC4 input
P10
INT3
TC3
10
IO
I
I
PORT10
External interrupt 3 input
TC3 pin input
P22
XTOUT
7
IO
O
PORT22
Resonator connecting pins(32.768kHz) for inputting external
clock
P21
XTIN
6
IO
I
PORT21
Resonator connecting pins(32.768kHz) for inputting external
clock
9
IO
I
I
I
PORT20
STOP mode release signal input
External interrupt 5 input
TC2 input
P47
AIN5
STOP5
29
IO
I
I
PORT47
AD converter analog input 5
STOP5 input
P46
AIN4
STOP4
28
IO
I
I
PORT46
AD converter analog input 4
STOP4 input
P45
AIN3
STOP3
27
IO
I
I
PORT45
AD converter analog input 3
STOP3 input
P44
AIN2
STOP2
26
IO
I
I
PORT44
AD converter analog input 2
STOP2 input
P43
AIN1
25
IO
I
PORT43
AD converter analog input 1
P42
AIN0
24
IO
I
PORT42
AD converter analog input 0
P17
CS
INT4
P16
SCK
P11
PWM4/PDO4
TC4
P20
STOP
INT5
TC2
Page 5
1.4 Pin Names and Functions
TMP86CH72FG
Table 1-1 Pin Names and Functions(2/3)
Pin Name
Pin Number
Input/Output
Functions
P41
22
IO
PORT41
P40
21
IO
PORT40
P52
INT1
20
IO
I
PORT52
External interrupt 1 input
19
IO
I
PORT51
External interrupt 0 input
18
IO
O
PORT50
Divider Output
P67
V7
56
IO
O
PORT67
Grid output7
P66
V6
57
IO
O
PORT66
Grid output6
P65
V5
58
IO
O
PORT65
Grid output5
P64
V4
59
IO
O
PORT64
Grid output4
P63
V3
60
IO
O
PORT63
Grid output3
P62
V2
61
IO
O
PORT62
Grid output2
P61
V1
62
IO
O
PORT61
Grid output1
P60
V0
63
IO
O
PORT60
Grid output0
P77
V15
48
IO
O
PORT77
Grid output15
P76
V14
49
IO
O
PORT76
Grid output14
P75
V13
50
IO
O
PORT75
Grid output13
P74
V12
51
IO
O
PORT74
Grid output12
P73
V11
52
IO
O
PORT73
Grid output11
P72
V10
53
IO
O
PORT72
Grid output10
P71
V9
54
IO
O
PORT71
Grid output9
P70
V8
55
IO
O
PORT70
Grid output8
P87
V23
40
IO
O
PORT87
Segment output23
P86
V22
41
IO
O
PORT86
Segment output22
P85
V21
42
IO
O
PORT85
Segment output21
P51
INT0
P50
DVO
Page 6
TMP86CH72FG
Table 1-1 Pin Names and Functions(3/3)
Pin Name
Pin Number
Input/Output
Functions
P84
V20
43
IO
O
PORT84
Segment output20
P83
V19
44
IO
O
PORT83
Segment output19
P82
V18
45
IO
O
PORT82
Segment output18
P81
V17
46
IO
O
PORT81
Segment output17
P80
V16
47
IO
O
PORT80
Segment output16
P97
V31
32
IO
O
PORT97
Segment output31
P96
V30
33
IO
O
PORT96
Segment output30
P95
V29
34
IO
O
PORT95
Segment output29
P94
V28
35
IO
O
PORT94
Segment output28
P93
V27
36
IO
O
PORT93
Segment output27
P92
V26
37
IO
O
PORT92
Segment output26
P91
V25
38
IO
O
PORT91
Segment output25
P90
V24
39
IO
O
PORT90
Segment output24
XIN
2
I
Resonator connecting pins for high-frequency clock
XOUT
3
O
Resonator connecting pins for high-frequency clock
RESET
8
I
Reset signal
TEST
4
I
Test pin for out-going test. Normally, be fixed to low.
VAREF
30
I
Analog reference voltage input (High)
AVSS
23
I
AD circuit power supply
VDD
5
I
Power Supply
VSS
1
I
0V(GND)
Page 7
1.4 Pin Names and Functions
TMP86CH72FG
Page 8
TMP86CH72FG
2. Operational Description
2.1 CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.
2.1.1
Memory Address Map
The TMP86CH72FG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special
function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the
memory address map.
0000H
SFR:
SFR
64 bytes
003FH
0040H
1024
bytes
RAM
RAM:
TMP86CH72FG
Special function register includes:
I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:
Data memory
Stack
043FH
0F80H
DBR:
128
bytes
DBR
Data buffer register includes:
Peripheral control registers
Peripheral status registers
0FFFH
C000H
MaskROM:
Program memory
16384
bytes
MaskROM
FFC0H
Vector table for vector call instructions
(32 bytes)
FFDFH
FFE0H
Vector table for interrupts
FFFFH
(32 bytes)
Figure 2-1 Memory Address Map
2.1.2
Program Memory (MaskROM)
The TMP86CH72FG has a 16384 bytes (Address C000H to FFFFH) of program memory (MaskROM ).
2.1.3
Data Memory (RAM)
The TMP86CH72FG has 1024bytes (Address 0040H to 043FH) of internal RAM. The first 192 bytes
(0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are
available against such an area.
Page 9
2. Operational Description
2.2 System Clock Controller
TMP86CH72FG
The data memory contents become unstable when the power supply is turned on; therefore, the data memory
should be initialized by an initialization routine.
Example :Clears RAM to “00H”. (TMP86CH72FG)
SRAMCLR:
LD
HL, 0040H
; Start address setup
LD
A, H
; Initial value (00H) setup
LD
BC, 03FFH
LD
(HL), A
INC
HL
DEC
BC
JRS
F, SRAMCLR
2.2 System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a standby controller.
Timing generator control register
TBTCR
0036H
Clock
generator
XIN
fc
High-frequency
clock oscillator
Timing
generator
XOUT
Standby controller
0038H
XTIN
Low-frequency
clock oscillator
SYSCR1
fs
System clocks
0039H
SYSCR2
System control registers
XTOUT
Clock generator control
Figure 2-2 System Colck Control
2.2.1
Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied to the CPU core
and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the
low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power
operation based on the low-frequency clock.
The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator
between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also
possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.
Page 10
TMP86CH72FG
Low-frequency clock
High-frequency clock
XIN
XOUT
XIN
XOUT
XTIN
XTOUT
(Open)
(a) Crystal/Ceramic
resonator
XTIN
XTOUT
(Open)
(c) Crystal
(b) External oscillator
(d) External oscillator
Figure 2-3 Examples of Resonator Connection
Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse
which the fixed frequency is outputted to the port by the program.
The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance.
Page 11
2. Operational Description
2.2 System Clock Controller
2.2.2
TMP86CH72FG
Timing Generator
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.
1. Generation of main system clock
2. Generation of divider output (DVO) pulses
3. Generation of source clocks for time base timer
4. Generation of source clocks for watchdog timer
5. Generation of internal source clocks for timer/counters
6. Generation of warm-up clocks for releasing STOP mode
2.2.2.1
Configuration of timing generator
The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,
and machine cycle counters.
An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.
fc or fs
Main system clock generator
Machine cycle counters
SYSCK
DV7CK
High-frequency
clock fc
Low-frequency
clock fs
1 2
fc/4
S
A
Divider
Y
1 2 3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
B
Multiplexer
S
B0
B1
A0 Y0
A1 Y1
Multiplexer
Warm-up
controller
Watchdog
timer
Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)
Figure 2-4 Configuration of Timing Generator
Page 12
TMP86CH72FG
Timing Generator Control Register
TBTCR
(0036H)
7
6
(DVOEN)
5
(DVOCK)
DV7CK
4
3
DV7CK
(TBTEN)
Selection of input to the 7th stage
of the divider
2
1
0
(TBTCK)
(Initial value: 0000 0000)
0: fc/28 [Hz]
1: fs
R/W
Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after
release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
2.2.2.2
Machine cycle
Instruction execution and peripheral hardware operation are synchronized with the main system clock.
The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
1/fc or 1/fs [s]
Main system clock
State
S0
S1
S2
S3
S0
S1
S2
S3
Machine cycle
Figure 2-5 Machine Cycle
2.2.3
Operation Mode Control Circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). Figure 2-6 shows the operating mode transition diagram.
2.2.3.1
Single-clock mode
Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT)
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].
(1)
NORMAL1 mode
In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.
The TMP86CH72FG is placed in this mode after reset.
Page 13
2. Operational Description
2.2 System Clock Controller
TMP86CH72FG
(2)
IDLE1 mode
In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are
halted; however on-chip peripherals remain active (Operate using the high-frequency clock).
IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1
mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF
(Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance
of the interrupt, and the operation will return to normal after the interrupt service is completed. When
the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the
IDLE1 mode start instruction.
(3)
IDLE0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.
This mode is enabled by SYSCR2<TGHALT> = "1".
When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back
again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =
“1”, EF7 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.
2.2.3.2
Dual-clock mode
Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and
P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the
high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in
SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and
4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.
The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program.
(1)
NORMAL2 mode
In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate
using the high-frequency clock and/or low-frequency clock.
(2)
SLOW2 mode
In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency
clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hardware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes
into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1
mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.
(3)
SLOW1 mode
This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.
Page 14
TMP86CH72FG
Switching back and forth between SLOW1 and SLOW2 modes are performed by
SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is
stopped; output from the 1st to 6th stages is also stopped.
(4)
IDLE2 mode
In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are
halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or
the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode,
except that operation returns to NORMAL2 mode.
(5)
SLEEP1 mode
In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU,
the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode.
In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from
the 1st to 6th stages is also stopped.
(6)
SLEEP2 mode
The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the
SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the highfrequency clock.
(7)
SLEEP0 mode
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode
is enabled by setting “1” on bit SYSCR2<TGHALT>.
When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back
again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF
= “1”, EF7 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to SLOW1 mode.
2.2.3.3
STOP mode
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The
internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a
inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After
the warm-up period is completed, the execution resumes with the instruction which follows the STOP
mode start instruction.
Page 15
2. Operational Description
2.2 System Clock Controller
TMP86CH72FG
IDLE0
mode
RESET
Reset release
Note 2
SYSCR2<TGHALT> = "1"
SYSCR1<STOP> = "1"
SYSCR2<IDLE> = "1"
NORMAL1
mode
Interrupt
STOP pin input
IDLE1
mode
(a) Single-clock mode
SYSCR2<XTEN> = "0"
SYSCR2<XTEN> = "1"
SYSCR2<IDLE> = "1"
IDLE2
mode
NORMAL2
mode
Interrupt
SYSCR1<STOP> = "1"
STOP pin input
SYSCR2<SYSCK> = "0"
SYSCR2<SYSCK> = "1"
STOP
SYSCR2<IDLE> = "1"
SLEEP2
mode
SLOW2
mode
Interrupt
SYSCR2<XEN> = "0"
SYSCR2<XEN> = "1"
SYSCR2<IDLE> = "1"
SLEEP1
mode
Interrupt
(b) Dual-clock mode
SYSCR1<STOP> = "1"
SLOW1
mode
STOP pin input
SYSCR2<TGHALT> = "1"
Note 2
SLEEP0
mode
Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1
and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.
Figure 2-6 Operating Mode Transition Diagram
Table 2-1 Operating Mode and Conditions
Oscillator
Operating Mode
High
Frequency
Low
Frequency
RESET
NORMAL1
CPU Core
TBT
Other
Peripherals
Reset
Reset
Reset
Operate
Oscillation
Single clock
Machine Cycle
Time
IDLE1
Operate
Stop
IDLE0
4/fc [s]
Operate
Halt
Halt
STOP
Stop
Halt
–
Operate with
high frequency
NORMAL2
IDLE2
4/fc [s]
Halt
Oscillation
Operate with
low frequency
SLOW2
Dual clock
Oscillation
SLEEP2
Operate
Operate
Operate with
low frequency
SLOW1
SLEEP1
Halt
4/fs [s]
Stop
SLEEP0
Halt
Halt
STOP
Stop
Halt
Page 16
–
TMP86CH72FG
System Control Register 1
SYSCR1
7
6
5
4
(0038H)
STOP
RELM
RETM
OUTEN
3
2
1
0
WUT
(Initial value: 0000 00**)
STOP
STOP mode start
0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)
R/W
RELM
Release method for STOP
mode
0: Edge-sensitive release
1: Level-sensitive release
R/W
RETM
Operating mode after STOP
mode
0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode
R/W
Port output during STOP mode
0: High impedance
1: Output kept
R/W
OUTEN
WUT
Warm-up time at releasing
STOP mode
Return to NORMAL mode
Return to SLOW mode
00
3 x 216/fc
3 x 213/fs
01
216/fc
213/fs
10
3 x 214/fc
3 x 26/fs
11
214/fc
26/fs
R/W
Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting
from SLOW mode to STOP mode.
Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external
interrupt request on account of falling edge.
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes
High-Z mode.
Note 8: The warmig-up time should be set correctly for using oscillator.
System Control Register 2
SYSCR2
(0039H)
7
6
5
4
XEN
XTEN
SYSCK
IDLE
3
2
1
TGHALT
0
(Initial value: 1000 *0**)
XEN
High-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
XTEN
Low-frequency oscillator control
0: Turn off oscillation
1: Turn on oscillation
SYSCK
Main system clock select
(Write)/main system clock monitor (Read)
0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)
IDLE
CPU and watchdog timer control
(IDLE1/2 and SLEEP1/2 modes)
0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes)
TGHALT
TG control (IDLE0 and SLEEP0
modes)
0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
(Start IDLE0 and SLEEP0 modes)
R/W
R/W
Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared
to “0” when SYSCK = “1”.
Note 2: *: Don’t care, TG: Timing generator, *; Don’t care
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period
of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.
Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals
may be set after IDLE0 or SLEEP0 mode is released.
Page 17
2. Operational Description
2.2 System Clock Controller
2.2.4
TMP86CH72FG
Operating Mode Control
2.2.4.1
STOP mode
STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input
(STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR).
The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
status in effect before STOP mode was entered.
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
which started STOP mode.
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releasing STOP mode in edge-sensitive mode.
Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2).
However, because the STOP pin is different from the key-on wakeup and can not inhibit the release
input, the STOP pin must be used for releasing STOP mode.
Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external
interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.
(1)
Level-sensitive release mode (RELM = “1”)
In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2
pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main
power supply is cut off and long term battery backup.
Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5
to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to
first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two
methods can be used for confirmation.
1. Testing a port.
2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).
Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
SSTOPH:
LD
(SYSCR1), 01010000B
; Sets up the level-sensitive release mode
TEST
(P2PRD). 0
; Wait until the STOP pin input goes low level
JRS
F, SSTOPH
; IMF ← 0
DI
SET
(SYSCR1). 7
; Starts STOP mode
Page 18
TMP86CH72FG
Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.
PINT5:
TEST
(P2PRD). 0
; To reject noise, STOP mode does not start if
JRS
F, SINT5
LD
(SYSCR1), 01010000B
port P20 is at high
; Sets up the level-sensitive release mode.
; IMF ← 0
DI
SET
SINT5:
(SYSCR1). 7
; Starts STOP mode
RETI
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Warm up
Confirm by program that the
STOP pin input is low and start
STOP mode.
NORMAL
operation
STOP mode is released by the hardware.
Always released if the STOP
pin input is high.
Figure 2-7 Level-sensitive Release Mode
Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted.
Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release
mode is not switched until a rising edge of the STOP pin input is detected.
(2)
Edge-sensitive release mode (RELM = “0”)
In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic
signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In
the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level.
Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode.
Example :Starting STOP mode from NORMAL mode
; IMF ← 0
DI
LD
(SYSCR1), 10010000B
; Starts after specified to the edge-sensitive release mode
VIH
STOP pin
XOUT pin
NORMAL
operation
STOP
operation
Warm up
NORMAL
operation
STOP mode started
by the program.
STOP
operation
STOP mode is released by the hardware at the rising
edge of STOP pin input.
Figure 2-8 Edge-sensitive Release Mode
Page 19
2. Operational Description
2.2 System Clock Controller
TMP86CH72FG
STOP mode is released by the following sequence.
1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency
clock oscillator is turned on.
2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all
internal operations remain halted. Four different warm-up times can be selected with the
SYSCR1<WUT> in accordance with the resonator characteristics.
3. When the warm-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction.
Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the
timing generator are cleared to "0".
Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately
performs the normal reset operation.
Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed.
The power supply voltage must be at the operating voltage level before releasing STOP mode.
The RESET pin input must also be “H” level, rising together with the power supply voltage. In this
case, if an external time constant circuit has been connected, the RESET pin input voltage will
increase at a slower pace than the power supply voltage. At this time, there is a danger that a
reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level
input voltage (Hysteresis input).
Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz)
Warm-up Time [ms]
WUT
00
01
10
11
Return to NORMAL Mode
Return to SLOW Mode
12.288
4.096
3.072
1.024
750
250
5.85
1.95
Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up
time may include a certain amount of error if there is any fluctuation of the oscillation frequency
when STOP mode is released. Thus, the warm-up time must be considered as an approximate
value.
Page 20
Page 21
Figure 2-9 STOP Mode Start/Release
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
STOP pin
input
Divider
Instruction
execution
Program
counter
Main
system
clock
Oscillator
circuit
0
Halt
Turn off
Turn on
Turn on
n
Count up
a+3
Warm up
a+2
n+2
n+3
n+4
0
(b) STOP mode release
1
Instruction address a + 2
a+4
2
Instruction address a + 3
a+5
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
n+1
SET (SYSCR1). 7
a+3
3
Instruction address a + 4
a+6
0
Halt
Turn off
TMP86CH72FG
2. Operational Description
2.2 System Clock Controller
2.2.4.2
TMP86CH72FG
IDLE1/2 mode and SLEEP1/2 mode
IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable
interrupts. The following status is maintained during these modes.
1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to
operate.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before these modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts these modes.
Starting IDLE1/2 and
SLEEP1/2 modes by
instruction
CPU and WDT are halted
Yes
Reset input
Reset
No
No
Interrupt request
Yes
“0”
IMF
“1” (Interrupt release mode)
Normal
release mode
Interrupt processing
Execution of the instruction which follows the
IDLE1/2 and SLEEP1/2
modes start instruction
Figure 2-10 IDLE1/2 and SLEEP1/2 Modes
Page 22
TMP86CH72FG
• Start the IDLE1/2 and SLEEP1/2 modes
After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2
and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”.
• Release the IDLE1/2 and SLEEP1/2 modes
IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and
SLEEP1/2 modes, the SYSCR2<IDLE> is automatically cleared to “0” and the operation mode
is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes.
IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
(1)
Normal release mode (IMF = “0”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual
interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the
instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt
latches (IL) of the interrupt source used for releasing must be cleared to “0” by load instructions.
(2)
Interrupt release mode (IMF = “1”)
IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual
interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the
program operation is resumed from the instruction following the instruction, which starts IDLE1/2
and SLEEP1/2 modes.
Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2
modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2
modes will not be started.
Page 23
Page 24
Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
Halt
Halt
Halt
Halt
Operate
Operate
Operate
Acceptance of interrupt
Instruction address a + 2
a+4
(b) IDLE1/2 and SLEEP1/2 modes release
㽳㩷Interrupt release mode
a+3
㽲㩷Normal release mode
a+3
(a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a)
Operate
SET (SYSCR2). 4
a+2
Halt
a+3
2.2 System Clock Controller
2. Operational Description
TMP86CH72FG
TMP86CH72FG
2.2.4.3
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base
timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes.
1. Timing generator stops feeding clock to peripherals except TBT.
2. The data memory, CPU registers, program status word and port output latches are all held in the
status in effect before IDLE0 and SLEEP0 modes were entered.
3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and
SLEEP0 modes.
Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals.
Stopping peripherals
by instruction
Starting IDLE0, SLEEP0
modes by instruction
CPU and WDT are halted
Reset input
Yes
Reset
No
No
TBT
source clock
falling
edge
Yes
No
TBTCR<TBTEN>
= "1"
Yes
No
TBT interrupt
enable
Yes
(Normal release mode)
No
IMF = "1"
Yes (Interrupt release mode)
Interrupt processing
Execution of the instruction
which follows the IDLE0,
SLEEP0 modes start
instruction
Figure 2-12 IDLE0 and SLEEP0 Modes
Page 25
2. Operational Description
2.2 System Clock Controller
TMP86CH72FG
• Start the IDLE0 and SLEEP0 modes
Stop (Disable) peripherals such as a timer counter.
To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”.
• Release the IDLE0 and SLEEP0 modes
IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
These modes are selected by interrupt master flag (IMF), the individual interrupt enable flag
of TBT and TBTCR<TBTEN>.
After releasing IDLE0 and SLEEP0 modes, the SYSCR2<TGHALT> is automatically
cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0
modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”,
INTTBT interrupt latch is set to “1”.
IDLE0 and SLEEP0 modes can also be released by inputting low level on the RESET pin.
After releasing reset, the operation mode is started from NORMAL1 mode.
Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR<TBTEN> setting.
(1)
Normal release mode (IMF•EF7•TBTCR<TBTEN> = “0”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK>. After the falling edge is detected, the program operation is resumed from the
instruction following the IDLE0 and SLEEP0 modes start instruction. Before starting the IDLE0 or
SLEEP0 mode, when the TBTCR<TBTEN> is set to “1”, INTTBT interrupt latch is set to “1”.
(2)
Interrupt release mode (IMF•EF7•TBTCR<TBTEN> = “1”)
IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the
TBTCR<TBTCK> and INTTBT interrupt processing is started.
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR<TBTCK>.
Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is
started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be
started.
Page 26
Page 27
Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release
Watchdog
timer
Instruction
execution
Program
counter
TBT clock
Halt
Halt
Halt
Watchdog
timer
Main
system
clock
Halt
Instruction
execution
Program
counter
TBT clock
Main
system
clock
Watchdog
timer
Instruction
execution
Program
counter
Interrupt
request
Main
system
clock
a+3
Halt
Operate
Operate
(b) IDLE and SLEEP0 modes release
㽳㩷Interrupt release mode
a+3
㽲㩷Normal release mode
a+3
Acceptance of interrupt
Instruction address a + 2
a+4
(a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a
Operate
SET (SYSCR2). 2
a+2
TMP86CH72FG
2. Operational Description
2.2 System Clock Controller
2.2.4.4
TMP86CH72FG
SLOW mode
SLOW mode is controlled by the system control register 2 (SYSCR2).
The following is the methods to switch the mode with the warm-up counter.
(1)
Switching from NORMAL2 mode to SLOW1 mode
First, set SYSCR2<SYSCK> to switch the main system clock to the low-frequency clock for
SLOW2 mode. Next, clear SYSCR2<XEN> to turn off high-frequency oscillation.
Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from
SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from
SLOW mode to stop mode.
Example 1 :Switching from NORMAL2 mode to SLOW1 mode.
SET
(SYSCR2). 5
; SYSCR2<SYSCK> ← 1
(Switches the main system clock to the low-frequency
clock for SLOW2)
CLR
(SYSCR2). 7
; SYSCR2<XEN> ← 0
(Turns off high-frequency oscillation)
Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized.
SET
(SYSCR2). 6
; SYSCR2<XTEN> ← 1
LD
(TC2CR), 14H
; Sets mode for TC2 (fs for source)
LDW
(TC2DRL), 8000H
; Sets warm-up time (Depend on oscillator accompanied)
; IMF ← 0
DI
SET
(EIRH). 6
; IMF ← 1
EI
SET
; Enables INTTC2
(TC2CR). 5
; Starts TC2
CLR
(TC2CR). 5
; Stops TC2
SET
(SYSCR2). 5
; SYSCR2<SYSCK> ← 1
:
PINTTC2:
(Switches the main system clock to the low-frequency clock)
CLR
(SYSCR2). 7
; SYSCR2<XEN> ← 0
(Turns off high-frequency oscillation)
RETI
:
VINTTC2:
DW
PINTTC2
; INTTC2 vector table
Page 28
TMP86CH72FG
(2)
Switching from SLOW1 mode to NORMAL2 mode
First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization
(Warm up) has been taken by the timer/counter (TC2), clear SYSCR2<SYSCK> to switch the main
system clock to the high-frequency clock.
SLOW mode can also be released by inputting low level on the RESET pin. After releasing reset, the
operation mode is started from NORMAL1 mode.
Note: After SYSCK is cleared to “0”, executing the instructions is continiued by the low-frequency clock
for the period synchronized with low-frequency and high-frequency clocks.
High-frequency clock
Low-frequency clock
Main system clock
SYSCK
Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms).
SET
(SYSCR2). 7
; SYSCR2<XEN> ← 1 (Starts high-frequency oscillation)
LD
(TC2CR), 10H
; Sets mode for TC2 (fc for source)
LD
(TC2DRH), 0F8H
; Sets warm-up time
; IMF ← 0
DI
SET
(EIRH). 6
; IMF ← 1
EI
SET
; Enables INTTC2
(TC2CR). 5
; Starts TC2
CLR
(TC2CR). 5
; Stops TC2
CLR
(SYSCR2). 5
; SYSCR2<SYSCK> ← 0
:
PINTTC2:
(Switches the main system clock to the high-frequency clock)
RETI
:
VINTTC2:
DW
PINTTC2
; INTTC2 vector table
Page 29
Page 30
Figure 2-14 Switching between the NORMAL2 and SLOW Modes
SET (SYSCR2). 7
SET (SYSCR2). 5
SLOW1 mode
Instruction
execution
XEN
SYSCK
Highfrequency
clock
Lowfrequency
clock
Main
system
clock
NORMAL2
mode
Instruction
execution
XEN
SYSCK
Highfrequency
clock
Lowfrequency
clock
Main
system
clock
(b) Switching to the NORMAL2 mode
Warm up during SLOW2 mode
CLR (SYSCR2). 5
(a) Switching to the SLOW mode
SLOW2 mode
CLR (SYSCR2). 7
NORMAL2
mode
SLOW1 mode
Turn off
2.2 System Clock Controller
2. Operational Description
TMP86CH72FG
TMP86CH72FG
2.3 Reset Circuit
The TMP86CH72FG has four types of reset generation procedures: An external reset input, an address trap reset, a
watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s].
The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5µs at 16.0 MHz) when
power is turned on.
Table 2-3 shows on-chip hardware initialization by reset action.
Table 2-3 Initializing Internal Status by Reset Action
On-chip Hardware
Initial Value
Program counter
(PC)
(FFFEH)
Stack pointer
(SP)
Not initialized
General-purpose registers
(W, A, B, C, D, E, H, L, IX, IY)
(JF)
Not initialized
Zero flag
(ZF)
Not initialized
Carry flag
(CF)
Not initialized
Half carry flag
(HF)
Not initialized
Sign flag
(SF)
Not initialized
Overflow flag
(VF)
Not initialized
(IMF)
0
(EF)
0
(IL)
0
Interrupt individual enable flags
Interrupt latches
2.3.1
Initial Value
Prescaler and divider of timing generator
0
Not initialized
Jump status flag
Interrupt master enable flag
On-chip Hardware
Watchdog timer
Enable
Output latches of I/O ports
Refer to I/O port circuitry
Control registers
Refer to each of control
register
RAM
Not initialized
External Reset Input
The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor.
When the RESET pin is held at “L” level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized.
When the RESET pin input goes high, the reset operation is released and the program execution starts at the
vector address stored at addresses FFFEH to FFFFH.
VDD
RESET
Internal reset
Watchdog timer reset
Malfunction
reset output
circuit
Address trap reset
System clock reset
Figure 2-15 Reset Circuit
Page 31
2. Operational Description
2.3 Reset Circuit
TMP86CH72FG
2.3.2
Address trap reset
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be
generated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz).
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative.
Instruction
execution
Reset release
JP a
Instruction at address r
Address trap is occurred
Internal reset
maximum 24/fc [s]
4/fc to 12/fc [s]
16/fc [s]
Note 1: Address “a” is in the SFR, DBR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Figure 2-16 Address Trap Reset
2.3.3
Watchdog timer reset
Refer to Section “Watchdog Timer”.
2.3.4
System clock reset
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
CPU. (The oscillation is continued without stopping.)
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
The reset time is maximum 24/fc (1.5 µs at 16.0 MHz).
Page 32
TMP86CH72FG
Page 33
2. Operational Description
2.3 Reset Circuit
TMP86CH72FG
Page 34
TMP86CH72FG
3. Interrupt Control Circuit
The TMP86CH72FG has a total of 19 interrupt sources excluding reset, of which 3 source levels are multiplexed.
Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are
maskable.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
Interrupt Factors
Internal/External
Enable Condition
Interrupt
Latch
Vector
Address
Priority
(Reset)
Non-maskable
–
FFFE
1
Internal
INTSWI (Software interrupt)
Non-maskable
–
FFFC
2
Internal
INTUNDEF (Executed the undefined instruction
interrupt)
Non-maskable
–
FFFC
2
Internal
INTATRAP (Address trap interrupt)
Non-maskable
IL2
FFFA
2
Internal
INTWDT (Watchdog timer interrupt)
Non-maskable
IL3
FFF8
2
External
INT0
IMF• EF4 = 1, INT0EN = 1
IL4
FFF6
5
Internal
INTRXD
IMF• EF5 = 1
IL5
FFF4
6
External
INT1
IMF• EF6 = 1
IL6
FFF2
7
Internal
INTTBT
IMF• EF7 = 1
IL7
FFF0
8
Internal
INTTC3
IMF• EF8 = 1
IL8
FFEE
9
Internal
INTSIO
IMF• EF9 = 1, IL9ER = 0
IL9
FFEC
10
Internal
INTI2C
IMF• EF9 = 1, IL9ER = 1
Internal
INTTC4
IMF• EF10 = 1
IL10
FFEA
11
External
INT3
IMF• EF11 = 1
IL11
FFE8
12
External
INT4
IMF• EF12 = 1
IL12
FFE6
13
Internal
INTTXD
IMF• EF13 = 1
IL13
FFE4
14
Internal
INTTC2
IMF• EF14 = 1, IL14ER = 0
IL14
FFE2
15
External
INT5
IMF• EF14 = 1, IL14ER = 1
Internal
INTADC
IMF• EF15 = 1, IL15ER = 0
IL15
FFE0
16
External
INT2
IMF• EF15 = 1, IL15ER = 1
Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL)).
Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is
cancelled). For details, see “Address Trap”.
Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
reset is released). For details, see "Watchdog Timer".
3.1 Interrupt latches (IL15 to IL2)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to “0” during reset.
The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt
latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions
such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed.
Page 35
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86CH72FG
Interrupt latches are not set to “1” by an instruction.
Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to
"0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL
(Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on
interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL
should be executed before setting IMF="1".
Example 1 :Clears interrupt latches
; IMF ← 0
DI
LDW
(ILL), 1110100000111111B
; IL12, IL10 to IL6 ← 0
; IMF ← 1
EI
Example 2 :Reads interrupt latchess
WA, (ILL)
; W ← ILH, A ← ILL
TEST
(ILL). 7
; if IL7 = 1 then jump
JR
F, SSET
LD
Example 3 :Tests interrupt latches
3.2 Interrupt enable register (EIR)
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR.
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions
(Including read-modify-write instructions such as bit manipulation or operation instructions).
3.2.1
Interrupt master enable flag (IMF)
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt.
While IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt
enable flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When
an interrupt is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data,
which was the status before interrupt acceptance, is loaded on IMF again.
The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction.
The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to “0”.
3.2.2
Individual interrupt enable flags (EF15 to EF4)
Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding
bit of an individual interrupt enable flag to “1” enables acceptance of its interrupt, and setting the bit to “0” disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to “0” and
all maskable interrupts are not accepted until they are set to “1”.
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor-
Page 36
TMP86CH72FG
mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Example 1 :Enables interrupts individually and sets IMF
; IMF ← 0
DI
LDW
:
(EIRL), 1110100010100000B
; EF15 to EF13, EF11, EF7, EF5 ← 1
Note: IMF should not be set.
:
; IMF ← 1
EI
Example 2 :C compiler description example
unsigned int _io (3AH) EIRL;
/* 3AH shows EIRL address */
_DI();
EIRL = 10100000B;
:
_EI();
Page 37
3. Interrupt Control Circuit
3.2 Interrupt enable register (EIR)
TMP86CH72FG
Interrupt Latches
(Initial value: 00000000 000000**)
ILH,ILL
(003DH, 003CH)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
IL15
IL14
IL13
IL12
IL11
IL10
IL9
IL8
IL7
IL6
IL5
IL4
IL3
IL2
ILH (003DH)
IL15 to IL2
1
0
ILL (003CH)
at RD
0: No interrupt request
Interrupt latches
at WR
0: Clears the interrupt request
1: (Interrupt latch is not set.)
1: Interrupt request
R/W
Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3.
Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Note 3: Do not clear IL with read-modify-write instructions such as bit operations.
Interrupt Enable Registers
(Initial value: 00000000 0000***0)
EIRH,EIRL
(003BH, 003AH)
15
14
13
12
11
10
9
8
7
6
5
4
EF15
EF14
EF13
EF12
EF11
EF10
EF9
EF8
EF7
EF6
EF5
EF4
EIRH (003BH)
EF15 to EF4
3
2
1
0
IMF
EIRL (003AH)
Individual-interrupt enable flag
(Specified for each bit)
0:
1:
Disables the acceptance of each maskable interrupt.
Enables the acceptance of each maskable interrupt.
Interrupt master enable flag
0:
1:
Disables the acceptance of all maskable interrupts
Enables the acceptance of all maskable interrupts
R/W
IMF
Note 1: *: Don’t care
Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to “1” at the same time.
Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0"
(Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt
by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1".
Page 38
TMP86CH72FG
3.3 Interrupt Source Selector (INTSEL)
Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the
interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt
requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated.
The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL.
1. INTSIO and INTI2C share the interrupt source level whose priority is 10.
2. INTTC2 and INT5 share the interrupt source level whose priority is 15.
3. INTADC and INT2 share the interrupt source level whose priority is 16.
Interrupt source selector
INTSEL
(003EH)
7
6
5
4
3
2
1
0
-
IL9ER
-
-
-
-
IL14ER
IL15ER
IL9ER
Selects INTSIO or INTI2C
0: INTSIO
1: INTI2C
R/W
IL14ER
Selects INTTC2 or INT5
0: INTTC2
1: INT5
R/W
IL15ER
Selects INTADC or INT2
0: INTADC
1: INT2
R/W
(Initial value: *0** **00)
3.4 Interrupt Sequence
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to
“0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 µs @16 MHz) after the
completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return
instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing
chart of interrupt acceptance processing.
3.4.1
Interrupt acceptance processing is packaged as follows.
a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any following interrupt.
b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
c. The contents of the program counter (PC) and the program status word, including the interrupt master
enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3.
d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter.
e. The instruction stored at the entry address of the interrupt service program is executed.
Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.
Page 39
3. Interrupt Control Circuit
3.4 Interrupt Sequence
TMP86CH72FG
Interrupt service task
1-machine cycle
Interrupt
request
Interrupt
latch (IL)
IMF
Execute
instruction
Execute
instruction
a−1
PC
SP
a
Execute
instruction
Interrupt acceptance
a+1
b
a
b+1 b+2 b + 3
n−1 n−2
n
Execute RETI instruction
c+2
c+1
a
n−2 n−1
n-3
a+1 a+2
n
Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored
Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first
machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt
service program
Vector table address
FFF0H
03H
FFF1H
D2H
Entry address
Vector
D203H
0FH
D204H
06H
Interrupt
service
program
Figure 3-2 Vector table address,Entry address
A maskable interrupt is not accepted until the IMF is set to “1” even if the maskable interrupt higher than the
level of current servicing interrupt is requested.
In order to utilize nested interrupt service, the IMF is set to “1” in the interrupt service program. In this case,
acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.
To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced,
before setting IMF to “1”. As for non-maskable interrupt, keep interrupt service shorten compared with length
between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply
nested.
3.4.2
Saving/restoring general-purpose registers
During interrupt acceptance processing, the program counter (PC) and the program status word (PSW,
includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are
saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using
the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers.
Page 40
TMP86CH72FG
3.4.2.1
Using PUSH and POP instructions
If only a specific register is saved or interrupts of the same source are nested, general-purpose registers
can be saved/restored using the PUSH/POP instructions.
Example :Save/store register using PUSH and POP instructions
PINTxx:
PUSH
WA
; Save WA register
(interrupt processing)
POP
WA
; Restore WA register
RETI
; RETURN
Address
(Example)
SP
b-5
A
SP
b-4
SP
b-3
PCL
W
PCL
PCH
PCH
PCH
PSW
PSW
PSW
At acceptance of
an interrupt
PCL
At execution of
PUSH instruction
At execution of
POP instruction
b-2
b-1
SP
b
At execution of
RETI instruction
Figure 3-3 Save/store register using PUSH and POP instructions
3.4.2.2
Using data transfer instructions
To save only a specific register without nested interrupts, data transfer instructions are available.
Example :Save/store register using data transfer instructions
PINTxx:
LD
(GSAVA), A
; Save A register
(interrupt processing)
LD
A, (GSAVA)
; Restore A register
RETI
; RETURN
Page 41
3. Interrupt Control Circuit
3.4 Interrupt Sequence
TMP86CH72FG
Main task
Interrupt
service task
Interrupt
acceptance
Saving
registers
Restoring
registers
Interrupt return
Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction
Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing
3.4.3
Interrupt return
Interrupt return instructions [RETI]/[RETN] perform as follows.
[RETI]/[RETN] Interrupt Return
1. Program counter (PC) and program status word
(PSW, includes IMF) are restored from the stack.
2. Stack pointer (SP) is incremented by 3.
As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to
restarting address, during interrupt service program.
Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and
INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and
PCH are located on address (SP + 1) and (SP + 2) respectively.
Example 1 :Returning from address trap interrupt (INTATRAP) service program
PINTxx:
POP
WA
; Recover SP by 2
LD
WA, Return Address
;
PUSH
WA
; Alter stacked data
(interrupt processing)
RETN
; RETURN
Example 2 :Restarting without returning interrupt
(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)
PINTxx:
INC
SP
; Recover SP by 3
INC
SP
;
INC
SP
;
(interrupt processing)
LD
EIRL, data
; Set IMF to “1” or clear it to “0”
JP
Restart Address
; Jump into restarting address
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed.
Page 42
TMP86CH72FG
Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example
2).
Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service
task is performed but not the main task.
3.5 Software Interrupt (INTSW)
Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW
is highest prioritized interrupt).
Use the SWI instruction only for detection of the address error or for debugging.
3.5.1
Address error detection
FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent
memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing
FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is
fetched from RAM, DBR or SFR areas.
3.5.2
Debugging
Debugging efficiency can be increased by placing the SWI instruction at the software break point setting
address.
3.6 Undefined Instruction Interrupt (INTUNDEF)
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is
requested.
Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt
(SWI) does.
3.7 Address Trap Interrupt (INTATRAP)
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address
trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested.
Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on
watchdog timer control register (WDTCR).
3.8 External Interrupts
The TMP86CH72FG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits
(Pulse inputs of less than a certain time are eliminated as noise).
Edge selection is also possible with INT1 to INT4. The INT0/p51 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset.
Edge selection, noise reject control and INT0/p51 pin function selection are performed by the external interrupt
control register (EINTCR).
Page 43
3. Interrupt Control Circuit
3.8 External Interrupts
Source
INT0
INT1
INT2
INT3
INT4
INT5
TMP86CH72FG
Pin
INT0
INT1
INT2
INT3
INT4
INT5
Enable Conditions
IMF ΠEF4 ΠINT0EN=1
IMF ΠEF6 = 1
IMF ΠEF15 = 1
and
IL15ER=1
IMF ΠEF11 = 1
IMF ΠEF12 = 1
IMF ΠEF14 = 1
and
IL14ER=1
Release Edge (level)
Digital Noise Reject
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Falling edge
or
Rising edge
Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or
more are considered to be signals. In the SLOW
or the SLEEP mode, pulses of less than 1/fs [s]
are eliminated as noise. Pulses of 3.5/fs [s] or
more are considered to be signals.
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Falling edge
or
Rising edge
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Falling edge,
Rising edge,
Falling and Rising edge
or
H level
Pulses of less than 7/fc [s] are eliminated as
noise. Pulses of 25/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Falling edge
Pulses of less than 2/fc [s] are eliminated as
noise. Pulses of 7/fc [s] or more are considered
to be signals. In the SLOW or the SLEEP mode,
pulses of less than 1/fs [s] are eliminated as
noise. Pulses of 3.5/fs [s] or more are considered to be signals.
Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch.
Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input.
Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such
as disabling the interrupt enable flag.
Page 44
TMP86CH72FG
External Interrupt Control Register
EINTCR
7
6
(0037H)
INT1NC
INT0EN
5
4
INT4ES
3
2
1
INT3ES
INT2ES
INT1ES
0
(Initial value: 0000 000*)
INT1NC
Noise reject time select
0: Pulses of less than 63/fc [s] are eliminated as noise
1: Pulses of less than 15/fc [s] are eliminated as noise
R/W
INT0EN
p51/INT0 pin configuration
0: p51 input/output port
1: INT0 pin (Port p51 should be set to an input mode)
R/W
INT4 ES
INT4 edge select
00: Rising edge
01: Falling edge
10: Rising edge and Falling edge
11: H level
R/W
INT3 ES
INT3 edge select
0: Rising edge
1: Falling edge
R/W
INT2 ES
INT2 edge select
0: Rising edge
1: Falling edge
R/W
INT1 ES
INT1 edge select
0: Rising edge
1: Falling edge
R/W
Note 1: fc: High-frequency clock [Hz], *: Don’t care
Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register
(EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR).
Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc.
Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated
even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released.
Page 45
3. Interrupt Control Circuit
3.8 External Interrupts
TMP86CH72FG
Page 46
TMP86CH72FG
5. Special Function Register (SFR)
The TMP86CH72FG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address
0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for
TMP86CH72FG.
5.1 SFR
Address
Read
Write
0000H
Reserved
0001H
P1DR
0002H
P2DR
0003H
Reserved
0004H
P4DR
0005H
P5DR
0006H
P6DR
0007H
P7DR
0008H
P8DR
0009H
P9DR
000AH
Reserved
000BH
P1OUTCR
000CH
P4CR1
000DH
P5CR
000EH
ADCCR1
000FH
ADCCR2
0010H
TC3DRA
0011H
TC3DRB
-
0012H
TC3CR
0013H
TC2CR
0014H
TC4CR
0015H
P1PRD
-
0016H
P2PRD
-
0017H
Reserved
0018H
TC4DR
0019H
SIOCR1
001AH
SIOCR2
001BH
SIOSR
001CH
SIOBUF
001DH
UARTSR
UARTCR1
001EH
-
UARTCR2
001FH
RDBUF
TDBUF
0020H
-
SBICRA
0021H
SBIDBR
0022H
-
0023H
SBISRB
I2CAR
SBICRB
0024H
TC2DRL
0025H
TC2DRH
Page 57
5. Special Function Register (SFR)
5.1 SFR
TMP86CH72FG
Address
Read
Write
0026H
ADCDR2
-
0027H
ADCDR1
-
0028H
P4CR2
0029H
TC3SEL
002AH
VFTCR1
002BH
VFTCR2
002CH
002DH
VFTCR3
VFTSR
-
002EH
Reserved
002FH
ROMCCR
0030H
0031H
Reserved
-
STOPCR
0032H
Reserved
0033H
Reserved
0034H
-
WDTCR1
0035H
-
WDTCR2
0036H
TBTCR
0037H
EINTCR
0038H
SYSCR1
0039H
SYSCR2
003AH
EIRL
003BH
EIRH
003CH
ILL
003DH
ILH
003EH
INTSEL
003FH
PSW
Note 1: Do not access reserved areas by the program.
Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 58
TMP86CH72FG
5.2 DBR
Address
Read
Write
0F80H
VFTDBR(T0,V7 to V0)
0F81H
VFTDBR(T1,V7 to V0)
0F82H
VFTDBR(T2,V7 to V0)
0F83H
VFTDBR(T3,V7 to V0)
0F84H
VFTDBR(T4,V7 to V0)
0F85H
VFTDBR(T5,V7 to V0)
0F86H
VFTDBR(T6,V7 to V0)
0F87H
VFTDBR(T7,V7 to V0)
0F88H
VFTDBR(T8,V7 to V0)
0F89H
VFTDBR(T9,V7 to V0)
0F8AH
VFTDBR(T10,V7 to V0)
0F8BH
VFTDBR(T11,V7 to V0)
0F8CH
VFTDBR(T12,V7 to V0)
0F8DH
VFTDBR(T13,V7 to V0)
0F8EH
VFTDBR(T14,V7 to V0)
0F8FH
VFTDBR(T15,V7 to V0)
0F90H
VFTDBR(T0,V15 to V8)
0F91H
VFTDBR(T1,V15 to V8)
0F92H
VFTDBR(T2,V15 to V8)
0F93H
VFTDBR(T3,V15 to V8)
0F94H
VFTDBR(T4,V15 to V8)
0F95H
VFTDBR(T5,V15 to V8)
0F96H
VFTDBR(T6,V15 to V8)
0F97H
VFTDBR(T7,V15 to V8)
0F98H
VFTDBR(T8,V15 to V8)
0F99H
VFTDBR(T9,V15 to V8)
0F9AH
VFTDBR(T10,V15 to V8)
0F9BH
VFTDBR(T11,V15 to V8)
0F9CH
VFTDBR(T12,V15 to V8)
0F9DH
VFTDBR(T13,V15 to V8)
0F9EH
VFTDBR(T14,V15 to V8)
0F9FH
VFTDBR(T15,V15 to V8)
Page 59
5. Special Function Register (SFR)
5.2 DBR
TMP86CH72FG
Address
Read
Write
0FA0H
VFTDBR(T0,V23 to V16)
0FA1H
VFTDBR(T1,V23 to V16)
0FA2H
VFTDBR(T2,V23 to V16)
0FA3H
VFTDBR(T3,V23 to V16)
0FA4H
VFTDBR(T4,V23 to V16)
0FA5H
VFTDBR(T5,V23 to V16)
0FA6H
VFTDBR(T6,V23 to V16)
0FA7H
VFTDBR(T7,V23 to V16)
0FA8H
VFTDBR(T8,V23 to V16)
0FA9H
VFTDBR(T9,V23 to V16)
0FAAH
VFTDBR(T10,V23 to V16)
0FABH
VFTDBR(T11,V23 to V16)
0FACH
VFTDBR(T12,V23 to V16)
0FADH
VFTDBR(T13,V23 to V16)
0FAEH
VFTDBR(T14,V23 to V16)
0FAFH
VFTDBR(T15,V23 to V16)
0FB0H
VFTDBR(T0,V31 to V24)
0FB1H
VFTDBR(T1,V31 to V24)
0FB2H
VFTDBR(T2,V31 to V24)
0FB3H
VFTDBR(T3,V31 to V24)
0FB4H
VFTDBR(T4,V31 to V24)
0FB5H
VFTDBR(T5,V31 to V24)
0FB6H
VFTDBR(T6,V31 to V24)
0FB7H
VFTDBR(T7,V31 to V24)
0FB8H
VFTDBR(T8,V31 to V24)
0FB9H
VFTDBR(T9,V31 to V24)
0FBAH
VFTDBR(T10,V31 to V24)
0FBBH
VFTDBR(T11,V31 to V24)
0FBCH
VFTDBR(T12,V31 to V24)
0FBDH
VFTDBR(T13,V31 to V24)
0FBEH
VFTDBR(T14,V31 to V24)
0FBFH
VFTDBR(T15,V31 to V24)
Page 60
TMP86CH72FG
Address
Read
Write
0FC0H
RCAD0L
0FC1H
RCAD0H
0FC2H
RCDT0L
0FC3H
RCDT0H
0FC4H
RCAD1L
0FC5H
RCAD1H
0FC6H
RCDT1L
0FC7H
RCDT1H
0FC8H
RCAD2L
0FC9H
RCAD2H
0FCAH
RCDT2L
0FCBH
RCDT2H
0FCCH
RCAD3L
0FCDH
RCAD3H
0FCEH
RCDT3L
0FCFH
RCDT3H
0FD0H
Reserved
0FD1H
Reserved
0FD2H
Reserved
0FD3H
Reserved
0FD4H
Reserved
0FD5H
Reserved
0FD6H
Reserved
0FD7H
Reserved
0FD8H
Reserved
0FD9H
Reserved
0FDAH
Reserved
0FDBH
Reserved
0FDCH
Reserved
0FDDH
Reserved
0FDEH
Reserved
0FDFH
Reserved
Address
Read
0FE0H
Write
Reserved
: :
: :
0FFFH
Reserved
Note 1: Do not access reserved areas by the program.
Note 2: − ; Cannot be accessed.
Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such
as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Page 61
5. Special Function Register (SFR)
5.2 DBR
TMP86CH72FG
Page 62
TMP86CH72FG
6. I/O Ports
The TMP86CH72FG has 8 parallel input/output ports (54 pins) as follows.
Primary Function
Secondary Functions
Port P1
8-bit I/O
External interrupt input, timer/counter input/output,
Serial interface input/output
Port P2
3-bit I/O
Low-frequency resonator connections, external interrupt input/output,
STOP mode release signal Input
Port P4
8-bit I/O
Analog input, STOP mode release signal input
Port P5
3-bit I/O
External interrupt input, DVO output
Port P6
8-bit I/O
VFT output
Port P7
8-bit I/O
VFT output
Port P8
8-bit I/O
VFT output
Port P9
8-bit I/O
VFT output
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 6-1 shows input/output timing examples.
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This
timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
port.
!
"
#
!
"
#
!
"
#
&'
!
"
#
!
"
%
#
!
"
#
$ $
$ &'
Note: The positions of the read and write cycles may vary, depending on the instruction.
Figure 6-1 Input/Output Timing (Example)
Page 63
(
)
6. I/O Ports
6.1 Port P1 (P17 to P10)
TMP86CH72FG
6.1 Port P1 (P17 to P10)
Port P1 is an 8-bit input/output port, and also used as a timer counter input/output, external interrupt input, and
serial interface input/output. To use port P1 as an input port or secondary function pins, set its output latch (P1DR) to
“1”. A reset sets the output latch to “1” and clears the push-pull control register (P1OUTCR) to “0”.
The P1OUTCR can be used to select sink open-drain output or CMOS output for the output circuit of port P1. To
use port P1 as an input port, set the P1DR to “1”, and then clear the corresponding bit of the P1OUTCR to “0”.
Port P1 has separate data input registers. To sense the state of the output latch, read the P1DR. To sense the state of
the pins the port, read the P1 port input data (P1PRD) register.
The input waveform of a TC3 input can be inverted in terms of phase, using the Timer Counter3 input control
(TC3SEL) register.
P10, P11, P12, and P13 can work not only as a port but also as, respectively, the TC3/INT3, PWM4/PDO4/TC4,
TXD, and RXD/INT2 functions. To use the TC3, INT3, TC4, RXD and INT2 functions, place the respective pins in
input mode. To use the PWM4 and PDO4 functions, place the respective pins in output mode.
P14, P15, P16, and P17 can work not only as a port but also as, respectively, the SI/SDA, SO/SCL, SCK, and CS/
INT4 functions. To use these functions, place the pin corresponding to the SI, CS, and INT4 function in input mode,
the pin corresponding to the SO, SDA, and SCL function in output mode (when using it in I2C bus, it is used by sink
open-drain output.), and the pin corresponding to the SCK function in either input or output mode.
STOP
OUTEN
P1OUTCRi
D
Q
D
Q
D
Q
P1OUTCRi input
Data input (P1PRD)
Data input (P1DR)
Data output (P1DR)
P1i
Note: i = 7 to 0
Control output
TC3INV
TC3INV input
Control input(TC3)
Control input
(except for TC3, CS)
Control input (CS)
For P11
only
Noise
canceller
Figure 6-2 Port P1
Page 64
TMP86CH72FG
P1DR
(0001H)
R/W
7
6
5
4
3
2
1
0
P17
P16
SCK
P15
SO
SCL
P14
SI
SDA
P13
RXD
INT2
P12
TXD
P11
CS
PWM4
P10
TC3
INT3
INT4
PDO4
(Initial value: 1111 1111)
TC4
P1OUTCR
(000BH)
7
TC3SBI
(0029H)
5
4
3
2
1
0
(Initial value: 0000 0000)
I/O control for port P1
(This register can be set on bit
basis.)
0: Sink open drain
1: CMOS output
7
6
7
6
P1OUTCR
P1PRD
(0015H)
Read only
6
CSEN
R/W
5
4
3
2
1
5
4
3
2
1
SBISEL
0
0
TC3INV
(Initial value: 0*0* ***0)
0: Normal input
1: Inverted input
TC3INV
TC3 input control
SBISEL
SIO/I2C BUS selection (P15)
CSEN
Chip enable function control
0: SIO (P15: SO pin)
R/W
1: I2C (P15: SCL pin)
0: Disable
1: Enable
P1OUTCR
P1DR
Function
0
0
Low output
0
1
Input, open-drain output, or control input
1
0
Low output
1
1
High output or control output
Page 65
6. I/O Ports
6.2 Port P2 (P22 to P20)
TMP86CH72FG
6.2 Port P2 (P22 to P20)
Port P2 is a 3-bit input/output port. It can work not only as a port but also as external input, STOP mode release
signal input, and low-frequency resonator connection pins. To use it as an input port or the secondary function pins,
set the output latch (P2DR) to “1”. A reset initializes the P2DR to “1”. To run the device in dual clock mode, connect
a low-frequency resonator (32.768 kHz) to pins P21 (XTIN) and P22 (XTOUT). When the device runs in single
clock mode, P21 and P22 can be used as an ordinary input/output port. It is recommended that pin P20 be used for
external interrupt input, STOP release signal input, or as an input port (if it is used as an output port, it is set with the
content of the interrupt latch at the negative-going edge of the signal).
Port P2 has separate data input registers. To sense the state of the output latch, read the P2DR. To sense the state of
the pins of the port, read the P2 port input data (P2PRD) register.
If a read instruction is executed for the P2DR or P2PRD on port P2, the sensed state of bits 7 to 3 is undefined.
$ %
! "#"
$ %
$ %
Figure 6-3 Port P2
7
6
5
4
3
P2DR
(0002H)
R/W
P2PRD
(0016H)
Read only
2
1
0
P22
XTOUT
P21
XTIN
INT5
P20
(Initial value: **** *111)
STOP
7
6
5
4
3
2
1
0
Note: Because pin P20 is used also as the STOP pin, its output high impedance becomes high when it enters the STOP mode
regardless of the state of OUTEN.
Page 66
TMP86CH72FG
6.3 Port P4 (P47 to P40)
Port P4 is an 8-bit input/output port. Each bit of the port can be configured for either input or output separately,
using the P4 port input/output control register (P4CR1). These pins can work not only as a port but also for analog
input and key-on-wakeup input. To use each bit for output, set the corresponding bit of the P4CR1 to “1” to place
them in output mode. To use them in input mode, clear the corresponding bit of the P4CR1 to “0”, then set the
P4CR2 to “1”. To use the bits for analog input and key-on-wakeup input, clear the P4CR1 and P4CR2 to “0” in the
stated order (then, for analog input, clear the ADCCR1<AINDS> to “0”, and start the AD). A reset initializes the
P4CR1 and P4CR2, respectively, to “0” and “1”, thereby placing port P4 in input mode. A reset also clears the P4
port output latch (P4DR) to “0”.
The “Low” level of P40 and P41 is a large current output ports.
When a sink open drain port uses, bit of P4CR2 is set to “0”, and when using it is a CMOS output port, bit of
P4CR2 is set to “1”.
!
& .& & (& 3& $
4 5
" # $ %& ' # ( )
" * + , $ ." * */ *-)
" * */ * 01
2 ! !
0
/-
4 5
& (& 3& $
4 5
Figure 6-4 Port P4
Page 67
6. I/O Ports
6.3 Port P4 (P47 to P40)
P4DR
(0004H)
R/W
P4CR1
(000CH)
TMP86CH72FG
7
6
5
4
3
2
1
0
P47
AIN5
STOP5
P46
AIN4
STOP4
P45
AIN3
STOP3
P44
AIN2
STOP2
P43
AIN1
P42
AIN0
P41
P40
7
6
5
4
3
2
1
0
(Initial value: 0000 0000)
P4CR1
P4CR2
(0028H)
(Initial value: 0000 0000)
7
I/O control for port P4
(This register can be set on bit
basis.)
0: Input mode or analog input/key-on wakeup input
1: Output mode
6
3
5
4
2
1
R/W
0
(Initial value: 1111 1111)
P4CR2
(Bit 7 to 2)
I/O control for port P4
(This register can be set on bit
basis.)
0: Analog input/key-on wakeup input
1: Input mode
P4CR2
(Bit 1, 0)
I/O control for port P4
(This register can be set on bit
basis.)
0: Sink open drain output
1: CMOS output
R/W
Note 1: If a port is in input mode, it senses the state of an input to its pins. If some pins of the port are in input mode, and others
are in output mode, the content of the output latch related to a port pin that is in input mode may be changed when a bit
manipulation instruction is executed on the port.
Note 2: The P4CR2 controls the input gate of pins used for analog input. In analog input mode, clear the P4CR2 to “0” to fix the
input gate, thereby protecting it from through current. In input mode, set the P4CR2 to “1”. When using the key-on wakeup
function, clear the P4CR2 to “0”, because the inputs are received separately. If the P4CR2 is “0”, read accessing the
P4CR2 yields “0”.
Page 68
TMP86CH72FG
6.4 Port P5 (P52 to P50)
Port P5 is a 3-bit general-purpose input/output port. Each bit of the port can be configured for either input or output separately, using the P5 port input/output control register (P5CR). A reset clears the P5CR to “0”, placing port P5
in input mode. A reset also initializes the P5 port output latch (P5DR) to “0”.
P51, and P52 can work not only as an input/output port but also, respectively, for the INT0, and INT1 functions. To
use these functions, place the corresponding pins in input mode.
P50 can work not only as a port but also as, respectively, the DVO function. To use the DVO function, place the
respective pin in output mode.
Figure 6-5 Port P5
7
6
5
4
3
P5DR
(0005H)
P5CR
(000DH)
7
6
5
4
3
2
1
0
P52
INT1
P51
P50
INT0
DVO
2
1
0
(Initial value: **** *000)
(Initial value: **** *000)
P5CR
I/O control for port P5
(This register can be set on bit
basis.)
0: Input mode
1: Output mode
R/W
Note: If a port is in input mode, it senses the state of an input to its pins. If some pins of the port are in input mode, and others are
in output mode, the content of the output latch related to a port pin that is in input mode may be changed when a bit manipulation instruction is executed on the port.
Page 69
6. I/O Ports
6.5 Ports P6 (P67 to P60), P7 (P77 to P70), P8 (P87 to P80), and
P9 (P97 to P90)
TMP86CH72FG
6.5 Ports P6 (P67 to P60), P7 (P77 to P70), P8 (P87 to P80),
and P9 (P97 to P90)
Ports P6, P7, P8, and P9 are 8-bit high-breakdown voltage input/output ports. They can work not only as a port but
also for VFT driver output. They can drive directly a vacuum fluorescent tube (VFT). To use them as an input port or
VFT driver, clear the output latch to “0”.
Pins not set up for VFT driver output can be used as an input/output port. To use a pin for ordinary input/output
when a VFT driver is used, clear the VFT driver output data buffer memory (DBR) for the pin to “0”. A reset initializes the output latch to “0”.
It is recommended that ports P6, P7, P8, and P9 be used to drive a VFT because they have a built-in pull-down
resistor.
"#$#"#$$ %
$"&'$"&$ %
( )
!
Figure 6-6 Port P6, P7, P8, and P9
P6DR
(0006H)
R/W
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
P7DR
(0007H)
R/W
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
P8DR
(0008H)
R/W
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
7
6
5
4
3
2
1
0
P97
P96
P95
P94
P93
P92
P91
P90
P9DR
(0009H)
R/W
Page 70
(Initial value: 0000 0000)
(Initial value: 0000 0000)
(Initial value: 0000 0000)
(Initial value: 0000 0000)
TMP86CH72FG
7. Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine.
The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request” or “interrupt request”. Upon the reset release, this signal is initialized to “reset request”.
When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt.
Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to
effect of disturbing noise.
7.1 Watchdog Timer Configuration
Reset release
23
15
Binary counters
Selector
fc/2 or fs/2
fc/221 or fs/213
fc/219 or fs/211
fc/217 or fs/29
Clock
Clear
R
Overflow
1
WDT output
2
S
2
Q
Interrupt request
Internal reset
Q
S R
WDTEN
WDTT
Writing
disable code
Writing
clear code
WDTOUT
Controller
0034H
WDTCR1
0035H
WDTCR2
Watchdog timer control registers
Figure 7-1 Watchdog Timer Configuration
Page 71
Reset
request
INTWDT
interrupt
request
7. Watchdog Timer (WDT)
7.2 Watchdog Timer Control
TMP86CH72FG
7.2 Watchdog Timer Control
The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release.
7.2.1
Malfunction Detection Methods Using the Watchdog Timer
The CPU malfunction is detected, as shown below.
1. Set the detection time, select the output, and clear the binary counter.
2. Clear the binary counter repeatedly within the specified detection time.
If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When
WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and then internal hardware is
initialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog timer interrupt (INTWDT) is generated.
The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/SLEEP
mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated.
Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH
is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow
time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/
4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter than 3/4 of the
time set to WDTCR1<WDTT>.
Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection
Within 3/4 of WDT
detection time
LD
(WDTCR2), 4EH
: Clears the binary counters.
LD
(WDTCR1), 00001101B
: WDTT ← 10, WDTOUT ← 1
LD
(WDTCR2), 4EH
: Clears the binary counters (always clears immediately before and
after changing WDTT).
(WDTCR2), 4EH
: Clears the binary counters.
(WDTCR2), 4EH
: Clears the binary counters.
:
:
LD
Within 3/4 of WDT
detection time
:
:
LD
Page 72
TMP86CH72FG
Watchdog Timer Control Register 1
WDTCR1
(0034H)
7
WDTEN
6
5
4
3
(ATAS)
(ATOUT)
WDTEN
Watchdog timer enable/disable
2
1
0
WDTT
WDTOUT
(Initial value: **11 1001)
0: Disable (Writing the disable code to WDTCR2 is required.)
1: Enable
NORMAL1/2 mode
WDTT
WDTOUT
Watchdog timer detection time
[s]
Watchdog timer output select
DV7CK = 0
DV7CK = 1
SLOW1/2
mode
00
225/fc
217/fs
217/fs
01
223/fc
215/fs
215fs
10
221fc
213/fs
213fs
11
219/fc
211/fs
211/fs
0: Interrupt request
1: Reset request
Write
only
Write
only
Write
only
Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”.
Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a
don’t care is read.
Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode.
After clearing the counter, clear the counter again immediately after the STOP mode is inactivated.
Note 5: To clear WDTEN, set the register in accordance with the procedures shown in “7.2.3 Watchdog Timer Disable”.
Watchdog Timer Control Register 2
WDTCR2
(0035H)
7
6
5
4
3
2
1
0
(Initial value: **** ****)
WDTCR2
Write
Watchdog timer control code
4EH: Clear the watchdog timer binary counter (Clear code)
B1H: Disable the watchdog timer (Disable code)
D2H: Enable assigning address trap area
Others: Invalid
Write
only
Note 1: The disable code is valid only when WDTCR1<WDTEN> = 0.
Note 2: *: Don’t care
Note 3: The binary counter of the watchdog timer must not be cleared by the interrupt task.
Note 4: Write the clear code 4EH using a cycle shorter than 3/4 of the time set in WDTCR1<WDTT>.
7.2.2
Watchdog Timer Enable
Setting WDTCR1<WDTEN> to “1” enables the watchdog timer. Since WDTCR1<WDTEN> is initialized
to “1” during reset, the watchdog timer is enabled automatically after the reset release.
Page 73
7. Watchdog Timer (WDT)
7.2 Watchdog Timer Control
7.2.3
TMP86CH72FG
Watchdog Timer Disable
To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller.
1. Set the interrupt master flag (IMF) to “0”.
2. Set WDTCR2 to the clear code (4EH).
3. Set WDTCR1<WDTEN> to “0”.
4. Set WDTCR2 to the disable code (B1H).
Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared.
Example :Disabling the watchdog timer
: IMF ← 0
DI
LD
(WDTCR2), 04EH
: Clears the binary counter
LDW
(WDTCR1), 0B101H
: WDTEN ← 0, WDTCR2 ← Disable code
Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz)
Watchdog Timer Detection Time[s]
WDTT
7.2.4
NORMAL1/2 mode
DV7CK = 0
DV7CK = 1
SLOW
mode
00
2.097
4
4
01
524.288 m
1
1
10
131.072 m
250 m
250 m
11
32.768 m
62.5 m
62.5 m
Watchdog Timer Interrupt (INTWDT)
When WDTCR1<WDTOUT> is cleared to “0”, a watchdog timer interrupt request (INTWDT) is generated
by the binary-counter overflow.
A watchdog timer interrupt is the non-maskable interrupt which can be accepted regardless of the interrupt
master flag (IMF).
When a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt
is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is
held pending. Therefore, if watchdog timer interrupts are generated continuously without execution of the
RETN instruction, too many levels of nesting may cause a malfunction of the microcontroller.
To generate a watchdog timer interrupt, set the stack pointer before setting WDTCR1<WDTOUT>.
Example :Setting watchdog timer interrupt
LD
SP, 043FH
: Sets the stack pointer
LD
(WDTCR1), 00001000B
: WDTOUT ← 0
Page 74
TMP86CH72FG
7.2.5
Watchdog Timer Reset
When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset
request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset
time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
219/fc [s]
217/fc
Clock
Binary counter
(WDTT=11)
1
2
3
0
1
2
3
0
Overflow
INTWDT interrupt request
(WDTCR1<WDTOUT>= "0")
Internal reset
A reset occurs
(WDTCR1<WDTOUT>= "1")
Write 4EH to WDTCR2
Figure 7-2 Watchdog Timer Interrupt
Page 75
7. Watchdog Timer (WDT)
7.3 Address Trap
TMP86CH72FG
7.3 Address Trap
The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address
traps.
Watchdog Timer Control Register 1
7
WDTCR1
(0034H)
6
ATAS
ATOUT
5
4
3
ATAS
ATOUT
(WDTEN)
2
1
(WDTT)
0
(WDTOUT)
(Initial value: **11 1001)
Select address trap generation in
the internal RAM area
0: Generate no address trap
1: Generate address traps (After setting ATAS to “1”, writing the control code
D2H to WDTCR2 is required)
Select operation at address trap
0: Interrupt request
1: Reset request
Write
only
Watchdog Timer Control Register 2
WDTCR2
(0035H)
7
5
4
3
2
1
0
(Initial value: **** ****)
WDTCR2
7.3.1
6
Write
Watchdog timer control code
and address trap area control
code
D2H: Enable address trap area selection (ATRAP control code)
4EH: Clear the watchdog timer binary counter (WDT clear code)
B1H: Disable the watchdog timer (WDT disable code)
Others: Invalid
Write
only
Selection of Address Trap in Internal RAM (ATAS)
WDTCR1<ATAS> specifies whether or not to generate address traps in the internal RAM area. To execute
an instruction in the internal RAM area, clear WDTCR1<ATAS> to “0”. To enable the WDTCR1<ATAS> setting, set WDTCR1<ATAS> and then write D2H to WDTCR2.
Executing an instruction in the SFR or DBR area generates an address trap unconditionally regardless of the
setting in WDTCR1<ATAS>.
7.3.2
Selection of Operation at Address Trap (ATOUT)
When an address trap is generated, either the interrupt request or the reset request can be selected by
WDTCR1<ATOUT>.
7.3.3
Address Trap Interrupt (INTATRAP)
While WDTCR1<ATOUT> is “0”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap interrupt (INTATRAP) will be generated.
An address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt master flag (IMF).
When an address trap interrupt is generated while the other interrupt including an address trap interrupt is
already accepted, the new address trap is processed immediately and the previous interrupt is held pending.
Therefore, if address trap interrupts are generated continuously without execution of the RETN instruction, too
many levels of nesting may cause a malfunction of the microcontroller.
To generate address trap interrupts, set the stack pointer beforehand.
Page 76
TMP86CH72FG
7.3.4
Address Trap Reset
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the
SFR area, address trap reset will be generated.
When an address trap reset request is generated, the internal hardware is reset. The reset time is maximum
24/fc [s] (1.5 µs @ fc = 16.0 MHz).
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Page 77
7. Watchdog Timer (WDT)
7.3 Address Trap
TMP86CH72FG
Page 78
TMP86CH72FG
8. Time Base Timer (TBT)
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base
timer interrupt (INTTBT).
8.1 Time Base Timer
8.1.1
Configuration
MPX
fc/223 or fs/215
fc/221 or fs/213
fc/216 or fs/28
fc/214 or fs/26
fc/213 or fs/25
fc/212 or fs/24
fc/211 or fs/23
fc/29 or fs/2
Source clock
IDLE0, SLEEP0
release request
Falling edge
detector
INTTBT
interrupt request
3
TBTCK
TBTEN
TBTCR
Time base timer control register
Figure 8-1 Time Base Timer configuration
8.1.2
Control
Time Base Timer is controlled by Time Base Timer control register (TBTCR).
Time Base Timer Control Register
7
TBTCR
(0036H)
6
(DVOEN)
TBTEN
5
(DVOCK)
Time Base Timer
enable / disable
4
3
(DV7CK)
TBTEN
2
1
0
TBTCK
(Initial Value: 0000 0000)
0: Disable
1: Enable
NORMAL1/2, IDLE1/2 Mode
TBTCK
Time Base Timer interrupt
Frequency select : [Hz]
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
Mode
000
fc/223
fs/215
fs/215
001
fc/221
fs/213
fs/213
010
fc/216
fs/28
–
011
fc/2
14
6
–
100
fc/213
fs/25
–
101
fc/2
12
4
–
110
fc/211
fs/23
–
111
9
fs/2
–
fc/2
Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care
Page 79
fs/2
fs/2
R/W
8. Time Base Timer (TBT)
8.1 Time Base Timer
TMP86CH72FG
Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously.
Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt.
LD
(TBTCR) , 00000010B
; TBTCK ← 010
LD
(TBTCR) , 00001010B
; TBTEN ← 1
; IMF ← 0
DI
SET
(EIRL) . 7
Table 8-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Time Base Timer Interrupt Frequency [Hz]
TBTCK
8.1.3
NORMAL1/2, IDLE1/2 Mode
NORMAL1/2, IDLE1/2 Mode
SLOW1/2, SLEEP1/2 Mode
DV7CK = 0
DV7CK = 1
000
1.91
1
1
001
7.63
4
4
010
244.14
128
–
011
976.56
512
–
100
1953.13
1024
–
101
3906.25
2048
–
110
7812.5
4096
–
111
31250
16384
–
Function
An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider
output of the timing generator which is selected by TBTCK. ) after time base timer has been enabled.
The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set
interrupt period ( Figure 8-2 ).
Source clock
TBTCR<TBTEN>
INTTBT
Interrupt period
Enable TBT
Figure 8-2 Time Base Timer Interrupt
Page 80
TMP86CH72FG
8.2 Divider Output (DVO)
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric
buzzer drive. Divider output is from DVO pin.
8.2.1
Configuration
Output latch
D
Data output
Q
DVO pin
MPX
A
B
C Y
D
S
2
fc/213 or fs/25
fc/212 or fs/24
fc/211 or fs/23
fc/210 or fs/22
Port output latch
TBTCR<DVOEN>
DVOCK
DVOEN
TBTCR
DVO pin output
Divider output control register
(a) configuration
(b) Timing chart
Figure 8-3 Divider Output
8.2.2
Control
The Divider Output is controlled by the Time Base Timer Control Register.
Time Base Timer Control Register
7
TBTCR
(0036H)
DVOEN
DVOEN
6
5
DVOCK
4
3
(DV7CK)
(TBTEN)
Divider output
enable / disable
2
1
0
(TBTCK)
(Initial value: 0000 0000)
0: Disable
1: Enable
R/W
DV7CK = 0
DV7CK = 1
SLOW1/2
SLEEP1/2
Mode
00
fc/213
fs/25
fs/25
01
fc/212
fs/24
fs/24
10
fc/211
fs/23
fs/23
11
fc/210
fs/22
fs/22
NORMAL1/2, IDLE1/2 Mode
DVOCK
Divider Output (DVO)
frequency selection: [Hz]
R/W
Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other
words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not
change the setting of the divider output frequency.
Page 81
8. Time Base Timer (TBT)
8.2 Divider Output (DVO)
TMP86CH72FG
Example :1.95 kHz pulse output (fc = 16.0 MHz)
LD
(TBTCR) , 00000000B
; DVOCK ← "00"
LD
(TBTCR) , 10000000B
; DVOEN ← "1"
Table 8-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )
Divider Output Frequency [Hz]
DVOCK
NORMAL1/2, IDLE1/2 Mode
DV7CK = 0
DV7CK = 1
SLOW1/2, SLEEP1/2
Mode
00
1.953 k
1.024 k
1.024 k
01
3.906 k
2.048 k
2.048 k
10
7.813 k
4.096 k
4.096 k
11
15.625 k
8.192 k
8.192 k
Page 82
TMP86CH72FG
9. 16-Bit Timer/Counter2 (TC2)
9.1 Configuration
TC2 pin
Port
(Note)
TC2S
H
Window
23,
15
fc/2 fs/2
fc/213, fs/25
fc/28
fc/23
fc
fs
A
B
C
D
E
F
S
3
Clear
B
Timer/
event counter
16-bit up counter
Y
A
S
Source
clock
CMP
TC2M
Match
INTTC2
interrupt
TC2S
TC2CK
TC2CR
TC2DR
TC2 control register
16-bit timer register 2
Note: When control input/output is used, I/O port setting should be set correctly. For details, refer to the section "I/O ports".
Figure 9-1 Timer/Counter2 (TC2)
Page 83
9. 16-Bit Timer/Counter2 (TC2)
9.2 Control
TMP86CH72FG
9.2 Control
The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2
(TC2DR).
TC2DR
(0025H,
0024H)
TC2CR
(0013H)
TC2S
15
7
14
13
12
11
10
9
8
7
6
5
4
3
TC2DRH (0025H)
TC2DRL (0024H)
(Initial value: 1111 1111 1111 1111)
R/W
6
5
4
TC2S
TC2 start control
3
2
1
TC2 source clock select
Unit : [Hz]
TC2M
(Initial value: **00 00*0)
R/W
Divider
SLOW1/2
mode
SLEEP1/2
mode
fs/215
DV21
fs/215
fs/215
fc/213
fs/25
DV11
fs/25
fs/25
010
fc/28
fc/28
DV6
–
–
011
3
3
fc/2
DV1
–
–
DV7CK = 0
DV7CK = 1
000
fc/223
001
fc/2
100
–
–
–
fc (Note7)
–
101
fs
fs
–
–
–
R/W
Reserved
External clock (TC2 pin input)
111
TC2 operating mode
select
0
0:Stop and counter clear
1:Start
110
TC2M
1
0
TC2CK
NORMAL1/2, IDLE1/2 mode
TC2CK
2
0:Timer/event counter mode
1:Window mode
R/W
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care
Note 2: When writing to the Timer Register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper side
(TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no effect.
Note 3: The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written to the upper
side (TC2DRH) after writing data to the lower side (TC2DRL).
Note 4: Set the mode and source clock when the TC2 stops (TC2S = 0).
Note 5: Values to be loaded to the timer register must satisfy the following condition.
TC2DR > 1 (TC2DR15 to TC2DR11 > 1 at warm up)
Note 6: If a read instruction is executed for TC2CR, read data of bit 7, 6 and 1 are unstable.
Note 7: The high-frequency clock (fc) canbe selected only when the time mode at SLOW2 mode is selected.
Note 8: On entering STOP mode, the TC2 start control (TC2S) is cleared to "0" automatically. So, the timer stops. Once the STOP
mode has been released, to start using the timer counter, set TC2S again.
Page 84
TMP86CH72FG
9.3 Function
The timer/counter 2 has three operating modes: timer, event counter and window modes.
And if fc or fs is selected as the source clock in timer mode, when switching the timer mode from SLOW1 to
NORMAL2, the timer/counter2 can generate warm-up time until the oscillator is stable.
9.3.1
Timer mode
In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the contents of up counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is
cleared. Counting up is resumed after the counter is cleared.
When fc is selected for source clock at SLOW2 mode, lower 11-bits of TC2DR are ignored and generated a
interrupt by matching upper 5-bits only. Though, in this situation, it is necessary to set TC2DRH only.
Table 9-1 Source Clock (Internal clock) for Timer/Counter2 (at fc = 16 MHz, DV7CK=0)
NORMAL1/2, IDLE1/2 mode
TC2C
K
SLOW1/2 mode
DV7CK = 0
SLEEP1/2 mode
DV7CK = 1
Resolution
Maximum Time Setting
Resolution
Maximum Time Setting
Resolution
Maximum
Time
Setting
Resolution
Maximum
Time
Setting
000
524.29 [ms]
9.54 [h]
1 [s]
18.2 [h]
1 [s]
18.2 [h]
1 [s]
18.2 [h]
001
512.0 [ms]
33.55 [s]
0.98 [ms]
1.07 [min]
0.98 [ms]
1.07
[min]
0.98 [ms]
1.07
[min]
010
16.0 [ms]
1.05 [s]
16.0 [ms]
1.05 [s]
–
–
–
–
011
0.5 [ms]
32.77 [ms]
0.5 [ms]
32.77 [ms]
–
–
–
–
100
–
–
–
–
62.5 [ns]
–
–
–
101
30.52 [ms]
2 [s]
30.52 [ms]
2 [s]
–
–
–
–
Note:When fc is selected as the source clock in timer mode, it is used at warm-up for switching from SLOW1 mode
to NORMAL2 mode.
Example :Sets the timer mode with source clock fc/23 [Hz] and generates an interrupt every 25 ms (at fc = 16 MHz )
LDW
; Sets TC2DR (25 ms ³ 28/fc = 061AH)
(TC2DR), 061AH
DI
SET
; IMF= “0”
(EIRH). 6
; Enables INTTC2 interrupt
EI
; IMF= “1”
LD
(TC2CR), 00001000B
; Source clock / mode select
LD
(TC2CR), 00101000B
; Starts Timer
Page 85
9. 16-Bit Timer/Counter2 (TC2)
9.3 Function
TMP86CH72FG
Timer start
Source clock
Up-counter
0
1
2
3
4
n 0
Match detect
TC2DR
㫅
INTTC2 interrupt
Figure 9-2 Timer Mode Timing Chart
Page 86
1
2
3
Counter clear
TMP86CH72FG
9.3.2
Event counter mode
In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are compared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the
counter is cleared. Counting up is resumed every the rising edge of the TC2 pin input after the up counter is
cleared.
Match detect is executed on the falling edge of the TC2 pin. Therefore, an INTTC2 interrupt is generated at
the falling edge after the match of TC2DR and up counter.
The minimum input pulse width of TC2 pin is shown in Table 9-2. Two or more machine cycles are required
for both the “H” and “L” levels of the pulse width.
Example :Sets the event counter mode and generates an INTTC2 interrupt 640 counts later.
LDW
(TC2DR), 640
; Sets TC2DR
DI
; IMF= “0”
SET
(EIRH). 6
;Enables INTTC2 interrupt
EI
; IMF= “1”
LD
(TC2CR), 00011100B
; TC2 source vclock / mode select
LD
(TC2CR), 00111100B
; Starts TC2
Table 9-2 Timer/Counter 2 External Input Clock Pulse Width
Minimum Input Pulse Width [s]
NORMAL1/2, IDLE1/2 mode
SLOW1/2, SLEEP1/2 mode
“H” width
23/fc
23/fs
“L” width
23/fc
23/fs
Timer start
TC2 pin input
0
Counter
1
2
3
n
Match detect
TC2DR
0
1
2
3
Counter clear
n
INTTC2 interrupt
Figure 9-3 Event Counter Mode Timing Chart
9.3.3
Window mode
In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input
(Window pulse) is “H” level. The contents of TC2DR are compared with the contents of up counter. If a match
found, an INTTC2 interrupt is generated, and the up-counter is cleared.
The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock
by the TC2CR<TC2CK>.
Note:It is not available window mode in the SLOW/SLEEP mode. Therefore, at the window mode in NORMAL
mode, the timer should be halted by setting TC2CR<TC2S> to "0" before the SLOW/SLEEP mode is entered.
Page 87
9. 16-Bit Timer/Counter2 (TC2)
9.3 Function
TMP86CH72FG
Example :Generates an interrupt, inputting “H” level pulse width of 120 ms or more. (at fc = 16 MHz, TBTCR<DV7CK> =
“0” )
LDW
; Sets TC2DR (120 ms ³ 213/fc = 00EAH)
(TC2DR), 00EAH
DI
; IMF= “0”
SET
(EIRH). 6
; Enables INTTC2 interrupt
LD
(TC2CR), 00000101B
; TC2sorce clock / mode select
LD
(TC2CR), 00100101B
; Starts TC2
EI
; IMF= “1”
Timer start
TC2 pin input
Internal clock
Counter
TC2DR
㪇
1
n
2
0
1
2
㫅
Match detect
INTTC2 interrupt
Figure 9-4 Window Mode Timing Chart
Page 88
Counter clear
3
TMP86CH72FG
10.2 TimerCounter Control
The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers
(TC3DRA and TC3DRB).
Timer Register and Control Register
TC3DRA
(0010H)
7
6
5
4
3
2
1
0
Read/Write (Initial value: 1111 1111)
TC3DRB
(0011H)
TC3CR
(0012H)
Read only (Initial value: 1111 1111)
7
6
5
4
ACAP
3
2
TC3S
1
0
TC3CK
TC3M
(Initial value: *0*0 0000)
ACAP
Auto capture control
0: –
1: Auto capture
R/W
TC3S
TC3 start control
0: Stop and counter clear
1: Start
R/W
NORMAL1/2, IDLE1/2 mode
TC3 source clock select
[Hz]
TC3CK
TC3 operating mode
select
SLOW1/2,
SLEEP1/2
mode
DV7CK = 0
DV7CK = 1
000
fc/213
fs/25
DV11
fs/25
001
fc/212
fs/24
DV10
fs/24
010
fc/211
fs/23
DV9
fs/23
011
fc/210
fs/22
DV8
fs/22
100
fc/29
fs/2
DV7
fs/2
101
fc/28
fc/28
DV6
–
110
7
7
DV5
–
fc/2
fc/2
111
TC3M
Divider
R/W
External clock (TC3 pin input)
0: Timer/event counter mode
1: Capture mode
R/W
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 2: Set the operating mode and source clock when TimerCounter stops (TC3S = 0).
Note 3: To set the timer registers, the following relationship must be satisfied.
TC3DRA > 1 (Timer/event counter mode)
Note 4: Auto-capture (ACAP) can be used only in the timer and event counter modes.
Note 5: When the read instruction is executed to TC3CR, the bit 5 and 7 are read as a don’t care.
Note 6: Do not program TC3DRA when the timer is running (TC3S = 1).
Note 7: When the STOP mode is entered, the start control (TC3S) is cleared to 0 automatically, and the timer stops. After
the STOP mode is exited, TC3S must be set again to use the timer counter.
TimerCounter 3 Input Control Register
TC3SEL
(0029H)
7
6
5
4
3
2
0
TC3INV
Event counter mode
TC3INV
1
TC3 input control
0:
1:
Count at the rising edge
Count at the falling edge
Read/Write (Initial value: **** ***0)
Capture mode
An interrupt is generated at the rising edge.
An interrupt is generated at the falling edge.
Note: When the read instruction is executed to TC3SEL, the bit 7 to 1 are read as a don’t care.
Page 91
R/W
10. 8-Bit TimerCounter 3 (TC3)
10.1 Configuration
TMP86CH72FG
10.3 Function
TimerCounter 3 has three types of operating modes: timer, event counter and capture modes.
10.3.1 Timer mode
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the timer register 3A (TC3DRA) value is detected, an INTTC3 interrupt is generated and the up-counter is
cleared. After being cleared, the up-counter restarts counting. Setting TC3CR<ACAP> to 1 captures the upcounter value into the timer register B (TC3DRB) with the auto-capture function. The count value during timer
operation can be checked by executing the read instruction to TC3DRB.
Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB.
(Figure 10-2)
Clock
TC3DRA
Match detect C8
Up-counter
C7
C6
TC3DRB
C8
C6
C7
00
01
C8
01
Note: In the case that TC3DRB is C8H
Figure 10-2 Auto-Capture Function
Table 10-1 Source Clock for TimerCounter 3 (Example: fc = 16 MHz, fs = 32.768 kHz)
TC3CK
NORMAL1/2, IDLE1/2 mode
DV7CK = 0
SLOW1/2, SLEEP1/2
mode
DV7CK = 1
Resolution
[µs]
Maximum Time Setting
[ms]
Resolution
[µs]
Maximum Time Setting
[ms]
Resolution
[µs]
Maximum
Time Setting
[ms]
000
512
130.6
976.56
249.0
976.56
249.0
001
256
65.3
488.28
124.5
488.28
124.5
010
128
32.6
244.14
62.3
244.14
62.3
011
64
16.3
122.07
31.1
122.07
31.1
100
32
8.2
61.01
15.6
61.01
15.6
101
16
4.1
16.0
4.1
–
–
110
8
2.0
8.0
2.0
–
–
Page 92
TMP86CH72FG
Timer start
Source clock
Counter
0
TC3DRA
?
1
2
3
n 0
4
1
2
3
4
5
6
7
n
Match detect
Counter clear
INTTC3 interrupt
(a)
Timer mode
Source clock
Counter
m
m+1
m+2
n
n+1
Capture
TC3DRB
?
m
Capture
m+1
m+2
TC3CR<ACAP>
(b)
Auto capture
Figure 10-3 Timer Mode Timing Chart
Page 93
n
n+1
10. 8-Bit TimerCounter 3 (TC3)
10.1 Configuration
TMP86CH72FG
10.3.2 Event Counter Mode
In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC3 pin. Either the
rising or falling edge of the input pulse is programmed as the count up edge in TC3SEL<TC3INV>.
When a match between the up-counter and TC3DRA value is detected, an INTTC3 interrupt is generated and
up-counter is cleared. After being cleared, the up-counter restarts counting at each edge of the input pulse to
the TC3 pin. Since a match between the up-counter and TC3DRA value is detected at the edge opposite to the
selected edge, an INTTC3 interrupt request is generated at the edge opposite to the selected edge immediately
after the up-counter reaches the value set in TC3DRA.
The maximum applied frequencies are shown in Table 10-2. The pulse width larger than one machine cycle
is required for high-going and low-going pulses.
Setting TC3CR<ACAP> to 1 captures the up-counter value into TC3DRB with the auto-capture function.
The count value during a timer operation can be checked by the read instruction to TC3DRB.
Note:00H which is stored in the up-counter immediately after detection of a match is not captured into TC3DRB.
(Figure 10-2)
Example :Inputting 50 Hz pulse to TC3, and generating interrupts every 0.5 s
LD
(TC3SEL), 00000000B
: Selects the count-up edge.
LD
(TC3CR), 00001110B
: Sets the clock mode
LD
(TC3DRA), 19H
: 0.5 s ÷ 1/50 = 25 = 19H
LD
(TC3CR), 00011110B
: Starts TC3.
Table 10-2 Maximum Frequencies Applied to TC3
Minimum Pulse Width
NORMAL1/2, IDLE1/2 mode
SLOW1/2, SLEEP1/2 mode
High-going
22/fc
22/fs
Low-going
22/fc
22/fs
Timer start
TC3 pin input
Counter
0
1
2
3
n
Match detect
TC3DRA
0
1
2
3
Counter clear
n
INTTC3 interrupt
Figure 10-4 Event Counter Mode Timing Chart (TC3SEL<TC3INV> = 0)
Page 94
TMP86CH72FG
10.3.3 Capture Mode
In the capture mode, the pulse width, frequency and duty cycle of the pulse input to the TC3 pin are measured with the internal clock. The capture mode is used to decode remote control signals, and identify AC50/60
Hz.
Either the rising or falling edge is programmed in TC3SEL<TC3IVN> as the INTTC3 interrupt generation
edge. Typically, program TC3SEL<TC3INV> = 0 when the first capture is performed at the falling edge, and
TC3SEL<TC3INV> = 1 when performed at the rising edge.
- When TC3SEL<TC3INV> = 0
When the falling edge of the TC3 input is detected after the timer starts, the up-counter value is
captured into TC3DRB. Hereafter, whenever the rising edge is detected, the up-counter value is captured into TC3DRA and the INTTC3 interrupt request is generated. The up-counter is cleared at this
time. Generally, read TC3DRB and TC3DRA during INTTC3 interrupt processing. After the upcounter is cleared, counting is continued and the next up-counter value is captured into TC3DRB.
When the rising edge is detected immediately after the timer starts, the up-counter value is captured into TCDRA only, but not into TC3DRB. The INTTC3 interrupt request is generated. When
the read instruction is executed to TC3DRB at this time, the value at the completion of the last capture (FF immediately after a reset) is read.
- When TC3SEL<TC3INV> = 1
When the rising edge of the TC3 input is detected after the timer starts, the up-counter value is captured into TC3DRB. Hereafter, whenever the falling edge is detected, the up-counter value is captured into TC3DRA and the INTTC3 interrupt request is generated. The up-counter is cleared at this
time. Generally, read TC3DRB and TC3DRA during INTTC3 interrupt processing. After the upcounter is cleared, counting is continued and the next up-counter value is captured into TC3DRB.
When the falling edge is detected immediately after the timer starts, the up-counter value is captured into TC3DRA only, but not into TC3DRB. The INTTC3 interrupt request is generated. When
the read instruction is executed to TC3DRB at this time, the value at the completion of the last capture (FF immediately after a reset) is read.
Table 10-3 Trigger Edge Programmed in TC3SEL<TC3INV>
TC3SEL<TC3INV>
Capture into TC3DRB
Capture into TC3DRA
INTTC3 Interrupt Request
0
Falling edge
Rising edge
1
Rising edge
Falling edge
The minimum input pulse width must be larger than one cycle width of the source clock programmed in
TC3CR<TC3CK>.
The INTTC3 interrupt request is generated if the up-counter overflow (FFH) occurs during capture operation
before the edge is detected. TC3DRA is set to FFH and the up-counter is cleared. Counting is continued by the
up-counter, but capture operation and overflow detection are stopped until TC3DRA is read. Generally, read
TC3DRB first because capture operation and overflow detection resume by reading TC3DRA.
Page 95
10. 8-Bit TimerCounter 3 (TC3)
10.1 Configuration
TMP86CH72FG
Timer start
TC3CR<TC3S>
Source
clock
0
Counter
1
i
i-1
i+1
k-1
1
k 0
m-1
m
m+1
n-1 n 0
2
1
3
FE FF 0
1
2
3
TC3 pin input
Internal waveform
Capture
Capture
n
k
TC3DRA
TC3DRB
FF (Overflow)
Capture
Capture
i
Capture
m
FE
Overflow
INTTC3
interrupt request
Read of TC3DRA
a) TC3SEL<TC3INV>=0
Timer start
TC3CR<TC3S>
Source
clock
Counter
0
1
i-1
i
0
1
k-1
k-1
k0
m-1 m 0 m+1
n-3
n-2
n-1
n 0
3
FE FF 0
1
2
3
TC3 pin input
Internal waveform
Capture
TC3DRA
Capture
m
i
TC3DRB
n
Capture
Capture
k
n-2
Capture
2
When TC3DRA is not read, capture operation and
overflow detection are stopped.
INTTC3
interrupt request
Read of TC3DRA
b) TC3SEL<TC3INV>=1
Figure 10-5 Capture Mode Timing Chart
Page 96
TMP86CH72FG
11. 8-Bit TimerCounter 4 (TC4)
11.1 Configuration
TC4S
fc/211 or fs/23
fc/27
fc/25
fc/23
fc/22
fc/2
fc
㪧㫆㫋㪼
(Note)
A
B
Source
C
Clock
Clear
D
E Y
Y
8-bit up-counter
F
G
Overflow detect
1
S
H
S
TC4 pin
Y
0
CMP
3
Match
detect
Timer F/F
TC4CK
Toggle
TC4S
0
TC4M
Clear
S
Y
2
TC4CR
1
PWM output
mode
TC4DR
INTTC4
interrupt
TC4S
PDO mode
Note: Function I/O may not operate depending on I/O port setting. For more details, see the chapter "I/O Port".
Figure 11-1 TimerCounter 4 (TC4)
Page 97
Port
(Note)
PWM4/
PDO4/
pin
11. 8-Bit TimerCounter 4 (TC4)
11.1 Configuration
TMP86CH72FG
11.2 TimerCounter Control
The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and timer registers 4 (TC4DR).
Timer Register and Control Register
TC4DR
(0018)
7
TC4CR
(0014)
7
TC4S
6
5
4
3
2
1
0
Read/Write (Initial value: 1111 1111)
6
5
4
3
TC4S
2
1
0
TC4CK
TC4M
Read/Write (Initial value: **00 0000)
0: Stop and counter clear
1: Start
TC4 start control
R/W
NORMAL1/2, IDLE1/2 mode
TC4CK
TC4 source clock select
[Hz]
TC4 operating mode
select
SLOW1/2,
SLEEP1/2
mode
DV7CK = 0
DV7CK = 1
000
fc/211
fs/23
DV9
fs/23
001
fc/27
fc/27
DV5
–
010
fc/25
fc/25
DV3
–
011
fc/23
fc/23
DV1
–
100
fc/22
fc/22
–
–
101
fc/2
fc/2
–
–
110
fc
fc
–
–
111
TC4M
Divider
R/W
External clock (TC4 pin input)
00: Timer/event counter mode
01: Reserved
10: Programmable divider output (PDO) mode
11: Pulse width modulation (PWM) output mode
R/W
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 2: To set the timer registers, the following relationship must be satisfied.
1 ≤ TC4DR ≤ 255
Note 3: To start timer operation (TC4S = 0 → 1) or disable timer operation (TC4S = 1→ 0), do not change the
TC4CR<TC4M, TC4CK> setting. During timer operation (TC4S = 1→ 1), do not change it, either. If the setting is
programmed during timer operation, counting is not performed correctly.
Note 4: The event counter and PWM output modes are used only in the NOMAL1/2 and IDLE1/2 modes.
Note 5: When the STOP mode is entered, the start control (TC4S) is cleared to “0” automatically.
Note 6: The bit 6 and 7 of TC4CR are read as a don’t care when these bits are read.
Note 7: In the timer, event counter and PDO modes, do not change the TC4DR setting when the timer is running.
Note 8: When the high-frequency clock fc exceeds 10 MHz, do not select the source clock of TC4CK = 110.
Note 9: The operating clock fs can not be used in NORMAL1 or IDEL1 mode (when low-frequency oscillation is stopped.)
Note 10:For available source clocks depending on the operation mode, refer to the following table.
TC4CK
Timer Mode
Event Counter Mode
PDO Mode
PWM Mode
000
O
−
O
−
001
O
−
O
−
010
O
−
O
−
011
O
−
−
O
100
−
−
−
O
101
−
−
−
O
110
−
−
−
O
111
−
O
−
×
Note: O : Available source clock
Page 98
TMP86CH72FG
11.3 Function
TimerCounter 4 has four types of operating modes: timer, event counter, programmable divider output (PDO), and
pulse width modulation (PWM) output modes.
11.3.1 Timer Mode
In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter
and the TC4DR value is detected, an INTTC4 interrupt is generated and the up-counter is cleared. After being
cleared, the up-counter restarts counting.
Table 11-1 Source Clock for TimerCounter 4 (Example: fc = 16 MHz, fs = 32.768 kHz)
NORMAL1/2, IDLE1/2 Mode
TC4CK
DV7CK = 0
SLOW1/2, SLEEP1/2
Mode
DV7CK = 1
Resolution
[µs]
Maximum Time Setting
[ms]
Resolution
[µs]
Maximum Time Setting
[ms]
Resolution
[µs]
Maximum
Time
Setting
[ms]
000
128.0
32.6
244.14
62.2
244.14
62.2
001
8.0
2.0
8.0
2.0
–
–
010
2.0
0.510
2.0
0.510
–
–
011
0.5
0.128
0.5
0.128
–
–
Page 99
11. 8-Bit TimerCounter 4 (TC4)
11.1 Configuration
TMP86CH72FG
11.3.2 Event Counter Mode
In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC4 pin.
When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated
and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC4
pin. Since a match is detected at the falling edge of the input pulse to the TC4 pin, the INTTC4 interrupt
request is generated at the falling edge immediately after the up-counter reaches the value set in TC4DR.
The minimum pulse width applied to the TC4 pin are shown in Table 11-2. The pulse width larger than two
machine cycles is required for high- and low-going pulses.
Note:The event counter mode can not used in the SLOW1/2 and SLEEP1/2 modes since the external clock is not
supplied in these modes.
Table 11-2 External Source Clock for TimerCounter 4
Minimum Pulse Width
NORMAL1/2, IDLE1/2 mode
High-going
23/fc
Low-going
23/fc
Page 100
TMP86CH72FG
11.3.3 Programmable Divider Output (PDO) Mode
The programmable divider output (PDO) mode is used to generated a pulse with a 50% duty cycle by counting with the internal clock.
When a match between the up-counter and the TC4DR value is detected, the logic level output from the
PDO4 pin is switched to the opposite state and INTTC4 interrupt request is generated. The up-counter is
cleared at this time and then counting is continued. When a match between the up-counter and the TC4DR
value is detected, the logic level output from the PDO4 pin is switched to the opposite state again and INTTC4
interrupt request is generated. The up-counter is cleared at this time, and then counting and PDO are continued.
When the timer is stopped, the PDO4 pin is high. Therefore, if the timer is stopped when the PDO4 pin is
low, the duty pulse may be shorter than the programmed value.
Example :Generating 1024 Hz pulse (fc = 16.0 Mhz)
LD
(TC4CR), 00000110B
: Sets the PDO mode. (TC4M = 10, TC4CK = 001)
LD
(TC4DR), 3DH
: 1/1024 ÷ 27/fc ÷ 2 (half cycle period) = 3DH
LD
(TC4CR), 00100110B
: Start TC4
Internal clock
Counter
TC4DR
0
1
2
n 0
1
2
n 0
1
2
n 0
n
Match detect
Timer F/F
PDO4 pin
INTTC4 interrupt
request
Figure 11-2 PDO Mode Timing Chart
Page 101
1
2
n 0
1
11. 8-Bit TimerCounter 4 (TC4)
11.1 Configuration
TMP86CH72FG
11.3.4 Pulse Width Modulation (PWM) Output Mode
The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of resolution by an internal clock.
When a match between the up-counter and the TC4DR value is detected, the logic level output from the
PWM4 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM4
pin becomes high. The INTTC4 interrupt request is generated at this time.
When the timer is stopped, the PWM4 pin is high. Therefore, if the timer is stopped when the PWM4 pin is
low, one PMW cycle may be shorter than the programmed value.
TC4DR is serially connected to the shift register. If TC4DR is programmed during PWM output, the data set
to TC4DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically.
For the first time, the data written to TC4DR is shifted when the timer is started by setting TC4CR<TC4S> to
1.
Note 1: The PWM output mode can be used only in the NORMAL1/2 and IDEL 1/2 modes.
Note 2: In the PWM output mode, program TC4DR immediately after the INTTC4 interrupt request is generated
(typically in the INTTC4 interrupt service routine.) When the programming of TC4DR and the INTTC4 interrupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different
from the programmed value until the next INTTC4 interrupt request is issued.
TC4CR<TC4S>
Internal clock
Counter
0
n
1
n+1
FF
0
1
n
TC4DR
n
?
0
1
m
Rewrite
m
p
Data shift
Data shift
Shift register
FF
Rewrite
Rewrite
?
n+1
Data shift
m
n
Match detect
Match detect
Match detect
Timer F/F
PWM4 pin
n
n
m
INTTC4
interrupt request
PWM cycle
Figure 11-3 PWM output Mode Timing Chart (TC4)
Page 102
TMP86CH72FG
Table 11-3 PWM Mode (Example: fc = 16 MHz)
NORMAL1/2, IDLE1/2 Mode
TC4CK
DV7CK = 0
DV7CK = 1
Resolution
[ns]
Cycle
[µs]
Resolution
[ns]
Cycle
[µs]
000
–
–
–
–
001
–
–
–
–
010
–
–
–
–
011
500
128
500
128
100
250
64
250
64
101
125
32
125
32
110
–
–
–
–
Page 103
11. 8-Bit TimerCounter 4 (TC4)
11.1 Configuration
TMP86CH72FG
Page 104
TMP86CH72FG
12. Synchronous Serial Interface (SIO)
The TMP86CH72FG contain one SIO (synchronous serial interface) channel. It is connected to external
devices via the SI, SO and SCK pins. The SI pin is used also as the P14 pin, the SO pin is used also as the P15 pin,
and the SCK pin is used also as the P16 pin. The CS pin is used also as the P17 pin, CS pin can be used as a chip
selection function (at external clock input mode). Using these pins for serial interfacing requires setting the output
latches of the each port to “1”.
SIO Functions.
• Transfer mode (8 bit)
• Receive mode (8 bit)
• Transfer/Receive mode (8 bit)
• Internal /External clock selection
• 32 bytes Buffer conbining Transfer and Receive
Table 12-1 lists the SIO1 register addresses.
Table 12-1 Control Registers
SIO1
Register name
Address
SIO control register 1
SIOCR1
0019H
SIO control register 2
SIOCR2
001AH
SIO status register
SIOSR
001BH
SIO data buffer
SIOBUF
001CH
12.1 Configuration
SIO buffer
SCK
13
5
A
fc/28
B
fc/26
C
fc/25
D
fc/24
E
fc/23
F
fc/22
G
fc/2 or fs/2
External clock
SIOCR1
SIOSR
SIOCR2
Buffer
control
Transmit shift register
SO pin
serial data output
SI pin
serial data input
Shift
clock
Control circuit
Y
MSB/LSB
selection
H
Receive shift register
SCK pin
serial clock
input/output
Chihp select
CSEN
TC3SBI
control circuit
Noise canceller
INTSIO
interrupt
Figure 12-1 Configuration of the Serial Interface
Page 105
CS pin
Chip select
input
12. Synchronous Serial Interface (SIO)
12.2 Control
TMP86CH72FG
12.2 Control
SIO is controlled using Serial Interface Control Register 1 (SIOCR1) and Serial Interface Control Register 2
(SIOCR2). The operating status of the serial interface can be determined by reading the Serial Interface Status Register (SIOSR).
Serial Interface Control Register 1
SIOCR1
(0019H)
7
6
5
SIOS
SIONH
4
SIOM
SIOS
SIOINH
SIOM
SIODIR
3
2
SIODIR
1
0
SCK
(Initial value: 0000 0000)
Start/Stop a transfer.
0: Stop
1: Start
Continue/Abort a transfer (Note 1)
0: Continue transfer.
1: Abort transfer (automatically cleared after abort).
Select transfer mode.
00: Transmit mode
01: Receive mode
10: Transmit/receive mode
11: Reserved
Select direction of transfer
0: MSB (transfer beginning with bit 7)
1: LSB (transfer beginning with bit 0)
NORMAL1/2, IDLE1/2 mode
SCK
Select a serial clock.
(Note 2)
SLOW1/2,
SLEEP1/2
mode
DV7CK = 0
DV7CK = 1
Source
clock
000
fc/213
fs/25
DV11
fs/25
001
fc/28
fc/28
DV6
–
010
fc/26
fc/26
DV4
–
011
fc/2
5
5
DV3
–
100
fc/24
fc/24
DV2
–
101
fc/2
3
fc/2
3
DV1
–
110
fc/2
2
fc/2
2
2
–
111
External clock
(supplied from
the SCK pin)
fc/2
External clock
(supplied from
the SCK pin)
fc/2
–
R/W
–
Note 1: If SIOCR1<SIOINH> is set, SIOCR1<SIOS>, SIOSR<SIOF>, SIOSR<SEF>, SIOSR<TXF>, SIOSR<RXF>,
SIOSR<TXERR>, and SIOSR<RXERR> are initialized.
Note 2: When selecting a serial clock, do not make such a setting that the serial clock rate will exceed 1 Mbps.
Note 3: Before setting SIOCR1<SIOS> to “1” or setting SIOCR1<SIOM>, SIOCR1<SIODIR>, or SIOCR1<SCK> to any value,
make sure the SIO is idle (SIOSR<SIOF> = “0”).
Note 4: Reserved: Setting prohibited
Page 106
TMP86CH72FG
Serial Interface Control Register 2
SIOCR2
(001AH)
7
6
5
“0”
“0”
“0”
SIORXD
4
3
2
1
0
SIORXD
Set the number of data bytes to
transmit/receive.
(Initial value: ***0 0000)
00H: 1-byte transfer
01H: 2-byte transfer
02H: 3-byte transfer
03H: 4-byte transfer
:
1FH: 32-byte transfer
R/W
Note 1: Before setting the number of data bytes to transfer, make sure the SIO is idle (SIOSR<SIOF> = “0”).
Note 2: The number of data bytes to transfer is used for transmit and receive operations in common.
Note 3: Always write “0” to bits 7 to 5.
Serial Interface Status Register
SIOSR
(001BH)
7
6
5
4
3
2
SIOF
SEF
TXF
RXF
TXERR
RXERR
1
0
(Initial value: 0010 00**)
SIOF
Monitor the operating status of
serial transfer.
0: Transfer ended (Note1)
1: Transfer in process
SEF
Shift operation status flag
0: Shift ended
1: Shift in process
TXF
Transmit buffer flag
0: The transmit buffer contains data.
1: The transmit buffer contains no data.
Receive buffer flag
0: The receive buffer contains no data.
1: As many data bytes specified in SIORXD have been received.
(The flag is reset to “0” when as many data bytes as specified in SIORXD have
been read.)
TXERR
Transmit error flag (Note2)
0: Transmit operation was normal.
1: Error occurred during transmission.
RXERR
Receive error flag (Note2)
0: Receive operation was normal.
1: Error occurred during reception.
RXF
Read
only
Note 1: The SIOSR<SIOF> bit is cleared to “0” by clearing SIOCR1<SIOS> to stop transferring or by setting SIOCR1<SIOINH> to
“1” to abort transfer.
Note 2: Neither the SIOSR<TXERR> nor SIOSR<RXERR> bit can be cleared when transfer ends on SIOCR1<SIOS> = “0”. To
clear them, set SIOCR1<SIOINH> to “1”
Note 3: Do not write to the SIOSR register.
Serial Interface Data Buffer
SIOBUF
(001CH)
7
6
5
4
3
2
1
0
(Initial value: **** ****)
SIOBUF
Transmit/receive data buffer
Transmit data are set, or received data are stored.
R/W
Note 1: Setting SIOCR1<SIOINH> causes the contents of SIOBUF to be lost.
Note 2: When setting transmit data or storing received data, be sure to handle as many bytes as specified in SIOCR2<SIORXD>
at a time.
Page 107
12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
12.3 Function
12.3.1 Serial clock
12.3.1.1 Clock source
One of the following clocks can be selected using SIOCR1<SCK>.
(1)
Internal clock
A clock having the frequency selected with SIOCR1<SCK> (except for “111”) is used as the serial
clock. The SCK pin output goes high when transfer starts or ends.
Table 12-2 Serial Clock Rate
Baud Rate
SCK
Clock
fc = 16 MHz
fc = 8 MHz
000
fc/213
1.91 Kbps
0.95 Kbps
001
fc/28
61.04 Kbps
30.51 Kbps
010
fc/26
244.14 Kbps
122.07 Kbps
011
fc/25
488.28 Kbps
244.14 Kbps
100
fc/24
976.56 Kbps
488.28 Kbps
101
fc/23
–
976.56 Kbps
110
fc/22
–
–
111
External
External
External
(1 Kbit = 1,024 bit)
(2)
External clock
Setting SIOCR1<SCK> to “111” causes an external clock to be selected. A clock supplied to the
SCK pin is used as the serial clock.
For a shift operation to be performed securely, both the high and low levels of the serial clock pulse
must be at least 4/fc. If fc = 8 MHz, therefore, the maximum available transfer rate is 976.56 Kbps.
SCK pin input
tSCKL
tSCKL, tSCKH
tSCKL, tSCKH
tSCKH
2.5/fc (High-frequency clock mode
2.5/fs (Low-frequency clock mode)
Figure 12-2 External Clock
Page 108
TMP86CH72FG
12.3.1.2 Shift edges
The SIO uses leading-edge shift for transmission and trailing-edge shift for reception.
(1)
Leading-edge shift
Data are shifted on each leading edge of the serial clock pulse (falling edge of the SCK pin input/
output).
(2)
Trailing-edge shift
Data are shifted on each trailing edge of the serial clock pulse (rising edge of the SCK pin input/
output).
SCK pin
SO pin
Shift register
Bit 7
Bit 6
Bit 5
Bit 4
*******7
******76
*****765
****7654
Bit 3
Bit 2
Bit 1
Bit 0
***76543 **765432 *7654321 76543210
(a) Leading-edge shift
SCK pin
SI pin
Shift register
Bit 7
Bit 6
*******7
Bit 5
******76
Bit 4
*****765
Bit 3
Bit 1
Bit 0
****7654 ***76543 **765432 *7654321 76543210
(b) Trailing-edge shift
Figure 12-3 Shift Edges
Page 109
Bit 2
12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
12.3.2 Transfer bit direction
The direction in which 8-bit serial data are transferred can be selected using SIOCR1<SIODIR>. The direction of data transfer applies in common to both transmission and reception, and cannot be set individually.
12.3.2.1 MSB transfer
MSB transfer is assumed by clearing SIOCR1<SIODIR> to “0”. In MSB transfer, data are transferred
sequentially beginning with the most significant bit (MSB). As for received data, the first data bit to
receive is stored as the MSB.
12.3.2.2 LSB transfer
LSB transfer is assumed by setting SIOCR1<SIODIR> to “1”. In LSB transfer, data are transferred
sequentially beginning with the least significant bit (LSB). As for received data, the first data bit to
receive is stored as the LSB.
SCK pin
SCK pin
SO pin
A7
Transmitdata write
A
A6
A5
A4
A3
A2
A1
A0
SI pin
A7
A6
A5
A4
A3
A2
A1
A0
Receiveddata store
A
(a) MSB transfer (when SIODIR = "0"
SCK pin
SCK pin
SO pin
A0
Transmitdata write
A
A1
A2
A3
A4
A5
A6
A7
SI pin
A0
A1
A2
A3
A4
A5
A6
Receiveddata store
(b) LSB transfer (when SIODIR = "1"
Figure 12-4 Transfer Bit Direction
12.3.3 Transfer modes
SIOCR1<SIOM> is used to select a transfer mode (transmit, receive, or transmit/receive mode).
12.3.3.1 Transmit mode
Transmit mode is assumed by setting SIOCR1<SIOM> to “00”.
(1)
Causing the SIO to start transmitting
1. Set the transmit mode, serial clock rate, and transfer direction, respectively, in
SIOCR1<SIOM>, SIOCR1<SCK>, and SIOCR1<SIODIR>.
2. Set the number of data bytes to transfer in SIOCR2<SIORXD>.
3. Set, in SIOBUF, as many transmit data bytes as specified in SIOCR2<SIORXD>.
Page 110
A7
A
TMP86CH72FG
4. SIOCR1<SIOS> to “1”.
If the selected serial clock is an internal clock, the SIO immediately starts transmitting data
sequentially in the direction selected using SIOCR1<SIODIR>.
If the selected serial clock is an external clock, the SIO immediately starts transmitting
data, upon external clock input, sequentially in the direction selected using
SIOCR1<SIODIR>.
(2)
Causing the SIO to stop transferring
1. When as many data bytes as specified in SIOCR2<SIORXD> have been transmitted, be
sure to clear SIOCR1<SIOS> to “0” to halt the SIO. Clearing of SIOCR1<SIOS> should be
executed within the INTSIO service routine or should be executed after confirmation of
SIOSR<TXF> = “1”. Before starting to transfer the next data, make sure SIOSR<SIOF> =
“0” and SIOSR<TXERR>= “0”, write the data to be transferred, and then set
SIOCR1<SIOS> = “1”.
Last byte
Second last byte
SCK pin
SO pin
SIOS
A0
B7
B6
B5
B4
B3
B2
B1
B0
SIOS = "0" causes the SIO to stop transferring.
SIOF
SEF
TXF
INTSIO
INTSIO is accepted.
TSODH (16.5/fc to 32.5/fc)
6.5 TSCK + TSODH
Figure 12-5 Time from INTSIO Occurrence to Transfer End (SIOSR<SIOF> = “0”) when the
SIO is Directed to Stop Transferring (SIOCR1<SIOS> = “0”) upon the Occurrence of a Transmit Interrupt
Note 1: Be sure to write as many bytes as specified in SIOCR2<SIORXD> to SIOBUF. If the number of
data bytes to be written to SIOBUF is not equal to the value specified in SIOCR2<SIORXD>, the
SIO fails to work normally.
Note 2: Before starting the SIO, be sure to write as many data bytes as specified in SIOCR2<SIORXD>
to SIOBUF.
Note 3: In the transmit mode, an INTSIO interrupt occurs when the transmission of the second bit of the
last byte begins.
Note 4: If an attempt is made to write SIOCR1<SIOS> = “0” within the INTSIO interrupt service routine,
the SIO stops transferring (SIOSR<SIOF> = “0”) after the last data byte is transmitted (the signal
at the SCK pin rises).
Note 5: Be sure to write to SIOBUF in the condition SIO stop status (SIOSR<SIOF>="0"). If write to
SIOBUF during SIO working status (SIOSR<SIOF>="1"), the SIO fails to work normally.
Page 111
12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
SIOS
SCK pin
SIOF
Last bit of transmit data
SO pin
TSODH
If transmission is completed after SIOS is cleared
16.5/fc
TSODH
32.5/fc
fc: High-frequency clock [Hz]
Figure 12-6 Last-Bit Hold Time
• Setting SIOCR1<SIOINH> to “1” causes the SIO to immediately stop a transmission
sequence even if any byte is being transmitted.
SIOS = "0" causes the SIO to stop transferring.
SIOS
SIOF
SEF
SCK pin
A7 A6
SO pin
C0 D7 D6 D5 D4 D3 D2 D1 D0
TXF
INTSIO
Clearing SIOS within the interrupt service routine
Figure 12-7 SIOCR1<SIOS> Clear Timing
12.3.3.2 Transmit error
During operation on an external clock, the following case may be detected as a transmit error, causing
the transmit error flag (SIOSR<TXERR>) to be set to “1”. If a transmit error occurs, the SO pin goes high.
• If the SCK pin goes low when the SIO is running (SIOSR<SIOF> = “1”) but there is no transmit
data in SIOBUF (SIOSR<TXF> = “1”).
If a transmit error is detected, be sure to set SIOCR1<SIOINH> to “1” to force the SIO to halt. Setting
SIOCR1<SIOINH> to “1” initializes the SIOCR1<SIOS> and SIOSR registers; no other registers or bits
are initialized.
Page 112
TMP86CH72FG
Example :Example of setting the transmit mode (transmit mode, external clock, and 32-byte transfer)
Port setting
(It is necessary to set P15 as SOpin by port setting.
LD
LD
(INTSEL),*0******B
; INTSIO Select
LDW
(EIRL), ******1********0B
; Enables INTSIO (EF9).
EI
START:
)
; IMF ← 0
DI
WAIT:
(TC3SBI),**0*****B
; Enables interrupts.
LD
(SIOCR1), 01******B
; Initializes the SIO (forces the SIO halt).
TEST
(SIOSR). 7
; Checks to see if the SIO has halted (SIOF = 0).
JRS
F, WAIT
; Jumps to START if the SIO is already at a halt.
LD
(SIOCR1), 00000111B
; Sets the transmit mode, selects the direction of transfer,
and sets a serial clock.
LD
(SIOCR2), 00011111B
; Sets the number of bytes (32 bytes) to transfer.
:
Transmit data setting
:
LD
(SIOCR1), 10000111B
; Directs the SIO to start transferring.
LD
(SIOCR1), 00000111B
; Directs the SIO to stop transferring.
TEST
(SIOSR). 3
; Checks TXERR.
JRS
T, NOERR
LD
(SIOCR1), 01000111B
INTSIO
(INTSIO service routine):
; Forces the SIO to halt (clears TXERR).
:
Error handling
:
NOERR:
END:
; End of transfer
Page 113
12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
External SCK input
External SCK input
Last-byte transfer
SCK pin
SO pin
A7 A6 A5 A4 A3 A2 A1 A0 B7 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
SIOS = "0" causes the SIO
to stop transferring
SIOS = "1" causes the SIO
to start transferring.
SIOS = "1" causes the SIO
to start transferring.
SIOS
SIOF
SEF
TXF
Transmit data
are written.
Transmit-data write
INTSIO is accepted.
(In the interrupt service
routine, clear SIOS to "0"
and check the TXERR flag.)
INTSIO
TXERR
After confirmation of SIOF
= "0", set the transfer data
to SIOBUF.
After confirmation of SIOF = "0", set
SIOCR1 and SIOCR2 and then write
the transmit data to SIOBUF.
Figure 12-8 Transmit Mode Operation
(where 3 bytes are transferred on an external source clock)
Last byte
Second last byte
More pulses than a specified
number of bytes occur.
SCK pin
SO pin
A0
B7
B6
B5
B4
B3
B2
B1
B0
SIOS = "0" causes the
SIO to stop transferring.
SIOS
SIOF
SEF
TXF
INTSIO is accepted.
SIOINH = "1" causes the flag to be
cleared and forces the SIO to halt
(be initialized).
INTSIO
TXERR
The SIO is forced to halt because of
SIOS = "0" and TXERR occurrence
(SIOINH = "1").
Figure 12-9 Occurrence of Transmit Error (where, before the SIO is directed to stop transferring (SIOCR1<SIOS> = “0” is written), the transfer of the last byte is completed and more
pulses than a specified number of bytes occur)
Note: When the SIO is running (SIOSR<SIOF> = “1”), do not supply more transfer clock pulses than the number of bytes specified in SIOCR2<SIORXD> to the SCK pin.
Page 114
TMP86CH72FG
12.3.3.3 Receive mode
Receive mode is assumed by setting SIOCR1<SIOM> to “01”.
(1)
Causing the SIO to start receiving
1. Set the receive mode, serial clock rate, and transfer direction, respectively, in
SIOCR1<SIOM>, SIOCR1<SCK>, and SIOCR1<SIODIR>.
2. Set the number of data bytes to transfer in SIOCR2<SIORXD>.
3. Set SIOCR1<SIOS> to “1”.
If the selected serial clock is an internal clock, the SIO immediately starts receiving data
sequentially in the direction selected using SIOCR1<SIODIR>.
If the selected serial clock is an external clock, the SIO immediately starts receiving data,
upon external clock input, sequentially in the direction selected using SIOCR1<SIODIR>.
(2)
Causing the SIO to stop receiving
1. When as many data bytes as specified in SIOCR2<SIORXD> have been received, be sure
to clear SIOCR1<SIOS> to “0” to halt the SIO. Clearing of SIOCR1<SIOS> should be executed within the INTSIO service routine or should be executed after confirmation of
SIOSR<RXF> = “1”.
Setting SIOCR1<SIOINH> to “1” causes the SIO to immediately stop a reception
sequence even if any byte is being received.
(3)
Received-data read timing
Before reading received data, be sure to make sure SIOBUF is full (SIOSR<RXF> = “1”) or clear
SIOCR1<SIOS> to “0” to halt the SIO in the INTSIO interrupt service routine.
To read the received data after SIOCR1<SIOS> to “0”, make sure SIOSR<SIOF> = “0” and
SIOSR<RXERR> = “0”. SIOSR<RXF> is cleared to “0” when as many received data bytes as specified in SIOCR2<SIORXD> are read.
To transfer the next data after SIOCR1<SIOS> to “0”, first read the received data, make sure
SIOSR<SIOF> = “0”, and set SIOCR1<SIOS> = “1” to start receiving data.
Note 1: Be sure to read, from SIOBUF, as many received data bytes as specified in SIOCR2<SIORXD>.
If the number of data bytes to be read from SIOBUF is not equal to the value specified in
SIOCR2<SIORXD>, the SIO fails to work normally.
Note 2: If an attempt is made to read data before the end of reception (SIOSR<RXF> = “0”), the SIO
fails to work normally.
Note 3: In the receive mode, an INTSIO interrupt occurs when the reception of the last bit of the last
data byte is completed.
Note 4: If an attempt is made to start transferring after a receive error has been detected, the SIO fails to
work normally. Before starting transferring, set SIOCR1<SIOINH> = “1” to force the SIO to halt.
Page 115
12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
SIOS = "0" causes the SIO
to stop transferring.
SIOS
SIOF
SEF
SCK pin
SI pin
A7
C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0
RXF
All data bytes
have been
read from
SIOBUF.
INTSIO
Clearing SIOS within the interrupt service routine
Figure 12-10 SIOCR1<SIOS> Clear Timing
12.3.3.4 Receive error
During operation on an external clock, the following case is detected as a receive error, causing the
receive error flag (SIOSR<RXERR>) to be set to “1”. If a receive error occurs, discard all data from the
receive buffer.
• If the reception of the next data byte ends with SIOBUF full (SIOSR<RXF> = “1”) (if eight clock
pulses are supplied to the SCK pin)
If a receive error is detected, be sure to set SIOCR1<SIOINH> to “1” to force the SIO to halt. Setting
SIOCR1<SIOINH> to “1” initializes the SIOCR1<SIOS> and SIOSR registers; no other registers or bits
are initialized.
Note: When the SIO is running on an external clock, it becomes impossible to read the content of the receive
data buffer (SIOBUF) correctly if the SCK pin goes low before as many data bytes as specified in
SIOCR2<SIORXD> are read.
A receive error flag (SIOSR<RXF>) can be set only after eight clock pulses are input upon completion
of reception. If only one to seven transfer clock pulses (including noise) are input to the SCK pin, therefore, it becomes impossible to determine whether the pulses at the pin are those unnecessary. So, it is
recommended that the system employ a backup method such as checksum-based verification.
Before restarting reception, be sure to force the SIO to halt (SIOCR1<SIOINH> = “1”).
Page 116
TMP86CH72FG
Example :Example of setting the receive mode (receive mode, external clock, and 32-byte transfer)
Port setting
(It is necessary to set P15 as SOpin by port setting.
LD
)
; IMF ← 0
DI
LD
(INTSEL),*0******B
; INTSIO Select
LDW
(EIRL), ******1********0B
; Enables INTSIO (EF9)
EI
WAIT:
(TC3SBI),**0*****B
; Enables interrupts.
LD
(SIOCR1), 01******B
; Initializes the SIO (Forces the SIO halt).
TEST
(SIOSR). 7
; Checks to see if the SIO has halted (SIOF = 0).
JRS
F, WAIT
; Jumps to START if the SIO is already at a halt.
LD
(SIOCR1), 00010111B
; Sets the receive mode, selects the direction of transfer,
and sets a serial clock.
LD
(SIOCR2), 00011111B
; Sets the number of bytes to transfer.
LD
(SIOCR1), 10010111B
; Directs the SIO to start transferring.
LD
(SIOCR1), 00010111B
; Directs the SIO to stop transferring.
START:
INTSIO (INTSIO
service routine):
:
Receive data reading
Checks a checksum or the
like to see if the received
data are normal.
:
LD
(SIOCR1), 01010111B
END:
; Forces the SIO to halt.
; End of transfer
External SCK input
Last-byte transfer
External SCK input
SCK pin
SI pin
SIOS
A7 A6 A0 B7 B6 B5 B4 B3 B2 B1 B0
C7 C6 C5 C4 C3 C
SIOS = "0" causes the SIO
to stop transferring.
SIOS = "1" causes the SIO
to start transferring.
SIOS = "1" causes the SIO
to start transferring.
SIOF
SEF
All data have been
read from SIOBUF.
RXF
INTSIO is accepted.
(In the interrupt service routine, clear
SIOS to "0" and read data from SIOBUF,
check a checksum or the like to see if
the received data are normal, and sets
SIOINH = "1".)
INTSIO
RXERR
Confirm
SIOF = "0".
After confirmation of SIOF = "0",
set SIOCR1 and SIOCR2.
Figure 12-11 Receive Mode Operation
(where 2 bytes are transferred on an external source clock)
Page 117
12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
External SCK input
Last-byte transfer
SCK pin
SI pin
A7 A6 A0 B7 B6 B5 B4 B3 B2 B1 B0
SIOS = "0" causes the SIO
to stop transferring.
SIOS = "1" causes the SIO
to start transferring.
SIOS
SIOF
SEF
RXF
INTSIO is accepted.
(In the interrupt service routine, clear SIOS to
"0" and read data from SIOBUF, check a
checksum or the like to see if the received data
are normal, and sets SIOINH = "1".)
INTSIO
SIOINH = "1" causes the
flag to be cleared and
forces the SIO to halt (be
initialized).
RXERR
After confirmation of SIOF = "0"
set SIOCR1 and SIOCR2.
Figure 12-12 Occurrence of Receive Error
(2 bytes are transferred on an external source clock)
Note 1: When the SIO is running (SIOSR<SIOF> = “1”), do not supply more transfer clock pulses than the
number of bytes specified in SIOCR2<SIORXD> at SCK pin.
Note 2: After data reception is completed, a receive error occurs if eight clock pulses are supplied to the SCK
pin before a direction to stop the SIO becomes valid (SIOCR1<SIOS> = “0”). Figure 12-8 shows a
case in which a receive error occurs when eight clock pulses are supplied to the SCK pin before the
INTSIO interrupt service routine writes SIOCR1<SIOS> = “0”.
12.3.3.5 Transmit/receive mode
Transmit/receive mode is assumed by setting SIOCR1<SIOM> to “10”.
(1)
Causing the SIO to start transmitting/receiving
1. Set the transmit/receive mode, serial clock rate, and transfer direction, respectively, in
SIOCR1<SIOM>, SIOCR1<SCK>, and SIOCR1<SIODIR>.
2. Set the number of data bytes to transfer in SIOCR2<SIORXD>.
3. Set, in SIOBUF, as many transmit data bytes as specified in SIOCR2<SIORXD>.
4. Set SIOCR1<SIOS> to “1”.
If the selected serial clock is an internal clock, the SIO immediately starts transmitting/
receiving data sequentially in the direction selected using SIOCR1<SIODIR>.
If the selected serial clock is an external clock, the SIO starts transmitting/receiving data,
in synchronization with a clock input to the SCK pin sequentially in the direction selected
using SIOCR1<SIODIR>.
Note 1: SIOCR2<SIORXD>, SIOCR1<SIODIR>, and SIOCR1<SCK> are used in common to both
transmission and reception. They cannot be set individually.
Note 2: Transmit data are output in synchronization with the falling edge of a signal at the SCK pin. The
data are received in synchronization with the rising edge of a signal at the SCK pin.
Page 118
TMP86CH72FG
(2)
Causing the SIO to stop transmitting/receiving
1. When as many data bytes as specified in SIOCR2<SIORXD> have been transmitted and
received, be sure to clear SIOCR1<SIOS> to “0” to halt the SIO. Clearing of
SIOCR1<SIOS> should be executed within the INTSIO service routine or should be executed after confirmation of SIOSR<RXF> = “1”.
Setting SIOCR1<SIOINH> to “1” causes the SIO to immediately stop the transmission/
reception sequence even if any byte is being transmitted or received.
(3)
Received-data read and transmit-data set timing
After as many bytes as specified in SIOCR2<SIORXD> have been transmitted and received, reading the received data and writing the next transmit data should be executed after confirmation of
SIOSR<RXF> = “1” or should be executed after SIOCR1<SIOS> is cleared to “0” in the INTSIO
interrupt service routine. To re-start transferring the next data after SIOCR1<SIOS> to “0”, first
make sure SIOSR<SIOF> = “0”, SIOSR<TXERR> = “0” and SIOSR<RXERR> = “0”, and read the
received data, and then write the transmit data and set SIOCR1<SIOS> = “1” to start transferring.
Note 1: An INTSIO interrupt occurs when the last bit of the last data byte is received.
Note 2: When writing to and reading from SIOBUF, make sure that the number of data bytes to transfer
is as specified in SIOCR2<SIORXD>. If the number is not equal to the value specified in
SIOCR2<SIORXD>, the SIO does not run normally.
Note 3: When as many data bytes as specified in SIOCR2<SIORXD> are read, SIOSR<RXF> is
cleared to “0”.
Note 4: In the transmit/receive mode, setting SIOCR1<SIOINH> to “1” to force the SIO to halt will cause
received data to be discarded.
Note 5: If a transfer sequence is started after a transmit or receive error has been detected, the SIO
does not run normally. Before starting transferring, set SIOCR1<SIOINH> = “1” to force the SIO
to halt.
SIOS = "0" causes
the SIO to stop
transferring.
SIOS
SIOF
SEF
SCK pin
SO pin
A7
C6 C 5 C4 C3 C 2 C1 C 0 C 5 D7 D 6 D5 D4 D 3 D2 D1
X7
X6 X 5 X4 X3 X 2 X1 X 0 X 5 W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0
D0
TXF
SI pin
All data bytes are
read from SIOBUF.
RXF
INTSIO
Figure 12-13 SIOCR1<SIOS> Clear Timing (Transmit/Receive Mode)
Page 119
12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
12.3.3.6 Transmit/receive error
During operation on an external clock, the following cases may be detected as a transmit or receive
error, causing an error flag (SIOSR<TXERR> or SIOSR<RXERR>) to be set. If an error occurs, the
transmit data go high.
• If the SCK pin goes low when the SIO is running (SIOSR<SIOF> = “1”) but there is no transmit
data in SIOBUF (SIOSR<TXF> = “1”).
• If the reception of the next data byte is completed when the SIO is running (SIOSR<SIOF> = “1”)
and SIOBUF is full (SIOSR<RXF> = “1”) (if eight clock pulses are supplied to the SCK pin)
(SIOSR<RXERR>)
If a transmit or receive error is detected, be sure to set SIOCR1<SIOINH> to “1” to force the SIO to
halt.
Note: When the SIO is running on an external clock, it becomes impossible to read the content of the receive
data buffer (SIOBUF) correctly if the SCK pin goes low before as many data bytes as specified in
SIOCR2<SIORXD> are read.
A receive error flag (SIOSR<RXF>) can be set only after eight clock pulses are input upon completion
of reception. If one to seven transfer clock pulses (including noise) are input to the SCK pin, therefore,
it becomes impossible to determine whether the pulses at the pin are those unnecessary. So, it is recommended that the system employ a backup method such as checksum-based verification.
Before restarting transmitting/receiving, be sure to force the SIO to halt (SIOCR1<SIOINH> = “1”).
Example :Example of setting the transmit/receive mode
(transmit/receive mode, external clock, and 32-byte transfer)
Port setting
(It is necessary to set P15 as SOpin by port setting.
LD
)
; IMF ← 0
DI
LD
(INTSEL),*0******B
; INTSIO Select
LDW
(EIRL), ******1********0B
; Enables INTSIO (EF9)
EI
WAIT:
(TC3SBI),**0*****B
; Enables interrupts.
LD
(SIOCR1), 01******B
; Initializes the SIO (forces the SIO halt).
TEST
(SIOSR). 7
; Checks to see if the SIO has halted (SIOF = 0).
JRS
F, WAIT
; Jumps to START if the SIO is already at a halt.
Page 120
TMP86CH72FG
Example :Example of setting the transmit/receive mode
(transmit/receive mode, external clock, and 32-byte transfer)
START:
LD
(SIOCR1), 00100111B
; Sets the transmit/receive mode, selects the direction of transfer,
and sets a serial clock.
LD
(SIOCR2), 00011111B
; Sets the number of bytes (32 bytes) to transfer.
Transmit data setting:
;
LD
(SIOCR1), 10100111B
; Starts transferring.
LD
(SIOCR1), 00100111B
; Directs the SIO to stop transferring.
TEST
(SIOSR). 3
; Checks TXERR.
JRS
T, TXNOERR
LD
(SIOCR1), 01100111B
INTSIO (INTSIO
service routine):
; Forces the SIO to halt (clears TXERR).
:
Error handling
:
JR
END
TXNOER:
:
Receive-data reading
Checks a checksum or the
like to see if the received
data are correct.
:
LD
END:
(SIOCR1), 01100111B
; Forces the SIO to halt.
; End of transfer
Page 121
12. Synchronous Serial Interface (SIO)
12.3 Function
TMP86CH72FG
External SCK input
Last-byte transfer
SCK pin
SO pin
A7 A6 A5 A4 A3 A2 A1 A0 B7 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
SI pin
D7 D6 D5 D4 D3 D2 D1 D0 E7 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0
SIOS = "1" causes the SIO
to start transferring.
SIOS
SIOS = "1" causes the SIO
to start transferring.
SIOS = "0" causes the SIO
to stop transferring.
SIOF
SEF
TXF
Transmit data
are written.
Transmit data are written.
All data have been
read from SIOBUF.
RXF
INTSIO is accepted.
(In the INTSIO service routine,
clear SIOS to "0" and check
the TXERR flag.)
INTSIO
TXERR
RXERR
After reading received data from SIOBUF,
check a checksum or the like to see if the
received data are correct. Clear SIOINH to "0"
to halt the SIO and then write the transmit data
to SIOBUF after confirmation of SIOF = "0".
After confirmation of SIOF = "0",
set SIOCR1 and SIOCR2 and then
write the transmit data to SIOBUF.
Figure 12-14 Transmit/Receive Mode Operation
(where 3 bytes are transferred on an external source clock)
Page 122
TMP86CH72FG
More clock pulses
than a specified
number of bytes
Last-byte transfer
Eighth clock pulse after a
specified number of bytes
are exceeded.
SCK pin
SO pin
A7 A6 A5 A4 A3 A2 A1 A0 B7 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
SI pin
D7 D6 D5 D4 D3 D2 D1 D0 E7 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0
SIOS = "0" causes the SIO
to stop transferring.
SIOS
SIOF
SEF
SIOINH = "1", the flag is
cleared, and the SIO is
forced to halt (be initialized).
TXF
RXF
INTSIO
INTSIO is accepted, a check is
made to see if SIOS = "0" and
on TXERR. Since TXERR has
occurred, the SIO is forced to
halt (SIOINH = "1")
TXERR
RXERR
Figure 12-15 Occurrence of Transmit/Receive Error
(3 bytes are transferred on an external source clock)
Note: When the SIO is running (SIOSR<SIOF> = “1”), do not supply more transfer clock pulses than the number of bytes specified in SIOCR2<SIORXD> to the SCK pin.
Page 123
12. Synchronous Serial Interface (SIO)
12.4 Chip selection function
TMP86CH72FG
12.4 Chip selection function
SIO is controlled using Serial Interfade Control Register 1(SIOCR1) and Serial Interface Control Register 2
(SIOCR2). The operating status of the serial interface can be determined by reading the Serial Interface Status Register (SIOSR).
9/fc or more
CS
SCK
SI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note: The internal SCK signal goes avilable after 9/fc[s] due to the Noise-cancellation function.
Figure 12-16 Chip selection function
Page 124
TMP86CH72FG
13. Asynchronous Serial interface (UART )
13.1 Configuration
UART control register 1
Transmit data buffer
UARTCR1
TDBUF
3
Receive data buffer
RDBUF
2
INTTXD
Receive control circuit
Transmit control circuit
2
Shift register
Shift register
Parity bit
Stop bit
Noise rejection
circuit
RXD
TXD
INTRXD
Transmit/receive clock
Y
M
P
X
S
fc/13
fc/26
fc/52
fc/104
fc/208
fc/416
INTTC4
fc/96
A
B
C
D
E
F
G
H
A
B
C
6
fc/2
fc/27
8
fc/2
S
2
Y
4
2
Counter
UARTSR
UARTCR2
UART status register
UART control register 2
MPX: Multiplexer
Baud rate generator
Figure 13-1 UART (Asynchronous Serial Interface)
Page 125
13. Asynchronous Serial interface (UART )
13.2 Control
TMP86CH72FG
13.2 Control
UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR).
UART Control Register1
UARTCR1
(001DH)
7
6
5
4
3
TXE
RXE
STBT
EVEN
PE
2
1
0
BRG
(Initial value: 0000 0000)
TXE
Transfer operation
0:
1:
Disable
Enable
RXE
Receive operation
0:
1:
Disable
Enable
STBT
Transmit stop bit length
0:
1:
1 bit
2 bits
EVEN
Even-numbered parity
0:
1:
Odd-numbered parity
Even-numbered parity
Parity addition
0:
1:
No parity
Parity
PE
BRG
000:
001:
010:
011:
100:
101:
110:
111:
Transmit clock select
Write
only
fc/13 [Hz]
fc/26
fc/52
fc/104
fc/208
fc/416
TC4 ( Input INTTC4)
fc/96
Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive
complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is
enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
Note 2: The transmit clock and the parity are common to transmit and receive.
Note 3: UARTCR1<RXE> and UARTCR1<TXE> should be set to “0” before UARTCR1<BRG> is changed.
UART Control Register2
UARTCR2
(001EH)
7
6
5
4
3
2
1
0
RXDNC
RXDNC
STOPBR
Selection of RXD input noise
rejection time
Receive stop bit length
00:
01:
10:
11:
0:
1:
STOPBR
(Initial value: **** *000)
No noise rejection (Hysteresis input)
Rejects pulses shorter than 31/fc [s] as noise
Rejects pulses shorter than 63/fc [s] as noise
Rejects pulses shorter than 127/fc [s] as noise
Write
only
1 bit
2 bits
Note: When UARTCR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded as signals; when UARTCR2<RXDNC>
= “10”, longer than 192/fc [s]; and when UARTCR2<RXDNC> = “11”, longer than 384/fc [s].
Page 126
TMP86CH72FG
UART Status Register
UARTSR
(001DH)
7
6
5
4
3
2
1
PERR
FERR
OERR
RBFL
TEND
TBEP
0
(Initial value: 0000 11**)
PERR
Parity error flag
0:
1:
No parity error
Parity error
FERR
Framing error flag
0:
1:
No framing error
Framing error
OERR
Overrun error flag
0:
1:
No overrun error
Overrun error
RBFL
Receive data buffer full flag
0:
1:
Receive data buffer empty
Receive data buffer full
TEND
Transmit end flag
0:
1:
On transmitting
Transmit end
TBEP
Transmit data buffer empty flag
0:
1:
Transmit data buffer full (Transmit data writing is finished)
Transmit data buffer empty
Note: When an INTTXD is generated, TBEP flag is set to "1" automatically.
UART Receive Data Buffer
RDBUF
(001FH)
7
6
5
4
3
2
1
0
Read only
(Initial value: 0000 0000)
UART Transmit Data Buffer
TDBUF
(001FH)
7
6
5
4
3
2
1
0
Write only
(Initial value: 0000 0000)
Page 127
Read
only
13. Asynchronous Serial interface (UART )
13.3 Transfer Data Format
TMP86CH72FG
13.3 Transfer Data Format
In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and
parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added to the
transfer data. The transfer data formats are shown as follows.
PE
STBT
0
Frame Length
8
1
2
3
9
10
0
Start
Bit 0
Bit 1
0
1
Start
Bit 0
1
0
Start
1
1
Start
11
Bit 6
Bit 7
Stop 1
Bit 1
Bit 6
Bit 7
Stop 1
Stop 2
Bit 0
Bit 1
Bit 6
Bit 7
Parity
Stop 1
Bit 0
Bit 1
Bit 6
Bit 7
Parity
Stop 1
12
Stop 2
Figure 13-2 Transfer Data Format
Without parity / 1 STOP bit
With parity / 1 STOP bit
Without parity / 2 STOP bit
With parity / 2 STOP bit
Figure 13-3 Caution on Changing Transfer Data Format
Note: In order to switch the transfer data format, perform transmit operations in the above Figure 13-3 sequence except
for the initial setting.
Page 128
TMP86CH72FG
13.4 Transfer Rate
The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows.
Table 13-1 Transfer Rate (Example)
Source Clock
BRG
16 MHz
8 MHz
4 MHz
000
76800 [baud]
38400 [baud]
19200 [baud]
001
38400
19200
9600
010
19200
9600
4800
011
9600
4800
2400
100
4800
2400
1200
101
2400
1200
600
When TC4 is used as the UART transfer rate (when UARTCR1<BRG> = “110”), the transfer clock and transfer
rate are determined as follows:
Transfer clock [Hz] = TC4 source clock [Hz] / TTREG4 setting value
Transfer Rate [baud] = Transfer clock [Hz] / 16
13.5 Data Sampling Method
The UART receiver keeps sampling input using the clock selected by UARTCR1<BRG> until a start bit is
detected in RXD pin input. RT clock starts detecting “L” level of the RXD pin. Once a start bit is detected, the start
bit, data bits, stop bit(s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock
interval (RT clock). (RT0 is the position where the bit supposedly starts.) Bit is determined according to majority
rule (The data are the same twice or more out of three samplings).
RXD pin
Start bit
RT0
1
2
3
Bit 0
4
5
6
7
8
9 10 11 12 13 14 15 0
1
2
3
4
5
6
7
8
9 10 11
2
3
4
5
6
7
8
9 10 11
RT clock
Start bit
Internal receive data
Bit 0
(a) Without noise rejection circuit
RXD pin
Start bit
RT0
1
2
3
Bit 0
4
5
6
7
8
9 10 11 12 13 14 15 0
1
RT clock
Internal receive data
Start bit
Bit 0
(b) With noise rejection circuit
Figure 13-4 Data Sampling Method
Page 129
13. Asynchronous Serial interface (UART )
13.6 STOP Bit Length
TMP86CH72FG
13.6 STOP Bit Length
Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>.
13.7 Parity
Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>.
13.8 Transmit/Receive Operation
13.8.1 Data Transmit Operation
Set UARTCR1<TXE> to “1”. Read UARTSR to check UARTSR<TBEP> = “1”, then write data in TDBUF
(Transmit data buffer). Writing data in TDBUF zero-clears UARTSR<TBEP>, transfers the data to the transmit
shift register and the data are sequentially output from the TXD pin. The data output include a one-bit start bit,
stop bits whose number is specified in UARTCR1<STBT> and a parity bit if parity addition is specified.
Select the data transfer baud rate using UARTCR1<BRG>. When data transmit starts, transmit buffer empty
flag UARTSR<TBEP> is set to “1” and an INTTXD interrupt is generated.
While UARTCR1<TXE> = “0” and from when “1” is written to UARTCR1<TXE> to when send data are
written to TDBUF, the TXD pin is fixed at high level.
When transmitting data, first read UARTSR, then write data in TDBUF. Otherwise, UARTSR<TBEP> is not
zero-cleared and transmit does not start.
13.8.2 Data Receive Operation
Set UARTCR1<RXE> to “1”. When data are received via the RXD pin, the receive data are transferred to
RDBUF (Receive data buffer). At this time, the data transmitted includes a start bit and stop bit(s) and a parity
bit if parity addition is specified. When stop bit(s) are received, data only are extracted and transferred to
RDBUF (Receive data buffer). Then the receive buffer full flag UARTSR<RBFL> is set and an INTRXD
interrupt is generated. Select the data transfer baud rate using UARTCR1<BRG>.
If an overrun error (OERR) occurs when data are received, the data are not transferred to RDBUF (Receive
data buffer) but discarded; data in the RDBUF are not affected.
Note:When a receive operation is disabled by setting UARTCR1<RXE> bit to “0”, the setting becomes valid when
data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting
may not become valid. If a framing error occurs, be sure to perform a re-receive operation.
Page 130
TMP86CH72FG
13.9 Status Flag
13.9.1 Parity Error
When parity determined using the receive data bits differs from the received parity bit, the parity error flag
UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
RXD pin
Shift register
Parity
Stop
pxxxx0*
xxxx0**
1pxxxx0
UARTSR<PERR>
After reading UARTSR then
RDBUF clears PERR.
INTRXD interrupt
Figure 13-5 Generation of Parity Error
13.9.2 Framing Error
When “0” is sampled as the stop bit in the receive data, framing error flag UARTSR<FERR> is set to “1”.
The UARTSR<FERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
Shift register
Stop
Final bit
RXD pin
xxxx0*
xxx0**
0xxxx0
After reading UARTSR then
RDBUF clears FERR.
UARTSR<FERR>
INTRXD interrupt
Figure 13-6 Generation of Framing Error
13.9.3 Overrun Error
When all bits in the next data are received while unread data are still in RDBUF, overrun error flag
UARTSR<OERR> is set to “1”. In this case, the receive data is discarded; data in RDBUF are not affected.
The UARTSR<OERR> is cleared to “0” when the RDBUF is read after reading the UARTSR.
Page 131
13. Asynchronous Serial interface (UART )
13.9 Status Flag
TMP86CH72FG
UARTSR<RBFL>
RXD pin
Stop
Final bit
Shift register
xxx0**
RDBUF
yyyy
xxxx0*
1xxxx0
UARTSR<OERR>
After reading UARTSR then
RDBUF clears OERR.
INTRXD interrupt
Figure 13-7 Generation of Overrun Error
Note:Receive operations are disabled until the overrun error flag UARTSR<OERR> is cleared.
13.9.4 Receive Data Buffer Full
Loading the received data in RDBUF sets receive data buffer full flag UARTSR<RBFL> to "1". The
UARTSR<RBFL> is cleared to “0” when the RDBUF is read after reading the UARTSR.
Stop
Final bit
RXD pin
Shift register
xxx0**
RDBUF
yyyy
xxxx0*
1xxxx0
xxxx
After reading UARTSR then
RDBUF clears RBFL.
UARTSR<RBFL>
INTRXD interrupt
Figure 13-8 Generation of Receive Data Buffer Full
Note:If the overrun error flag UARTSR<OERR> is set during the period between reading the UARTSR and reading
the RDBUF, it cannot be cleared by only reading the RDBUF. Therefore, after reading the RDBUF, read the
UARTSR again to check whether or not the overrun error flag which should have been cleared still remains
set.
13.9.5 Transmit Data Buffer Empty
When no data is in the transmit buffer TDBUF, that is, when data in TDBUF are transferred to the transmit
shift register and data transmit starts, transmit data buffer empty flag UARTSR<TBEP> is set to “1”. The
UARTSR<TBEP> is cleared to “0” when the TDBUF is written after reading the UARTSR.
Page 132
TMP86CH72FG
Data write
xxxx
TDBUF
*****1
Shift register
TXD pin
Data write
zzzz
yyyy
1xxxx0
*1xxxx
****1x
*****1
Start
Bit 0
Final bit
Stop
1yyyy0
UARTSR<TBEP>
After reading UARTSR writing TDBUF
clears TBEP.
INTTXD interrupt
Figure 13-9 Generation of Transmit Data Buffer Empty
13.9.6 Transmit End Flag
When data are transmitted and no data is in TDBUF (UARTSR<TBEP> = “1”), transmit end flag
UARTSR<TEND> is set to “1”. The UARTSR<TEND> is cleared to “0” when the data transmit is started after
writing the TDBUF.
Shift register
TXD pin
***1xx
****1x
*****1
1yyyy0
Stop
Start
*1yyyy
Bit 0
Data write for TDBUF
UARTSR<TBEP>
UARTSR<TEND>
INTTXD interrupt
Figure 13-10 Generation of Transmit End Flag and Transmit Data Buffer Empty
Page 133
13. Asynchronous Serial interface (UART )
13.9 Status Flag
TMP86CH72FG
Page 134
TMP86CH72FG
14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
The TMP86CH72FG has a serial bus interface which employs an I2C bus.
The serial interface is connected to an external devices through SDA and SCL.
The serial bus interface pins are also used as the port. When used as serial bus interface pins, set the output latches
of these pins to "1". When not used as serial bus interface pins, the port is used as a normal I/O port.
Note 1: The serial bus interface can be used only in NORMAL1/2 and IDLE1/2 mode. It can not be used in IDLE0,
SLOW1/2 and SLEEP0/1/2 mode.
Note 2: The serial bus interface can be used only in the Standard mode of I2C. The fast mode and the high-speed mode
can not be used.
Note 3: Please refer to the I/O port section about the detail of setting port.
14.1 Configuration
INTSBI interrupt request
SCL
fc/4
Noise
canceller
Input/
output
control
Divider
Transfer
control
circuit
I2C bus
clock sysn.
Control
Shift
register
SBICRB/
SBISRB
SBI control register B/
SBI status register B
I C bus
address register
I2C bus data
control
SBI data
buffer register
Noise
canceller
SDA
SDA
SBICRA/
SBISRA
SBIDBR
I2CAR
2
SCL
SBI control register A/
SBI status register A
Figure 14-1 Serial Bus Interface (SBI)
14.2 Control
The following registers are used for control the serial bus interface and monitor the operation status.
• Serial bus interface control register A (SBICRA)
• Serial bus interface control register B (SBICRB)
• Serial bus interface data buffer register (SBIDBR)
• I2C bus address register (I2CAR)
• Serial bus interface status register A (SBISRA)
• Serial bus interface status register B (SBISRB)
14.3 Software Reset
A serial bus interface circuit has a software reset function, when a serial bus interface circuit is locked by an external noise, etc.
To reset the serial bus interface circuit, write “10”, “01” into the SWRST (Bit1, 0 in SBICRB).
And a status of software reset canbe read from SWRMON (Bit0 in SBISRA).
Page 135
14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.4 The Data Format in the I2C Bus Mode
TMP86CH72FG
14.4 The Data Format in the I2C Bus Mode
The data format of the I2C bus is shown below.
(a) Addressing format
8 bits
1
RA
S Slave address / C
WK
1 to 8 bits
1
1 to 8 bits
Data
A
C
K
Data
1
1
A
CP
K
1 or more
(b) Addressing format (with restart)
8 bits
1
RA
S Slave address / C
WK
1
1 to 8 bits
1
8 bits
1
A
RA
C S Slave address / C
K
WK
Data
1 or more
1
S
1
1 to 8 bits
1
1 to 8 bits
Data
A
C
K
Data
A
C
K
Data
1
S
R/W
ACK
P
1
A
CP
K
1 or more
: Start condition
: Direction bit
: Acknowledge bit
: Stop condition
Figure 14-2 Data Format in of I2C Bus
Page 136
Data
1 or more
(c) Free data format
8 bits
1 to 8 bits
1
A
CP
K
TMP86CH72FG
14.5 I2C Bus Control
The following registers are used to control the serial bus interface and monitor the operation status of the I2C bus.
Serial Bus Interface Control Register A
7
SBICRA
(0020H)
6
5
4
BC
3
2
1
ACK
0
SCK
(Initial value: 0000 *000)
ACK = 0
BC
BC
Number of transferred bits
Number of
Clock
000:
Bits
Bits
8
8
9
8
001:
1
1
2
1
010:
2
2
3
2
011:
3
3
4
3
100:
4
4
5
4
101:
5
5
6
5
110:
6
6
7
6
111:
7
7
8
ACK
ACK
SCK
Acknowledgement mode
specification
ACK = 1
Number of
Clock
Master mode
Write
only
7
Slave mode
0:
Not generate a clock pulse for
an acknowledgement.
Not count a clock pulse for
an acknowledgement.
1:
Generate a clock pulse for an
acknowledgement.
Count a clock pulse for an
acknowledgement.
SCK
n
At fc = 16 MHz
At fc = 8 MHz
At fc = 4 MHz
000:
4
Reserved
Reserved
100.0 kHz
001:
5
Reserved
Reserved
55.6 kHz
Serial clock (fscl) selection
(Output on SCL pin)
010:
6
Reserved
58.8 kHz
29.4 kHz
011:
7
60.6 kHz
30.3 kHz
15.2 kHz
[fscl = 1/(2n+1/fc + 8/fc)]
100:
8
30.8 kHz
15.4 kHz
7.7 kHz
101:
9
15.5 kHz
7.8 kHz
3.9 kHz
110:
10
7.8 kHz
3.9 kHz
1.9 kHz
111:
R/W
Write
only
Reserved
Note 1: fc: High-frequency clock [Hz], *: Don't care
Note 2: SBICRA cannot be used with any of read-modify-write instructions such as bit manipulation, etc.
Note 3: Do not set SCK as the frequency that is over 100 kHz.
Serial Bus Interface Data Buffer Register
SBIDBR
(0021H)
7
6
5
4
3
2
1
0
(Initial value: **** ****) R/W
Note 1: For writing transmitted data, start from the MSB (Bit7).
Note 2: The data which was written into SBIDBR can not be read, since a write data buffer and a read buffer are independent in
SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions such as bit manipulation, etc.
Note 3: *: Don't care
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14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.5 I2C Bus Control
TMP86CH72FG
I2C bus Address Register
I2CAR
(0022H)
7
6
5
SA6
SA5
SA4
4
3
2
1
SA2
SA1
SA0
0
Slave address
(Initial value: 0000 0000)
ALS
SA
Slave address selection
ALS
Address recognition mode specification
SA3
Write
only
0:
Slave address recognition
1:
Non slave address recognition
Note 1: I2CAR is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc.
Note 2: Do not set I2CAR to "00H" to avoid the incorrect response of acknowledgment in slave mode. ( If "00H" is set to I2CAR as
the Slave Address and a START Byte "01H" in I2C bus standard is recived, the device detects slave address match.)
Serial Bus Interface Control Register B
SBICRB
(0023H)
7
6
5
4
3
MST
TRX
BB
PIN
SBIM
0:
MST
TRX
BB
PIN
SBIM
SWRST1
SWRST0
2
1
0
SWRST1
SWRST0
(Initial value: 0001 0000)
Slave
Master/slave selection
1:
Master
0:
Receiver
1:
Transmitter
0:
Generate a stop condition when MST, TRX and PIN are "1"
1:
Generate a start condition when MST, TRX and PIN are "1"
0:
– (Can not clear this bit by a software)
1:
Cancel interrupt service request
Transmitter/receiver selection
Start/stop generation
Write
only
Cancel interrupt service request
Serial bus interface operating
mode selection
Software reset start bit
00:
Port mode (Serial bus interface output disable)
01:
Reserved
10:
I2C bus mode
11:
Reserved
Software reset starts by first writing "10" and next writing "01"
Note 1: Switch a mode to port after confirming that the bus is free.
Note 2: Switch a mode to I2C bus mode after confiming that the port is high level.
Note 3: SBICRB has write-only register and must not be used with any of read-modify-write instructions such as bit manipulation,
etc.
Note 4: When the SWRST (Bit1, 0 in SBICRB) is written to "10", "01" in I2C bus mode, software reset is occurred. In this case, the
SBICRA, I2CAR, SBISRA and SBISRB registers are initialized and the bits of SBICRB except the SBIM (Bit3, 2 in SBICRB) are also initialized.
Serial Bus Interface Status Register A
7
SBISRA
(H)
6
5
4
3
2
1
0
SWRMON
SWRMON
0:
During software reset
1:
– (Initial value)
(Initial value: **** ***1)
Read
only
Software reset monitor
Serial Bus Interface Status Register B
SBISRB
(0023H)
7
6
5
4
3
2
1
0
MST
TRX
BB
PIN
AL
AAS
AD0
LRB
Page 138
(Initial value: 0001 0000)
TMP86CH72FG
MST
TRX
BB
Master/slave selection status
monitor
0:
Slave
1:
Master
Transmitter/receiver selection
status monitor
0:
Receiver
1:
Transmitter
0:
Bus free
Bus status monitor
1:
Bus busy
0:
Requesting interrupt service
1:
Releasing interrupt service request
0:
–
1:
Arbitration lost detected
Slave address match detection
monitor
0:
-
1:
Detect slave address match or "GENERAL CALL"
"GENERAL CALL" detection
monitor
0:
-
Interrupt service requests status monitor
PIN
AL
Read
only
Arbitration lost detection monitor
AAS
AD0
LRB
1:
Detect "GENERAL CALL"
0:
Last receive bit is "0"
1:
Last receiv bit is "1"
Last received bit monitor
14.5.1 Acknowledgement mode specification
14.5.1.1 Acknowledgment mode (ACK = “1”)
To set the device as an acknowledgment mode, the ACK (Bit4 in SBICRA) should be set to “1”. When
a serial bus interface circuit is a master mode, an additional clock pulse is generated for an acknowledge
signal. In a slave mode, a clock is counted for the acknowledge signal.
In the master transmitter mode, the SDA pin is released in order to receive an acknowledge signal from
the receiver during additional clock pulse cycle. In the master receiver mode, the SDA pin is set to low
level generation an acknowledge signal during additional clock pulse cycle.
In a slave mode, when a received slave address matches to a slave address which is set to the I2CAR or
when a “GENERAL CALL” is received, the SDA pin is set to low level generating an acknowledge signal. After the matching of slave address or the detection of “GENERAL CALL”, in the transmitter, the
SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock
pulse cycle. In a receiver, the SDA pin is set to low level generation an acknowledge signal during additional clock pulse cycle after the matching of slave address or the detection of “GENERAL CALL”
The Table 14-1 shows the SCL and SDA pins status in acknowledgment mode.
Table 14-1 SCL and SDA Pins Status in Acknowledgement Mode
Mode
Pin
Transmitter
SCL
An additional clock pulse is generated.
Master
Released in order to receive
an acknowledge signal.
SDA
SCL
Set to low level generating an
acknowledge signal
A clock is counted for the acknowledge signal.
When slave address matches
or a general call is detected
Slave
Receiver
–
Set to low level generating an
acknowledge signal.
SDA
After matching of slave
address or general call
Released in order to receive
an acknowledge signal.
Set to low level generating an
acknowledge signal.
14.5.1.2 Non-acknowledgment mode (ACK = “0”)
To set the device as a non-acknowledgement mode, the ACK (Bit4 in SBICRA) should be cleared to
“0”.
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14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.5 I2C Bus Control
TMP86CH72FG
In the master mode, a clock pulse for an acknowledge signal is not generated.
In the slave mode, a clock for a acknowledge signal is not counted.
14.5.2 Number of transfer bits
The BC (Bits7 to 5 in SBICRA) is used to select a number of bits for next transmitting and receiving data.
Since the BC is cleared to “000” by a start condition, a slave address and direction bit transmissions are
always executed in 8 bits. Other than these, the BC retains a specified value.
14.5.3 Serial clock
14.5.3.1 Clock source
The SCK (Bits2 to 0 in SBICRA) is used to select a maximum transfer frequency output from the SCL
pin in the master mode.
Four or more machine cycles are required for both high and low levels of pulse width in the external
clock which is input from SCL pin.
Note: Since the serial bus interface can not be used as the fast mode and the high-speed mode, do not set
SCK as the frequency that is over 100 kHz.
tHIGH
tLOW
1/fscl
SCK (Bits2 to 0 in the SBICRA)
n
000
001
010
011
100
101
110
tLOW = 2 /fc
n
tHIGH = 2 /fc + 8/fc
fscl = 1/(tLOW + tHIGH)
tSCKL
n
4
5
6
7
8
9
10
tSCKH
tSCKL, tSCKH > 4 tcyc
Note 1: fc = High-frequency clock
Note 2: tcyc = 4/fc (in NORMAL mode, IDLE mode)
Figure 14-3 Clock Source
14.5.3.2 Clock synchronization
In the I2C bus, in order to drive a bus with a wired AND, a master device which pulls down a clock
pulse to low will, in the first place, invalidate a clock pulse of another master device which generates a
high-level clock pulse.
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TMP86CH72FG
The serial bus interface circuit has a clock synchronization function. This function ensures normal
transfer even if there are two or more masters on the same bus.
The example explains clock synchronization procedures when two masters simultaneously exist on a
bus.
Count start
Wait
SCL pin (Master 1)
Count restart
SCL pin (Master 2)
Count reset
SCL (Bus)
a
b
c
Figure 14-4 Clock Synchronization
As Master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of the bus becomes the
low level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets
the SCL pin to the low level.
Master 1 finishes counting a clock pulse in the low level at point “b” and sets the SCL pin to the high
level. Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock
pulse in the high level. After Master 2 sets a clock pulse to the high level at point “c” and detects the SCL
line of the bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master,
which has finished the counting a clock pulse in the high level, pulls down the SCL pin to the low level.
The clock pulse on the bus is determined by the master device with the shortest high-level period and
the master device with the longest low-level period from among those master devices connected to the
bus.
14.5.4 Slave address and address recognition mode specification
When the serial bus interface circuit is used with an addressing format to recognize the slave address, clear
the ALS (Bit0 in I2CAR) to “0”, and set the SA (Bits7 to 1 in I2CAR) to the slave address.
When the serial bus interface circuit is used with a free data format not to recognize the slave address, set the
ALS to “1”. With a free data format, the slave address and the direction bit are not recognized, and they are
processed as data from immediately after start condition.
14.5.5 Master/slave selection
To set a master device, the MST (Bit7 in SBICRB) should be set to “1”. To set a slave device, the MST
should be cleared to “0”.
When a stop condition on the bus or an arbitration lost is detected, the MST is cleared to “0” by the hardware.
14.5.6 Transmitter/receiver selection
To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to "1". To set the device as a
receiver, the TRX should be cleared to “0”. When data with an addressing format is transferred in the slave
mode, the TRX is set to "1" by a hardware if the direction bit (R/W) sent from the master device is “1”, and is
cleared to “0” by a hardware if the bit is “0”. In the master mode, after an acknowledge signal is returned from
the slave device, the TRX is cleared to “0” by a hardware if a transmitted direction bit is “1”, and is set to "1"
by a hardware if it is “0”. When an acknowledge signal is not returned, the current condition is maintained.
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14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.5 I2C Bus Control
TMP86CH72FG
When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to “0” by the hardware.
" Table 14-2 TRX changing conditions in each mode " shows TRX changing conditions in each mode and TRX
value after changing
Table 14-2 TRX changing conditions in each mode
Mode
Direction Bit
Conditions
TRX after Changing
Slave
Mode
"0"
A received slave address is
the same value set to I2CAR
"0"
"1"
"1"
"0"
Master
Mode
"1"
ACK signal is returned
"1"
"0"
When a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not
recognized. They are handled as data just after generating a start condition. The TRX is not changed by a hardware.
14.5.7 Start/stop condition generation
When the BB (Bit5 in SBISRB) is “0”, a slave address and a direction bit which are set to the SBIDBR are
output on a bus after generating a start condition by writing “1” to the MST, TRX, BB and PIN. It is necessary
to set ACK to “1” beforehand.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
A6
A5
A4
A3
A2
A1
A0
R/W
Slave address and the direction bit
Start condition
9
Acknowledge signal
Figure 14-5 Start Condition Generation and Slave Address Generation
When the BB is “1”, sequence of generating a stop condition is started by writing “1” to the MST, TRX and
PIN, and “0” to the BB. Do not modify the contents of MST, TRX, BB and PIN until a stop condition is generated on a bus.
When a stop condition is generated and the SCL line on a bus is pulled-down to low level by another device,
a stop condition is generated after releasing the SCL line.
SCL pin
SDA pin
Stop condition
Figure 14-6 Stop Condition Generation
The bus condition can be indicated by reading the contents of the BB (Bit5 in SBISRB). The BB is set to “1”
when a start condition on a bus is detected (Bus Busy State) and is cleared to “0” when a stop condition is
detected (Bus Free State).
14.5.8 Interrupt service request and cancel
When a serial bus interface circuit is in the master mode and transferring a number of clocks set by the BC
and the ACK is complete, a serial bus interface interrupt request (INTSBI) is generated.
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TMP86CH72FG
In the slave mode, the conditions of generating INTSBI interrupt request are follows:
• At the end of acknowledge signal when the received slave address matches to the value set by the
I2CAR
• At the end of acknowledge signal when a “GENERAL CALL” is received
• At the end of transferring or receiving after matching of slave address or receiving of “GENERAL
CALL”
When a serial bus interface interrupt request occurs, the PIN (Bit4 in SBISRB) is cleared to “0”. During the
time that the PIN is “0”, the SCL pin is pulled-down to low level.
Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to “1”.
The time from the PIN being set to “1” until the SCL pin is released takes tLOW.
Although the PIN (Bit4 in SBICRB) can be set to “1” by the softrware, the PIN can not be cleared to “0” by
the softrware.
Note:When the arbitration lost occurs, if the slave address sent from the other master devices is not match, the
INTSBI interrupt request is generated. But the PIN is not cleared.
14.5.9 Setting of I2C bus mode
The SBIM (Bit3 and 2 in SBICRB) is used to set I2C bus mode.
Set the SBIM to “10” in order to set I2C bus mode. Before setting of I2C bus mode, confirm serial bus interface pins in a high level, and then, write “10” to SBIM. And switch a port mode after confirming that a bus is
free.
14.5.10Arbitration lost detection monitor
Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is implemented in order to guarantee the contents of transferred data.
Data on the SDA line is used for bus arbitration of the I2C bus.
The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on a bus. Master 1 and Master 2 output the same data until point “a”. After that, when Master 1 outputs
“1” and Master 2 outputs “0”, since the SDA line of a bus is wired AND, the SDA line is pulled-down to the
low level by Master 2. When the SCL line of a bus is pulled-up at point “b”, the slave device reads data on the
SDA line, that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is
called “arbitration lost”. A master device which loses arbitration releases the SDA pin and the SCL pin in order
not to effect data transmitted from other masters with arbitration. When more than one master sends the same
data at the first word, arbitration occurs continuously after the second word.
SCL (Bus)
SDA pin (Master 1)
SDA pin becomes "1" after losing arbitration.
SDA pin (Master 2)
SDA (Bus)
a
b
Figure 14-7 Arbitration Lost
The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of
the SCL line. If the levels are unmatched, arbitration is lost and the AL (Bit3 in SBISRB) is set to “1”.
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14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.5 I2C Bus Control
TMP86CH72FG
When the AL is set to “1”, the MST and TRX are cleared to “0” and the mode is switched to a slave receiver
mode. Thus, the serial bus interface circuit stops output of clock pulses during data transfer after the AL is set
to “1”.
The AL is cleared to “0” by writing data to the SBIDBR, reading data from the SBIDBR or writing data to
the SBICRB.
SCL pin
1
2
3
4
5
6
7
8
9
1
2
3
Master A
SDA pin
SCL pin
D7A D6A D5A D4A D3A D2A D1A D0A
1
2
3
4
5
6
7
8
D7A’ D6A’ D5A’
9
Stop clock output
Master B
SDA pin
D7B D6B
Releasing SDA pin and SCL pin to high level as losing arbitration.
AL
MST
TRX
Accessed to SBIDBR or SBICRB
INTSBI
Figure 14-8 Example of when a Serial Bus Interface Circuit is a Master B
14.5.11Slave address match detection monitor
In the slave mode, the AAS (Bit2 in SBISRB) is set to “1” when the received data is “GENERAL CALL” or
the received data matches the slave address setting by I2CAR with an address recognition mode (ALS = 0).
When a serial bus interface circuit operates in the free data format (ALS = 1), the AAS is set to “1” after
receiving the first 1-word of data.
The AAS is cleared to “0” by writing data to the SBIDBR or reading data from the SBIDBR.
14.5.12GENERAL CALL detection monitor
The AD0 (Bit1 in SBISRB) is set to “1” when all 8-bit received data is “0” immediately after a start condition in a slave mode. The AD0 is cleared to “0” when a start or stop condition is detected on a bus.
14.5.13Last received bit monitor
The SDA line value stored at the rising edge of the SCL line is set to the LRB (Bit0 in SBISRB). In the
acknowledge mode, immediately after an INTSBI interrupt request is generated, an acknowledge signal is read
by reading the contents of the LRB.
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TMP86CH72FG
14.6 Data Transfer of I2C Bus
14.6.1 Device initialization
For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”. Specify the data length to 8
bits to count clocks for an acknowledge signal. Set a transfer frequency to the SCK in SBICRA.
Next, set the slave address to the SA in I2CAR and clear the ALS to “0” to set an addressing format.
After confirming that the serial bus interface pin is high level, for specifying the default setting to a slave
receiver mode, clear “0” to the MST, TRX and BB in SBICRB, set “1” to the PIN, “10” to the SBIM, and “00”
to bits SWRST1 and SWRST0.
Note:The initialization of a serial bus interface circuit must be complete within the time from all devices which are
connected to a bus have initialized to and device does not generate a start condition. If not, the data can not
be received correctly because the other device starts transferring before an end of the initialization of a serial
bus interface circuit.
14.6.2 Start condition and slave address generation
Confirm a bus free status (BB = 0).
Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to the SBIDBR.
By writing “1” to the MST, TRX, BB and PIN, the start condition is generated on a bus and then, the slave
address and the direction bit which are set to the SBIDBR are output. The time from generating the START
condition until the falling SCL pin takes tLOW.
An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle, and the PIN is cleared to
“0”. The SCL pin is pulled-down to the low level while the PIN is “0”. When an interrupt request occurs, the
TRX changes by the hardware according to the direction bit only when an acknowledge signal is returned from
the slave device.
Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If data is written to the
SBIDBR, data to been outputting may be destroyed.
Note 2: The bus free must be confirmed by software within 98.0 µs (The shortest transmitting time according to the
I2C bus standard) after setting of the slave address to be output. Only when the bus free is confirmed, set
"1" to the MST, TRX, BB, and PIN to generate the start conditions. If the writing of slave address and setting
of MST, TRX, BB and PIN doesn't finish within 98.0 µs, the other masters may start the transferring and the
slave address data written in SBIDBR may be broken.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
A6
A5
A4
A3
A2
A1
A0
R/W
Start condition
9
Slave address + Direction bit
Acknowledge
signal from a
slave device
PIN
INTSBI
interrupt request
Figure 14-9 Start Condition Generation and Slave Address Transfer
14.6.3 1-word data transfer
Check the MST by the INTSBI interrupt process after an 1-word data transfer is completed, and determine
whether the mode is a master or slave.
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14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.6 Data Transfer of I2C Bus
TMP86CH72FG
14.6.3.1 When the MST is “1” (Master mode)
Check the TRX and determine whether the mode is a transmitter or receiver.
(1)
When the TRX is “1” (Transmitter mode)
Test the LRB. When the LRB is “1”, a receiver does not request data. Implement the process to
generate a stop condition (Described later) and terminate data transfer.
When the LRB is “0”, the receiver requests next data. When the next transmitted data is other than
8 bits, set the BC, set the ACK to “1”, and write the transmitted data to the SBIDBR. After writing
the data, the PIN becomes “1”, a serial clock pulse is generated for transferring a next 1 word of data
from the SCL pin, and then the 1 word of data is transmitted. After the data is transmitted, and an
INTSBI interrupt request occurs. The PIN become “0” and the SCL pin is set to low level. If the data
to be transferred is more than one word in length, repeat the procedure from the LRB test above.
SCL pin
1
2
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
9
Write to SBIDBR
SDA pin
Acknowledge
signal from a
receiver
PIN
INTSBI
interrupt request
Figure 14-10 Example of when BC = “000”, ACK = “1”
(2)
When the TRX is “0” (Receiver mode)
When the next transmitted data is other than of 8 bits, set the BC again. Set the ACK to “1” and
read the received data from the SBIDBR (Reading data is undefined immediately after a slave
address is sent). After the data is read, the PIN becomes “1”. A serial bus interface circuit outputs a
serial clock pulse to the SCL pin to transfer next 1-word of data and sets the SDA pin to “0” at the
acknowledge signal timing.
An INTSBI interrupt request occurs and the PIN becomes “0”. Then a serial bus interface circuit
outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received
data is read from the SBIDBR.
Read SBIDBR
SCL pin
1
2
3
4
5
6
7
8
SDA pin
D7
D6
D5
D4
D3
D2
D1
D0
9
New D7
Acknowledge
signal to a
transmitter
PIN
INTSBI
interrupt request
Figure 14-11 Example of when BC = “000”, ACK = “1”
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TMP86CH72FG
To make the transmitter terminate transmit, clear the ACK to “0” before reading data which is 1word before the last data to be received. A serial bus interface circuit does not generate a clock pulse
for the acknowledge signal by clearing ACK. In the interrupt routine of end of transmission, when
the BC is set to “001” and read the data, PIN is set to “1” and generates a clock pulse for a 1-bit data
transfer. In this case, since the master device is a receiver, the SDA line on a bus keeps the high-level.
The transmitter receives the high-level signal as an ACK signal. The receiver indicates to the transmitter that data transfer is complete.
After 1-bit data is received and an interrupt request has occurred, generate the stop condition to terminate data transfer.
SCL pin
1
2
3
4
5
6
7
8
SDA pin
D7
D6
D5
D4
D3
D2
D1
D0
1
Acknowledge signal
sent to a transmitter
PIN
INTSBI
interrupt request
Clear ACK to "0"
before reading SBIDBR
Set BC to "001"
before reading SBIDBR
Figure 14-12 Termination of Data Transfer in Master Receiver Mode
14.6.3.2 When the MST is “0” (Slave mode)
In the slave mode, a serial bus interface circuit operates either in normal slave mode or in slave mode
after losing arbitration.
In the slave mode, the conditions of generating INTSBI interrupt request are follows:
• At the end of acknowledge signal when the received slave address matches to the value set by the
I2CAR
• At the end of acknowledge signal when a “GENERAL CALL” is received
• At the end of transferring or receiving after matching of slave address or receiving of “GENERAL
CALL”
A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode. And an
INTSBI interrupt request occurs when word data transfer terminates after losing arbitration. The behavior
of INTSBI interrupt request and PIN after losing arbitration are shown in Table 14-3.
Table 14-3 The Behavior of INTSBI interrupt request and PIN after Losing Arbitration
When the Arbitration Lost Occurs during Transmission of Slave Address as a Master
INTSBI
interrupt
request
PIN
When the Arbitration Lost Occurs during Transmission of Data as a Master Transmit Mode
INTSBI interrupt request is generated at the termination of word data.
When the slave address matches the value set
by I2CAR, the PIN is cleared to "0" by generating
of INTSBI interrupt request. When the slave
address doesn't match the value set by I2CAR,
the PIN keeps "1".
PIN keeps "1" (PIN is not cleared to "0").
When an INTSBI interrupt request occurs, the PIN (bit 4 in the SBICRB) is reset, and the SCL pin is set
to low level. Either reading or writing from or to the SBIDBR or setting the PIN to “1” releases the SCL
pin after taking tLOW.
Page 147
14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.6 Data Transfer of I2C Bus
TMP86CH72FG
Check the AL (Bit3 in the SBISRB), the TRX (Bit6 in the SBISRB), the AAS (Bit2 in the SBISRB),
and the AD0 (Bit1 in the SBISRB) and implements processes according to conditions listed in " Table 144 Operation in the Slave Mode ".
Table 14-4 Operation in the Slave Mode
TRX
AL
1
AAS
1
1
AD0
Conditions
0
A serial bus interface circuit loses arbitration when transmitting a slave address.
And receives a slave address of which the
value of the direction bit sent from another
master is "1".
0
1
Process
Set the number of bits in 1 word to the BC
and write transmitted data to the SBIDBR.
In the slave receiver mode, a serial bus
interface circuit receives a slave address
of which the value of the direction bit sent
from the master is "1".
0
In the slave transmitter mode, 1-word data
is transmitted.
Test the LRB. If the LRB is set to "1", set
the PIN to "1" since the receiver does not
request next data. Then, clear the TRX to
"0" to release the bus. If the LRB is set to
"0", set the number of bits in 1 word to the
BC and write transmitted data to the
SBIDBR since the receiver requests next
data.
1/0
A serial bus interface circuit loses arbitration when transmitting a slave address.
And receives a slave address of which the
value of the direction bit sent from another
master is "0" or receives a "GENERAL
CALL".
Read the SBIDBR for setting the PIN to
"1" (Reading dummy data) or write "1" to
the PIN.
0
A serial bus interface circuit loses arbitration when transmitting a slave address or
data. And terminates transferring word
data.
A serial bus interface circuit is changed to
slave mode. To clear AL to "0", read the
SBIDBR or write the data to SBIDBR.
1
1/0
In the slave receiver mode, a serial bus
interface circuit receives a slave address
of which the value of the direction bit sent
from the master is "0" or receives "GENERAL CALL".
Read the SBIDBR for setting the PIN to
"1" (Reading dummy data) or write "1" to
the PIN.
0
1/0
In the slave receiver mode, a serial bus
interface circuit terminates receiving of 1word data.
Set the number of bits in 1-word to the BC
and read received data from the SBIDBR.
0
0
1
1
0
0
0
Note: In the slave mode, if the slave address set in I2CAR is "00H", a START Byte "01H" in I2C bus standard is recived, the
device detects slave address match and the TRX is set to "1".
14.6.4 Stop condition generation
When the BB is “1”, a sequence of generating a stop condition is started by setting “1” to the MST, TRX and
PIN, and clear “0” to the BB. Do not modify the contents of the MST, TRX, BB, PIN until a stop condition is
generated on a bus.
When a SCL line on a bus is pulled-down by other devices, a serial bus interface circuit generates a stop condition after they release a SCL line.
The time from the releasing SCL line until the generating the STOP condition takes tLOW.
Page 148
TMP86CH72FG
"1"
"1"
"0"
"1"
MST
TRX
BB
PIN
Stop condition
SCL pin
SDA pin
PIN
BB (Read)
Figure 14-13 Stop Condition Generation
14.6.5 Restart
Restart is used to change the direction of data transfer between a master device and a slave device during
transferring data. The following explains how to restart a serial bus interface circuit.
Clear “0” to the MST, TRX and BB and set “1” to the PIN. The SDA pin retains the high-level and the SCL
pin is released. Since a stop condition is not generated on a bus, a bus is assumed to be in a busy state from
other devices. Test the BB until it becomes “0” to check that the SCL pin of a serial bus interface circuit is
released. Test the LRB until it becomes “1” to check that the SCL line on a bus is not pulled-down to the low
level by other devices. After confirming that a bus stays in a free state, generate a start condition with procedure " 14.6.2 Start condition and slave address generation ".
In order to meet setup time when restarting, take at least 4.7 µs of waiting time by software from the time of
restarting to confirm that a bus is free until the time to generate a start condition.
Note:When the master is in the receiver mode, it is necessary to stop the data transmission from the slave devcie
before the STOP condtion is generated. To stop the transmission, the master device make the slave device
receiving a negative acknowledge. Therefore, the LRB is "1" before generating the Restart and it can not be
confirmed that SCL line is not pulled-down by other devices. Please confirm the SCL line state by reading the
port.
"0"
"0"
"0"
"1"
"1"
"1"
"1"
"1"
MST
TRX
BB
PIN
MST
TRX
BB
PIN
4.7µs (Min)
SCL (Bus)
SCL pin
SDA pin
LRB
BB
PIN
Figure 14-14 Timing Diagram when Restarting
Page 149
Start condition
14. Serial Bus Interface(I2C Bus) Ver.-D (SBI)
14.6 Data Transfer of I2C Bus
TMP86CH72FG
Page 150
TMP86CH72FG
15. 8-Bit AD Converter (ADC)
The TMP86CH72FG have a 8-bit successive approximation type AD converter.
15.1 Configuration
The circuit configuration of the 8-bit AD converter is shown in Figure 15-1.
It consists of control registers ADCCR1 and ADCCR2, converted value registers ADCDR1 and ADCDR2, a DA
converter, a sample-and-hold circuit, a comparator, and a successive comparison circuit.
DA converter
VAREF
AVSS
R/2
VDD
AIN0
Analog input
multiplexer
0
R
R/2
Reference
voltage
Sample hold
circuit
Y
8
to
Analog
comparator
n
Successive approximate circuit
Shift clock
S EN
AINDS
ADCCR1
IREFON
SAIN
INTADC interrupt
Control circuit
4
ADRS
AIN5
3
8
ACK
ADCCR2
AD converter control register 1,2
ADCDR1
ADBF
ADCDR2
AD conversion result register1,2
Figure 15-1 8-bit AD Converter (ADC)
Page 151
EOCF
15. 8-Bit AD Converter (ADC)
15.1 Configuration
TMP86CH72FG
15.2 Control
The AD converter consists of the following four registers:
1. AD converter control register 1 (ADCCR1)
This register selects the analog channels in which to perform AD conversion and controls the AD converter as it starts operating.
2. AD converter control register 2 (ADCCR2)
This register selects the AD conversion time and controls the connection of the DA converter (ladder
resistor network).
3. AD converted value register (ADCDR1)
This register is used to store the digital value after being converted by the AD converter.
4. AD converted value register (ADCDR2)
This register monitors the operating status of the AD converter.
AD Converter Control Register 1
ADCCR1
(000EH)
7
6
5
4
ADRS
"0"
"1"
AINDS
3
2
1
SAIN
ADRS
AD conversion start
0:
1:
−
Start
AINDS
Analog input control
0:
1:
Analog input enable
Analog input disable
Analog input channel select
0000:
0001:
0010:
0011:
0100:
0101:
0110:
0111:
1000:
1001:
1010:
1011:
1100:
1101:
1110:
1111:
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SAIN
0
(Initial value: 0001 0000)
R/W
Note 1: Select analog input when AD converter stops (ADCDR2<ADBF> = “0”).
Note 2: When the analog input is all use disabling, the ADCCR1<AINDS> should be set to “1”.
Note 3: During conversion, do not perform output instruction to maintain a precision for all of the pins. And port near to analog
input, do not input intense signaling of change.
Note 4: The ADRS is automatically cleared to “0” after starting conversion.
Note 5: Do not set ADCCR1<ADRS> newly again during AD conversion. Before setting ADCCR1<ADRS> newly again, check
ADCDR2<EOCF> to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g.,
interrupt handling routine).
Note 6: After STOP or SLOW/SLEEP mode are started, AD converter control register 1 (ADCCR1) is all initialized and no data
can be written in this register. Therefore, to use AD converter again, set the ADCCR1 newly after returning to NORMAL1
or NORMAL2 mode.
Note 7: Always set bit 5 in ADCCR1 to “1” and set bit 6 in ADCCR1 to “0”.
Page 152
TMP86CH72FG
AD Converter Control Register 2
7
ADCCR2
(000FH)
6
IREFON
ACK
5
4
3
IREFON
“1”
2
1
0
ACK
“0”
(Initial value: **0* 000*)
DA converter (ladder resistor)
connection control
0:
1:
Connected only during AD conversion
Always connected
R/W
AD conversion time select
000:
001:
010:
011:
100:
101:
110:
111:
39/fc
Reserved
78/fc
156/fc
312/fc
624/fc
1248/fc
Reserved
R/W
Note 1: Always set bit 0 in ADCCR2 to “0” and set bit 4 in ADCCR2 to “1”.
Note 2: When a read instruction for ADCCR2, bit 6 to 7 in ADCCR2 read in as undefined data.
Note 3: After STOP or SLOW/SLEEP mode are started, AD converter control register 2 (ADCCR2) is all initialized and no data
can be written in this register. Therefore, to use AD converter again, set the ADCCR2 newly after returning to NORMAL1
or NORMAL2 mode.
Table 15-1 Conversion Time according to ACK Setting and Frequency
Condition
Conbersion
time‘
16MHz
8MHz
4 MHz
2 MHz
10MHz
5 MHz
2.5 MHz
39/fc
-
-
-
19.5 µs
-
-
15.6 µs
010
78/fc
-
-
19.5 µs
39.0 µs
-
15.6 µs
31.2 µs
011
156/fc
-
19.5 µs
39.0 µs
78.0 µs
15.6 µs
31.2 µs
62.4 µs
100
312/fc
19.5 µs
39.0 µs
78.0 µs
156.0 µs
31.2 µs
62.4 µs
124.8 µs
ACK
000
001
Reserved
101
624/fc
39.0 µs
78.0 µs
156.0 µs
-
62.4 µs
124.8 µs
-
110
1248/fc
78.0 µs
156.0 µs
-
-
124.8 µs
-
-
111
Reserved
Note 1: Settings for “−” in the above table are inhibited.
Note 2: Set conversion time by Analog Reference Voltage (VAREF) as follows.
-
VAREF = 4.5 to 5.5 V
(15.6 µs or more)
-
VAREF = 2.7 to 5.5 V
(31.2 µs or more)
AD Conversion Result Register
ADCDR1
(0027H)
7
6
5
4
3
2
1
0
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
5
4
3
2
1
0
EOCF
ADBF
(Initial value: 0000 0000)
AD Conversion Result Register
ADCDR2
(0026H)
7
EOCF
ADBF
6
(Initial value: **00 ****)
AD conversion end flag
0: Before or during conversion
1: Conversion completed
AD conversion busy flag
0: During stop of AD conversion
1: During AD conversion
Note 1: The ADCDR2<EOCF> is cleared to “0” when reading the ADCDR1.
Therefore, the AD conversion result should be read to ADCDR2 more first than ADCDR1.
Note 2: ADCDR2<ADBF> is set to “1” when AD conversion starts and cleared to “0” when the AD conversion is finished. It
also is cleared upon entering STOP or SLOW mode.
Note 3: If a read instruction is executed for ADCDR2, read data of bits 7, 6 and 3 to 0 are unstable.
Page 153
Read
only
15. 8-Bit AD Converter (ADC)
15.3 Function
TMP86CH72FG
15.3 Function
15.3.1 AD Conveter Operation
When ADCCR1<ADRS> is set to "1", AD conversion of the voltage at the analog input pin specified by
ADCCR1<SAIN> is thereby started.
After completion of the AD conversion, the conversion result is stored in AD converted value registers
(ADCDR1) and at the same time ADCDR2<EOCF> is set to “1”, the AD conversion finished interrupt
(INTADC) is generated.
ADCCR1<ADRS> is automatically cleared after AD conversion has started. Do not set ADCCR1<ADRS>
newly again (restart) during AD conversion. Before setting ADRS newly again, check ADCDR<EOCF> to see
that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine).
AD conversion start
AD conversion start
ADCCR1<ADRS>
ADCDR2<ADBF>
ADCDR1 status
Indeterminate
First conversion result
Second conversion result
EOCF cleared by reading
conversion result
ADCDR2<EOCF>
INTADC interrupt
Conversion
result read
Reading ADCDR1
Conversion
result read
Reading ADCDR2
Figure 15-2 AD Converter Operation
15.3.2 AD Converter Operation
1. Set up the AD converter control register 1 (ADCCR1) as follows:
• Choose the channel to AD convert using AD input channel select (SAIN).
• Specify analog input enable for analog input control (AINDS).
2. Set up the AD converter control register 2 (ADCCR2) as follows:
• Set the AD conversion time using AD conversion time (ACK). For details on how to set the conversion time, refer to Table 15-1.
• Choose IREFON for DA converter control.
3. After setting up 1. and 2. above, set AD conversion start (ADRS) of AD converter control register 1
(ADCCR1) to “1”.
4. After an elapse of the specified AD conversion time, the AD converted value is stored in AD converted value register 1 (ADCDR1) and the AD conversion finished flag (EOCF) of AD converted
value register 2 (ADCDR2) is set to “1”, upon which time AD conversion interrupt INTADC is generated.
5. EOCF is cleared to “0” by a read of the conversion result. However, if reconverted before a register
read, although EOCF is cleared the previous conversion result is retained until the next conversion is
completed.
Page 154
TMP86CH72FG
Example :After selecting the conversion time of 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD
conversion once. After checking EOCF, read the converted value and store the 8-bit data in address 009FH on
RAM.
; AIN SELECT
:
:
:
:
; Before setting the AD converter register, set each port register suitably (For detail, see chapter of I/O port.)
LD
(ADCCR1), 00100011B
; Select AIN3
LD
(ADCCR2), 11011000B
; Select conversion time (312/fc) and operation mode
SET
(ADCCR1). 7
; ADRS = 1
TEST
(ADCDR2). 5
; EOCF = 1 ?
JRS
T, SLOOP
; AD CONVERT START
SLOOP:
; RESULT DATA READ
LD
A, (ADCDR1)
LD
(9FH), A
15.3.3 STOP and SLOW Mode during AD Conversion
When the STOP or SLOW mode is entered forcibly during AD conversion, the AD convert operation is suspended and the AD converter is initialized (ADCCR1 and ADCCR2 are initialized to initial value.). Also, the
conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to
read the conversion results before entering STOP or SLOW mode.) When restored from STOP or SLOW
mode, AD conversion is not automatically restarted, so it is necessary to restart AD conversion. Note that since
the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the
analog reference voltage.
Page 155
15. 8-Bit AD Converter (ADC)
15.3 Function
TMP86CH72FG
15.3.4 Analog Input Voltage and AD Conversion Result
The analog input voltage is corresponded to the 8-bit digital value converted by the AD as shown in Figure
15-3.
AD conversion result
FFH
FEH
FDH
03H
02H
01H
×
0
1
2
3
253
254
Analog input voltage
255
256
VAREF
AVSS
256
Figure 15-3 Analog Input Voltage and AD Conversion Result (typ.)
Page 156
TMP86CH72FG
15.4 Precautions about AD Converter
15.4.1 Analog input pin voltage range
Make sure the analog input pins (AIN0 to AIN5) are used at voltages within AVSS below VAREF. If any
voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes
uncertain. The other analog input pins also are affected by that.
15.4.2 Analog input shared pins
The analog input pins (AIN0 to AIN5) are shared with input/output ports. When using any of the analog
inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary
to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other
pins may also be affected by noise arising from input/output to and from adjacent pins.
15.4.3 Noise countermeasure
The internal equivalent circuit of the analog input pins is shown in Figure 15-4. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output
impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capacitor
external to the chip.
AINx
Allowable signal
source impedance
Internal resistance
5 kΩ (typ)
Analog comparator
Internal capacitance
C = 22 pF (typ.)
5 kΩ (max)
DA converter
Note) i = 5~0
Figure 15-4 Analog Input Equivalent Circuit and Example of Input Pin Processing
Page 157
15. 8-Bit AD Converter (ADC)
15.4 Precautions about AD Converter
TMP86CH72FG
Page 158
TMP86CH72FG
16. Key-on Wakeup (KWU)
In the TMP86CH72FG, the STOP mode is released by not only P20(INT5/STOP) pin but also four (STOP2 to
STOP5) pins.
When the STOP mode is released by STOP2 to STOP5 pins, the STOP pin needs to be used.
In details, refer to the following section " 16.2 Control ".
16.1 Configuration
INT5
STOP
STOP mode
release signal
(1: Release)
STOP2
STOP3
STOP4
STOPCR
(0031H)
STOP5
STOP4
STOP3
STOP2
STOP5
Figure 16-1 Key-on Wakeup Circuit
16.2 Control
STOP2 to STOP5 pins can controlled by Key-on Wakeup Control Register (STOPCR). It can be configured as
enable/disable in 1-bit unit. When those pins are used for STOP mode release, configure corresponding I/O pins to
input mode by I/O port register beforehand.
Key-on Wakeup Control Register
STOPCR
7
6
5
4
(0031H)
STOP5
STOP4
STOP3
STOP2
3
2
1
0
(Initial value: 0000 ****)
STOP5
STOP mode released by STOP5
0:Disable
1:Enable
Write
only
STOP4
STOP mode released by STOP4
0:Disable
1:Enable
Write
only
STOP3
STOP mode released by STOP3
0:Disable
1:Enable
Write
only
STOP2
STOP mode released by STOP2
0:Disable
1:Enable
Write
only
16.3 Function
Stop mode can be entered by setting up the System Control Register (SYSCR1), and can be exited by detecting the
"L" level on STOP2 to STOP5 pins, which are enabled by STOPCR, for releasing STOP mode (Note1).
Page 159
16. Key-on Wakeup (KWU)
16.3 Function
TMP86CH72FG
Also, each level of the STOP2 to STOP5 pins can be confirmed by reading corresponding I/O port data register,
check all STOP2 to STOP5 pins "H" that is enabled by STOPCR before the STOP mode is started (Note2,3).
Note 1: When the STOP mode released by the edge release mode (SYSCR1<RELM> = “0”), inhibit input from STOP2 to
STOP5 pins by Key-on Wakeup Control Register (STOPCR) or must be set "H" level into STOP2 to STOP5 pins
that are available input during STOP mode.
Note 2: When the STOP pin input is high or STOP2 to STOP5 pins input which is enabled by STOPCR is low, executing an
instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release
sequence (Warm up).
Note 3: The input circuit of Key-on Wakeup input and Port input is separated, so each input voltage threshold value is different. Therefore, a value comes from port input before STOP mode start may be different from a value which is
detected by Key-on Wakeup input (Figure 16-2).
Note 4: STOP pin doesn’t have the control register such as STOPCR, so when STOP mode is released by STOP2 to
STOP5 pins, STOP pin also should be used as STOP mode release function.
Note 5: In STOP mode, Key-on Wakeup pin which is enabled as input mode (for releasing STOP mode) by Key-on
Wakeup Control Register (STOPCR) may generate the penetration current, so the said pin must be disabled AD
conversion input (analog voltage input).
Note 6: When the STOP mode is released by STOP2 to STOP5 pins, the level of STOP pin should hold "L" level (Figure
16-3).
External pin
Port input
Key-on wakeup
input
Figure 16-2 Key-on Wakeup Input and Port Input
b) In case of STOP2 to STOP5
a) STOP
STOP pin
STOP pin "L"
STOP mode
Release
STOP mode
STOP2 pin
STOP mode
Release
STOP mode
Figure 16-3 Priority of STOP pin and STOP2 to STOP5 pins
Table 16-1 Release level (edge) of STOP mode
Release level (edge)
Pin name
SYSCR1<RELM>="1"
(Note2)
SYSCR1<RELM>="0"
STOP
"H" level
Rising edge
STOP2
"L" level
Don’t use (Note1)
STOP3
"L" level
Don’t use (Note1)
STOP4
"L" level
Don’t use (Note1)
STOP5
"L" level
Don’t use (Note1)
Page 160
TMP86CH72FG
17. Vacuum Fluorescent Tube (VFT) Driver Circuit
The TMP86CH72FG features built-in high-breakdown voltage output buffers for directly driving fluorescent
tubes, and a display control circuit used to automatically transfer display data to the output port.
The segment and the digit, as it is the VFT drive circuit which included in the usual products, are not allocated.
The segment and the digit can be freely allocated in the timing (T0 to T15) which is specified according to the display tube types and the layout.
17.1 Functions
1. 32 high-breakdown voltage output buffers built-in.
• Large current output pin
16 (V0 to V15)
• Middle current output pin
16 (V16 to V31)
There is also the VKK pin used for the VFT drive power supply.
2. The dynamic lighting system makes it possible to select 1 to 16 digits (T0 to T15) by program.
3. Display data (64 bytes in DBR) are automatically transferred to the VFT output pin.
4. Brightness level can be adjusted in 7 steps using the dimmer function.
5. Display time are shown in Table 17-1.
Table 17-1 tdisp Time setting
SDT1
SDT2
tdisp Time
at 16 MHz
at 8 MHz
at 4 MHz
at 2 MHz
at 1 MHz
29/fc [s]
32 µs
64 µs
128 µs
256 µs
512 µs
210/fc [s]
64 µs
128 µs
256 µs
512 µs
1024 µs
10
211/fc [s]
128 µs
256 µs
512 µs
1024 µs
2048 µs
11
212/fc [s]
256 µs
512 µs
1024 µs
2048 µs
4096 µs
00
28/fc [s]
16 µs
32 µs
64 µs
128 µs
256 µs
29/fc [s]
32 µs
64 µs
128 µs
256 µs
512 µs
10
210/fc [s]
64 µs
128 µs
256 µs
512 µs
1024 µs
11
211/fc [s]
128 µs
256 µs
512 µs
1024 µs
2048 µs
00
01
0
01
1
Page 161
17. Vacuum Fluorescent Tube (VFT) Driver Circuit
17.2 Configuration
TMP86CH72FG
17.2 Configuration
Internal data bus
VFT status
register
Display data memory
VFT control register 1
VFT control register 2
VFT control register 3
(64 byte in DBR)
VFT timing generator
Dimer generating circuit
T0 to T15
Output data latch
Output data latch
High-breakdown voltage output
V0
V1
V2
V3
V4
V5
V15
V29
V30
Figure 17-1 Vacuum Fluorescent Display (VFT) Circuit
Page 162
V31
TMP86CH72FG
17.3 Control
The VFT driver circuit is controlled by the VFT control registers (VFTCR1, VFTCR2, VFTCR3). Reading VFT
status register (VFTSR) determines the VFT operating status.
Switching the mode from NORMAL1/2 to SLOW or STOP puts the VFT driver circuit into blanking state (BLK is
set to “1” ; values set in the VFT control registers except BLK is maintained), and sets segment outputs and digit outputs are cleared to “0”. Thus, ports P6 to P9 function as general-purpose output ports with pull-down.
VFT control register 1
VFTCR1
7
(002AH)
BLK
BLK
6
5
4
3
2
SDT1
1
0
"0"
(Initial value: 1000 0000)
0: Display enable
1: Disable
VFT display control
R/W
SDT2 = 0
SDT1
Display time select1 (tdisp)
(Display time of 1 digit)
9
SDT2 = 1
00
2 /fc
28/fc
01
210/fc
29/fc
11
R/W
10
10
2 /fc
2 /fc
11
212/fc
211/fc
Note 1: fc: High frequency clock [Hz]
Note 2: It is necessary to set diplay blanking staus by setting VFTCR1<BLK> to "1", when you would like to change display
time(SDT1) on VFT display operation. At the same time, please make sure not to modify SDT1.
Note 3: Reserved: Can not access.
VFTSR
(002DH)
7
6
5
4
3
2
1
WAIT
WAIT
0
(Initial value: 1000 0000)
VFT operational status monitor
0: VFT display in operation
1: VFT display operation disabled
Read
only
Note 1: VFTSR<WAIT> is initialized to 1 after resetting.
Note 2: When VFTCR1<BLK> is cleared to 0, WAIT flag is cleared to 0 at an end of display timing. And a VFT driving circuit is
enabled at an end of next display timing.
Note 3: During a VFT driving circuit is enabled, it is disabled just after an end of display timing (tdisp) by setting VFTCR1<BLK> to
1. And WAIT flag is set to 1 simultaneously.
Note 4: When a VFT driving circuit is enabled again, it is necessary that VFTCR1<BLK> is set to 1 after confirming
VFTSR<WAIT> is 1.
Page 163
17. Vacuum Fluorescent Tube (VFT) Driver Circuit
17.2 Configuration
TMP86CH72FG
VFT control register 2
VFTCR2
(002BH)
7
6
5
4
DIM
DIM
STA
3
2
1
0
STA
Dimmer time select
000: Reserved
001: (14/16) × tdisp (s)
010: (12/16) × tdisp (s)
011: (10/16) × tdisp (s)
100: (8/16) × tdisp (s)
101: (6/16) × tdisp (s)
110: (4/16) × tdisp (s)
111: (2/16) × tdisp (s)
Number of state (display)
00000: 1 display mode (T0)
00001: 2 display mode (T1 to T0)
00010: 3 display mode (T2 to T0)
00011: 4 display mode (T3 to T0)
00100: 5 display mode (T4 to T0)
00101: 6 display mode (T5 to T0)
00110: 7 display mode (T6 to T0)
00111: 8 display mode (T7 to T0)
01000: 9 display mode (T8 to T0)
01001: 10 display mode (T9 to T0)
01010: 11 display mode (T10 to T0)
01011: 12 display mode (T11 to T0)
01100: 13 display mode (T12 to T0)
01101: 14 display mode (T13 to T0)
01110: 15 display mode (T14 to T0)
01111: 16 display mode (T15 to T0)
Others: Reserved
(Initial value: 0010 0000)
R/W
Note 1: Even if a number of the display digit is set a pin which is equal to the digit dose not output.
It is necessary to write data to the data buffer which corresponds to the digit according to the display timing (T0 to T15).
Page 164
TMP86CH72FG
VFT control register 3
VFTCR3
(002CH)
7
6
5
4
3
OWSEL
SDT2
HVTR0
OWSEL
Display time select 2 (tdisp)
(Display time of 1 digit)
2
1
0
-
HVTR0
SDT2
(Initial value: 0000 0000)
SDT1 = “00”
SDT1 = “01”
SDT1 = “10”
SDT1 = “11”
0
29/fc [s]
210/fc [s]
211/fc [s]
212/fc [s]
1
28/fc [s]
29/fc [s]
210/fc [s]
211/fc [s]
0
Tr normal mode
typ. 150 ns (VDD = 3 V, Vkk = −35 V)
1
Tr increment mode
typ. 3 µs (VDD = 3 V, Vkk = −35 V)
P6 to P9 Ports Tr time select
Output waveform select
(Select grid or segment)
R/W
R/W
GRID output (Dimmer enable)
SEG output
00000
P60
P61 to P97
00001
P60 to P61
P62 to P97
00010
P60 to P62
P63 to P97
00011
P60 to P63
P64 to P97
00100
P60 to P64
P65 to P97
00101
P60 to P65
P66 to P97
00110
P60 to P66
P67 to P97
00111
P60 to P67
P70 to P97
01000
P60 to P70
P71 to P97
01001
P60 to P71
P72 to P97
01010
P60 to P72
P73 to P97
R/W
01011
P60 to P73
P74 to P97
01100
P60 to P74
P75 to P97
01101
P60 to P75
P76 to P97
01110
P60 to P76
P77 to P97
01111
P60 to P77
P80 to P97
10000
Reserved
Reserved
to
to
to
11111
Reserved
Reserved
Note 1: It is possible to reduce the VFT port noise by using Tr increment mode. When Tr increment mode is enabled, a time of Tr
is increased and also Tf. Therefore, the display time and dimmer value should be decided with the stray capacitor on a
PCB. Otherwise the switching timing between grid and segment is overlapped each other and a VFT display is dimmed.
Please confirm a VFT display with your set.
Page 165
17. Vacuum Fluorescent Tube (VFT) Driver Circuit
17.2 Configuration
TMP86CH72FG
17.3.1 Setting of Display mode
VFT display mode is set by VFT control register 1 (VFTCR1), VFT control register 2 (VFTCR2) and VFT
control register 3 (VFTCR3). VFT control register 1 (VFTCR1) sets 1 display time (tdisp) and the number of
display lines (VSEL), VFT control register 2 (VFTCR2) sets dimmer timer (DIM) and state (STA) and VFT
control register 3 (VFTCR3) sets Port Tr mode (HVTR0/1). (BLK of VFTCR1 must be set to “1”.) The segments and the digits are not fixed, so that they can be freely allocated. However the number of states must be
specified according to the number of digits of VFT which you use. Thought the layout of VFT display mode is
freely allocated, the followings are recommended; usually, large current output (V0 to V15) is used for a digit,
and middle current output (V16 to V31) is used for a segment.
In case of changeing the setting of dimmer time (DIM) in display-on, it is available to change whenever the
BLK status is "0".
17.3.2 Display data setting
Data are converted into VFT display data by instructions. The converted data stored in the display data buffer
(addresses 0F80H to 0FBFH in DBR) are automatically transferred to the VFT driver circuit (V0 to V31), then
transferred to the high-breakdown voltage output buffer. Thus, to change the display pattern, just change the
data in the display data buffer.
Bits in the VFT segment (dot) and display data area correspond one to one. When data are set to 1, the segments corresponding to the bits light. The display data buffer is assigned to the DBR area shown in Figure 172. (The display data buffer can not be used as data memory)
Bit
Output pin
0
7
0
7
0
7
0
7
Timing
0F80
0F90
0FA0
0FB0
T0
0F81
0F91
0FA1
0FB1
T1
0F82
0F92
0FA2
0FB2
T2
0F83
0F93
0FA3
0FB3
T3
0F84
0F94
0FA4
0FB4
T4
0F85
0F95
0FA5
0FB5
T5
0F86
0F96
0FA6
0FB6
T6
0F87
0F97
0FA7
0FB7
T7
0F88
0F98
0FA8
0FB8
T8
0F89
0F99
0FA9
0FB9
T9
0F8A
0F9A
0FAA
0FBA
T10
0F8B
0F9B
0FAB
0FBB
T11
0F8C
0F9C
0FAC
0FBC
T12
0F8D
0F9D
0FAD
0FBD
T13
0F8E
0F9E
0FAE
0FBE
T14
0F8F
0F9F
0FAF
0FBF
T15
V0
V7
V8
V15
V16
V23
V24
V31
Figure 17-2 VFT Display Data Buffer Memory (DBR)
Note: Contents in data memory is cleared ( unknown data ) after power-on.
Page 166
TMP86CH72FG
17.4 Display Operation
As the above-mentioned, the segment and the digit are not allocated. After setting of the display timing for the
number of digits according to the using VFT and storing the segment and digit data according to the respective timings, clearing VFTCR1<BLK> to 0 starts VFT display.
Figure 17-3 shows the VFT drive pulse and Figure 17-4, Figure 17-5 show the display operation.
Dimmer time (DIM)
Vn
Vn − 1
Vn − 2
Vn − 15
V31 to Vn+1
On display time (tdisp)
DIM [s]
toff = tdisp/16 + 2/fc [s]
Vn
Note: 0
n
Vn − 1
V31 to Vn+1
On display time (tdisp)
Figure 17-3 VFT Drive Wafeform and Display Timing
Page 167
15
17. Vacuum Fluorescent Tube (VFT) Driver Circuit
17.2 Configuration
TMP86CH72FG
17.5 Example of Display Operation
17.5.1 For Conventional type VFT
When using the conventional type VFT, the output timing of the digits is specified to output 1 digit for 1 timing. Data must be set to output the pins which are specified to the digit in sequence. The following figure
shows a data allocation of the display data buffer (DBR) and the output timing when VFT of 10 digits is used
and V0 to V9 pins are allocated as the digit outputs. (When data is first written by the data buffer which corresponds to the digit pin, it is unnecessary to rewrite the data later.)
T
9 8 7 6 5 4 3 2 1 0
Add- 0 0 0 0 0 0 0 0 0 0
ress F F F F F F F F F F
9 9 8 8 8 8 8 8 8 8
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
9 8 7 6 5 4 3 2 1 0
V0
0 0 0 0 0 0 0 1
LSB
V1
V2
0 0 0 0 0 1 0 0
V3
0 0 0 0 1 0 0 0
V4
0 0 0 1 0 0 0 0
V5
0 0 1 0 0 0 0 0
V6
V7
G0
0 0 0 0 0 0 1 0
G1
G2
G3
G4
G5
0 1 0 0 0 0 0 0
G6
1 0 0 0 0 0 0 0
MSB
V8
LSB 0 1
V9
1 0
SEG
*
*
SEG
*
*
SEG
*
*
SEG
*
*
SEG
*
*
SEG
MSB *
*
G7
G8
G9
SEG (Write change by display data)
Figure 17-4 Example of Conventional type VFT driver pulse
Page 168
TMP86CH72FG
17.5.2 For Grid scan type VFT
When using the grid scan type VFT, two or more grids must be simultaneously selected to turn the display
pattern which contains two or more grids on. Additionally, the timing and the data must be determined to set
the grid scan mode as follows.
• When the display pattern which is fully set in the respective grids is turned on, only the grids which
correspond as ever must be scanned in sequence to turn on the display pattern. (timing of T8 to T3 in
the following figure)
• When the display pattern which contains two or more grids is turned on, two or more corresponding
grids are simultaneously selected to turn on the display pattern. (timing of T2 to T0 in the following
figure)
T
8 7 6 5 4 3 2 1 0
T8
T7
T6
T5
T4
T3
T2
T1
0 0 0 0 0 0 0 0 0
Address F F F F F F F F F
8 8 8 8 8 8 8 8 8
8 7 6 5 4 3 2 1 0
V0
LSB
1 0 0 0 0 0 1 0 1
V1
0 1 0 0 0 0 1 0 1
V2
0 0 1 0 0 0 0 0 1
V3
0 0 0 1 0 0 0 1 1
V4
0 0 0 0 1 0 0 1 1
V5
0 0 0 0 0 1 0 1 1
G0
G1
G2
G3
G4
G5
MSB
SEG (a
g (Dig 1
6))
S1
S2
S3
S4
Figure 17-5 Grid Scan Type Display Vacuum Fluorescent Tube Ware
Page 169
T0
17. Vacuum Fluorescent Tube (VFT) Driver Circuit
17.2 Configuration
TMP86CH72FG
17.6 Port Function
17.6.1 High-breakdown voltage buffer
To drive fluorescent display tube, clears the port output latch to “0”. The port output latch is initialized to 0 at
reset.
Precaution for using as general-purpose I/O pins are follows.
Note:When not using a pin which is pulled down (RK = typ. 80 kΩ) to pin VKK , it must be set to open. It is necessary to clear the port output latch and the data buffer memory (DBR) to “0”.
17.6.1.1 Ports P6 to P9
When a part of P6 to P9 is used as the input/output pin (VFT driver in operation), the data buffer memory (DBR) of the segment which is also used as the input/output pin must be cleared to “0”.
17.6.2 Caution
When a pin which is pulled down to pin VKK is used as usual output or input, the following cautions are
required.
17.6.2.1 When outputting
When level “L” is output, a port which is pulled down to pin VKK is pin VKK voltage. Such processes
as clamping with the diode as shown in Figure 17-6 (a) are necessary to prevent pin VKK voltage applying to the external circuit.
17.6.2.2 When inputting
When the external data is input, the port output latch is cleared to “0”.
The input threshold is the same as that of the other usual input/output port. However it is necessary to
drive RK(typ. 80 kΩ) sufficiently because of pulled down to pin VKK.
VDD
RK
VDD
R
R
RK
VKK
VKK
R1
R1
(a) at output
(b) at input
Figure 17-6 External Circuit Interface
Page 170
TMP86CH72FG
19. Electrical Characteristics
19.1 Absolute Maximum Ratings
The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant.
Any one of the ratings must not be exceeded. If any absolute maximum ratings is exceeded, a device may break
down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus,
when designing products, which include this device, ensure that no absolute maximum rating value will ever be
exceeded.
(VSS = 0 V)
Parameter
Symbol
Pins
Ratings
Unit
Supply voltage
VDD
−0.3 to 6.5
V
Input voltage
VIN
−0.3 to VDD + 0.3
V
VOUT1
−0.3 to VDD + 0.3
V
VOUT2
Sink open drain port
VDD − 41 to VDD + 0.3
V
IOUT1
P1, P2, P4 (P43 to P47), P5 ports
5
IOUT2
P4 (P40, P41) port
40
IOUT3
P1, P4, P5 ports
−3
IOUT4
P6, P7 ports
−30
IOUT5
P8, P9 ports
−20
120
Output voltage
IOL
Output current (Per 1 pin)
IOH
IOL
Σ IOUT1
P1, P2, P4, P5 ports
IOH
Σ IOUT2
P6, P7, P8, P9 ports
Output current (Total)
−120
Power dissipation [Topr = 25°C]
PD
1200
Soldering temperture (Time)
Tsld
260 (10 s)
Storage temperature
Tstg
−55 to 125
Operating temperature
Topr
−30 to 70
Note 1: All VDDs should be connected externally for keeping the same voltage level.
Note 2: Power Dissipation (PD): For PD, it is necessary to decrease −11.5 mW/°C.
Page 175
mA
mW
°C
19. Electrical Characteristics
19.1 Absolute Maximum Ratings
TMP86CH72FG
19.2 Operating Conditions
The Operating Conditions shows the conditions under which the device be used in order for it to operate normally
while maitaining its quality. If the device is used outside the range of Operating Conditions (power supply voltage,
operating temperature range, or AC/DC rated values), it may operate erratically. Therefore, when designing your
application equipment, always make sure its intended working conditions will not exceed the range of Operating
Conditions.
Parameter
Symbol
Pins
Condition
Min
Max
Unit
NORMAL1/2 modes
fc = 16 MHz
4.5
IDLE1/2 modes
NORMAL1/2 modes
Supply voltage
fc = 8 MHz
VDD
IDLE1/2 modes
fs =
32.768 kHz
SLOW mode
5.5
2.7
SLEEP mode
V
STOP mode
Output voltage
VOUT3
VDD − 38
Sink open drain pins
VIH1
Except hysteresis input
VDD × 0.70
VIH2
Hysteresis input
VDD × 0.75
VIL1
Except hysteresis input
Input high voltage
0
Hysteresis input
VDD = 2.7 V to 5.5 V
fc
XIN, XOUT
Clock frequency
VDD × 0.25
8.0
1.0
VDD = 4.5 V to 5.5 V
fs
VDD
VDD × 0.30
Input low voltage
VIL2
VDD
XTIN, XTOUT
30.0
Page 176
MHz
16.0
34.0
kHz
TMP86CH72FG
19.3 How to Calculate Power Consumption
The share of VFT driver loss (VFT driver output loss + pull-down resistor (RK) loss) in power consumption Pmax
of TMP86CH72FG is high. When using a fluorescent display tube with a large number of segments, the maximum
power consumption PD must not be exceeded.
19.3.1 Power consumption Pmax = Operating power consumption
+ Normal output port loss + VFT driver loss.
Where,
Operating power consumption: VDD × IDD
Normal output port loss: Σ IOUT1 × 0.4
VFT driver loss: VFT driver output loss + pull-down resistor (RK) loss
Example:
When Ta = −10°C to 50°C (When using a fluorescent display tube with a conventional type which can use
only one grid output at the same time.) and a fluorescent display tube with segment output = 3 mA, digit output
= 12 mA, VKK = −34.5 V is used.
Operating conditions ; VDD = 5 V ± 10%, fc = 8 MHz, VFT dimmer time (DIM) = (14/16) × tSEG,
Power consumption Pmax = (1) + (2) + (3)
Where,
1. Operating power consumption: VDD × IDD = 5.5 V × 10 mA = 55 mW
2. Normal output port loss: Σ IOUT2 × 0.4 = 60 mA × 0.4 V = 24 mW
3. VFT driver loss:
Segment pin = 3 mA × 2 V × Number of segments X = 6 mW × X
Grid pin = 12 mA × 2 V × 14/16 (DIM) × Number of grids Y = 21 mW × Y
RK loss = (5.5 V + 34.5 V)2 / 50 kΩ × (Number of segments X + Number of grids Y)
= 32 mW × (X + Y)
Therefore, Pmax = 55 mW + 24 mW + 6 mW × X + 21 mW + 32 mW × (X + Y)
= 132 mW + 38 mWXÅc
Maximum power consumption PD when Ta = 50°C is determined by the following equation;
PD = 1200 mW − (11.5 mW × 25°C) = 912.5 mW
The number of segments X that can be lit is:
PD > Pmax
912.5 mW > 132 + 38X
20.53 > X
Thus, a fluorescent display tube with less than 20 segments can be used. If a fluorescent display tube with 20
segments or more is used, the number of segments to be lit must be kept to less than 20 by software.
Page 177
19. Electrical Characteristics
19.1 Absolute Maximum Ratings
TMP86CH72FG
19.4 DC Characteristics
19.4.1 DC Characteristics (1) (VDD = 5 V)
[Condition] VDD = 5.0 V ± 10%, VSS = AVSS = 0 V, Topr = −30 to 70°C (Typ.: VDD = 5.0 V, Topr = 25°C, Vin = 5.0 V/0 V)
Parameter
Symbol
Pins
VHS
Hysteresis input
IIN1
TEST
IIN2
Sink open-drain, Tri-st
IIN3
RESET, STOP
Input resistance
RIN
RESET pull-up
Pull-down resistance (Note4)
RK
Hysteresis voltage
Input current
Condition
VDD = 5.5 V, VIN = 5.5 V/0 V
Min
Typ.
Max
Unit
–
0.9
–
V
–
–
±2
µA
100
220
450
Sink open-drain
VDD = 5.5 V, VKK = −30 V
50
–
120
ILO1
Sink open-drain, Tri-st
VDD = 5.5 V, VOUT = 5.5 V
–
–
±2
ILO2
Sink open-drain
VDD = 5.5 V, VKK = −32 V
–
–
±2
Output high voltage
VOH
Tri-st port
VDD = 4.5 V, IOH = −0.7 mA
4.1
–
–
Output low voltage
VOL
Except XOUT (P40,
P41 port)
VDD = 4.5 V, IOL = 1.6 mA
–
–
0.4
Output leakage current
IOH1
P6, P7 port
VDD = 4.5 V, VOH = 2.4 V
−18
−28
–
IOH2
P8, P9, PD port
VDD = 4.5 V, VOH = 2.4 V
−9
−14
–
IOL
High-current (P40, P41
port)
VDD = 4.5 V, VOL = 1.0 V
–
20
–
fc = 16.0 MHz
fs = 32.768 kHz
–
12
18
–
6
9
Supply current in
NORMAL1/2 modes
fc = 8.0 MHz
fs = 32.768 kHz
fc = 16.0 MHz
fs = 32.768 kHz
Supply current in IDLE0/1/2
modes
IDD
Supply current in
NORMAL1/2 modes
Supply current in STOP
mode
µA
V
Output high current
Output low current
kΩ
AD
converte
disable
(IREF off)
–
6
9
–
3
4.5
AD
converter
enable
–
13
19
–
7
10
AD
converter
disable
–
fc = 8.0 MHz
fs = 32.768 kHz
fc = 16.0 MHz
fs = 32.768 kHz
fc = 8.0 MHz
fs = 32.768 kHz
Topr = to 50°C
Topr = to 70°C
mA
–
Note 1: Typical values show those at Topr = 25°C, VDD = 5 V.
Note 2: Input current (IIN1, IIN3) ; The current through pull-up or pull-down resistor is not included.
Note 3: IDD does not include IREF current.
Note 4: Topr = −10 to 70°C
Page 178
5
µA
0.5
10
TMP86CH72FG
19.4.2 DC Characteristics (2) (VDD = 3 V)
[Condition] VDD = 3.0 V ± 10%, VSS = AVSS = 0 V, Topr = −30 to 70°C (Typ.: VDD = 3.0 V, Topr = 25°C, Vin = 3.0 V/0 V)
Parameter
Symbol
Pins
VHS
Hysteresis input
IIN1
TEST
IIN2
Sink open-drain, Tri-st
IIN3
RESET, STOP
Input resistance
RIN
RESET pull-up
Pull-down resistance (Note5)
RK
Hysteresis voltage
Input current
Condition
VDD = 3.3 V, VIN = 3.3 V/0 V
Min
Typ.
Max
Unit
–
0.4
–
V
–
–
±2
µA
100
220
450
Sink open-drain
VDD = 3.3 V, VKK = −30 V
45
–
115
ILO1
Sink open-drain, Tri-st
VDD = 3.3 V, VOUT = 3.3 V/0 V
–
–
±2
ILO2
Sink open-drain
VDD = 3.3 V, VKK = −32 V
–
–
±2
Output high voltage
VOH
Tri-st
VDD = 2.7 V, IOH = −0.6 mA
2.3
–
–
Output low voltage
VOL
Except XOUT (P40,
P41 port)
VDD = 2.7 V, IOL = 0.9 mA
–
–
0.4
Output leakage current
kΩ
V
IOH1
P6, P7 port
VDD = 2.7 V, VOH = 1.5 V
−5.5
−8
–
IOH2
P8, P9, PD port
VDD = 2.7 V, VOH = 1.5 V
−3
−4.5
–
IOL
High-current (P40, P41
port)
VDD = 2.7 V, VOL = 1.0 V
–
6
–
Supply current in
NORMAL1/2 modes
fc = 8.0 MHz
fs = 32.768 kHz
–
3
4.5
Supply current in IDLE0/1/2
modes
fc = 8.0 MHz
fs = 32.768 kHz
–
2
2.5
Supply current in
NORMAL1/2 modes
fc = 8.0 MHz
fs = 32.768 kHz
–
3.5
5
–
30
60
–
15
30
Output high current
Output low current
IDD
AD
converter
disable
(IREF off)
AD
converter
enable
Supply current in SLOW1/2
modes
fs = 32.768 kHz
Supply current in SLEEP0/1/
2 modes
Supply current in STOP
mode
µA
AD
converter
disable
Topr = to 50°C
–
Topr = to 70°C
–
5
0.5
Note 1: Typical values show those at Topr = 25°C, VDD = 3 V.
Note 2: Input current (IIN1, IIN3) ; The current through pull-up or pull-down resistor is not included.
Note 3: IDD does not include IREF current.
Note 4: The supply currents of SLOW2 and SLEEP2 modes are equivalent to IDLE0, 1, 2.
Note 5: Topr = −10 to 70°C
Page 179
10
mA
µA
19. Electrical Characteristics
19.1 Absolute Maximum Ratings
TMP86CH72FG
19.5 AD Characteristics
(VSS = 0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −30 to 70°C)
Parameter
Symbol
Analog reference voltage
Analog reerence voltage range
Analog input voltage
Analog supply current
Condition
Min
Typ.
Max
VAREF
VDD − 1.5
–
VDD
∆VAREF
3.0
–
–
0
–
VAREF
–
0.6
1.0
VAIN
IREF
VDD = VAREF = 5.5 V,
VSS = AVSS = 0.0 V
Non linearity error
–
–
±1
Zero point error
VDD = VAREF = 4.5 to 5.5 V,
–
–
±1
Full scale error
VSS = AVSS = 0.0 V
–
–
±1
–
–
±2
Total error
Unit
V
mA
LSB
(VSS = 0 V, 2.7 V ≤ VDD < 4.5 V, Topr = −30 to 70°C)
Parameter
Symbol
Typ.
Max
Analog reference voltage
VAREF
VDD − 1.5
–
VDD
∆VAREF
2.5
–
–
Analog input voltage
VAIN
0
–
VAREF
Analog supply current
IREF
–
0.5
0.8
Analog reerence voltage range
Condition
VDD = VAREF = 4.5 V,
VSS = AVSS = 0.0 V
Min
–
–
±1
Zero point error
VDD = VAREF = 2.7 to 4.5 V,
–
–
±1
Full scale error
VSS = AVSS = 0.0 V
–
–
±1
–
–
±2
Non linearity error
Total error
Unit
V
mA
LSB
Note 1: Total errors includes all errors, except quantization error, and is defined as a maximum deviation from the ideal conversion
line.
Note 2: Conversion time is different in recommended value by power supply voltage. About conversion time, please refer to “ Register Configuration”.
Note 3: Please use input voltage to AIN input pin in limit of VAREF - VSS. When voltage of range outside is input, conversion value
becomes unsettled and gives affect to other channel conversion value.
Note 4: Analog Reference Voltage Range:∆VAREF = VAREF - VSS
Page 180
TMP86CH72FG
19.6 AC Characteristics
(VSS = 0 V, 4.5 V ≤ VDD ≤ 5.5 V, Topr = −30 to 70°C)
Parameter
Symbol
Conditions
Min
Typ.
Max
0.25
–
4
Unit
NORMAL1/2 modes
IDLE0/1/2 modes
Machine cycle time
µs
tcyc
SLOW1/2 modes
117.6
–
133.3
For external clock operation
(XIN input)
fc = 16 MHz
–
31.25
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
SLEEP0/1/2 modes
High level clock pulse width
tWCH
Low level clock pulse width
tWCL
High level clock pulse width
tWCH
Low level clock pulse width
tWCL
(VSS = 0 V, 2.7 V ≤ VDD ≤ 4.5 V, Topr = −30 to 70°C)
Parameter
Symbol
Conditions
Min
Typ.
Max
Unit
0.5
–
8
117.6
–
133.3
For external clock operation
(XIN input)
fc = 8 MHz
–
62.5
–
ns
For external clock operation
(XTIN input)
fs = 32.768 kHz
–
15.26
–
µs
NORMAL1/2 modes
IDLE0/1/2 modes
Machine cycle time
µs
tcyc
SLOW1/2 modes
SLEEP0/1/2 modes
High level clock pulse width
tWCH
Low level clock pulse width
tWCL
High level clock pulse width
tWCH
Low level clock pulse width
tWCL
Page 181
19. Electrical Characteristics
19.1 Absolute Maximum Ratings
TMP86CH72FG
19.7 HSIO AC Characteristics
(VSS = 0 V, 2.7 V ≤ VDD ≤ 5.5 V, Topr = −30 to 70°C)
Parameter
Symbol
SCK output period (Internal clock)
Conditions
TSCK1
SCK output low width (Internal clock)
TSCL1
SCK output high width (Internal clock)
TSCH1
SCK output period (Internal clock)
TSCK2
SCK output low width (Internal clock)
TSCL2
SCK output high width (Internal clock)
TSCH2
SCK output period (Internal clock)
TSCK3
SCK output low width (Internal clock)
TSCL3
SCK output high width (Internal clock)
TSCH3
SCK input period (External clock)
TSCK4
SCK input low width (External clock)
TSCL4
SCK input low width (External clock)
8 MHz < fc ≤ 16 MHz
VDD = 4.5 V to 5.5 V
4 MHz < fc ≤ 8 MHz
VDD = 2.7 V to 5.5 V
fc ≤ 4 MHz
VDD = 2.7 V to 5.5 V
Min
Typ.
Max
16/fc
–
–
8/fc − 100 ns
–
–
8/fc − 100 ns
–
–
8/fc
–
–
4/fc − 100 ns
–
–
4/fc − 100 ns
–
–
4/fc
–
–
2/fc − 100 ns
–
–
2/fc − 100 ns
–
–
800
–
–
300 (Note1)
–
–
TSCH4
300 (Note1)
–
–
SI input setup time
TSUP
150
–
–
SI input hold time
THLD
150
–
–
SO output delay time
TDEL
–
–
200
–
–
100
–
–
100
16.5/fc
–
32.5/fc
Rising time
TR
Falling time
TF
fc ≤ 8 MHz (VDD = 2.7 V to 5.5 V)
fc ≤16 MHz (VDD = 4.5 V to 5.5 V)
VDD = 3.0 V, CL ≤ 50 pF (Note2)
TSODH
SO last bit hold time
Note 1: TSCKL, TSCKH ≥ 2.5/fc (High-frequency clock mode), TSCKL, TSCKH ≥ 2.5/fc (Low-frequency clock mode)
Note 2: CL, external capacitance
TSCK
TF
VDD × 0.8
SCK
TR
TSCL
VDD × 0.2
TSCH
SO
SI
TDEL
TSUP
THLD
Page 182
TSODH
Unit
s
ns
TMP86CH72FG
19.8 Recommended Oscillating Conditions
XIN
C1
XOUT
XTIN
C2
XTOUT
C1
(1) High-frequency oscillation
C2
(2) Low-frequency oscillation
Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these
factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the
device will actually be mounted.
Note 2: For the resonators to be used with Toshiba microcontrollers, we recommend ceramic resonators manufactured by
Murata Manufacturing Co., Ltd.
For details, please visit the website of Murata at the following URL:
http://www.murata.com
19.9 Handling Precaution
- The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown
below.
1. When using the Sn-37Pb solder bath
Solder bath temperature = 230 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
2. When using the Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature = 245 °C
Dipping time = 5 seconds
Number of times = once
R-type flux used
Note: The pass criteron of the above test is as follows:
Solderability rate until forming ≥ 95 %
- When using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition.
Page 183
19. Electrical Characteristics
19.9 Handling Precaution
TMP86CH72FG
Page 184
TMP86CH72FG
20. Package Dimensions
QFP64-P-1414-0.80C Rev 01
+0.08
−0.04
Unit: mm
Page 185
20. Package Dimensions
TMP86CH72FG
Page 186
This is a technical document that describes the operating functions and electrical specifications of the 8-bit
microcontroller series TLCS-870/C (LSI).
Toshiba provides a variety of development tools and basic software to enable efficient software
development.
These development tools have specifications that support advances in microcomputer hardware (LSI) and
can be used extensively. Both the hardware and software are supported continuously with version updates.
The recent advances in CMOS LSI production technology have been phenomenal and microcomputer
systems for LSI design are constantly being improved. The products described in this document may also
be revised in the future. Be sure to check the latest specifications before using.
Toshiba is developing highly integrated, high-performance microcomputers using advanced MOS
production technology and especially well proven CMOS technology.
We are prepared to meet the requests for custom packaging for a variety of application areas.
We are confident that our products can satisfy your application needs now and in the future.