TI TPS2205DB

TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
D
D
D
D
D
D
D
D
D
D
Fully Integrated VCC and Vpp Switching for
Dual-Slot PC Card Interface
Compatible with Controllers From Cirrus,
Ricoh, O2Micro, Intel, and Texas Instruments
3.3-V Low-Voltage Mode
Meets PC Card Standards
12-V Supply Can Be Disabled Except During
12-V Flash Programming
Short Circuit and Thermal Protection
30-Pin SSOP (DB) and 32-Pin TSSOP (DAP)
Compatible With 3.3-V, 5-V and 12-V PC Cards
Low rDS(on) (140-mΩ 5-V VCC Switch; 110-mΩ
3.3-V VCC Switch)
Break-Before-Make Switching
DB OR DF PACKAGE
(TOP VIEW)
5V
5V
A_VPP_PGM
A_VPP_VCC
A_VCC5
A_VCC3
12V
AVPP
AVCC
AVCC
AVCC
GND
NC
SHDN
3.3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
B_VPP_PGM
B_VPP_VCC
B_VCC5
B_VCC3
NC
12V
BVPP
BVCC
BVCC
BVCC
NC
OC
3.3V
3.3V
description
The TPS2205 PC Card power-interface switch
provides an integrated power-management
solution for two PC Cards. All of the discrete
power MOSFETs, a logic section, current limiting,
and thermal protection for PC Card control are
combined on a single integrated circuit (IC), using
the Texas Instruments LinBiCMOS process.
The circuit allows the distribution of 3.3-V, 5-V,
and/or 12-V card power, and is compatible with
many PCMCIA controllers. The current-limiting
feature eliminates the need for fuses, which
reduces component count and improves
reliability.
The TPS2205 is backward compatible with the
TPS2201, except that there is no VDD connection.
Bias current is derived from either the 3.3-V input
pin or the 5-V input pin. The TPS2205 also
eliminates the APWR_GOOD and BPWR_GOOD
pins of the TPS2201.
DAP PACKAGE
(TOP VIEW)
5V
5V
NC
A_VPP_PGM
A_VPP_VCC
A_VCC5
A_VCC3
12V
AVPP
AVCC
AVCC
AVCC
GND
SHDN
NC
3.3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5V
NC
B_VPP_PGM
B_VPP_VCC
B_VCC5
NC
B_VCC3
12V
BVPP
BVCC
BVCC
BVCC
OC
NC
3.3V
3.3V
NC – No internal connection
The TPS2205 features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. This
facilitates low-power system designs such as sleep mode and pager mode where only 3.3 V is available.
End equipment for the TPS2205 includes notebook computers, desktop computers, personal digital assistants
(PDAs), digital cameras, and bar-code scanners.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC SMALL OUTLINE
(DB)
PLASTIC SMALL OUTLINE
(DF)
TSSOP
(DAP)
– 40°C to 85°C
TPS2205IDBLE
TPS2205IDFLE
TPS2205IDAPR
CHIP FORM
(Y)
TPS2205Y
The DB package and the DF package are only available left-end taped and reeled (indicated by the LE suffix on the
device type; e.g., TPS2205IDBLE). The DAP package is only available taped and reeled (indicated by the R suffix
on the device type; e.g., TPS2205IDAPR).
typical PC card power-distribution application
Power Supply
12V
5V
3.3V
12 V
5V
3.3 V
SHDN
Supervisor
8
PCMCIA
Controller
Control Lines
OC
2
TPS2205
AVPP
AVCC
AVCC
Vpp1
Vpp2
VCC
VCC
PC
Card A
Vpp1
Vpp2
VCC
VCC
PC
Card B
AVCC
BVPP
BVCC
BVCC
BVCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
TPS2205Y chip information
This chip, when properly assembled, displays characteristics similar to those of the TPS2205. Thermal
compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
4
3
26
25
24
5V
5V
5
2
1
A_VPP_PGM
27
23
A_VPP_VCC
A_VCC5
6
A_VCC3
12V
22
7
AVPP
AVCC
8
21
144
AVCC
AVCC
9
20
GND
SHDN
3.3V
10
1
27
2
26
3
25
4
24
5
23
6
22
7
8
21
TPS2205Y
9
10
20
19
11
18
12
17
13
16
14
15
5V
B_VPP_PGM
B_VPP_VCC
B_VCC5
B_VCC3
12V
BVPP
BVCC
BVCC
BVCC
OC
3.3V
3.3V
19
11
12
18
13
15
14
16
17
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJ max = 150°C
142
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
DB, DF
DAP
A_VCC3
6
7
I
Logic input that controls voltage on AVCC (see TPS2205 Control-Logic table)
A_VCC5
5
6
I
Logic input that controls voltage on AVCC (see TPS2205 Control-Logic table)
A_VPP_PGM
3
4
I
Logic input that controls voltage on AVPP (see TPS2205 Control-Logic table)
A_VPP_VCC
AVCC
AVPP
4
5
I
Logic input that controls voltage on AVPP (see TPS2205 Control-Logic table)
9, 10, 11
10, 11, 12
O
Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
8
9
O
Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
B_VCC3
26
26
I
Logic input that controls voltage on BVCC (see TPS2205 Control-Logic table)
B_VCC5
27
28
I
Logic input that controls voltage on BVCC (see TPS2205 Control-Logic table)
B_VPP_PGM
29
30
I
Logic input that controls voltage on BVPP (see TPS2205 Control-Logic table)
B_VPP_VCC
28
29
I
Logic input that controls voltage on BVPP (see TPS2205 Control-Logic table)
BVCC
20, 21, 22
21, 22, 23
O
Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
BVPP
23
24
O
Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
SHDN
14
14
I
Logic input that shuts down the TPS2205 and set all power outputs to high-impedance
state
OC
18
20
O
Logic-level overcurrent reporting output that goes low when an overcurrent condition
exists
GND
12
13
3.3V
15, 16, 17
16, 17, 18
I
3.3-V VCC in for card power
1, 2, 30
1, 2, 32
I
5-V VCC in for card power
5V
Ground
12V
7, 24
8, 25
I
12-V VPP in for card power
NC
13, 19, 25
3, 15, 19,
27, 31
I
No internal connection
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range for card power: VI(5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
VI(3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
VI(12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 14 V
Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Output current (each card): IO(xVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
IO(xVPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
PACKAGE
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DB
1024 mW
8.2 mW/°C
655 mW
532 mW
DF
1158 mW
9.26 mW/°C
741 mW
602 mW
1625 mW
13 mW/°C
1040 mW
845 mW
6044 mW
48.36 mW/°C
3869 mW
3143 mW
DAP
No backplane
Backplane§
‡ These devices are mounted on an FR4 board with no special thermal considerations.
§ 2-oz backplane with 2-oz traces; 5.2-mm × 11-mm thermal pad with 6-mil solder; 0.18-mm diameter vias in a 3×6 array.
recommended operating conditions
Input voltage range, VI
Output current
MIN
MAX
UNIT
VI(5V)
VI(3.3V)
0
5.25
V
0
5.25
V
VI(12V)
IO(xVCC) at 25°C
0
13.5
V
1
A
IO(xVPP) at 25°C
Operating virtual junction temperature, TJ
– 40
150
mA
125
°C
electrical characteristics, TA = 25°C, VI(5V) = 5 V (unless otherwise noted)
dc characteristics
PARAMETER
TEST CONDITIONS
TPS2205
MIN
5 V to xVCC
3.3 V to xVCC
Switch resistances†
VO(xVPP)
VO(xVCC)
Ilk
lkg
II
IOS
3.3 V to xVCC
103
140
69
110
96
180
6
3.3 V to xVPP
6
12 V to xVPP
1
Ipp at 10 mA
ICC at 10 mA
Clamp low voltage
UNIT
mΩ
Ω
0.8
V
0.8
V
Ipp high-impedance
g
state
TA = 25°C
TA = 85°C
1
ICC high-impedance
g
state
TA = 25°C
TA = 85°C
1
VI(5V) = 5 V
VO(AVCC) = VO(BVCC) = 5 V,
VO(AVPP) = VO(BVPP) = 12 V
117
150
VI(5V) = 0,
VI(3.3V) = 3.3 V
VO(AVCC) = VO(BVCC) = 3.3 V,
VO(AVPP) = VO(BVPP) = 0
131
150
Shutdown mode
VO(BVCC) = VO(AVCC)
= VO(AVPP) = VO(BVPP) = Hi-Z
IO(xVCC)
IO(xVPP)
TJ = 85°C,
Output powered up into a short to GND
Leakage current
Short-circuit
output-current limit
VI(3.3 V) = 3.3 V
VI(3.3V) = 3.3 V
MAX
5 V to xVPP
Clamp low voltage
Input current
VI(5V) = 5 V,
VI(5V) = 0,
TYP
10
50
10
µA
50
µA
1
µA
1
2.2
A
120
400
mA
† Pulse-testing techniques are used to maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
electrical characteristics, TA = 25°C, VI(5V) = 5 V (unless otherwise noted)
logic section
PARAMETER
TEST CONDITIONS
TPS2205
MIN
MAX
Logic input current
1
Logic input high level
2
0.8
Logic output high level
Logic output low level
IO = 1mA
IO = 1mA
IO = 1mA,
µA
V
Logic input low level
VI(5V)= 5 V,
VI(5V)= 0 V,
VI(3.3V) = 3.3 V
UNIT
V
VI(5V)–0.4
V
VI(3.3V)–0.4
0.4
V
switching characteristics†‡
PARAMETER
tr
tf
tpd
d
MIN
TYP
Output rise time
VO(xVCC)
VO(xVPP)
1.2
Output fall time
VO(xVCC)
VO(xVPP)
10
5
MAX
UNIT
ms
14
4.4
ms
VI(x_VPP_PGM)
(
G ) to VO(xVPP)
O(
)
ton
toff
18
ms
ton
toff
6.5
ms
(3 3 V),
V) VI(5V)
VI(
VCC ) to xVCC (3.3
I( V) = 5 V
I(x_VCC5)
20
ms
VI(
VCC5) to xVCC (5 V)
I(x_VCC5)
ton
toff
5.7
ms
25
ms
VI(
(3 3 V),
V) VI(5V) = 0
VCC5) to xVCC (3.3
I(x_VCC5)
ton
toff
6.6
ms
21
ms
Propagation delay (see Figure 1)
† Refer to Parameter Measurement Information
‡ Switching Characteristics are with CL = 150 µF.
6
TPS2205
TEST CONDITIONS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
electrical characteristics, TA = 25°C, VI(5V) = 5 V (unless otherwise noted)
dc characteristics
PARAMETER
TPS2205Y
TEST CONDITIONS
MIN
5 V to xVCC
VO(xVPP)
VO(xVCC)
Ilk
lkg
3.3 V to xVCC
VI(5V) = 5 V,
VI(5V) = 0,
VI(3.3 V) = 3.3 V
VI(3.3V) = 3.3 V
UNIT
mΩ
69
96
5 V to xVPP
4.74
3.3 V to xVPP
4.74
12 V to xVPP
0.724
Clamp low voltage
Ipp at 10 mA
ICC at 10 mA
Clamp low voltage
Leakage current
MAX
103
3.3 V to xVCC
Switch resistances§
TYP
Ipp High-impedance state
ICC High-impedance state
TA = 25°C
TA = 25°C
VI(5V) = 5 V
VO(AVCC) = VO(BVCC) = 5 V,
VO(AVPP) = VO(BVPP) = 12 V
Ω
0.275
V
0.275
V
1
µA
1
117
µA
VI(5V) = 0,
VO(AVCC) = VO(BVCC) = 3.3 V,
131
VI(3.3V) = 3.3 V
VO(AVPP) = VO(BVPP) = 0
§ Pulse-testing techniques are used to maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
II
Input current
switching characteristics†‡
PARAMETER
TPS2205Y
TEST CONDITIONS
MIN
TYP
tr
Output rise time
VO(xVCC)
VO(xVPP)
1.2
tf
Output fall time
VO(xVCC)
VO(xVPP)
10
tpd
d
5
MAX
UNIT
ms
14
ton
toff
4.4
ms
VI(
VPP PGM) to VO(xVPP)
O( VPP)
I(x_VPP_PGM)
18
ms
6.5
ms
VI(x_VCC5)
(3 3 V),
V) VI(5V)
(
CC ) to xVCC (3.3
( )=5V
ton
toff
20
ms
VI(
VCC5) to xVCC (5 V)
I(x_VCC5)
ton
toff
5.7
ms
25
ms
VI(
(3 3 V),
V) VI(5V) = 0
VCC5) to xVCC (3.3
I(x_VCC5)
ton
toff
6.6
ms
21
ms
Propagation delay (see Figure 1)
† Refer to Parameter Measurement Information
‡ Switching Characteristics are with CL = 150 µF.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
Vpp
VCC
CL
CL
LOAD CIRCUIT
LOAD CIRCUIT
VDD
VX_VPP_PGM
50%
50%
VDD
50%
Vx_VCCx
50%
GND
VO(xVPP)
GND
toff
ton
toff
ton
VI(12V)
90%
10%
VI(5V)
90%
VO(xVCC)
10%
GND
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
FIGURE
xVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch, VI(5V) = 5 V
2
xVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch, VI(5V) = 5 V
3
xVCC Propagation Delay and Rise Time With 150-µF Load, 3.3-V Switch, VI(5V) = 5 V
4
xVCC Propagation Delay and Fall Time With 150-µF Load, 3.3-V Switch, VI(5V) = 5 V
5
xVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch, VI(5V) = 0
6
xVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch, VI(5V) = 0
7
xVCC Propagation Delay and Rise Time With 150-µF Load, 3.3-V Switch, VI(5V) = 0
8
xVCC Propagation Delay and Fall Time With 150-µF Load, 3.3-V Switch, VI(5V) = 0
xVCC Propagation Delay and Rise Time With 1-µF Load, 5-V Switch
8
9
10
xVCC Propagation Delay and Fall Time With 1-µF Load, 5-V Switch
11
xVCC Propagation Delay and Rise Time With 150-µF Load, 5-V Switch
12
xVCC Propagation Delay and Fall Time With 150-µF Load, 5-V Switch
13
xVPP Propagation Delay and Rise Time With 1-µF Load, 12-V Switch
14
xVPP Propagation Delay and Fall Time With 1-µF Load, 12-V Switch
15
xVPP Propagation Delay and Rise Time With 150-µF Load, 12-V Switch
16
xVPP Propagation Delay and Fall Time With 150-µF Load, 12-V Switch
17
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GND
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
x_VCC5 (2 V/div)
x_VCC5 (2 V/div)
xVCC (2 V/div)
0
1
2
3
xVCC (2 V/div)
4
5
6
7
8
9
0
5
10
15
20
25
30
35
40
t – Time – ms
t – Time – ms
Figure 2. xVCC Propagation Delay and
Rise Time With 1-µF Load, 3.3-V Switch,
(VI(5 V) = 5 V)
Figure 3. xVCC Propagation Delay and
Fall Time With 1-µF Load, 3.3-V Switch,
(VI(5 V) = 5 V)
45
x_VCC5 (2 V/div)
x_VCC5 (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2
3
4
5
6
7
8
9
0
t – Time – ms
5
10
15
20
25
30
35
40
45
t – Time – ms
Figure 4. xVCC Propagation Delay and
Rise Time With 150-µF Load, 3.3-V Switch,
VI(5 V) = 5 V
POST OFFICE BOX 655303
Figure 5. xVCC Propagation Delay and
Fall Time With 150-µF Load, 3.3-V Switch,
VI(5 V) = 5 V
• DALLAS, TEXAS 75265
9
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
x_VCC5 (2 V/div)
x_VCC5 (2 V/div)
xVCC (2 V/div)
0
1
2
3
xVCC (2 V/div)
4
5
6
7
8
9
0
5
10
15
20
25
30
35
40
t – Time – ms
t – Time – ms
Figure 6. xVCC Propagation Delay and
Rise Time With 1-µF Load, 3.3-V Switch,
VI(5 V) = 0
Figure 7. xVCC Propagation Delay and
Fall Time With 1-µF Load, 3.3-V Switch,
VI(5 V) = 0
45
x_VCC5 (2 V/div)
x_VCC5 (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2
3
4
5
6
7
8
9
0
t – Time – ms
10
15
20
25
30
35
40
45
t – Time – ms
Figure 8. xVCC Propagation Delay and
Rise Time With 150-µF Load, 3.3-V Switch,
VI(5 V) = 0
10
5
POST OFFICE BOX 655303
Figure 9. xVCC Propagation Delay and
Fall Time With 150-µF Load, 3.3-V Switch,
VI(5 V) = 0
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
x_VCC5 (2 V/div)
x_VCC5 (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2
3
4
0
5
10
t – Time – ms
15
20
25
30
35
40
45
t – Time – ms
Figure 10. xVCC Propagation Delay and
Rise Time With 1-µF Load, 5-V Switch
Figure 11. xVCC Propagation Delay and
Fall Time With 1-µF Load, 5-V Switch
x_VCC5 (2 V/div)
x_VCC5 (2 V/div)
xVCC (2 V/div)
xVCC (2 V/div)
0
1
2
3
4
5
6
7
8
9
0
t – Time – ms
5
10
15
20
25
30
35
40
45
t – Time – ms
Figure 12. xVCC Propagation Delay and
Rise Time With 150-µF Load, 5-V Switch
POST OFFICE BOX 655303
Figure 13. xVCC Propagation Delay and
Fall Time With 150-µF Load, 5-V Switch
• DALLAS, TEXAS 75265
11
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
x_VPP_PGM (2 V/div)
X_VPP_PGM (2 V/div)
xVPP (5 V/div)
xVPP (5 V/div)
0
0.2
0.4 0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
1
2
t – Time – ms
3
4
5
6
7
8
9
t – Time – ms
Figure 14. xVPP Propagation Delay and
Rise Time With 1-µF Load, 12-V Switch
Figure 15. xVPP Propagation Delay and
Fall Time With 1-µF Load, 12-V Switch
x_VPP_PGM (2 V/div)
x_VPP_PGM (2 V/div)
xVPP (5 V/div)
xVPP (5 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
t – Time – ms
15
20
25
30
35
40
45
t – Time – ms
Figure 16. xVPP Propagation Delay and
Rise Time With 150-µF Load, 12-V Switch
12
10
POST OFFICE BOX 655303
Figure 17. xVPP Propagation Delay and
Fall Time With 150-µF Load, 12-V Switch
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IDD
IDD
Supply current
vs Junction temperature
18
Supply current, VI(5V) = 0, VI(12V) =0,VO(AVCC) = VO(BVCC) = 3.3 V
vs Junction temperature
19
rDS(on)
Static drain-source on-state resistance, 3.3-V switch, VI(5V) = 5 V
vs Junction temperature
20
rDS(on)
Static drain-source on-state resistance, 3.3-V switch, VI(5V) = 0
vs Junction temperature
21
rDS(on)
Static drain-source on-state resistance, 5-V switch
vs Junction temperature
22
rDS(on)
Static drain-source on-state resistance, 12-V switch
vs Junction temperature
23
VO(xVCC)
VO(xVCC)
Output voltage, 5-V switch
vs Output current
24
Output voltage, 3.3-V switch
vs Output current
25
VO(xVCC)
VO(xVPP)
Output voltage, 3.3-V switch, VI(5V) = 0
vs Output current
26
Output voltage, 12-V Vpp switch
vs Output current
27
IOS(xVCC)
IOS(xVCC)
Short-circuit current, 5-V switch
vs Junction temperature
28
Short-circuit current, 3.3-V switch
vs Junction temperature
29
IOS(xVPP)
Short-circuit current, 12-V switch
vs Junction temperature
30
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
155
150
145
I CC – Supply Current – µ A
I CC – Supply Current – µ A
150
155
VO(AVCC) = VO(BVCC) = 5 V
VO(AVPP) = VO(BVPP) = 12 V
No load
140
135
130
ÁÁ
ÁÁ
145
140
135
130
ÁÁ
ÁÁ
125
120
115
110
– 50
VO(AVCC) = VO(BVCC) = 3.3 V
VO(AVPP) = VO(BVPP) = 0 V
No load
125
120
115
– 25
0
25
50
75
100
125
TJ – Junction Temperature – °C
110
– 50
– 25
0
25
50
75
100
125
TJ – Junction Temperature – °C
Figure 19
Figure 18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
3.3-V SWITCH
3.3-V SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
220
200
VI(5 V) = 5 V
VI(3.3V) = 3.3 V
VCC = 3.3 V
180
160
140
120
100
80
60
– 50
– 25
0
25
50
75
100
125
r DS(on) – Static Drain-Source On-State Resistance – m Ω
r DS(on) – Static Drain-Source On-State Resistance – m Ω
TYPICAL CHARACTERISTICS
220
200
VI(5 V) = 0
VI(3.3V) = 3.3 V
VCC = 3.3 V
180
160
140
120
100
80
60
– 50
– 25
50
75
100
125
5-V SWITCH
12-V SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
240
220
VI(5 V) = 5 V
VCC = 5 V
200
180
160
140
120
100
80
60
– 50
– 25
0
25
50
75
100
125
r DS(on) – Static Drain-Source On-State Resistance – m Ω
r DS(on) – Static Drain-Source On-State Resistance – m Ω
25
Figure 21
Figure 20
1100
1000
VI(5 V) = 5 V
Vpp = 12 V
900
800
700
600
500
– 50
– 25
0
25
Figure 23
Figure 22
POST OFFICE BOX 655303
50
75
100
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
14
0
TJ – Junction Temperature – °C
TJ – Junction Temperature – °C
• DALLAS, TEXAS 75265
125
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
TYPICAL CHARACTERISTICS
5-V SWITCH
3.3-V SWITCH
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.3
5
25°C
– 40°C
4.95
VO(xVCC) – Output Voltage – V
VO(xVCC) – Output Voltage – V
3.27
– 40°C
85°C
4.9
125°C
4.85
VI(5V) = 5 V
VCC = 5 V
4.8
0
0.2
0.4
0.6
0.8
IO(xVCC) – Output Current – A
85°C
3.24
125°C
3.21
3.18
3.15
1
25°C
VI(5V) = 5 V
VI(3.3V) = 3.3 V
VCC = 3.3 V
0
Figure 24
0.2
0.4
0.6
0.8
IO(xVCC) – Output Current – A
1
Figure 25
3.3-V SWITCH
12-V SWITCH
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.3
12
– 40°C
– 40°C
25°C
3.25
VO(xVPP) – Output Voltage – V
VO(xVCC) – Output Voltage – V
25°C
11.98
85°C
3.2
125°C
3.15
VI(5 V) = 0 V
VCC = 3.3 V
3.1
11.96
85°C
125°C
11.94
11.92
VI(5 V) = 5 V
VPP = 12 V
11.9
0
0.2
0.4
0.6
0.8
IO(xVCC) – Output Current – A
1
0
Figure 26
0.03
0.06
0.09
IO(xVPP) – Output Current – A
0.12
Figure 27
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
TYPICAL CHARACTERISTICS
5-V SWITCH
3.3-V SWITCH
SHORT-CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
SHORT-CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
2
VI(5 V) = 5 V
VCC = 5 V
I OS(xVCC) – Short-Circuit Current – A
I OS(xVCC) – Short-Circuit Current – A
2
1.8
1.6
1.4
1.2
1
0.8
– 50
0
25
75
– 25
50
100
TJ – Junction Temperature – °C
1.8
VI(5 V) = 0
VI(3.3V) = 3.3 V
VCC = 3.3 V
1.6
1.4
1.2
1
0.8
– 50
125
– 25
0
25
50
75
100
TJ – Junction Temperature – °C
Figure 28
Figure 29
12-V SWITCH
SHORT-CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
I OS(xVPP) – Short-Circuit Current – A
0.32
VI(5 V) = 5 V
Vpp = 12 V
0.3
0.28
0.26
0.24
0.22
0.2
– 50
– 25
0
25
75
50
100
TJ – Junction Temperature – °C
Figure 30
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
125
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited on-board memory. The idea of add-in cards quickly took hold; modems, wireless LANs, global positioning
satellite system (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card
applications grew, the engineering community quickly recognized the need for a standard to ensure
compatibility across platforms. To this end, the PCMCIA was established, comprised of members from leading
computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the
“plug-and-play” concept. Cards and hosts from different vendors should be compatible — able to communicate
with one another transparently.
PC Card power specification
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four
ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two
Vpp terminals were originally specified as separate signals, but are commonly tied together in the host to form
a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals;
flash-memory programming and erase voltage is supplied through the Vpp terminals.
designing for voltage regulation
The current PCMCIA specification for output-voltage regulation (VO(reg)) of the 5-V output is 5% (250 mV). In
a typical PC power-system design, the power supply has an output-voltage regulation (VPS(reg)) of 2% (100 mV).
Also, a voltage drop from the power supply to the PC Card will result from resistive losses (VPCB) in the PCB
traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than
1% (50 mV) of the output voltage. Therefore, the allowable voltage drop (VDS) for the TPS2205 would be the
PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops:
V
DS
+ VOǒregǓ–VPSǒregǓ–VPCB
Typically, this would leave 100 mV for the allowable voltage drop across the TPS2205. The voltage drop is the
output current multiplied by the switch resistance of the TPS2205. Therefore, the maximum output current that
can be delivered to the PC Card in regulation is the allowable voltage drop across the TPS2205 divided by the
output switch resistance.
I max
O
V
DS
+ rDS
ǒonǓ
The xVCC outputs have been designed to deliver 700 mA at 5 V within regulation over the operating temperature
range. Current proposals for the PCMCIA specifications are to limit the power dissipated in the PCMCIA slot
to 3 W. With an input voltage of 5 V, 700 mA continous is the maximum current that can be delivered to the PC
Card. The TPS2205 is capable of delivering up to 1 A continuously, but during worst-case conditions the output
may not be within regulation. This is generally acceptable because the majority of PC Cards require less than
700 mA continuous. Some cards require higher peak currents (disk drives during initial platter spin-up), but it
is generally acceptable for small voltage sags to occur during these peak currents.
The xVCC outputs have been designed to deliver 1 A continuously at 3.3 V within regulation over the operating
temperature range. The PCMCIA specification for output voltage regulation of the 3.3-V output is 300 mV. Using
the voltage drop percentages (2%) for power supply regulation and PCB resistive loss (1%), the allowable
voltage drop for the 3.3 V switch is 200 mV.
The xVPP outputs have been designed to deliver 150 mA continuously at 12 V.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
overcurrent and over-temperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems sufficiently
robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. Most hosts include fuses for protection.
The reliability of fused systems is poor, as blown fuses require troubleshooting and repair, usually by the
manufacturer.
The TPS2205 takes a two-pronged approach to overcurrent protection. First, instead of fuses, sense FETs
monitor each of the power outputs. Excessive current generates an error signal that linearly limits the output
current, preventing host damage or failure. Sense FETs, unlike sense resistors or polyfuses, have an advantage
in that they do not add to the series resistance of the switch and thus produce no additional voltage losses.
Second, when an overcurrent condition is detected, the TPS2205 asserts a signal at OC that can be monitored
by the microprocessor to initiate diagnostics and/or send the user a warning message. In the event that an
overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection
circuitry activates, shutting down all power outputs until the device cools to within a safe operating region.
12-V supply not required
Most PC Card switches use the externally supplied 12-V Vpp power for switch-gate drive and other chip
functions, which requires that power be present at all times. The TPS2205 offers considerable power savings
by using an internal charge pump to generate the required higher voltages from the 5-V or 3.3-V input; therefore,
the external 12-V supply can be disabled except when needed for flash-memory functions, thereby extending
battery lifetime. Do not ground the 12-V inputs when the 12-V input is not used. Additional power savings are
realized by the TPS2205 during a software shutdown in which quiescent current drops to a maximum of 1 µA.
backward compatibility and 3.3-V low-voltage mode
The TPS2205 is backward compatible with the TPS2201, with the following considerations. Pin 25 (VDD on
TPS2201) is a no connect because bias current is derived from either the 3.3-V input pin or the 5-V input pin.
Also, the TPS2205 does not have the APWR_GOOD or BPWR_GOOD VPP reporting outputs. These are left
as no connects.
The TPS2205 operates in 3.3-V low-voltage mode when 3.3 V is the only available input voltage (VI(5V)=0). This
allows host and PC Cards to be operated in low-power 3.3-V-only modes such as sleep modes or pager modes.
Note that in this operation mode, the TPS2205 derives its bias current from the 3.3-V input pin and only 3.3 V
can be delivered to the PC Card. The 3.3-V switch resistance will be increased, but the added switch resistance
should not be critical, because only a small amount of current is delivered in this mode. If 6% (198 mV) is allowed
for the 3.3-V switch voltage drop, a 500 mΩ switch could deliver over 350 mA to the PC Card.
voltage transitioning requirement
PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space,
and increase logic speeds. The TPS2205 is designed to meet all combinations of power delivery as currently
defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering
the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the
capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures
that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The
TPS2205 offers a selectable VCC and Vpp ground state, in accordance with PCMCIA 3.3-V/5-V switching
specifications, to fully discharge the card capacitors while switching between VCC voltages.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
output ground switches
Several PCMCIA power-distribution switches on the market do not have an active-grounding FET switch. These
devices do not meet the PC Card specification requiring a discharge of VCC within 100 ms. PC Card resistance
can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible
high-impedance isolation by power-management schemes. A method commonly shown to alleviate this
problem is to add to the switch output an external 100-kΩ resistor in parallel with the PC Card. Considering that
this is the only discharge path to ground, a timing analysis shows that the RC time constant delays the required
discharge time to more than 2 seconds. The only way to ensure timing compatibility with PC Card standards
is to use a power-distribution switch that has an internal ground switch, like that of the TPS22xx family, or add
an external ground FET to each of the output lines with the control logic necessary to select it.
In summary, the TPS2205 is a complete single-chip dual-slot PC Card power interface. It meets all currently
defined PCMCIA specifications for power delivery in 5-V, 3.3-V, and mixed systems, and offers a serial control
interface. The TPS2205 offers functionality, power savings, overcurrent and thermal protection, and fault
reporting in one 30-pin SSOP surface-mount package, for maximum value added to new portable designs.
power supply considerations
The TPS2205 has multiple pins for each of its 3.3-V, 5-V, and 12-V power inputs and for the switched VCC
outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in
parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and
lost power. Both 12-V inputs must be connected for proper Vpp switching; it is recommended that all input and
output power pins be paralleled for optimum operation.
Although the TPS2205 is fairly immune to power input fluctuations and noise, it is generally considered good
design practice to bypass power supplies, typically with a 1-µF electrolytic or tantalum capacitor paralleled by
a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly recommended that the switched VCC and Vpp outputs be
bypassed with a 0.1-µF or larger capacitor; doing so improves the immunity of the TPS2205 to electrostatic
discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2205 and
the load. High switching currents can produce large negative-voltage transients, which forward biases substrate
diodes, resulting in unpredictable performance. Similary, no pin should be taken below – 0.3 V.
overcurrent and thermal protection
The TPS2205 uses sense FETs to check for overcurrent conditions in each of the VCC and Vpp outputs. Unlike
sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage
and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent
condition is detected, only the power output affected is limited; all other power outputs continue to function
normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected,
providing for initiation of system diagnostics and/or sending a warning message to the user.
During power up, the TPS2205 controls the rise time of the VCC and Vpp outputs and limits the current into a
faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card),
current is initially limited only by the impedance between the short and the power supply. In extreme cases, as
much as 10 A to 15 A may flow into the short before the current limiting of the TPS2205 engages. If the VCC
or Vpp outputs are driven below ground, the TPS2205 may latch nondestructively in an off state. Cycling power
will reestablish normal operation.
Overcurrent limiting for the VCC outputs is designed to activate if powered up into a short in the range of
1 A to 2.2 A, typically at about 1.6 A. The Vpp outputs limit from 120 mA to 400 mA, typically around 280 mA.
The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full
shutdown of the supply. Shutdown occurs only during thermal limiting.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
overcurrent and thermal protection (continued)
Thermal limiting prevents destruction of the IC from overheating if the package power-dissipation ratings are
exceeded. Thermal limiting disables all power outputs (both A and B slots) until the device has cooled.
calculating junction temperature
The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature
is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures
20, 21, 22, and 23 using an initial temperature estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
P
D
+ rDS(on)
ǒS
I2
Ǔ)
Next, sum the power dissipation and calculate the junction temperature:
T
J
+
P
D
R
qJA
T , R
A
qJA
+ 108°CńW
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not
within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
logic input and outputs
The TPS2205 was designed to be compatible with most popular PCMCIA controllers and current PCMCIA and
JEIDA standards. However, some controllers require slightly counterintuitive connections to achieve desired
output states. The TPS2205 control logic inputs A_VCC3, A_VCC5, B_VCC3 and B_VCC5 are defined active
low (see Figure 31 and control-logic table). As such, they are directly compatible with the logic outputs of the
Cirrus Logic CL-PD6720 controller.
The shutdown input (SHDN) of the TPS2205, when held at a logic low, places all VCC and Vpp outputs in a
high-impedance state and reduces chip quiescent current to 1 µA to conserve battery power.
An overcurrent output (OC) is provided to indicate an overcurrent condition in any of the VCC or Vpp supplies
(see discussion above).
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
TPS2205
S7
S9
S2
3.3V
S3
CS
3.3V
3.3V
17
12V
12V
CPU
Controller
10
17
11
51
20
17
21
51
VCC
VCC
Card B
S4
S6
5V
Vpp2
CS
CS
5V
Vpp1
9
See Note A
16
S5
5V
18
52
S8
S1
15
Card A
8
S10
1
S12
30
CS
VCC
22
S11
2
VCC
18
23
52
Vpp1
Vpp2
7
See Note A
24
14
3
4
5
6
29
28
27
26
18
Internal
Current Monitor
SHDN
A_VPP_PGM
A_VPP_VCC
A_VCC5
A_VCC3
B_VPP_PGM
B_VPP_VCC
B_VCC5
B_VCC3
Thermal
D0–D7
GND
OC
12
NOTE A: MOSFET switches S9 and S12 have a back-gate diode from the source to the drain. Unused switch inputs ;should never be grounded.
Figure 31. Internal Switching Matrix
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
TPS2205 control logic
AVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
D8 SHDN
D0 A_VPP_PGM
D1 A_VPP_VCC
S7
1
0
0
1
0
1
1
1
OUTPUT
S8
S9
VAVPP
CLOSED
OPEN
OPEN
0V
OPEN
CLOSED
OPEN
VCC†
0
OPEN
OPEN
CLOSED
VPP(12 V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
OPEN
OPEN
OPEN
Hi-Z
BVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
D8 SHDN
D4 B_VPP_PGM
D5 B_VPP_VCC
S10
1
0
0
1
0
1
1
1
1
1
0
X
OUTPUT
S11
S12
VBVPP
CLOSED
OPEN
OPEN
0V
OPEN
CLOSED
OPEN
VCC‡
0
OPEN
OPEN
CLOSED
VPP(12 V)
1
OPEN
OPEN
OPEN
Hi-Z
X
OPEN
OPEN
OPEN
Hi-Z
AVCC
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
D8 SHDN
D3 A_VCC3
D2 A_VCC5
S1
S2
S3
1
0
0
CLOSED
OPEN
OPEN
VAVCC
0V
1
0
1
OPEN
CLOSED
OPEN
3.3 V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
0V
0
X
X
OPEN
OPEN
OPEN
Hi-Z
BVCC
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
D8 SHDN
D6 B_VCC3
D7 B_VCC5
S4
S5
S6
VBVCC
1
0
0
CLOSED
OPEN
OPEN
0V
1
0
1
OPEN
CLOSED
OPEN
3.3 V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
0V
0
X
X
OPEN
OPEN
OPEN
Hi-Z
† Output depends on AVCC
‡ Output depends on BVCC
ESD protection
All TPS2205 inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The VCC and Vpp outputs can be
exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
AVCC
0.1 µF
AVCC
12 V
12V
AVCC
VCC
VCC
Vpp1
Vpp2
12V
PC Card
Connector A
BVCC
BVCC
BVCC
0.1 µF
TPS2205
AVPP
0.1 µF
1 µF
1 µF
PC Card
Connector B
BVPP
3.3V
0.1 µF
Vpp1
Vpp2
5V
5V
3.3 V
0.1 µF
AVPP
5V
5V
VCC
VCC
3.3V
3.3V
A_VCC5
A_VCC_EN0
A_VCC_EN1
A_VCC3
A_VPP_VCC
A_VPP_EN0
A_VPP_EN1
A_VPP_PGM
B_VCC5
B_VCC_EN0
B_VCC_EN1
B_VCC3
B_VPP_VCC
B_VPP_EN0
B_VPP_EN1
B_VPP_PGM
OC
GND
PCMCIA
Controller
0.1 µF
BVPP
To CPU
CS
SHDN
Shutdown Signal
From CPU
Figure 32. Detailed Interconnections and Capacitor Recommendations
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
APPLICATION INFORMATION
12-V flash memory supply
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as
2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower
supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 1, the only
external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter
capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB
space when implemented with surface-mount components. An enable input is provided to shut the converter
down and reduce the supply current to 3 µA when 12 V is not needed.
The TPS6734 is a 170-kHz current-mode PWM ( pulse-width modulation) controller with an n-channel MOSFET
power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area
needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is
accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use.
For additional information, see the TPS6734 data sheet (SLVS127).
3.3 V or 5 V
R1
10 kΩ
ENABLE
(see Note A)
C1
33 µF, 20 V
TPS6734
1
VCC
EN
+
2
REF
3
FB
8
7
TPS2205
L1
18 µH
U1
SS
OUT
COMP
GND
C2
0.01 µF
AVCC
AVCC
D1
6
5
4
AVCC
12 V
12V
C5
+
33 µF, 20 V
BVCC
12V
BVCC
BVCC
C4 0.001 µF
AVPP
AVPP
5V
5V
0.1 µF
1 µF
5V
5V
BVPP
BVPP
3.3V
3.3 V
0.1 µF
1 µF
3.3V
3.3V
A_VCC5
A_VCC3
A_VPP_VCC
A_VPP_PGM
B_VCC5
B_VCC3
B_VPP_VCC
B_VPP_PGM
OC
GND
SHDN
NOTE A: The enable terminal can be tied to a generall purpose I/O terminal on the PCMCIA controller or tied high.
Figure 33. TPS2205 with TPS6734 12-V, 120-mA Supply
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
To CPU
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°– 8°
1,03
0,63
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
A MAX
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 / C 10/95
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
MECHANICAL DATA
DF (R-PDSO-G30)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,25
0,80
30
0,12 M
16
7,80
7,20
10,80
10,00
0,15 NOM
1
15
Gage Plane
13,10
12,50
0,25
0°– 8°
0,84
0,76
Seating Plane
2,65 MAX
0,10 MIN
0,10
4040038 / B 02/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2205
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
FOR PARALLEL PCMCIA CONTROLLERS
SLVS128D OCTOBER 1995 – REVISED JUNE 1998
MECHANICAL DATA
DAP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
38-PIN SHOWN
0,30
0,19
0,65
38
0,13 M
20
Thermal Pad
(see Note D)
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
32
38
A MAX
9,80
11,10
11,10
12,60
A MIN
9,60
10,90
10,90
12,40
DIM
4073257/A 07/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusion.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This solderable pad
is electrically and thermally connected to the backside of the die and possiblly selected leads. The maximum pad size on the printed
circult board should be equal to the package body size (2,0 mm).
PowerPAD is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1998, Texas Instruments Incorporated