TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS Check for Samples: TPS70345, TPS70348, TPS70351, TPS70358, TPS70302 FEATURES DESCRIPTION • The TPS703xx family of devices is designed to provide a complete power management solution for TI DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any TI DSP application with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power-on reset), manual reset inputs, and enable function, provide a complete system solution. 1 23 • • • • • • • • • • • • • • • Dual Output Voltages for Split-Supply Applications Independent Enable Functions (See Part Number TPS704xx for Independent Enabling of Each Output) Output Current Range of 1 A on Regulator 1 and 2A on Regulator 2 Fast Transient Response Voltage Options: 3.3 V/2.5 V, 3.3 V/1.8 V, 3.3 V/1.5 V, 3.3 V/1.2 V, and Dual Adjustable Outputs Open Drain Power-On Reset with 120 ms Delay Open Drain Power Good for Regulator 1 Ultralow 185 mA (typ) Quiescent Current 2 mA Input Current During Standby Low Noise: 78 mVRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature Two Manual Reset Inputs 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 24-Pin PowerPAD™ TSSOP Package Thermal Shutdown Protection PWP PACKAGE (TOP VIEW) GND/HEATSINK 1 24 GND/HEATSINK VIN1 2 23 VOUT1 VIN1 3 22 VOUT1 NC 4 21 VSENSE1/FB1 MR2 5 20 NC MR1 6 19 PG1 EN 7 18 RESET NC SEQ 8 17 GND 9 16 VSENSE2/FB2 VIN2 10 15 VOUT2 VIN2 11 14 VOUT2 GND/HEATSINK 12 13 GND/HEATSINK NC = No internal connection 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com TPS70351 PWP 5V VIN1 0.22 mF 3.3 V VOUT1 250 kW PG1 PG1 0.22 mF >2 V EN MR2 MR2 >2 V <0.7 V 250 kW RESET RESET EN <0.7 V MR1 VSENSE2 SEQ I/O 22 mF VSENSE1 VIN2 DSP MR1 >2 V <0.7 V 1.8 V VOUT2 Core 47 mF The TPS703xx family of voltage regulators offers very low dropout voltage and dual outputs with power up sequence control, designed primarily for DSP applications. These devices have low noise output performance without using any added filter bypass capacitors, and are designed to have a fast transient response and be stable with 47 mF low ESR capacitors. These devices have fixed 3.3 V/2.5 V, 3.3 V/1.8 V, 3.3 V/1.5 V, 3.3 V/1.2 V, and adjustable voltage options. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power. Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 mA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1 mA at TJ = +25°C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (that is, in an overload condition) of its regulated voltage, VOUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement an SVS (POR, or power-on reset) for the circuitry supplied by regulator 1. The TPS703xx features a RESET (SVS, POR, or power-on reset). RESET is an active low, open drain output and requires a pull-up resistor for normal operation. When pulled up, RESET goes to a high impedance state (that is, logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. RESET can be used to drive power-on reset or a low-battery indicator. If RESET is not used, it can be left floating. Internal bias voltages are powered by VIN1 and require 2.7V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V. 2 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOLTAGE (V) (1) (2) (2) PRODUCT VOUT1 VOUT2 PACKAGELEAD (DESIGNATOR) SPECIFIED TEMPERATURE RANGE (TJ) TPS70302 Adjustable Adjustable HTSSOP-24 (PWP) -40°C to +125°C TPS70345 3.3 V 1.2 V HTSSOP-24 (PWP) -40°C to +125°C TPS70348 3.3 V 1.5 V HTSSOP-24 (PWP) -40°C to +125°C TPS70351 3.3 V 1.8 V HTSSOP-24 (PWP) -40°C to +125°C TPS70358 3.3 V 2.5 V HTSSOP-24 (PWP) -40°C to +125°C ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TPS70302PWP Tube, 60 TPS70302PWPR Tape and Reel, 2000 TPS70345PWP Tube, 60 TPS70345PWPR Tape and Reel, 2000 TPS70348PWP Tube, 60 TPS70348PWPR Tape and Reel, 2000 TPS70351PWP Tube, 60 TPS70351PWPR Tape and Reel, 2000 TPS70358PWP Tube, 60 TPS70358PWPR Tape and Reel, 2000 For the most current package and ordering information see the Package Option Addendum located at the end of this document, or see the TI web site at www.ti.com. For fixed 1.20V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). TPS703xx UNIT Input voltage range: VIN1, VIN2 (2) –0.3 to +7 V Voltage range at EN –0.3 to +7 V Output voltage range (VOUT1, VSENSE1) 5.5 V Output voltage range (VOUT2, VSENSE2) 5.5 V 7 V Maximum RESET, PG1 voltage Maximum MR1, MR2, and SEQ voltage VIN1 V Internally limited — See Dissipation Ratings Table — Operating virtual junction temperature range, TJ –40 to +150 °C Storage temperature range, TSTG –65 to +150 °C 2 kV Peak output current Continuous total power dissipation ESD rating, HBM (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are tied to network ground. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com DISSIPATION RATINGS PACKAGE AIR FLOW (CFM) TA ≤ +25°C DERATING FACTOR TA = +70°C TA = +85°C 0 3.067 W 30.67 mW/°C 1.687 W 1.227 W 250 4.115 W 41.15 mW/°C 2.265 W 1.646 W PWP (1) (1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in ground layer. For more information, refer to TI technical brief SLMA002. RECOMMENDED OPERATING CONDITIONS Over operating temperature range (unless otherwise noted). Input voltage, VI (1) (regulator 1 and 2) Output current, IO (regulator 1) Output current, IO (regulator 2) MIN MAX 2.7 6 UNIT V 0 1 A A 0 2 Output voltage range (for adjustable option) 1.22 5.5 V Operating virtual junction temperature, TJ –40 +125 °C (1) 4 To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUTX(nom) + 1V, IOUTX = 1mA, EN = 0V, COUT1 = 22mF, and COUT2 = 47mF (unless otherwise noted). PARAMETER TEST CONDITIONS 2.7 V < VIN < 6 V, TJ = +25°C FB connected to VO 2.7 V < VIN < 6 V, FB connected to VO 1.2 V output (VOUT2) 2.7 V < VIN < 6 V, TJ = +25°C 1.5 V output (VOUT2) 2.7 V < VIN < 6 V, 1.8 V output (VOUT2) 2.8 V < VIN < 6 V, 2.5 V output (VOUT2) 3.5 V < VIN < 6 V, 3.3 V output (VOUT1) 4.3 V < VIN < 6 V, Reference voltage Output voltage VO (1) (2) 2.7 V < VIN < 6 V, 2.7 V < VIN < 6 V, 4.3 V < VIN < 6 V, TJ = +25°C (1) VO + 1 V < VIN ≤ 6 V (1) Load regulation for VOUT 1 and VOUT2 TJ = +25°C TJ = +25°C PSRR Power-supply Regulator 1 ripple rejection Regulator 2 (TPS70351) mA 250 0.01 %V 0.1 1 mV 79 BW = 300 Hz to 50 kHz, CO = 33 mF, TJ = +25°C mVRMS 77 VOUT = 0 V Thermal shutdown junction temperature Standby current 3.366 185 Regulator 1 II (standby) 2.55 3.3 3.234 VO + 1 V < VIN ≤ 6 V, V 1.836 2.45 Output voltage line regulation (∆VO/VO) for regulator 1 and regulator 2 (3) Regulator 2 1.53 2.5 TJ = +25°C (2) Regulator 1 1.224 1.764 See Regulator 2 1.248 1.8 TJ = +25°C 3.5 V < VIN < 6 V, UNIT 1.5 TJ = +25°C 2.8 V < VIN < 6 V, MAX 1.2 1.47 (2) Output current limit 1.196 1.176 See Vn TYP 1.224 TJ = +25°C Quiescent current (GND current) for regulator 1 and regulator 2, EN = 0 V (1) Output noise voltage (TPS70351) MIN 1.75 2.2 3.8 4.5 A +150 EN1 = VIN, EN2 = VI TJ = +25°C 1 EN1 = VIN, EN2 = VI f = 1 kHz, f = 1 kHz, °C 2 mA 10 TJ = +25°C (1) 65 TJ = +25°C (1) 60 dB RESET Terminal Minimum input voltage for valid RESET IRESET = 300 mA, Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO t (RESET) RESET pulse duration tr (RESET) Rising edge deglitch Output low voltage VIN = 3.5 V, Leakage current V(RESET) = 6 V (1) (2) (3) V(RESET) ≤ 0.8 V 1.0 1.3 V 92 95 98 %VOUT 80 120 0.5 %VOUT 160 30 I(RESET) = 1 mA 0.15 ms ms 0.4 V 1 mA Minimum input operating voltage is 2.7 V or VO(typ) + 1V, whichever is greater. Maximum input voltage = 6V, minimum output current = 1 mA. IO = 1 mA to 1 A for Regulator 1 and 1mA to 2A for Regulator 2. (VImax - 2.7) x 1000 Line regulation (mV) = (%/V) x Vo 100 If VO < 1.8 V then VImax = 6 V, VImin = 2.7 V: [ VImax - (Vo + 1) ] x 1000 Line regulation (mV) = (%/V) x Vo 100 If VO > 2.5 V then VImax = 6 V, VImin = VO + 1 V: Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUTX(nom) + 1V, IOUTX = 1mA, EN = 0V, COUT1 = 22mF, and COUT2 = 47mF (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.0 1.3 V 95 98 %VOUT PG Terminal V(PG1) ≤ 0.8 V Minimum input voltage for valid PG I(PG) = 300 mA, Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO 0.5 %VOUT tr(PG1) Rising edge deglitch 30 ms Output low voltage VIN = 2.7 V, Leakage current V(PG1) = 6 V 92 I(PG) = 1 mA 0.15 0.4 V 1 mA EN Terminal High-level EN input voltage 2 V Low-level EN input voltage Input current (EN) –1 0.7 V 1 mA SEQ Terminal High-level SEQ input voltage 2 V Low-level SEQ input voltage 0.7 SEQ pull-up current source 6 V mA MR1/MR2 Terminal High-level input voltage 2 V Low-level input voltage 0.7 Pull-up current source 6 V mA VOUT2 Terminal VOUT2 UV comparator: positive-going input threshold voltage at VOUT1 UV comparator 80 VOUT2 UV comparator: hysteresis 3 VOUT2 UV comparator: falling edge deglitch VSENSE2 decreasing below threshold Peak output current 2 ms pulse width Discharge transistor current VOUT2 = 1.5 V 6 Submit Documentation Feedback 83 140 3 7.5 86 %VOUT %VOUT, mV ms A mA Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = –40°C to +125°C), VIN1 or VIN2 = VOUTX(nom) + 1V, IOUTX = 1mA, EN = 0V, COUT1 = 22mF, and COUT2 = 47mF (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX 80 83 86 UNIT VOUT1 Terminal VOUT1 UV comparator: positive-going input threshold voltage at VOUT2 UV comparator VOUT1 UV comparator: hysteresis %VOUT, mV 3 VOUT1 UV comparator: falling edge deglitch Dropout voltage (4) VSENSE1 decreasing below threshold 140 IO = 1 A, VIN1 = 3.2 V 160 TJ = +25°C IO = 1 A, VIN1 = 3.2 V %VOUT ms 250 mV Peak output current 2ms pulse width 1.2 A Discharge transistor current VOUT1 = 1.5 V 7.5 mA VIN1/VIN2 Terminal UVLO threshold 2.3 UVLO hysteresis 2.65 V 110 mV 1 mA FB Terminal Input current: TPS70302 (4) FB = 1.8 V Input voltage (VIN1 or VIN2) = VO(typ) – 100mV. For 1.5 V, 1.8 V and 2.5 V regulators, the dropout voltage is limited by input voltage range. The 3.3 V regulator input is set to 3.2 V to perform this test. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION EN 7 I Active low enable GND 9 — Regulator ground 1, 12, 13, 24 — Ground/heatsink 6 I Manual reset input 1, active low, pulled up internally Manual reset input 2, active low, pulled up internally GND/HEATSI NK MR1 MR2 5 I NC 4, 17, 20 — No connection PG1 19 O Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage RESET 18 O Open drain output, SVS (power-on reset) signal, active low SEQ 8 I Power-up sequence control: SEQ = High, VOUT2 powers up first; SEQ = Low, VOUT1 powers up first. SEQ terminal pulled up internally. VIN1 2, 3 I Input voltage of regulator 1 VIN2 10, 11 I Input voltage of regulator 2 VOUT1 22, 23 O Output voltage of regulator 1 VOUT2 14, 15 O Output voltage of regulator 2 VSENSE2/FB2 16 I Regulator 2 output voltage sense/regulator 2 feedback for adjustable VSENSE1/FB1 21 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com DEVICE INFORMATION Adjustable Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) - UVLO1 Comp Current Sense FB1 ENA_1 + 2.5 V (see Note A) GND Reference Thermal Shutdown + ENA_1 Vref Vref PG1 FB1 - 0.95 x Vref + Rising Edge Deglitch VIN1 PG Comp MR2 Reset Comp VOUT2 UV Comp FB2 - 0.83 x Vref + FB1 - 0.83 x Vref + FB2 - 0.95 x Vref + VIN1 Falling Edge Deglitch Falling Edge Deglitch Power Sequence Logic ENA_1 VIN1 2.5 V MR1 ENA_2 Vref VOUT1 UV Comp EN RESET 120ms Delay Rising Edge Deglitch + - SEQ (see Note B) VIN2 (2 Pins) + ENA_2 UVLO2 Comp FB2 Current Sense ENA_2 (see Note A) VOUT2 (2 Pins) A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT1 and VOUT2, respectively, as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the Application Information section. 8 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 Fixed Voltage Version VOUT1 (2 Pins) VIN1 (2 Pins) - UVLO1 Comp 10 kW Current Sense VSENSE1 ENA_1 + 2.5 V (see Note A) GND Reference Thermal Shutdown + ENA_1 Vref FB1 Vref PG1 FB1 - 0.95 x Vref + Rising Edge Deglitch VIN1 PG Comp MR2 Reset Comp VOUT2 UV Comp FB2 - 0.83 x Vref + FB1 - 0.83 x Vref + FB2 - 0.95 x Vref + SEQ (see Note B) VIN1 Falling Edge Deglitch 2.5 V 120ms Delay VIN1 Falling Edge Deglitch Power Sequence Logic ENA_1 MR1 ENA_2 Vref VOUT1 UV Comp EN RESET Rising Edge Deglitch + - VIN2 (2 Pins) + ENA_2 UVLO2 Comp VSENSE2 Current Sense ENA_2 (see Note A) 10 kW VOUT2 (2 Pins) A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other implementations, refer to FB terminals connection discussion in the Application Information section. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com RESET Timing Diagram with VIN1 Powered Up, MR1 and MR2 at Logic High VIN2 VRES (see Note A) VRES t VOUT2 VIT+ (see Note B) VIT +(see Note B) Threshold Voltage VIT(see Note B) VIT(see Note B) t RESET Output 120 ms Delay 120 ms Delay Output Undefined Output Undefined t NOTES: A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT- trip voltage is typically 5% lower than the output voltage (95%VO). VIT- to VIT+ is the hysteresis voltage. PG1 Timing Diagram VIN1 VUVLO VUVLO VPG1 VPG1 (see Note A) t VOUT2 VIT +(see Note B) VIT+ (see Note B) Threshold Voltage VIT(see Note B) VIT(see Note B) t PG1 Output Output Undefined Output Undefined t NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT- trip voltage is typically 5% lower than the output voltage (95%VO). VIT- to VIT+ is the hysteresis voltage. 10 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 Detailed Description The TPS703xx low dropout regulator family provides dual regulated output voltages for DSP applications that require a high-performance power management solution. These devices provide fast transient response and high accuracy, while drawing low quiescent current. Programmable sequencing provides a power solution for DSPs without any external component requirements. This reduces the component cost and board space while increasing total system reliability. The TPS703xx family has an enable feature that puts the device into sleep mode, reducing the input current to 1 mA. Other features are the integrated SVS (power-on reset, RESET) and power good (PG1). These differential features monitor output voltages and provide logic output to the system, and provide a complete DSP power solution. The TPS703xx, unlike many other LDOs, features very low quiescent current that remains virtually constant even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/b). The TPS703xx uses a PMOS transistor to pass current. Because the gate of the PMOS is voltage driven, operating current is low and stable over the full load range. Pin Functions Enable (EN) The EN terminal is an input that enables or shuts down the device. If EN is at a logic high signal, the device is in shutdown mode. When EN goes to voltage low, then the device is enabled. Sequence (SEQ) The SEQ terminal is an input that programs the output voltage (VOUT1 or VOUT2) that turns on first. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. If VOUT2 is pulled below 83% (that is, goes to an overload) VOUT1 is turned off. This terminal has a 6 mA pull-up current to VIN1. Pulling the SEQ terminal low reverses the power-up order and VOUT1 turns on first. For detailed timing diagrams, see Figure 33 through Figure 39. Power-Good (PG1) The PG1 terminal is an open drain, active high output terminal that indicates the status of the VOUT1 regulator. When VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. PG1 goes to a low impedance state when VOUT1 is pulled below 95% (that is, goes to an overload condition) of its regulated voltage. The open drain output of the PG1 terminal requires a pull-up resistor. Manual Reset Pins (MR1 and MR2) MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled to logic low, a POR (RESET) occurs. These terminals have a 6mA pull-up current to VIN1. It is recommended that these pins be pulled high to VIN when they are not used.. Sense (VSENSE1 and VSENSE2) The sense terminals of fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, the sense terminals connect to high-impedance wide-bandwidth amplifiers through resistor-divider networks and noise pickup feeds through to the regulator output. It is essential to route the sense connections in such a way to minimize or avoid noise pickup. Adding RC networks between the VSENSE terminals and VOUT terminals to filter noise is not recommended because these networks can cause the regulators to oscillate. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize or avoid noise pickup. Adding RC networks between the FB terminals and the VOUT terminals to filter noise is not recommended because these networks can cause the regulators to oscillate. RESET Indicator RESET is an active low, open drain output that requires a pull-up resistor for normal operation. When pulled up, RESET goes to a high impedance state (that is, logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. VIN1 and VIN2 VIN1 and VIN2 are inputs to each regulator. Internal bias voltages are powered by VIN1. VOUT1 and VOUT2 VOUT1 and VOUT2 are output terminals of each regulator. 12 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO vs Output current Figure 1, Figure 2 vs Junction temperature Figure 3, Figure 4 Ground current vs Junction temperature Figure 5 Power-supply rejection ratio vs Frequency Figure 6 to Figure 9 Output spectral noise density vs Frequency Figure 10 to Figure 13 Output impedance vs Frequency Figure 14 to Figure 17 Output voltage PSRR ZO Dropout voltage vs Temperature Figure 18, Figure 19 vs Input voltage Figure 20, Figure 21 Load transient response Figure 22, Figure 23 Line transient response (VOUT1) Figure 24 Line transient response (VOUT2) VO Figure 25 Output voltage vs Time (start-up) Figure 26, Figure 27 Equivalent series resistance (ESR) vs Output current Figure 29 to Figure 32 TPS70351 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS70351 OUTPUT VOLTAGE vs OUTPUT CURRENT 1.815 3.33 VIN1 = 4.3 V TJ = 25°C VOUT1 3.31 3.30 3.29 1.805 1.8 1.795 1.79 3.28 3.27 VIN2 = 2.8 V TJ = 25°C VOUT2 1.81 VO - Output Voltage - V VO - Output Voltage - V 3.32 1.785 0 200 400 600 800 IO - Output Current - mA Figure 1. Copyright © 2000–2010, Texas Instruments Incorporated 1000 0 500 1000 1500 2000 IO - Output Current - mA Figure 2. Submit Documentation Feedback 13 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS70351 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE TPS70351 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 1.834 3.354 VIN1 = 4.3 V VOUT1 VIN2 = 2.8 V VOUT2 1.824 3.314 VO - Output Voltage - V VO - Output Voltage - V 3.334 IO = 1 mA 3.294 IO = 1 A 3.274 3.254 1.814 IO = 2 A 1.804 IO = 1 mA 1.794 1.784 1.774 3.234 40 25 10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C 1.764 40 25 10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 3. Figure 4. TPS70351 GROUND CURRENT vs JUNCTION TEMPERATURE 210 Regulator 1 and Regulator 2 Ground Current - mA 200 IOUT1 = 1 mA IOUT2 = 1 mA 190 IOUT1 = 1 A IOUT2 = 2 A 180 170 160 150 40 25 14 Submit Documentation Feedback 10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - °C Figure 5. Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) TPS70351 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70351 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 20 30 0 VIN1 = 4.3 V VOUT1 = 3.3 V IO = 10 mA Co = 22 mF PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB 10 40 50 60 70 80 90 10 100 1k 10 k f - Frequency - Hz 100 k 30 40 50 60 70 80 90 100 1k 10 k f - Frequency - Hz 100 k Figure 7. TPS70351 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70351 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 1M 0 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 10 mA Co = 47 mF 30 40 50 60 70 80 90 100 10 VIN1 = 4.3 V VOUT1 = 3.3 V IO = 1 A Co = 22 mF Figure 6. PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB 20 20 100 10 1M 0 10 10 100 1k 10 k f - Frequency - Hz Figure 8. Copyright © 2000–2010, Texas Instruments Incorporated 100 k 1M 10 20 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 2 A Co = 47 mF 30 40 50 60 70 80 90 100 10 100 1k 10 k f - Frequency - Hz 100 k 1M Figure 9. Submit Documentation Feedback 15 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN1 = 4.3 V VOUT1 = 3.3 V COUT1 = 22 mF IO = 10 mA TJ = 25°C Output Spectral Noise Density - mV/ÖHz Output Spectral Noise Density - mV/ÖHz 10 1 0.1 0.01 100 1k 10 k f - Frequency - Hz 1k 10 k f - Frequency - Hz Figure 11. OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 100 k 10 VIN1 = 4.3 V VOUT1 = 3.3 V COUT1 = 22 mF IO = 1 A TJ = 25°C Output Spectral Noise Density - mV/ÖHz Output Spectral Noise Density - mV/ÖHz 0.1 Figure 10. 1 0.1 1k 10 k f - Frequency - Hz Figure 12. 16 1 0.01 100 100 k 10 0.01 100 VIN2 = 2.8 V VOUT2 = 1.8 V COUT2 = 47 mF IO = 10 mA TJ = 25°C Submit Documentation Feedback 100 k VIN2 = 2.8 V VOUT2 = 1.8 V COUT2 = 47 mF IO = 2 A TJ = 25°C 1 0.1 0.01 100 1k 10 k f - Frequency - Hz 100 k Figure 13. Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY VOUT1 = 3.3 V IO = 1 A Co = 22 mF ZO - Output Impedance - W ZO - Output Impedance - W VOUT1 = 3.3 V IO = 10 mA Co = 22 mF 1 0.1 0.01 10 100 1k 10 k 100 k f - Frequency - Hz 1M 1 0.1 0.01 10 10 M Figure 15. OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY ZO - Output Impedance - W ZO - Output Impedance - W 0.1 0.01 1k 10 k 100 k f - Frequency - Hz Figure 16. Copyright © 2000–2010, Texas Instruments Incorporated 1M 10 M 1M 10 M VOUT2 = 1.8 V IO = 2 A Co = 47 mF 1 100 1k 10 k 100 k f - Frequency - Hz Figure 14. VOUT2 = 1.8 V IO = 10 mA Co = 47 mF 10 100 1M 10 M 1 0.1 0.01 10 100 1k 10 k 100 k f - Frequency - Hz Figure 17. Submit Documentation Feedback 17 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) DROPOUT VOLTAGE vs TEMPERATURE DROPOUT VOLTAGE vs TEMPERATURE 250 25 VOUT1 VIN1 = 3.2 V VOUT1 VIN1 = 3.2 V 200 20 Dropout Voltage - mV Dropout Voltage - mV IO = 1 A 150 100 IO = 100 mA 15 10 5 50 IO = 1 mA IO = 10 mA 0 0 40 25 10 5 20 35 50 65 80 T - Temperature - °C 95 110 125 40 25 TPS70302 DROPOUT VOLTAGE vs INPUT VOLTAGE TPS70302 DROPOUT VOLTAGE vs INPUT VOLTAGE 300 VOUT1 IO = 1 A TJ = 125°C 200 TJ = 25°C 150 100 TJ = -40°C 50 95 110 125 VOUT2 IO = 2 A 250 Dropout Voltage - mV Dropout Voltage - mV 20 35 50 65 80 T - Temperature - °C Figure 19. 250 TJ = 125°C 200 TJ = 25°C 150 TJ = -40°C 100 50 3 3.5 4 4.5 VI - Input Voltage - V Figure 20. 18 5 Figure 18. 300 0 2.5 10 Submit Documentation Feedback 5 5.5 0 2.5 3 3.5 4 4.5 5 5.5 VI - Input Voltage - V Figure 21. Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) 0.5 0 DVO - Change in Output Voltage - mV 50 0 50 100 0.2 0.4 0.6 0.8 1 1.2 t - Time - ms 1.4 1.6 1.8 0 50 0 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 t - Time - ms Figure 23. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE VOUT1 = 3.3 V IO = 1 A Co = 22 mF 4.3 50 0 50 0 1 Figure 22. 5.3 100 VOUT2 = 1.8 V IO = 2 A Co = 22 mF TJ = 25°C 2 2 DVO - Change in Output Voltage - mV VIN - Input Voltage - V IO - Output Current - A VIN1 = 4.3 V VOUT1 = 3.3 V Co = 22 mF TJ = 25°C 1 0 DVO - Change in Output Voltage - mV LOAD TRANSIENT RESPONSE VIN - Input Voltage - V DVO - Change in Output Voltage - mV IO - Output Current - A LOAD TRANSIENT RESPONSE 20 40 60 80 100 120 140 160 180 200 t - Time - ms Figure 24. Copyright © 2000–2010, Texas Instruments Incorporated 1.8 2 VOUT2 = 1.8 V IO = 2 A Co = 47 mF 3.8 2.8 100 0 100 200 0 20 40 60 80 100 120 140 160 180 20 t - Time - ms Figure 25. Submit Documentation Feedback 19 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) VO - Output Voltage - V 3 VOUT1 = 3.3 V IO = 1 A Co = 22 mF VIN1 = 4.3 V SEQ = Low 2 1 0 Enable Voltage - V Enable Voltage - V VO - Output Voltage - V 4 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 t - Time (Start-Up) - ms 2 2 1 0 VOUT2 = 1.8 V IO = 2 A Co = 47 mF VIN2 = 2.8 V SEQ = High 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 t - Time (Start-Up) - ms Figure 26. VIN 2 Figure 27. To Load IN OUT + COUT EN RL GND ESR Figure 28. Test Circuit for Typical Regions of Stability 20 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 VOUT1 = 3.3 V Co = 22 mF ESR - Equivalent Series Resistance - W ESR - Equivalent Series Resistance - W 10 REGION OF INSTABILITY 1 0.1 50 mW 0.01 VOUT1 = 3.3 V Co = 220 mF REGION OF INSTABILITY 1 0.1 15 mW 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 IO - Output Current - A 1 0 0.3 0.4 0.5 0.6 0.7 IO - Output Current - A 0.8 0.9 Figure 29. Figure 30. TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 1 10 10 REGION OF INSTABILITY ESR - Equivalent Series Resistance - W REGION OF INSTABILITY ESR - Equivalent Series Resistance - W 0.1 0.2 VOUT2 = 1.8 V Co = 47 mF 1 0.1 50 mW VOUT2 = 1.8 V Co = 680 mF 1 0.1 15 mW 0.01 0.01 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 IO - Output Current - A Figure 31. 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 IO - Output Current - A 1 Figure 32. (1) Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com THERMAL INFORMATION Thermally-Enhanced TSSOP-24 (PWP— PowerPAD™) The thermally-enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad [see Figure 33(c)] to provide an effective thermal contact between the IC and the printed wiring board (PWB). Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages, however, suffer from several shortcomings: they do not address the very low profile requirements (<2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to accommodate increasing integration. On the other hand, traditional low-power surface-mount packages require power-dissipation derating that severely limits the usable range of many high-performance analog circuits. The PWP package (thermally-enhanced TSSOP) combines fine-pitch surface-mount technology with thermal performance comparable to much larger power packages. The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch, surface-mount package can be reliably achieved. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 33. Views of Thermally-Enhanced PWP Package Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface), which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference Figure 35(a), 8 cm2 of copper heat sink and natural convection). Increasing the heat-sink size increases the power dissipation range for the component. The power dissipation limit can be further improved by adding airflow to a PWB/IC assembly (see Figure 34 and Figure 35). The line drawn at 0.3 cm2 in Figure 34 and Figure 35 indicates performance at the minimum recommended heat-sink size, illustrated in Figure 36. 22 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 The thermal pad is directly connected to the substrate of the IC, which for the TPS703xx series is a secondary electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary electrical connection for a given terminal which is not always ground. The PWP package provides up to 24 independent leads that can be used as inputs and outputs (Note: leads 1, 12, 13, and 24 are internally connected to the thermal pad and the IC substrate). THERMAL RESISTANCE vs COPPER HEATSINK AREA 150 RqJA - Thermal Resistance - °C/W 125 Natural Convection 50 ft/min 100 ft/min 100 150 ft/min 200 ft/min 75 50 250 ft/min 300 ft/min 25 0 0.3 1 2 3 4 6 5 Copper Heatsink Area - cm 7 8 2 Figure 34. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 23 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com 3.5 3.5 TA = 25°C TA = 55°C 300 ft/min 3 PD - Power Dissipation Limit - W PD - Power Dissipation Limit - W 3 150 ft/min 2.5 2 Natural Convection 1.5 1 0.5 0 300 ft/min 2.5 2 150 ft/min 1.5 Natural Convection 1 0.5 0 0.3 2 4 Copper Heatsink Size - cm 0 8 6 2 0 2 0.3 4 6 Copper Heatsink Size - cm (a) 8 2 (b) 3.5 TA = 105°C PD - Power Dissipation Limit - W 3 2.5 2 1.5 150 ft/min 300 ft/min 1 Natural Convection 0.5 0 0 0.3 2 4 6 Copper Heatsink Size - cm 8 2 (c) Figure 35. Power Ratings of the PWP Package at Ambient Temperatures of +25°C, +55°C, and +105°C 24 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 Figure 36 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This board configuration was used in the thermal experiments that generated the power ratings shown in Figure 34 and Figure 35. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. RqJA for this assembly is illustrated in Figure 34 as a function of heat-sink area. A family of curves is included to illustrate the effect of airflow introduced into the system. Heatsink Area 1 oz Copper Board thickness Board size Board material Copper trace/heat sink Exposed pad mounting 62 mils 3.2 in ´ 3.2 in FR4 1 oz 63/67 tin/lead solder Figure 36. PWB Layout (Including Copper Heatsink Area) for Thermally-Enhanced PWP Package From Figure 34, RqJA for a PWB assembly can be determined and used to calculate the maximum power-dissipation limit for the component/PWB assembly, with the equation: TJmax - TA PD(max) = RqJA(system) where: • TJmax is the maximum specified junction temperature (+150°C absolute maximum limit, +125°C recommended operating limit) and TA is the ambient temperature. (1) PD(max) should then be applied to the internal power dissipated by the TPS703xx regulator. The equation for calculating total internal power dissipation of the TPS703xx is: PD(total) = VIN1 - VOUT1 ´ IOUT1 + VIN1 ´ IQ + VIN2 - VOUT2 ´ IOUT2 + VIN2 ´ IQ 2 2 (2) ( ( ( ( Since the quiescent current of the TPS703xx is very low, the second term is negligible, further simplifying the equation to: ( ( ( ( PD(total) = VIN1 - VOUT1 ´ IOUT1 + VIN2 - VOUT2 ´ IOUT2 (3) 2 For the case where TA = +55°C, airflow = 200 ft/min, copper heat-sink area = 4 cm , the maximum power-dissipation limit can be calculated. First, from Figure 34, we find the system RqJA is +50°C/W; therefore, the maximum power-dissipation limit is: TJmax - TA +125°C - 55°C PD(max) = = 1.4 W = RqJA(system) +50°C/W (4) If the system implements a TPS703xx regulator, where VIN1 = 5.0V, VIN2 = 2.8 V, IOUT1 = 500 mA, and IOUT2 = 800 mA, the internal power dissipation is: ( ( ( ( PD(total) = VIN1 - VOUT1 ´ IOUT1 + VIN2 - VOUT2 ´ IOUT2 = (5.0 - 3.3) ´ 0.5 + (2.8 - 1.8) ´ 0.8 = 1.65 W Copyright © 2000–2010, Texas Instruments Incorporated (5) Submit Documentation Feedback 25 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com Comparing PD(total) with PD(max) reveals that the power dissipation in this example does not exceed the calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input voltage or the load current. In either case, the above calculations should be repeated with the new system parameters. This parameter is measured with the recommended copper heat sink pattern on a 4-layer PWB, 2 oz. copper traces on 4-in × 4-in ground layer. Simultaneous and continuous operation of both regulator outputs at full load may exceed the power dissipation rating of the PWP package. Mounting Information The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted. Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data included in Figure 34 and Figure 36 are for soldered connections with voiding between 20% and 50%. The thermal analysis shows no significant difference resulting from the variation in voiding percentage. Figure 37 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink area is also illustrated. This is simply a copper plane under the body extent of the package, including metal routed under terminals 1, 12, 13, and 24. Minimum Recommended Heatsink Area Location of Exposed Thermal Pad on PWP Package Figure 37. PWP Package Land Pattern 26 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 APPLICATION INFORMATION MR1 and MR2 (tied to PG1) are at logic high, RESET is pulled to logic high after a 120 ms delay. When EN returns to a logic high, both devices power down and both PG1 (tied to MR2) and RESET return to logic low. Sequencing Timing Diagrams This section provides a number of timing diagrams showing how this device functions in different configurations. Application conditions not shown in block diagram: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO; SEQ is tied to logic low; PG1 is tied to MR2; MR1 is not used and is connected to VIN. TPS703xxPWP (Fixed Output Option) VI VIN1 0.22 mF Explanation of timing diagrams: EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic low, when EN is taken to logic low, VOUT1 turns on. VOUT2 turns on after VOUT1 reaches 83% of its regulated output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both VOUT1 VOUT1 22 mF VSENSE1 250 kW PG1 VIN2 0.22 mF >2 V EN MR2 MR2 RESET RESET MR1 EN <0.7 V MR1 VIN VSENSE2 SEQ VOUT2 VOUT2 47 mF EN SEQ VOUT2 95% 83% 95% VOUT1 83% PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 (see Note A) 120 ms NOTE A: t1: Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high. Figure 38. Timing When SEQ = Low Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 27 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com Application conditions not shown in block diagram: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO; SEQ is tied to logic high; PG1 is tied to MR2; MR1 is not used and is connected to VIN. TPS703xxPWP (Fixed Output Option) VI VIN1 0.22 mF Explanation of timing diagrams: EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic high, when EN is taken to logic low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to PG1) are at logic high, RESET is pulled to logic high after a 120 ms delay. When EN returns to logic high, both devices turn off and both PG1 (tied to MR2) and RESET return to logic low. VOUT1 VOUT1 22 mF VSENSE1 250 kW PG1 MR2 VIN2 0.22 mF EN MR2 RESET RESET MR1 MR1 EN VIN >2 V VSENSE2 <0.7 V SEQ VOUT2 VOUT2 47 mF EN SEQ VOUT2 95% 83% VOUT1 95% 83% PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 (see Note A) 120ms NOTE A: t1: Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high. Figure 39. Timing When SEQ = High 28 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 Application conditions not shown in block diagram: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO; SEQ is tied to logic high; PG1 is tied to MR2; MR1 is initially at logic high but is eventually toggled. TPS703xxPWP (Fixed Output Option) VI VIN1 VOUT1 VOUT1 0.22 mF 22 mF VSENSE1 Explanation of timing diagrams: EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic high, when EN is taken low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to PG1) are at logic high, RESET is pulled to logic high after a 120 ms delay. When MR1 is taken low, RESET returns to logic low but the outputs remain in regulation. When MR1 returns to logic high, because both VOUT1 and VOUT2 remain above 95% of their respective regulated output voltages and MR2 (tied to PG1) remains at logic high, RESET is pulled to logic high after a 120 ms delay. 250 kW PG1 VIN2 0.22 mF EN MR2 RESET MR1 EN >2 V VSENSE2 <0.7 V SEQ VOUT2 MR2 RESET MR1 2V 0.7 V VOUT2 47 mF EN SEQ VOUT2 95% 83% 95% VOUT1 83% PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 (see Note A) 120 ms 120 ms NOTE A: t1: Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high. Figure 40. Timing When MR1 is Toggled Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 29 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com Application conditions not shown in block diagram: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO; SEQ is tied to logic high; PG1 is tied to MR2; MR1 is not used and is connected to VIN. TPS703xxPWP (Fixed Output Option) VI VIN1 0.22 mF Explanation of timing diagrams: EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic high, when EN is taken low, VOUT2 turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to PG1) are at logic high, RESET is pulled to logic high after a 120 ms delay. When a fault on VOUT1 causes it to fall below 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic low. VOUT1 VSENSE1 VOUT1 22 mF 250 kW PG1 VIN2 0.22 mF EN EN MR2 MR2 RESET RESET MR1 MR1 VIN >2 V VSENSE2 <0.7 V SEQ VOUT2 VOUT2 47 mF EN SEQUENCE VOUT2 95% 83% 95% VOUT1 83% Fault on VOUT1 PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 (see Note A) 120 ms NOTE A: t1: Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high. Figure 41. Timing When a Fault Occurs on VOUT1 30 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 Application conditions not shown in block diagram: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO; SEQ is tied to logic high; PG1 is tied to MR2; MR1 is not used and is connected to VIN. TPS703xxPWP (Fixed Output Option) VI VOUT1 VIN1 0.22 mF Explanation of timing diagrams: EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic high, when EN is taken low, VOUT2turns on. VOUT1 turns on after VOUT2 reaches 83% of its regulated output voltage. When VOUT1 reaches 95% of its regulated output voltage, PG1 (tied to MR2) goes to logic high. When both VOUT1 and VOUT2 reach 95% of their respective regulated output voltages and both MR1 and MR2 (tied to PG1) are at logic high, RESET is pulled to logic high after a 120 ms delay. When a fault on VOUT2 causes it to fall below 95% of its regulated output voltage, RESET returns to logic low and VOUT1 begins to power down because SEQ is high. When VOUT1 falls below 95% of its regulated output voltage, PG1 (tied to MR2) returns to logic low. VSENSE1 VOUT1 22 mF 250 kW PG1 VIN2 0.22 mF EN MR2 MR2 RESET RESET MR1 EN MR1 VIN >2 V VSENSE2 <0.7 V SEQ VOUT2 VOUT2 47 mF ENABLE SEQUENCE 95% 83% VOUT2 Fault on VOUT2 95% VOUT1 83% PG1 MR1 MR2 (MR2 tied to PG1) RESET t1 (see Note A) 120 ms NOTE A: t1: Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high. Figure 42. Timing When a Fault Occurs on VOUT2 Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 31 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com APPLICATION INFORMATION Split Voltage DSP Application Figure 43 shows a typical application where the TPS70351 is powering up a DSP. In this application, by grounding the SEQ pin, VOUT1 (I/O) powers up first, and then VOUT2 (core). TPS70351 PWP 5V VIN1 0.22 mF 22 mF VSENSE1 MR2 0.22 mF >2 V EN I/O 250 kW PG1 PG1 VIN2 DSP 3.3 V VOUT1 MR2 250 kW RESET RESET MR1 EN MR1 <0.7 V VSENSE2 SEQ 1.8 V VOUT2 Core 47 mF EN SEQ VOUT2 (Core) 95% 83% VOUT1 (I/O) 95% 83% PG1 RESET t1 (see Note A) 120ms NOTE A: t1: Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high. Figure 43. Application Timing Diagram (SEQ = Low) 32 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 Figure 44 shows a typical application where the TPS70351 is powering up a DSP. In this application, by pulling up the SEQ pin, VOUT2 (core) powers up first, and then VOUT1 (I/O). TPS70351 PWP 5V VIN1 0.22 mF 22 mF VSENSE1 MR2 EN 250 kW MR2 250 kW 0.22 mF >2 V I/O PG1 PG1 VIN2 DSP 3.3 V VOUT1 RESET RESET MR1 EN MR1 <0.7 V VSENSE2 SEQ 1.8 V VOUT2 Core 47 mF EN SEQ VOUT2 (Core) 95% 83% VOUT1 (I/O) 95% 83% PG1 RESET t1 (see Note A) 120ms NOTE A: t1: Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high. Figure 44. Application Timing Diagram (SEQ = High) Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 33 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com Input Capacitor For a typical application, a ceramic input bypass capacitor (0.22 mF to 1 mF) is recommended to ensure device stability. This capacitor should be as close as possible to the input pin. Because of the impedance of the input supply, large transient currents cause the input voltage to droop. If this droop causes the input voltage to drop below the UVLO threshold, the device turns off. Therefore, it is recommended that a larger capacitor be placed in parallel with the ceramic bypass capacitor at the regulator input. The size of this capacitor depends on the output current, response time of the main power supply, and the main power supply distance to the regulator. At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum UVLO threshold voltage during normal operating conditions. Output Capacitor As with most LDO regulators, the TPS703xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value for VOUT1 is 22 mF and the ESR (equivalent series resistance) must be between 50 mΩ and 800 mΩ. The minimum recommended capacitance value for VOUT2 is 47mF and the ESR must be between 50 mΩ and 2 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Larger capacitors provide a wider range of stability and better load transient response. Table 1 gives a partial listing of surface-mount capacitors suitable for use with the TPS703xx for fast transient response applications. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for user applications. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. Table 1. Partial Listing of TPS703xx-Compatible Surface-Mount Capacitors 34 VALUE MANUFACTURER MFR PART NO. 680 mF Kemet T510X6871004AS 470 mF Sanyo 4TPB470M 150 mF Sanyo 4TPC150M 220 mF Sanyo 2R5TPC220M 100 mF Sanyo 6TPC100M 68 mF Sanyo 10TPC68M 68 mF Kemet T495D6861006AS 47 mF Kemet T495D4761010AS 33 mF Kemet T495C3361016AS 22 mF Kemet T495C2261010AS Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 www.ti.com SLVS285H – AUGUST 2000 – REVISED APRIL 2010 Programming the TPS70302 Adjustable LDO Regulator The output voltage of the TPS70302 adjustable regulators is programmed using external resistor dividers as shown in Figure 45. Resistors R1 and R2 should be chosen for approximately a 50 mA divider current. Lower value resistors can be used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at the sense terminal increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at approximately 50 mA, and then calculate R1 using Equation 6: VOUT - 1 ´ R2 R1 = VREF (6) ( ( where: • VREF = 1.224 V typ (the internal reference voltage) OUTPUT VOLTAGE PROGRAMMING GUIDE TPS70302 VI IN 0.1 mF >2.0 V OUT EN VO <0.7 V R1 + OUTPUT VOLTAGE R1 R2 UNIT 2.5 V 31.6 30.1 kW 3.3 V 51.1 30.1 kW 3.6 V 59.0 30.1 kW FB GND R2 Figure 45. TPS70302 Adjustable LDO Regulator Programming Regulator Protection Both TPS703xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input voltage drops below the output voltage (for example, during power-down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS703xx also features internal current limiting and thermal protection. During normal operation, the TPS703xx regulator 1 limits output current to approximately 1.75 A (typ) and regulator 2 limits output current to approximately 3.8 A (typ). When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds +150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below +130°C (typ), regulator operation resumes. Copyright © 2000–2010, Texas Instruments Incorporated Submit Documentation Feedback 35 TPS70345, TPS70348 TPS70351, TPS70358 TPS70302 SLVS285H – AUGUST 2000 – REVISED APRIL 2010 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (December 2009) to Revision H • Changed Tube transport media, quantity value from 70 to 60 in Ordering Information table .............................................. 3 Changes from Revision F (September 2009) to Revision G • 36 Page Page Changed Dissipation Ratings table ....................................................................................................................................... 4 Submit Documentation Feedback Copyright © 2000–2010, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS70302PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70302 TPS70302PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70302 TPS70302PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70302 TPS70302PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70302 TPS70345PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70345 TPS70345PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70345 TPS70345PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70345 TPS70345PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70345 TPS70348PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70348 TPS70348PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70348 TPS70348PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70348 TPS70348PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70348 TPS70351PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70351 TPS70351PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70351 TPS70351PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70351 TPS70351PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70351 TPS70358PWP ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70358 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS70358PWPG4 ACTIVE HTSSOP PWP 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70358 TPS70358PWPR ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70358 TPS70358PWPRG4 ACTIVE HTSSOP PWP 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 PT70358 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS70345, TPS70358 : Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 • Enhanced Product: TPS70345-EP • Military: TPS70358M NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS70302PWPR HTSSOP PWP 24 2000 330.0 16.4 TPS70345PWPR HTSSOP PWP 24 2000 330.0 TPS70348PWPR HTSSOP PWP 24 2000 330.0 TPS70351PWPR HTSSOP PWP 24 2000 TPS70358PWPR HTSSOP PWP 24 2000 6.95 8.3 1.6 8.0 16.0 Q1 16.4 6.95 8.3 1.6 8.0 16.0 Q1 16.4 6.95 8.3 1.6 8.0 16.0 Q1 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70302PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70345PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70348PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70351PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS70358PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated