TPS782xx www.ti.com SBVS115B – AUGUST 2008 – REVISED MAY 2010 500nA, IQ 150mA, Ultra-Low Quiescent Current Low-Dropout Linear Regulator FEATURES DESCRIPTION • • • • • • The TPS782 family of low-dropout regulators (LDOs) offers the benefits of ultra-low power (IQ = 1mA), and miniaturized packaging (2×2 SON). 1 2 • • • • Low IQ: 500nA 150mA, Low-Dropout Regulator Low-Dropout at +25°C, 130mV at 150mA Low-Dropout at +85°C, 175mV at 150mA 3% Accuracy Over Load/Line/Temperature Available in Fixed Voltage Options (2.5V, 2.7V, and 2.8V) Using Innovative Factory EEPROM Programming Stable with a 1.0mF Ceramic Capacitor Thermal Shutdown and Overcurrent Protection CMOS Logic Level-Compatible Enable Pin Available in DDC (TSOT23-5) or DRV (2mm x 2mm SON-6) Packages APPLICATIONS • • • TI MSP430 Attach Applications Power Rails with Programming Mode Wireless Handsets, Smartphones, PDAs, MP3 Players, and Other Battery-Operated Handheld Products TPS782xxDDC TSOT23-5 (TOP VIEW) 5 This LDO is designed specifically for battery-powered applications where ultra-low quiescent current is a critical parameter. The TPS782, with ultra-low IQ (1mA), is ideal for microprocessors, memory cards, and smoke detectors. The ultra-low power and miniaturized packaging allow designers to customize power consumption for specific applications. Consult with your local factory representative for exact voltage options and ordering information; minimum order quantities may apply. The TPS782 family is designed to be compatible with the TI MSP430 and other similar products. The enable pin (EN) is compatible with standard CMOS logic. This LDO is stable with any output capacitor greater than 1.0mF. Therefore, this device requires minimal board space because of miniaturized packaging and a potentially small output capacitor. The TPS782 series also features thermal shutdown and current limit to protect the device during fault conditions. All packages have an operating temperature range of TJ = –40°C to +125°C. For high-performance applications that require a dual-level voltage option, consider the TPS780 series, with an IQ of 500nA and dynamic voltage scaling. TPS782xxDRV 2mm x 2mm SON-6 (TOP VIEW) IN 1 OUT 1 GND 2 N/C 2 3 GND 3 EN 4 OUT GND Thermal Pad 6 IN 5 GND 4 EN 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2010, Texas Instruments Incorporated TPS782xx SBVS115B – AUGUST 2008 – REVISED MAY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT VOUT TPS782xx yyy z (1) (2) (2) XX is the nominal output voltage YYY is the package designator. Z is the tape and reel quantity (R = 3000, T = 250). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Additional output voltage combinations are available on a quick-turn basis using innovative, factory EEPROM programming. Minimum-order quantities apply; contact your sales representative for details and availability ABSOLUTE MAXIMUM RATINGS (1) At TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND. PARAMETER TPS782xx UNIT –0.3 to +6.0 V Enable –0.3 to VIN + 0.3V V Output voltage range, VOUT –0.3 to VIN + 0.3V V Input voltage range, VIN Maximum output current, IOUT Internally limited Output short-circuit duration Indefinite Total continuous power dissipation, PDISS ESD rating See the Dissipation Ratings table Human body model (HBM) 2 kV 500 V Operating junction temperature range, TJ –40 to +125 °C Storage temperature range, TSTG –55 to +150 °C (1) Charged device model (CDM) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. DISSIPATION RATINGS BOARD DERATING FACTOR ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C 20°C/W 65°C/W 15.4mW/°C 1540mW 845mW 615mW 90°C/W 200°C/W 5.0mW/°C 500mW 275mW 200mW RqJC (1) DRV High-K (1) DDC High-K (1) 2 RqJA PACKAGE The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated TPS782xx www.ti.com SBVS115B – AUGUST 2008 – REVISED MAY 2010 ELECTRICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 0.5V or 2.2V, whichever is greater; IOUT = 100mA, VEN = VIN, COUT = 1.0mF, fixed VOUT test conditions, unless otherwise noted. Typical values at TJ = +25°C. TPS782xx PARAMETER VIN TEST CONDITIONS Input voltage range ΔVOUT/ΔVIN DC output accuracy Line regulation (1) Operating junction temperature VIN = 4.3V, VOUT = 3.3V, IOUT = 150mA 250 mV mVRMS 230 400 mA 0.42 1.3 mA 8 VEN = 5.5V TJ 150 IOUT = 150mA EN pin current Thermal shutdown temperature % IOUT = 0mA Shutdown current (IGND) TSD +3.0 86 VEN ≤ 0.4V, 2.2V ≤ VIN < 5.5V, TJ = –40°C to +100°C Shutdown time (3) ±2.0 130 Ground pin current tSHDN –3.0 VIN = 95% VOUT(NOM), IOUT = 150mA IGND Startup time % % VOUT = 0.90 × VOUT(NOM) tSTR +2 % Output current limit (2) ±1 ±2.0 ICL Power-supply rejection ratio V –2 ±1.0 Output noise voltage PSRR UNIT 5.5 0mA ≤ IOUT ≤ 150mA VN IEN MAX VOUT(NOM) + 0.5V ≤ VIN ≤ 5.5V, IOUT = 5mA BW = 100Hz to 100kHz, VIN = 2.2V, VOUT = 1.2V, IOUT = 1mA ISHDN (1) (2) (3) (4) Dropout voltage TJ = +25°C Over VIN, IOUT, VOUT + 0.5V ≤ VIN ≤ 5.5V, temperature 0mA ≤ IOUT ≤ 150mA ΔVOUT/ΔIOUT Load regulation VDO TYP 2.2 Nominal VOUT MIN 18 mA 130 nA 40 nA f = 10Hz 40 dB f = 100Hz 20 dB f = 1kHz 15 dB 500 ms 500 (4) ms +160 °C COUT = 1.0mF, VOUT = 10% VOUT(NOM) to VOUT = 90% VOUT(NOM) IOUT = 150mA, COUT = 1.0mF, VOUT = 2.8V, VOUT = 90% VOUT(NOM) to VOUT = 10% VOUT(NOM) Shutdown, temperature increasing Reset, temperature decreasing +140 –40 °C +125 °C VDO is not measured for devices with VOUT(NOM) ≤ 2.3V because minimum VIN = 2.2V. Time from VEN = 1.2V to VOUT = 90% (VOUT(NOM)). Time from VEN = 0.4V to VOUT = 10% (VOUT(NOM)). See Shutdown in the Application Information section for more details. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS782xx SBVS115B – AUGUST 2008 – REVISED MAY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM IN OUT Current Limit Mux Thermal Shutdown EEPROM Bandgap EN Active PullDown 10kW Logic GND PIN CONFIGURATIONS DDC PACKAGE TSOT23-5 (TOP VIEW) IN GND (1) EN 1 5 DRV PACKAGE 2mm x 2mm SON-6 (TOP VIEW) OUT 2 3 4 GND (1) OUT 1 N/C 2 GND (1) All ground pins must be connected to ground for proper operation. (2) It is recommended that the thermal pad be grounded. (1) Thermal Pad 3 (2) 6 IN 5 GND 4 EN (1) Table 1. PIN DESCRIPTIONS PIN 4 NAME DRV DDC OUT 1 5 Regulated output voltage pin. A small (1mF) ceramic capacitor is needed from this pin to ground to assure stability. See the Input and Output Capacitor Requirements in the Application Information section for more details. N/C 2 — Not connected. EN 4 3 Driving the enable pin (EN) over 1.2V turns ON the regulator. Driving this pin below 0.4V puts the regulator into shutdown mode, reducing operating current to 18nA typical. GND 3, 5 2, 4 IN 6 1 Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input capacitor = 1.0mF. Both input and output capacitor grounds should be tied back to the IC ground with no significant impedance between them. Thermal pad Thermal pad — It is recommended that the thermal pad on the SON-6 package be connected to ground. Submit Documentation Feedback DESCRIPTION ALL ground pins must be tied to ground for proper operation. Copyright © 2008–2010, Texas Instruments Incorporated TPS782xx www.ti.com SBVS115B – AUGUST 2008 – REVISED MAY 2010 TYPICAL CHARACTERISTICS Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted. LINE REGULATION IOUT = 5mA, VOUT = 2.7V (typ) TPS78227 LINE REGULATION IOUT = 150mA, VOUT = 2.7V (typ) TPS78227 1.0 3 0.8 TJ = -40°C 0.6 0.4 1 0.2 VOUT (%) VOUT (%) 2 TJ = +25°C 0 -0.2 TJ = +85°C -0.4 TJ = -40°C 0 -1 -0.6 -2 TJ = +85°C -0.8 -1.0 -3 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 5.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 Figure 1. Figure 2. LOAD REGULATION VIN = 3.8V, VOUT = 2.7V TPS78227 DROPOUT VOLTAGE vs OUTPUT CURRENT VOUT = 2.7V (typ), VIN = 0.95 × VOUT (typ) TPS78227 3 5.6 250 TJ = +125°C VDO (VIN - VOUT) (mV) 2 TJ = -40°C 1 VOUT (%) TJ = +25°C 0 -1 TJ = +25°C TJ = +85°C 200 TJ = +85°C 150 100 50 -2 TJ = -40°C TJ = +25°C 0 -3 0 25 50 75 IOUT (mA) 100 Figure 3. Copyright © 2008–2010, Texas Instruments Incorporated 125 150 0 25 50 75 IOUT (mA) 100 125 150 Figure 4. Submit Documentation Feedback 5 TPS782xx SBVS115B – AUGUST 2008 – REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted. DROPOUT VOLTAGE vs JUNCTION TEMPERATURE VOUT = 2.7V (typ), VIN = 0.95 × VOUT (typ) TPS78227 GROUND PIN CURRENT vs INPUT VOLTAGE IOUT = 0mA, VOUT = 3.3V TPS78233 250 900 100mA 100 TJ = +25°C 500 400 300 50mA TJ = -40°C 200 100 10mA 0 0 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 95 110 125 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VIN (V) Figure 5. Figure 6. GROUND PIN CURRENT vs INPUT VOLTAGE IOUT = 50mA, VOUT = 2.7V TPS78227 GROUND PIN CURRENT vs INPUT VOLTAGE IOUT = 150mA, VOUT = 2.7V TPS78227 6 3 5 TJ = +85°C 2 TJ = +125°C 1 VOUT (%) 4 IGND (mA) TJ = +85°C 600 150 50 3 2 TJ = -40°C 0 -1 TJ = +25°C TJ = -40°C 1 -2 0 TJ = +85°C TJ = +25°C -3 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) Figure 7. 6 TJ = +125°C 700 150mA IGND (nA) VDO (VIN - VOUT) (mV) 800 200 Submit Documentation Feedback 5.0 5.2 5.4 5.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 5.6 Figure 8. Copyright © 2008–2010, Texas Instruments Incorporated TPS782xx www.ti.com SBVS115B – AUGUST 2008 – REVISED MAY 2010 TYPICAL CHARACTERISTICS (continued) Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted. CURRENT LIMIT vs INPUT VOLTAGE VOUT = 95% VOUT (typ), VOUT = 2.7V (typ) TPS78227 ENABLE PIN CURRENT vs INPUT VOLTAGE IOUT = 100mA, VOUT = 2.7V TPS78227 300 2.0 290 1.8 1.6 270 1.4 TJ = -40°C 260 250 IEN (nA) Current Limit (mA) 280 TJ = +25°C 240 TJ = +85°C 230 220 TJ = +25°C 1.0 TJ = +85°C 0.8 0.6 0.4 TJ = +125°C 210 TJ = -40°C 1.2 0.2 200 0 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 5.6 3.8 4.0 4.2 4.4 4.6 4.8 VIN (V) 5.0 5.2 5.4 Figure 9. Figure 10. ENABLE PIN HYSTERESIS vs JUNCTION TEMPERATURE IOUT = 1mA, TPS78227 %ΔVOUT vs JUNCTION TEMPERATURE VIN = 3.3V, VOUT = 2.7V (typ) TPS78227 1.2 5.6 1 1.1 0.1mA 0.9 VEN On %DVOUT (V) VEN (V) 1.0 0.8 0.7 0 5mA -1 VEN Off 150mA 0.6 0.5 0.4 -2 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 Figure 11. Copyright © 2008–2010, Texas Instruments Incorporated 95 110 125 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 95 110 125 Figure 12. Submit Documentation Feedback 7 TPS782xx SBVS115B – AUGUST 2008 – REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted. %ΔVOUT vs JUNCTION TEMPERATURE VIN = 3.7V, VOUT = 2.7V (typ) TPS78227 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY CIN = 1mF, COUT = 2.2mF, VIN = 3.2V TPS78227 Output Spectral Noise Density (mV/ÖHz) 3 %DVOUT (V) 2 1 0.1mA 0 5mA -1 150mA -2 -3 -40 -25 -10 5 20 35 50 TJ (°C) 65 80 95 100 10 150mA 109mVRMS 1 0.1 50mA 109mVRMS 0.01 1mA 108mVRMS 0.001 110 125 10 100 10k 100k Figure 13. Figure 14. RIPPLE REJECTION vs FREQUENCY VIN = 4.2V, VOUT = 2.7V, COUT = 2.2mF TPS78227 INPUT VOLTAGE RAMP vs OUTPUT VOLTAGE TPS78233 80 VIN 60 50 40 50mA Enable VOUT Load Current 30 0V 20 VIN = 0.0V to 5.0V VOUT = 3.3V IOUT = 150mA COUT = 10mF Current (50mA/div) Voltage (1V/div) 1mA 70 PSRR (dB) 1k Frequency (Hz) 150mA 10 0 10 100 1k 10k 100k Frequency (Hz) Figure 15. 8 Submit Documentation Feedback 1M 10M Time (20ms/div) Figure 16. Copyright © 2008–2010, Texas Instruments Incorporated TPS782xx www.ti.com SBVS115B – AUGUST 2008 – REVISED MAY 2010 TYPICAL CHARACTERISTICS (continued) Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted. OUTPUT VOLTAGE vs ENABLE (SLOW RAMP) TPS78233 Load Current VIN = 5.5V VOUT = 3.3V IOUT = 150mA COUT = 10mF 0A 0V 0V VIN Load Current Time (1ms/div) Figure 17. Figure 18. LOAD TRANSIENT RESPONSE TPS78233 ENABLE PIN vs OUTPUT VOLTAGE RESPONSE AND OUTPUT CURRENT TPS78233 Enable VOUT Load Current Current (10mA/div) VIN = 5.5V VOUT = 3.3V IOUT = 0mA to 10mA COUT = 10mF Voltage (1V/div) Enable VOUT VIN Load Current VIN = 5.50V VOUT = 3.3V IOUT = 150mA COUT = 10mF 0V 0A Time (5ms/div) Current (50mA/div) Voltage (100mV/div) Time (20ms/div) VIN VIN = 0.0V to 5.5V VOUT = 2.2V IOUT = 100mA COUT = 10mF VOUT Current (50mA/div) VOUT Voltage (1V/div) Enable Current (50mA/div) Voltage (1V/div) VIN INPUT VOLTAGE vs DELAY TO OUTPUT TPS78222 Time (1ms/div) Figure 19. Figure 20. VIN Enable VOUT Load Current 0V VIN = 5.5V VOUT = 3.3V IOUT = 150mA COUT = 10mF Current (50mA/div) Voltage (1V/div) ENABLE PIN vs OUTPUT VOLTAGE DELAY TPS78233 Time (1ms/div) Figure 21. Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS782xx SBVS115B – AUGUST 2008 – REVISED MAY 2010 www.ti.com APPLICATION INFORMATION APPLICATION EXAMPLES The TPS782 family of LDOs is factory-programmable to have a fixed output. Note that during startup or steady-state conditions, it is important that the EN pin voltage never exceed VIN + 0.3V. 4.2V to 5.5V VIN 2.7V IN VOUT OUT 1 mF 1mF TPS78227 On Off EN GND Figure 22. Typical Application Circuit The TPS782 series are designed to be stable with standard ceramic capacitors with values of 1.0mF or larger at the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. Maximum ESR should be less than 1.0Ω. With tolerance and dc bias effects, the minimum capacitance to ensure stability is 1mF. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance (such as PSRR, output noise, and transient response), it is recommended that the printed circuit board (PCB) be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. High ESR capacitors may degrade PSRR. INTERNAL CURRENT LIMIT INPUT AND OUTPUT CAPACITOR REQUIREMENTS Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1mF to 1.0mF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located near the power source. If source impedance is not sufficiently low, a 0.1mF input capacitor may be necessary to ensure stability. 10 Submit Documentation Feedback The TPS782 is internally current-limited to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the device should not be operated in a current limit state for extended periods of time. The PMOS pass element in the TPS782 series has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current may be appropriate. Copyright © 2008–2010, Texas Instruments Incorporated TPS782xx www.ti.com SBVS115B – AUGUST 2008 – REVISED MAY 2010 SHUTDOWN DROPOUT VOLTAGE The enable pin (EN) is active high and is compatible with standard and low-voltage CMOS levels. When shutdown capability is not required, EN should be connected to the IN pin, as shown in Figure 23. The TPS782 series, with internal active output pull-down circuitry, discharges the output to within 5% VOUT with a time (t) shown in Equation 1: The TPS782 series use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in the Typical Characteristics section. Refer to application report SLVA207, Understanding LDO Dropout, available for download from www.ti.com. t=3 10kW ´ RL ´ COUT 10kW + RL (1) Where: RL= output load resistance COUT = output capacitance 4.2V to 5.5V VIN TRANSIENT RESPONSE 2.7V IN VOUT OUT 1 mF 1mF TPS78227 As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. For more information, see Figure 19. ACTIVE VOUT PULL-DOWN EN GND Figure 23. Circuit Showing EN Tied High when Shutdown Capability is Not Required Copyright © 2008–2010, Texas Instruments Incorporated In the TPS782 series, the active pull-down discharges VOUT when the device is off. However, the input voltage must be greater than 2.2V for the active pull-down to work. MINIMUM LOAD The TPS782 series are stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at very light output loads. The TPS782 employs an innovative, low-current circuit under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero output current. See Figure 19 for the load transient response. Submit Documentation Feedback 11 TPS782xx SBVS115B – AUGUST 2008 – REVISED MAY 2010 www.ti.com THERMAL INFORMATION THERMAL PROTECTION Thermal protection disables the device output when the junction temperature rises to approximately +160°C, allowing the device to cool. Once the junction temperature cools to approximately +140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off again. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS782 series has been designed to protect against overload conditions. However, it is not intended to replace proper heatsinking. Continuously running the TPS782 series into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Dissipation Ratings table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2: PD = (VIN - VOUT) ´ IOUT (2) PACKAGE MOUNTING Solder pad footprint recommendations for the TPS782 series are available from the Texas Instruments web site at www.ti.com through the TPS782 series product folders. 12 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated TPS782xx www.ti.com SBVS115B – AUGUST 2008 – REVISED MAY 2010 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September, 2008) to Revision B Page • Updated title of data sheet .................................................................................................................................................... 1 • Changed first bullet of Features list ...................................................................................................................................... 1 • Changed ground pin current, IOUT = 0mA typical specification from 1.0mA to 0.42mA .......................................................... 3 • Added Figure 6 ..................................................................................................................................................................... 6 Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS78218DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78218DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78222DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78222DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78223DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78223DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78225DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78225DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78225DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78225DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78225DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78225DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78225DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78225DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78227DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78227DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78227DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 23-Mar-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS78227DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78227DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78227DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78227DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78227DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78228DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78228DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78228DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78228DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78228DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78228DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78228DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78228DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78230DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78230DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78230DRVR ACTIVE SON DRV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78230DRVT ACTIVE SON DRV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78233DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 23-Mar-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS78233DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS78236DDCR ACTIVE SOT DDC 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS78236DDCT ACTIVE SOT DDC 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS78225, TPS78227, TPS78228, TPS78230 : • Automotive: TPS78225-Q1, TPS78227-Q1, TPS78228-Q1, TPS78230-Q1 NOTE: Qualified Version Definitions: Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2012 • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 22-Mar-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS78218DRVR SON DRV 6 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78218DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78222DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78222DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78223DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78223DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78225DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78225DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78225DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78225DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78227DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78227DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78227DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78227DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78228DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78228DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78228DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78228DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Mar-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS78230DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78230DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78230DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78230DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 TPS78233DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78233DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78236DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TPS78236DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS78218DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS78218DRVT SON DRV 6 250 203.0 203.0 35.0 TPS78222DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS78222DRVT SON DRV 6 250 203.0 203.0 35.0 TPS78223DDCR SOT DDC 5 3000 195.0 200.0 45.0 TPS78223DDCT SOT DDC 5 250 195.0 200.0 45.0 TPS78225DDCR SOT DDC 5 3000 195.0 200.0 45.0 TPS78225DDCT SOT DDC 5 250 195.0 200.0 45.0 TPS78225DRVR SON DRV 6 3000 203.0 203.0 35.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 22-Mar-2012 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS78225DRVT SON DRV 6 250 203.0 203.0 35.0 TPS78227DDCR SOT DDC 5 3000 195.0 200.0 45.0 TPS78227DDCT SOT DDC 5 250 195.0 200.0 45.0 TPS78227DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS78227DRVT SON DRV 6 250 203.0 203.0 35.0 TPS78228DDCR SOT DDC 5 3000 195.0 200.0 45.0 TPS78228DDCT SOT DDC 5 250 195.0 200.0 45.0 TPS78228DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS78228DRVT SON DRV 6 250 203.0 203.0 35.0 TPS78230DDCR SOT DDC 5 3000 195.0 200.0 45.0 TPS78230DDCT SOT DDC 5 250 195.0 200.0 45.0 TPS78230DRVR SON DRV 6 3000 203.0 203.0 35.0 TPS78230DRVT SON DRV 6 250 203.0 203.0 35.0 TPS78233DDCR SOT DDC 5 3000 203.0 203.0 35.0 TPS78233DDCT SOT DDC 5 250 203.0 203.0 35.0 TPS78236DDCR SOT DDC 5 3000 195.0 200.0 45.0 TPS78236DDCT SOT DDC 5 250 195.0 200.0 45.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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