TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 D Single-Chip RF Transceiver for 915-MHz D D D D D D D D D Typical Output Frequency Resolution of ISM Band 902-MHz to 928-MHz Operation FM/FSK Operation for Transmit and Receive 24-Bit Direct Digital Synthesizer (DDS) With 11-Bit DAC On-Chip VCO and PLL On-Chip Reference Oscillator Minimal External Components Required Low Power Consumption Typical Output Power of 4.5 dBm 230 Hz D Ultrafast Lock Times From DDS D D D D D Implementation Two Fully Programmable Operational Modes 3-V to 3.6-V Operation Fast Radio Strength Signal Indicator (RSSI) Flexible Serial Interface to TI MSP430 Microcontroller 48-Pin Low-Profile Plastic Quad Flat Package (PQFP) IF1_IN IF1_OUT IF_GND IF2_IN DEM_GND VREF LNA_VCC LNA_OUT MIX_IN MIX_VCC MIX_OUT MIX_GND PQFP PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 LNA_GND LNA_IN LNA_GND PA_VCC PA_OUT PA_GND PLL_GND PD_SET PD_OUT2 PD_OUT1 LOCKDET PLL_VCC 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 DEM_VCC DEM_TANK DEM_TANK RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT DATA CLOCK STROBE VCO_TANK1 VCO_TANK2 DDS_GND STDBY MODE DDS_VCC TX_DATA DIG_VCC DIG_GND GND XOSC1 XOSC2 13 14 15 16 17 18 19 20 21 22 23 24 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 description The TRF5901 single-chip solution is a low cost FSK transceiver to establish a frequency-agile, half-duplex, bidirectional RF link. The device is available in a 48-lead TQFP package and is designed to provide a fully functional multichannel FM transceiver. The single-chip transceiver operates down to 3 V and is expressly designed for low power consumption. The synthesizer has a typical channel spacing of approximately 230 Hz to allow narrow-band as well as wide-band application. Due to the narrow channel spacing of the direct digital synthesizer (DDS), the DDS can be used to adjust the TX/RX frequency and allows the use of inexpensive reference crystals. Two fully-programmable operation modes, Mode0 and Mode1, allow fast switching between two preprogrammed settings (e.g., TX(RX)_frequency_0, RX(TX)_frequency_1) without reprogramming the device. Each functional block of the transceiver can be specifically enabled or disabled via the serial interface. transmitter The transmitter consists of an integrated VCO, a complete fully programmable direct digital synthesizer, and a power amplifier. The internal VCO can be used with an external tank circuit or an external VCO. The divider, prescaler, and reference oscillator require only the addition of an external crystal and a loop filter to provide a complete DDS with a typical frequency resolution of 230 Hz. The 8-bit FSK frequency deviation register determines the frequency deviation in FSK mode. The modulation itself is done in the direct digital synthesizer, hence no additional external components are necessary. Since the typical RF output power is approximately 4.5 dBm, no additional external RF power amplifier is necessary in most applications. receiver The integrated receiver is intended to be used as a single-conversion FSK receiver. It consists of an integrated VCO, a complete fully programmable direct digital synthesizer, a low-noise amplifier, mixer, IF amplifier, limiter, FM/FSK demodulator with an external LC tank circuit, and a data slicer. The receive strength signal indicator ( RSSI ) can be used for fast carrier sense detection or as an on/off keying, or amplitude shift keying, (OOK/ASK) demodulator. In the learning mode, during a learning sequence (0,1,0,1,0,....), the initial tolerances of the LC demodulator tank circuit are compensated and an external capacitor is charged to a dc voltage that is proportional to the average demodulation dc level. This level is the zero reference for the data slicer to generate the logical levels of the data sequence that follow the learning sequence. Using the internal data switch, the demodulated OOK and FSK signals are available at the same DATA_OUT terminal. baseband interface The TRF5901 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430 ultralow-power microcontroller (see Figure 1). The TRF5901 serial control registers are programmed by the MSP430 and the MSP430 performs baseband operations in software. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 Antenna Microcontroller Section RF Section RSSI_OUT TX_DATA RF In LNA_IN DATA_OUT LOCKDET RF Out PA_OUT MODE TRF5901 TRANSCEIVER + DISCRETES STDBY DATA CLOCK STROBE RSSI Out (Analog Signal) Transmit Data Receive Data Lock Detect Mode Select Standby MSP430 Family µC Programmable Digital I/O Pins Serial Control Data Serial Control Clock Serial Control Strobe Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 LNA_GND LNA_IN LNA_GND PA_VCC PA_OUT PA_GND PLL_GND PD_SET 45 44 43 42 41 40 39 RF Buffer Amplifier VREF 37 FM/FSK Demodulator RSSI 1st IF Amplifier 4 Power Amplifier 36 35 RF Mixer LNA 3 38 2nd IF Amplifier/ Limiter 1 2 DEM_GND IF2_IN IF_GND IF1_OUT IF1_IN MIX_GND MIX_VCC MIX_IN 46 MIX_OUT 47 LNA_OUT 48 LNA_VCC functional block diagram LO Buffer Amplifier 34 33 Buffer Amplifier Data Switch 32 5 LPF Amplifier/ Post-Detection Amplifier 6 31 30 7 8 Data Slicer TRF5901 (TOP VIEW) 29 PD_OUT2 9 28 DEM_VCC DEM_TANK DEM_TANK RSSI_OUT AMP_IN AMP_CAP AMP_OUT S&H_CAP DATA_OUT PLL 11 12 Serial Interface 22 23 DATA CLOCK STROBE 24 XOSC2 21 XOSC1 20 GND 19 DIG_GND 18 DIG_VCC 17 TX_DATA 16 DDS_VCC 15 MODE 14 VCO_TANK1 13 26 25 VCO STDBY PLL_VCC 27 Direct Digital Synthesizer, Power-Down Logic, and Buffers DDS_GND LOCKDET 10 VCO_TANK2 PD_OUT1 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION Connection for LPF amplifier/post-detection amplifier capacitor/resistor used to reduce the internal low-pass filter frequency and to adjust the post-detection gain. AMP_CAP 31 I/O AMP_IN 32 I Analog post-detection amplifier input AMP_OUT 30 O Analog post-detection amplifier output CLOCK 26 I Serial interface clock signal DATA 27 I Serial interface data signal DATA_OUT 28 O Digital output of the data slicer, active high DDS_GND 15 4 Direct digital synthesizer ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 Terminal Functions (Continued) TERMINAL NAME DDS_VCC NO. I/O 18 DESCRIPTION Direct digital synthesizer supply voltage DEM_GND 38 DEM_TANK 34, 35 Quadrature demodulator ground DEM_VCC 36 Quadrature demodulator supply voltage DIG_GND 21 Digital ground DIG_VCC 20 Digital supply voltage IF_GND 40 IF1_IN 42 I IF1_OUT 41 O IF2_IN 39 I LNA_GND 1, 3 I/O Quadrature demodulator tank connection Intermediate frequency (IF) section ground Single-ended input for the 1st intermediate frequency (IF) amplifier Single-ended output for the 1st intermediate frequency (IF) amplifier Single-ended input for the 2nd IF amplifier/limiter Low-noise amplifier ground LNA_IN 2 I Low-noise amplifier input LNA_OUT 47 O Low-noise amplifier output, open collector LNA_VCC 48 Low-noise amplifier supply voltage LOCKDET 11 MIX_GND 43 O PLL lock detect output, active high. PLL locked when LOCKDET = 1. MIX_IN 46 I Single-ended RF mixer input MIX_OUT 44 O Single-ended RF mixer output MIX_VCC 45 MODE 17 GND 22 PA_GND 6 PA_OUT 5 Mixer ground Mixer supply voltage I Mode select input. The functionality of the device in Mode0 or Mode1 can be programmed via the A-, B-, C-, and D-word of the serial control interface. Ground Power amplifier ground O Power amplifier output, open collector PA_VCC 4 PD_OUT1 10 O Power amplifier supply voltage Charge pump output – PLL in locked condition PD_OUT2 9 O Charge pump output – PLL in unlocked condition PD_SET 8 Charge pump current setting terminal. An external resistor (RPD) is connected to this terminal to set the nominal charge pump current. PLL_GND 7 PLL ground PLL_VCC 12 RSSI_OUT 33 O Receive strength signal indicator, analog output S&H_CAP 29 I/O Connection for sample and hold capacitor for the data slicer. This capacitor determines the integration time constant of the integrator while in the learning mode. STDBY 16 I Standby control for the TRF5901, active low. While STDBY = 0, the contents of the control registers are still valid and can be programmed via the serial control interface. STROBE 25 I Serial interface strobe signal TX_DATA 19 I Digital modulation buffered input for FSK/FM modulation of the carrier, active high VCO_TANK1 13 I VCO tank circuit connection. Should be left open if an external VCO is used. VCO_TANK2 14 I VCO tank circuit connection. May also be used to input an external VCO signal. VREF 37 I Reference voltage for the quadrature demodulator XOSC1 23 O Reference crystal oscillator connection XOSC2 24 I Reference crystal oscillator connection. May be used as a single-ended clock input if an external crystal is not used. PLL supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, PLL_VCC, DDS_VCC, DIG_VCC, PA_VCC, DEM_VCC, MIX_VCC, LNA_VCC (see Note 1) . . . . . . . . . . . . . . . . . . . –0.6 to 4.5 Vdc Input voltage, logic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 to 4.5 Vdc Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All GND and VCC terminals must be connected to either ground or supply, respectively, even if the function block is not used. ESD NOTE: Terminal 5 is not protected against ESD; other terminals have limited ESD protection to 1 kV HBM. recommended operating conditions MIN Supply voltage, PA_VCC, PLL_VCC, DIG_VCC, DDS_VCC, DEM_VCC, MIX_VCC, LNA_VCC Operating temperature High-level input voltage, VIH (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY) TYP UNIT 3 3.6 V –40 85 °C VCC–0.5 V Low-level input voltage, VIL (DATA, CLOCK, STROBE, TX_DATA, MODE, STDBY) High-level output voltage, VOH (LOCKDET, DATA_OUT); IOH = 0.5 mA MAX 0.5 VCC–0.5 V V Low-level output voltage, VOL (LOCKDET, DATA_OUT); IOL = 0.5 mA 0.5 V electrical characteristics over full range of operating conditions, (typical values are at PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC, PA_VCC = 3 V, TA = 25°C) (unless otherwise noted) supply current consumption in each mode MODE ACTIVE STAGES MIN TYP MAX UNIT Power down (standby mode) None 0.5 5 µA RX – FSK (narrow band) or carrier sense DDS, PLL, VCO, LNA (normal mode), mixer, first IF amplifier, limiter, (demodulator, LPF amplifier, data slicer or RSSI) 28 35 mA 37 53 26 35 20-dB attenuation 21 27 PA disabled 9.5 13 PA STATE 0-dB attenuation TX 6 10-dB attenuation DDS,, PLL,, VCO,, PA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 electrical characteristics over full range of operating conditions, (typical values are at PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC, PA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) LNA/RF mixer PARAMETER TEST CONDITIONS RF frequency range MIN TYP 902 LNA in normal mode LNA gain LNA noise figure 1 dB compression LNA input 1-dB LNA input IP3 7.5 MAX UNIT 928 MHz 12 LNA in low-gain mode 4 LNA in normal mode 4 dB dB 5.8 LNA in normal mode –20 –15 dBm LNA in low-gain mode –18 –13 dBm LNA in normal mode –12 –5 dBm –6 1 dBm LNA in low-gain mode LNA input impedance Ω See Figure 3 LNA output impedance Ω See Figure 4 LO frequency range 891 IF frequency range Mixer conversion gain 3 Mixer SSB noise figure IF frequency = 10.7 MHz Mixer input impedance 939 Mixer input IP3 MHz 7.5 dB 17.5 dB –8 Mixer input 1-dB compression Ω 1 dBm –9 dBm LO level at mixer input –35 IF frequency = 10.7 MHz, See Figure 6 MHz 10.7 See Figure 5 Mixer output impedance dB dBm Ω 330 VCO PARAMETER TEST CONDITIONS Frequency range MIN TYP 891 Tuning range Phase noise 50-kHz offset Tuning voltage 0.5 MAX UNIT 939 MHz 60 MHz –86 dBc/Hz VCC–0.4 V first IF amplifier PARAMETER TEST CONDITIONS MIN IF amplifier frequency range TYP MAX 10.7 IF amplifier gain 5.5 IF amplifier noise figure MHz 7 12 UNIT dB 14 dB IF amplifier input 1-dB compression –12 –3 dBm IF amplifier input IP3 –3.5 4 dBm IF amplifier input impedance IF frequency = 10.7 MHz, See Figure 8 330 Ω IF amplifier output impedance IF frequency = 10.7 MHz, See Figure 9 330 Ω POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 electrical characteristics over full range of operating conditions, (typical values are at PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC, PA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) second IF amplifier/limiter PARAMETER TEST CONDITIONS MIN IF amplifier/limiter frequency range IF amplifier/limiter gain† TYP MAX 10.7 IF frequency = 10.7 MHz, See Figure 10 MHz 80 dB 9 dB 330 Ω IF amplifier/limiter noise figure† IF amplifier/limiter input impedance † Not directly accessible, specified by design UNIT RSSI PARAMETER TEST CONDITIONS MIN RSSI range at limiter input –80 RSSI output voltage range 0.44 TYP MAX UNIT –10 dBm 2.6 Nominal slope 19 Response time step from power off to –20 dBm at limiter input V mV/dB 1 5 TYP MAX µs low-pass filter amplifier [second order] PARAMETER TEST CONDITIONS MIN Internal low-pass filter frequency 0.75 UNIT MHz demodulator PARAMETER Demodulation output bandwidth} TEST CONDITIONS Acquisition range} Slew rate} MIN TYP MAX UNIT IF frequency = 10.7 MHz 0.3 IF frequency = 10.7 MHz 300 MHz kHz 2 V/µs ‡ Dependent upon external LC tank circuit. data slicer PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output current R(load) = 3.3 kΩ, C(load) = 10 pF 1 mA Rise time R(load) = 3.3 kΩ, C(load) = 10 pF 0.1 µs direct digital synthesizer (DDS) PARAMETER frequency ƒref Reference oscillator input frequency, Programmable DDS divider ratio TEST CONDITIONS MAX 26 as buffer 15 26 0 4194303 22 bits N × ƒref ÷ 224 8 bits 0 N × ƒref ÷ 222 FSK – modulation resolution 8 TYP 15 DDS divider resolution, ∆ƒ FSK – modulation register ratio MIN as oscillator POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1020 UNIT MHz TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 electrical characteristics over full range of operating conditions, (typical values are at PLL_VCC, DDS_VCC, DIG_VCC, DEM_VCC, MIX_VCC, LNA_VCC, PA_VCC = 3 V, TA = 25°C) (unless otherwise noted) (continued) PLL PARAMETER TEST CONDITIONS RF input frequency MIN TYP MAX UNIT 939 MHz 891 RF input power Internal VCO bypassed; external input applied to VCO_TANK2 RF input divider ratio, N dBm 512 N × ƒref ÷ 224 RF output frequency resolution Charge pump current –10 256 Programmable with external resistor, 100 kΩ nominal, APLL = 0 µA 70 power amplifier PARAMETER TEST CONDITIONS Frequency range MIN TYP MAX UNIT 928 MHz 902 Amplifier output power 0-dB attenuation –1 4.5 10-dB attenuation –5 –0.5 20-dB attenuation –14 –8 dBm Amplifier off Optimal load impedance 2nd-order harmonic –56 See Figure 22 VCC = 3 V, 0-dB attenuation VCC = 3 V, 0-dB attenuation 3rd-order harmonic –13 dBc –27 dBc typical mode switching and lock times OPERATION TEST CONDITIONS MIN TYP MAX UNIT Frequency hop time between adjacent channels, during receive† From transition of MODE to DATA_OUT valid, channel spacing = 500 kHz, APLL = 111b (maximum) 30 µs Receive-to-transmit turnaround time† From transition of MODE to valid RF signal at PA_OUT, PLL locked, 10.7 MHz RX to TX separation 200 µs Transmit-to-receive turnaround time† From transition of MODE to valid data at DATA_OUT, PLL locked, 10.7 MHz RX to TX separation 200 µs Standby to receive time† From rising edge of STDBY to valid data at DATA_OUT, APLL = 111b (maximum) 600 µs Standby to transmit time† From rising edge of STDBY to valid RF signal at PA_OUT, APLL = 111b (maximum) 500 µs † Highly dependent upon loop filter topology. timing data for serial interface (see Figure 2) PARAMETER MIN MAX UNIT 20 MHz f(CLOCK) tw(CLKHI) CLOCK frequency CLOCK high time pulse width, CLOCK high 25 ns tw(CLKLO) tsu(DATA) CLOCK low time pulse width, CLOCK low 25 ns Setup time, data valid before CLOCK high 25 ns th(DATA) tw(STROBEHI) Hold time, data valid after CLOCK high 25 ns Strobe high time pulse width, STROBE high (see Note 2) 25 ns 25 ns tw(STROBELO) Strobe low time pulse width, STROBE low NOTE 2: CLOCK and DATA must both be low when STROBE is asserted (STROBE = 1). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 tw(CLKLO) tw(CLKHI) tw(STROBEHI) CLOCK tsu(DATA) DATA tw(STROBELO) th(DATA) STROBE Figure 2. Serial Data Interface Timing detailed description low-noise amplifier The low-noise amplifier (LNA) provides a typical gain of 13 dB and a typical noise figure of 3.3 dB. Two operating modes, normal and low-gain mode, can be selected. The normal operation mode is selected when maximum sensitivity at low input levels is required. If high RF input levels are applied to the TRF5901, the LNA should be operated in the low-gain mode. This ensures a minimum of nonlinear distortions in the overall receiver chain. ↑1 U CH1 S11 ↑1 U CH1 S22 1 1 0.5 2 0.5 5 2 5 CAL OFS 0 0.2 0.5 1 2 5 10 CAL OFS 0 0.2 0.5 1 2 5 10 1 CPL –5 CPL –5 1 FIL 1k –0.5 FIL 1k –0.5 –2 –1 START 850 MHz –2 –1 STOP 950 MHz Figure 3. Typical LNA Input Impedance (S11) at Device Terminal LNA_IN START 850 MHz STOP 950 MHz Figure 4. Typical LNA Output Impedance (S22) at Device Terminal LNA_OUT The low impedance of the LNA input can be easily matched to 50 Ω to interface with a filter or an RF switch. At the LNA open collector output, a filter network can be used for image suppression as well as impedance matching. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 RF mixer The RF mixer is designed to operate with the on-chip VCO. If an external LO is used, a typical drive level of –10 dBm should be applied at the VCO input terminal. The mixer is a conventional double-balanced Gilbert cell mixer designed to provide a high IP3, typically 1 dBm. Since the mixer output’s push-pull amplifier has a 330-Ω output impedance, a conventional 330-Ω ceramic filter can be directly connected to the output without additional matching. The mixer output can also be directly connected to the second IF amplifier/limiter input terminal, IF2_IN, through a single conventional 330-Ω ceramic filter, thus bypassing the first IF amplifier. Figure 5 and Figure 6 show the RF mixer input and output impedances, respectively. ↑1 U CH1 S11 ↑1 U CH1 S22 1 1 0.5 2 0.5 5 2 5 CAL OFS 0 0.2 1 0.5 1 2 5 10 OFS 0 0.2 0.5 1 2 5 1 10 CPL CPL –5 –5 FIL 1k –0.5 FIL 1k –0.5 –2 –1 START 850 MHz CAL –2 –1 STOP 950 MHz Figure 5. Typical RF Mixer Input Impedance (S11) at Device Terminal MIX_IN START 5 MHz STOP 25 MHz Figure 6. Typical RF Mixer Output Impedance (S22) at Device Terminal MIX_OUT first IF amplifier The first IF amplifier provides a typical gain of 7 dB to compensate for losses caused by a ceramic filter. The input and output of the first IF amplifier is matched internally to 330 Ω, permitting direct connections to 330-Ω ceramic filters. If filters with different impedances are used, an impedance matching network is required. A second filter can be connected between the first IF amplifier and the second IF amplifier/limiter to increase the receiver selectivity. Alternately, the RF mixer output can be directly connected to the second IF amplifier as shown in Figure 7. A single ceramic filter can also be used to connect terminal 41 to terminal 39. In this case, a 0.1-µF dc-blocking capacitor should be used to connect terminal 44 to 42 to maximize receiver sensitivity. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 first IF amplifier (continued) BPF External Components 46 44 RF Mixer 42 1st IF Amplifier 39 41 2nd IF Amplifier/ Limiter Figure 7. Bypassing the First IF Amplifier Figure 8 and Figure 9 show the first IF amplifier input and output impedances, respectively. ↑1 U CH1 S11 ↑1 U CH1 S22 1 1 PRN 0.5 2 0.5 5 2 5 CAL OFS 0 0.2 0.5 1 2 5 10 OFS 0 0.2 0.5 1 2 5 10 CPL CPL –5 –5 FIL 1k –0.5 FIL 1k –0.5 –2 –1 START 5 MHz CAL –2 –1 STOP 25 MHz Figure 8. Typical First IF Amplifier Input Impedance (S11) at Device Terminal IF1_IN START 5 MHz STOP 25 MHz Figure 9. Typical FIrst IF Amplifier Output Impedance (S22) at Device Terminal IF1_OUT second IF amplifier/limiter The second IF amplifier/limiter consists of several differential amplifier stages with an overall gain of approximately 80 dB. At the IF2_IN 330-Ω input, a minimum signal level of approximately 32 µV is required to generate a limited signal at the limiter output. The limiter output is directly fed to the FM/FSK demodulator. Figure 10 shows the second IF amplifier/limiter input impedance. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 second IF amplifier/limiter (continued) ↑1 U CH1 S11 1 0.5 2 5 CAL OFS 0 0.2 0.5 1 2 5 10 CPL –5 FIL 1k –0.5 –2 –1 START 5 MHz STOP 25 MHz Figure 10. Typical Second IF Amplifier/Limiter Input Impedance (S11) at Device Terminal IF2_IN received signal strength indicator (RSSI) The received signal strength indicator provides a voltage at terminal 33, RSSI_OUT, that is proportional to the RF limiter input level. The slope of the RSSI circuit is typically 19 mV/dB over a frequency range of 10 MHz to 21.4 MHz. Because of its ultrafast response time (typically 1 µs per –20 dBm to off step), the RSSI can easily be used as an amplitude-shift keying (ASK) or on/off keying (OOK) demodulator for data rates up to 100K bit/sec. FM/FSK demodulator The demodulator is intended for analog (FM) and digital (FSK) frequency demodulation. It consists of a quadrature demodulator with an external LC tank circuit. A variable inductor, internal to the TRF5901, operates in parallel with the external tank circuit (see Figure 13), and is used to adjust the external tank circuit’s resonant frequency. If the tolerances of the external demodulator tank circuit components can provide a maximum frequency error of less than 5%, then no additional adjustments are required. As long as the device is in the learning mode, the internal reactance automatically fine-adjusts the resonant frequency of the external LC tank circuit. Depending on the supply voltage, the tank circuit tuning range is approximately four times the discriminator 3-dB bandwidth. While in the learning mode i.e., during a dc-free learning sequence of 0,1,0,1,0,...., the initial tolerances of the LC demodulator tank circuit are compensated and an external capacitor (connected to terminal 29, S&H_CAP) is charged to a dc voltage that is proportional to the average demodulation dc level. This level establishes the decision threshold voltage and consequently sets the zero reference for the data slicer to generate the logical levels of the data sequence that follow the learning sequence. Therefore, the user can use a non-dc-free data signal. The demodulator is automatically activated if the limiter (x_LIM) and low-pass filter amplifier (x_LPF) are activated and the data switch is set to FSK/FM reception (x_SW = 0). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 data switch The TRF5901 incorporates an internal data switch used to select the input signal for the low-pass filter amplifier/post detection amplifier. Depending on the settings in the Mode0 or Mode1 enable registers (C-word, D-word), the user can select between OOK/ASK or FSK baseband processing without having to change external components. low-pass filter amplifier/post-detection amplifier The low-pass filter amplifier/post-detection amplifier is configured to operate as a current-to-voltage amplifier and may be used to realize a low-pass filter for post detection. The low-pass amplifier bandwidth may be adjusted according to noise and signal bandwidth requirements. An internal 10-pF capacitor sets the maximum –3-dB corner frequency to approximately 0.75 MHz (see Figure 11 and Figure 12). C1 External Components R1 R1 32 31 From Data Switch 30 32 R2 – Vref C2 C1 From Data Switch To Data Slicer + 31 30 R2 – Vref Figure 11. First-Order Low-Pass Filter Example External Components To Data Slicer + Figure 12. Second-Order Low-Pass Filter Example The amplifier can be configured as a first- or second-order low-pass filter with bandwidths that are determined by external components. The internal resistor R2 is set to 10 kΩ, hence the –3-dB corner frequency for a second-order low pass filter (as shown in Figure 12) can be derived from the following formula: ƒg ^ 2 p Ǹ10 kW 1 , where R1 C1 C2 C1 [ 3 C2 data slicer The data slicer is fundamentally a comparator. The data slicer provides binary logic level signals, derived from the demodulated and low-pass filtered IF signal, that are able to drive external CMOS compatible inputs. The noninverting input is directly connected to the internal reference voltage, Vref, and the inverting input is driven by the output of the low-pass filter amplifier/post-detection amplifier. The decision threshold of the data slicer is determined by the internal reference voltage, Vref. The automatic frequency control (AFC) loop scheme for the TRF5901 is shown in Figure 13. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 data slicer (continued) Low-Pass Filter Amplifier/ Post-Detection Amplifier C1 External Tank Circuit 35 IF2_IN 34 R1 32 31 FM/FSK Demodulator 39 Limiter External Components C2 30 – Vref Internal Variable Inductor – DATA_OUT + 28 + Vref – + Integrator Vref Figure 13. AFC Loop to Control the Data Slicer Decision Threshold The integrator, acting as an error amplifier, takes the low-pass filtered output signal and generates a control voltage proportional to the frequency error of the external tank circuit as compared to the limiter output signal. By adjusting the value of the internal variable inductor, this control voltage is used to fine-tune the external tank to its nominal value. The acquisition time of the AFC loop can be adjusted by an external capacitor connected to terminal 29, S&H_CAP. This capacitor determines the integration time constant of the integrator while in learning mode. As a rule of thumb, the time constant of the AFC loop should be at least five times greater than the baseband signal fundamental period. The time constant of the entire AFC control loop can be calculated as follows: t AFC [ 22 kW C terminal 29 The automatic frequency control loop controls the resonant frequency of the external LC tank without any additional external adjustments as long as learning mode operation is selected. If hold mode is selected, the AFC loop is open and an external dc voltage can be applied at terminal 29 to set the threshold of the data slicer. During learning mode, a precharged capacitor (connected to terminal 29, S&H_CAP) can be used to set the dc threshold voltage of the data slicer in hold mode. In other words, the data slicer constantly integrates the incoming signal during the learning sequence (0,1,0,1. . .) and charges the external capacitor connected to terminal 29, S&H_CAP to a dc voltage level, Vref, that is proportional to the average demodulation dc level. After a predefined time (dependent upon the application), the data slicer is switched to hold mode. The data slicer stops integrating and uses the voltage stored on the external capacitor as the decision threshold between a logic 0 or a logic 1 on the DATA_OUT terminal 28. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 reference oscillator The reference oscillator provides the DDS system clock. It allows operation, with a suitable external crystal, between 15 MHz and 26 MHz. An external oscillator may be used to supply clock frequencies between 15 MHz and 26 MHz. The external oscillator should be directly connected to XOSC2, terminal 24. The other oscillator terminal (XOSC1, terminal 23) should be left open or can be used as a buffered version of the signal applied at terminal 24 (see Figure 14). The same crystal or externally supplied oscillator signal is used to derive the transmit and receive frequencies. XOSC1 XOSC2 23 24 NC External Signal, ƒref Figure 14. Applying an External Oscillator Signal direct digital synthesizer (DDS) general principles of DDS operation In general, a direct digital synthesizer (DDS) is based on the principle of generating a sinewave signal in the digital domain. Benefits include high precision, wide frequency range, a high degree of software programmability, and extremely fast lock times. A block diagram of a typical DDS is shown in Figure 15. It generally consists of an accumulator, sine lookup table, a digital-to-analog converter, and a low-pass filter. All digital blocks are clocked by the reference oscillator. Synthesizer + N-Bit Register Sine Lookup Table DAC Low-Pass Filter Analog Output Signal Frequency Register Load With Frequency Word Figure 15. Typical DDS Block Diagram The DDS constructs an analog sine waveform using an N-bit adder counting up from 0 to 2N in steps of the frequency register, whereby generating a digital ramp waveform. Each number in the N-bit output register is used to select the corresponding sine wave value out of the sine lookup table. After the digital-to-analog conversion, a low-pass filter is necessary to suppress unwanted spurious responses. The analog output signal can be used as a reference input signal for a phase locked loop. The PLL circuit then multiplies the reference frequency by a predefined factor. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 TRF5901 direct digital synthesizer implementation A block diagram of the DDS implemented in the TRF5901 is shown in Figure 16. It consists of a 24-bit accumulator clocked by the reference oscillator along with control logic settings. 24 Reference Frequency, ƒref + 24-Bit Register 11 11-Bit DAC Sine Shaper Low-Pass Filter ƒDDS to PLL DDS Frequency Register MODE – (Terminal 17) A – Word DDS Mode0 Frequency Setting B – Word DDS Mode1 Frequency Setting 22 D – Word / DEV Bits (FSK Deviation) 24 22 Mode0/1 Select Logic FSK Frequency Deviation Register Modulation Control Logic + 8 TX_DATA – (Terminal 19) C – Word / MM Bit (Modulation Mode Select) Figure 16. DDS Block Diagram as Implemented in the TRF5901 The frequency of the reference oscillator, ƒref, is the DDS sample frequency, which also determines the maximum DDS output frequency. Together with the accumulator width (in bits), the frequency resolution of the DDS can be calculated. Multiplied by the divider ratio (prescaler) of the PLL, N, the minimum frequency step size of the TRF5901 is calculated as follows: Dƒ + N ƒ ref 2 24 The 24-bit accumulator can be programmed via two 22-bit frequency setting registers (the A-word determines the mode0 frequency, the B-word determines the mode1 frequency) with the two MSB bits set to zero. Consequently, the maximum bit weight of the DDS system is reduced to 1/8 (see Figure 17). This bit weight corresponds to a VCO output frequency of (ƒref/8) × N. Depending on the MODE terminal’s (terminal 17) logic level, the internal mode select logic loads the frequency register with either the DDS_0 or DDS_1 frequency (see Figure 16 and Figure 17). 22 DDS Frequency Setting For Mode0/1 From A-Word/B-Word ... X X X X X 0 0 X X .... 23 DDS Frequency Register LSB MSB 22 21 20 . . . ... 4 3 Bit weight: 1/2 1/4 1/8 1/16 . . . 8 2 1 0 ... 1 2 24 FSK Frequency Deviation Register – DEV 0 0 .... MSB 23 22 . . . . .... X X X X X X X X 0 0 DDS Frequency Register LSB ....9 8 7 6 5 4 3 2 1 0 Figure 17. Implementation of the DDS Frequency and FSK Frequency Deviation in the DDS Frequency Register POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 TRF5901 direct digital synthesizer implementation (continued) The VCO output frequency, ƒout, which is dependent on the DDS_x frequency settings ( DDS_0 in the A-word or DDS_1 in the B-word ), can be calculated as follows: ƒ out + DDS_x ƒ ref N 2 24 +N ƒ ref DDS_x 2 24 If FSK modulation is selected (MM=0; C-Word, bit 16) the 8-bit FSK deviation register can be used to program the frequency deviation of the 2-FSK modulation. Figure 17 illustrates where the 8 bits of the FSK deviation register map into the 24-bit DDS frequency register. Since the two LSBs are set to zero, the total FSK deviation can be determined as follows: Dƒ 2–FSK + N ƒ ref DEV 2 22 Hence, the 2-FSK frequency, set by the level of TX_DATA, is calculated as follows: ƒ out1:TX_DATA+Low + N ƒ ref DDS_x 2 24 ƒ out2:TX_DATA+High + N ƒ ref (DDS_x ) 4 DEV) 2 24 This frequency modulated output signal is used as a reference input signal for the PLL circuit. Note that the frequencies ƒout1 and ƒout2 are centered about the frequency ƒcenter = (ƒout1 + ƒout2)/2. When transmitting FSK, ƒcenter is considered to be the effective carrier frequency and any receiver local oscillator (LO) should be set to the same ƒcenter frequency ± the receiver’s IF frequency (ƒIF) for proper reception and demodulation. For the case of low-side injection, the receiver LO would be set to ƒLO = ƒcenter – ƒIF. Using low-side injection, the received data at terminal 28, DATA_OUT, would be inverted from the transmitted data applied at terminal 19, TX_DATA. Conversely, for high-side injection, the receiver LO would be set to ƒLO = ƒcenter + ƒIF. Using high-side injection, the received data would be the same as the transmitted data. In addition, when the TRF5901 is placed in receive mode, it is recommended that the TX_DATA terminal be kept low. In this manner, the actual LO frequency injected into the mixer is ƒout1 = ƒLO. If TX_DATA is set high, the contents of the deviation register would offset the receiver LO resulting in poor receiver sensitivity. Channel width (frequency deviation) for 2-FSK modulation and channel spacing are software programmable. The minimum channel width and minimum channel spacing depend on the RF system frequency plan. Since the DDS registers are static, preprogrammed values are retained during standby mode. This feature greatly reduces turnon time, reduces current consumption when coming out of standby mode, and enables very fast lock-times. The PLL lock-times ultimately determine when data can be transmitted or received. phase-locked loop The phase-locked loop (PLL) of the TRF5901 consists of a phase detector (PD) and a frequency acquisiton aid (FD), two charge pumps, an external loop filter, a voltage controlled oscillator (VCO), and a programmable fixed prescaler (N-divider) in the feedback loop (see Figure 18). The PLL as implemented in the TRF5901 multiplies the DDS output frequency and further suppresses the unwanted spurious signals produced by the direct digital synthesizer. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 phase-locked loop (continued) DDS ƒDDS PD 10 IPD_1 IPD_2 ƒref FD External Loop Filter 13, 14 VCO ƒout 9 N-Divider 256 / 512 Figure 18. Basic PLL Structure VCO A modified Colpitts oscillator architecture with an external resonant circuit is used for the TRF5901. The internal bias current network adjusts the signal amplitude of the VCO. This allows a wide range of Q-factors (30….60) for the external tank circuit. The VCO can be bypassed by applying an external RF signal at VCO_TANK2, terminal 14. To drive the internal PLL, a typical level of –10 dBm should be applied. When an external VCO is used, the x_VCO bit should be set to 0. phase detector and charge pumps The TRF5901 contains two charge pumps for locking to the desired frequency: one for coarse tuning of the frequency differences (called the frequency acquisition aid), and one for fine tuning of the phase differences (used in conjunction with the phase detector). The XOR phase detector and charge pumps produce a mean output current that is proportional to the phase difference between the reference frequency and the VCO frequency divided by N; N=256 or 512. The TRF5901 generates the current pulses IPD_1 during normal operation (PLL locked). An additional slip detector and acquisition aid charge pump generates current pulses at terminal PD_OUT2 during the lock-in of the PLL. This charge pump is turned off when the PLL locks in order to reduce current consumption. The multiplication factor of the acquisition aid current IPD_2 can be programmed by three bits (APLL) in the C-word. The slip detector output, PD_OUT2, at terminal 9 should be connected directly to the loop filter capacitor C1, as in Figure 21. The nominal charge pump current I0 is determined by the external resistor RPD, connected to terminal 8, and can be calculated as follows: I0 + 7 V R PD During normal operation (PLL locked), the acquisition aid charge pump is disabled and the maximum charge pump current IPD_1 is determined by the nominal value I0 (see Figure 19). I0 1 IPD_1 Figure 19. Normal Operation Charge Pump Current, IPD_1 Each time the PLL is in an unlocked condition, the acquisition aid charge pump generates current pulses IPD_2. The IPD_2 current pulses are APLL times larger than I0 (see Figure 20). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 phase detector and charge pumps (continued) I0 1 IPD_1 APLL IPD_2 Figure 20. Acquisition Aid (IPD_2) and Normal Operation (IPD_1) Charge Pump Currents programmable divider The internal divider ratio, N, can be set to 256 or 512 via the C-word. Since a higher divider ratio adds additional noise within the multiplication loop, the lowest divider ratio possible for the target application should be used. loop filter Loop filter designs are a balance between lock-time, noise, and spurious suppression. For the TRF5901, common loop filter design rules can be used to determine an appropriate low-pass filter. Standard formulas can be used as a first approach to calculate a basic loop filter. Figure 21 illustrates a basic third-order loop filter. VCO_TANK1 C3 VCO_TANK2 14 13 R2 10 PD_OUT1 C3c L1 R1 PD_OUT2 9 C3d C2 VCO C4 C1 2nd-Order Loop Filter 3rd-Order Loop Filter Figure 21. Basic Third-Order Loop Filter Structure For maximum suppression of the unwanted frequency components, the loop filter bandwidth should generally be made as narrow as possible. At the same time, the filter bandwidth has to be wide enough to allow for the 2-FSK modulation and appropriate lock-time. A detailed simulation of the phase-locked loop should be performed and later verified on PCB implementations. power amplifier The power amplifier (PA) can be programmed via two bits (P0 and P1 in the D-word) to provide varying output power levels. Several control loops are implemented internally to set the output power and to minimize the sensitivity of the power amplifier to temperature, load impedance, and power supply variations. The output stage of the PA usually operates in Class-C and enables easy impedance matching. PA_OUT, terminal 5, is an open collector output terminal. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 power amplifier (continued) ↑1 U CH1 S22 1 2 0.5 5 CAL OFS 0 0.2 0.5 1 2 10 CPL –5 1 FIL 1k –2 –0.5 –1 START 850 MHz STOP 950 MHz Figure 22. Power Amplifier Output Impedance (S22) at Device Terminal 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 PRINCIPLES OF OPERATION serial control interface A 3-wire unidirectional serial bus (CLOCK, DATA, STROBE) is used to program the TRF5901 (see Figure 23). The internal registers contain all user programmable variables including the DDS frequency setting registers as well as all control registers. At each rising edge of the CLOCK signal, the logic value on the DATA terminal is written into a 24-bit shift register. Setting the STROBE terminal high loads the programmed information into the selected latch. While the STROBE signal is high, the DATA and CLOCK lines must be low (see Figure 2). Since the CLOCK and STROBE signals are asynchronous, care should be taken to ensure these signals remain free of glitches and noise. As additional leading bits are ignored, only the least significant 24 bits are serial-clocked into the shift register. Due to the static CMOS design, the serial interface consumes virtually no current and it can be programmed in active as well as in standby mode. The control words are 24 bits in length. The first incoming bit functions as the most significant bit ( MSB ). To fully program the TRF5901, four 24-bit words must be sent: the A-, B-, C-, and D-word. If individual bits within a word are to be changed, then it is sufficient to program only the appropriate 24-bit word. The definition of the control words are illustrated in Figure 24. Tables 1, 2, and 3 describe the function of each parameter. CLOCK STROBE Serial Interface Logic Shift Register DATA 22 A - Latch 22 ADDR 3 B - Latch ADDR Decoder 21 C - Latch 21 D - Latch 21 E - Latch Figure 23. Serial Interface Block Diagram The E-latch, addressed by an ADDR equal to 111, is reserved for test purposes and should not be used. Inadvertently addressing the E-latch activates the test modes of the TRF5901. If the test mode has been inadvertently activated, it can only be exited by switching VCC on and off or by clearing the E-latch. The E-latch can be cleared by addressing it and resetting its entire contents by programming 1110 0000 0000 0000 0000 0000. As part of a proper power-up sequence, it is recommended to clear the E-latch each time VCC is applied before starting further operations with the TRF5901. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 PRINCIPLES OF OPERATION A-Word (Programming of DDS_0) MSB 23 0 22 21 20 19 18 17 0 LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDS Frequency Setting for Mode0 (DDS_0 [21:0]) ADDR B-Word (Programming of DDS_1) MSB 23 0 22 21 20 19 18 17 1 LSB 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDS Frequency Setting for Mode1 (DDS_1 [21:0]) ADDR C-Word (Control Register for PLL, Data Slicer and Mode1 Settings) MSB 23 1 22 21 0 20 19 18 17 A2 A1 14 13 X APLL ADDR 16 15 PLL 1 12 11 10 X NPLL MM SLCTL 9 LSB 8 7 6 5 4 3 2 1 PLL VCO SLC LPF SW RSSI LIM IF MIX LNAM L1 A0 D-Word (Control Register for Mode0 Settings) MSB 23 1 22 21 1 0 20 0 19 18 17 0 0 0 16 15 0 0 L0 LSB 14 13 0 0 Mode1 Control Register [12:0] 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode0 Control Register [12:0] 0 PLL VCO SLC LPF SW RSSI LIM IF MIX LNAM L1 ADDR L0 NOTE: Start programming with MSB and ensure that the CLOCK and DATA lines are low during the rising edge of the strobe signal. Figure 24. Serial Control Word Format POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 PRINCIPLES OF OPERATION Table 1. Mode0 Control Register Description (D-Word) SYMBOL BIT LOCATION 0_LNAM [1:0] INITIAL SETTINGS AFTER POWER UP NUMBER OF BITS DESCRIPTION Low-noise amplifier operation mode 2 L1 0 0 1 1 L0 0 1 0 1 DEFAULT VALUE Disabled 00b : LNA disabled : LNA enable – low-gain mode : LNA disabled : LNA enable – normal operation mode 0_MIX [2] 1 0_IF [3] 1 Enable mixer Enable 1st IF amplifier 0_LIM [4] 1 Enable limiter 0_RSSI [5] 1 Enable RSSI 0_SW [6] 1 DEFAULT STATE 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b Routed to Demodulator 0b 0b Data switch 0 : LPF amplifier input routed to demodulator (FSK/FM) 1 : LPF amplifier input routed to RSSI (OOK/ASK) 0_LPF 0_SLC 0_PA [7] 1 Enable LPF amplifier 1: enabled 0: disabled Disabled [8] 1 Enable data slicer 1: enabled 0: disabled Disabled 0b Disabled 00b [10:9] Power amplifier mode 2 0_VCO [11] 0_PLL [12] P1 0 0 1 1 P0 0 : disabled 1 : 10-dB attenuation, enable modulation via TX_DATA 0 : 20-dB attenuation, enable modulation via TX_DATA 1 : 0-dB attenuation, enable modulation via TX_DATA 1 During operation, this bit should always be enabled (1: enabled), unless an external VCO is used. Disabled 0b Enable PLL (DDS system, RF, VCO, divider, phase comparator and charge pump) 1: enabled 0: disabled Disabled 0b 1 NOTE: The FM/FSK demodulator is automatically enabled if the limiter and low-pass amplifier are enabled and the data switch is set to FSK reception. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 PRINCIPLES OF OPERATION Table 2. Mode1 Control Register Description (C-Word) SYMBOL BIT LOCATION 1_LNAM [1:0] INITIAL SETTINGS AFTER POWER UP NUMBER OF BITS DESCRIPTION Low-noise amplifier operation mode 2 L1 0 0 1 1 L0 0 1 0 1 DEFAULT VALUE Disabled 00b : LNA disabled : LNA enable – low-gain mode : LNA disabled : LNA enable – normal operation mode 1_MIX [2] 1 1_IF [3] 1 Enable mixer Enable 1st IF amplifier 1_LIM [4] 1 Enable limiter 1_RSSI [5] 1 Enable RSSI 1_SW [6] 1 DEFAULT STATE 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b 1: enabled 0: disabled Disabled 0b Routed to Demodulator 0b 0b Data switch 0 : LPF amplifier input routed to demodulator (FSK/FM) 1 : LPF amplifier input routed to RSSI (OOK/ASK) 1_LPF 1_SLC 1_PA [7] 1 Enable LPF amplifier 1: enabled 0: disabled Disabled [8] 1 Enable data slicer 1: enabled 0: disabled Disabled 0b Disabled 00b [10:9] Power amplifier mode 2 1_VCO [11] 1_PLL [12] P1 0 0 1 1 P0 0 : disabled 1 : 10-dB attenuation, enable modulation via TX_DATA 0 : 20-dB attenuation, enable modulation via TX_DATA 1 : 0-dB attenuation, enable modulation via TX_DATA 1 During operation, this bit should always be enabled (1: enabled), unless an external VCO is used. Disabled 0b Enable PLL (DDS system, VCO, RF divider, phase comparator and charge pump) 1: enabled 0: disabled Disabled 0b 1 NOTE: The FM/FSK demodulator is automatically enabled if the limiter and low-pass amplifier are enabled and the data switch is set to FSK reception. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 PRINCIPLES OF OPERATION Table 3. Miscellaneous Control Register Description SYMBOL WORD BIT LOCATION NUMBER OF BITS DDS_0 A-word [21:0] 22 DDS_1 B-word [21:0] DEV D-word [20:13] SLCTL C-word APLL INITIAL SETTINGS AFTER POWER UP DESCRIPTION DEFAULT STATE DEFAULT VALUE DDS frequency setting in Mode0 Zero All zeroes 22 DDS frequency setting in Mode1 Zero All zeroes 8 FSK frequency deviation register Zero All zeroes [15] 1 Slicer mode select bit 0 : hold mode 1 : learning mode Hold mode 0b C-word [20:18] 3 Acceleration factor for the frequency acquisition aid charge pump A2 A1 A0 0 0 0 :1 0 0 1 : 20 0 1 0 : 40 0 1 1 : 60 : 1 1 1 : 140 Zero 000b NPLL C-word [17] 1 PLL divider ratio 0 : 256 1 : 512 256 0b MM C-word [16] 1 Modulation mode select. Sets the behavior of pin TX_DATA to FSK data input. 0 : FSK/FM 1 : Do not use FSK mode 0b operating modes Table 4 and Table 5 illustrate operating modes and transmit frequencies as set by the STDBY, MODE and TX_DATA terminals used in conjunction with the DDS frequency settings. Table 4. Transmitting Data in FSK Mode (MM bit set to 0) TERMINAL TRANSMIT FREQUENCY STDBY MODE TX_DATA 1 0 0 ƒout =ƒref × N × (DDS_0)/224 1 0 1 1 1 0 ƒout =ƒref × N × (DDS_0 + 4 × DEV)/224 ƒout = ƒref × N × (DDS_1)/224 1 1 1 ƒout = ƒref × N × (DDS_1 + 4 × dev)/224 Table 5. Operating Mode Per STDBY Terminal STDBY OPERATING MODE 0 Standby/programming mode – power down of all blocks 1 Operating mode and programming mode Two independent operating modes, Mode0 and Mode1, allow extremely fast switching between two preprogrammed settings by toggling the MODE terminal. Each mode can be viewed as a bank of configuration registers which store the frequency settings and the enable/disable settings for each functional block of the TRF5901. The MODE terminal is then used to asynchronously switch between Mode0 and Mode1 as shown in Figure 25. Several examples of operating sequences are shown in Table 6. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 PRINCIPLES OF OPERATION operating modes (continued) MODE Terminal (Terminal 17) = 1 Mode0 Register Settings (D-Word) Mode1 Register Settings (C-Word) Mixer Enable Mixer Enable 1st IF Amplifier Enable 1st IF Amplifier Enable Limiter Enable Limiter Enable RSSI Enable RSSI Enable Data Switch Data Switch LPF Amplifier Enable LPF Amplifier Enable Data Slicer Enable Data Slicer Enable Power Amplifier Mode Power Amplifier Mode VCO Enable VCO Enable PLL Enable PLL Enable Synthesizer: Synthesizer: DDS Frequency DDS Frequency MODE Terminal (Terminal 17) = 0 Figure 25. Interaction Between MODE Terminal and Preprogrammed Mode0 and Mode1 Control Registers Table 6. Operating Mode Examples FUNCTION/DESCRIPTION MODE0 MODE1 Receive polling with frequency hopping, or scan band Receive on frequency 0 Receive on frequency 1 Transmit and receive on different frequencies Transmit on frequency 0 Receive on frequency 1 Broadcast on one frequency and receive on another Transmit on frequency 0 (broadcast channel) Receive on frequency 1 Rapid switch between receive and power saving mode (keep DDS/VCO running) Receive on frequency 0 All blocks off except DDS, VCO, and PLL Emulate FSK transmit operation using the MODE terminal for wideband FSK Transmit on frequency 0 Transmit on frequency 0 + deviation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 PRINCIPLES OF OPERATION operating modes (continued) Received Data Stream RSSI Active PLL Locked, Wait For RSSI Signal Enter Operating Mode Store Control Word Enter Standby/Programming Mode, Scan in Serial Control Word (MSB Scanned in First) OPERATION RSSI_OUT LOCKDET STDBY STROBE CLOCK DATA_OUT Bit 21 Bit 22 DATA MSB Bit 23 ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Not Valid Data Bit 2 Bit 1 LSB Bit 0 Valid Valid Valid Data Data Data Figure 26 illustrates how the user of the TRF5901 can preload the serial control words while in standby/programming mode and then receive baseband data while in operating mode. Figure 26. Preloading Serial Control Word and Receiving Baseband Data 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF5901 SINGLE-CHIP RF TRANSCEIVER SWRS014 – DECEMBER 2002 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°–ā7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads connected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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