TI TRF6903PT

SWRS022B − MARCH 2004 − REVISED AUGUST 2004
D Single-Chip RF Transceiver for 315-MHz,
D
D
D
D
D
D
D
D Clock Recovery With Integrated Data Bit
433-MHz, 868-MHz, and 915-MHz Industrial,
Scientific, and Medical (ISM) Bands
2.2-V to 3.6-V Operation
Low Power Consumption
FSK/OOK Operation
Integer-N Synthesizer With Fully Integrated
Voltage Controlled Oscillator (VCO)
On-Chip Reference Oscillator and
Phase-Locked Loop (PLL)
Power Amplifier With 8-dBm Typical Output
Power
Programmable Brownout Detector
D
D
D
D
D
D
D
D
Synchronizer and Baud Rate Selection
Linear Receive Strength Signal Indicator
(RSSI)
Flexible 3-Wire Serial Interface
Minimal Number of External Components
Required
48-Pin Low-Profile Plastic Quad Flat
Package (PQFP)
Programmable XTAL Trimming
Lock Detect Indicator
Programmable Training Sequence
Recognition
Pin Compatible to the TRF6901
GND
RSSI_OUT
DEM_VCC
LEARN/HOLD
DEM_GND
LPF_IN
MIX_VCC
MIX_OUT
MIX_GND
DET_OUT
IF_IN1
IF_IN2
PQFP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
LNA_IN1
LNA_IN2
LNA_VCC
PA_OUT
PA_GND1
PA_VCC
PA_GND2
VCO_GND1
VCO_VCC
VCO_VCC2
VCO_BYPASS
VCO_GND2
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
LPF_OUT
CER_DIS
SLC_CAP
RX_DATA
TX_DATA
XTAL_SW
XTAL
XTAL_VCC
DGND
DCLK
STDBY
NC
VCO_TUNE
CP_GND
CP_OUT
CP_VCC
DVDD
CLOCK
STROBE
DATA
MODE
LOCK_DETECT
RX_FLAG
NC
13 14 15 16 17 18 19 20 21 22 23 24
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
POST OFFICE BOX 655303
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1
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
description
The TRF6903 single-chip solution is an integrated circuit intended for use as a low-cost multiband FSK or OOK
transceiver to establish a frequency-programmable, half-duplex, bidirectional RF link. The multichannel
transceiver is intended for digital (FSK, OOK) modulated applications in the North American and European
315-MHz, 433-MHz, 868-MHz, and 915-MHz ISM bands. The single-chip transceiver operates down to 2.2 V
and is designed for low power consumption. The synthesizer has a typical channel spacing of better than
200 kHz and features a fully-integrated VCO. Only the PLL loop filter is external to the device.
Two fully-programmable operation modes, Mode0 and Mode1, allow extremely fast switching between two
preprogrammed settings (for example, receive (RX)/transmit (TX); TX_frequency_0/TX_frequency_1;
RX_frequency_0/RX_frequency_1; …) without reprogramming the device.
ISM band standards
Europe has assigned an unlicensed frequency band of 868 MHz to 870 MHz. This band is specifically defined
for short range devices with duty cycles from 0.1% to 100% in several subbands. The new European frequency
band, due to the duty cycle assignment, allows a reliable RF link and makes many new applications possible.
The North American unlicensed ISM band covers 902 MHz to 928 MHz (center frequency of 915 MHz), and is
suitable for short range RF links.
transmitter
The transmitter consists of an integrated VCO and tank circuit, a complete integer-N synthesizer, and a power
amplifier. The dividers, prescaler, and reference oscillator require only the addition of an external crystal and
a loop filter to provide a complete PLL with a typical frequency resolution of better than 200 kHz.
Since the typical RF output power is approximately 8 dBm, no additional external RF power amplifier is
necessary in most applications.
Four attenuation settings for the power amplifier are offered. This feature allows the user to fine tune the
amplifier for optimal output power.
receiver
The integrated receiver is intended to be used as a single-conversion FSK/OOK receiver. It consists of a low
noise amplifier, mixer, limiter, FM/FSK demodulator with an external LC tank circuit or ceramic resonator, LPF
amplifier, and a data slicer with clock recovery and an integrated data bit synchronizer. The received strength
signal indicator (RSSI) can also be used for fast carrier sense on/off keying, or amplitude shift keying,
(OOK/ASK) demodulator.
baseband interface
The TRF6903 can easily be interfaced to a baseband processor such as the Texas Instruments MSP430
ultralow-power microcontroller (see Figure 1). The TRF6903 serial control registers are programmed by the
MSP430 and the MSP430 performs baseband operations in the software.
A synchronized data clock, programmable for most common data rates, is provided by the TRF6903. This
feature reduces the need for extensive oversampling and data decision in the microcontroller during receive.
During transmit, the data clock can be used to clock the transmit data from the microcontroller to the TRF6903
at predefined data rates.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
Antenna
Microcontroller
Section
RF Section
RSSI_OUT
TX_DATA
RF In
RX_DATA
LNA_IN1, 2
DCLK
RF Out
PA_OUT
LEARN/HOLD
TRF6903
Transceiver
+
Discretes
MODE
STDBY
DET_OUT
DATA
CLOCK
STROBE
LOCK_DETECT
RX_FLAG
RSSI Out (Analog Signal)
Transmit Data
Receive Data
Data Clock
Learn/Hold Select
Mode Select
Standby
Brownout Detector Out
MSP430
Family µC
Serial Control Data
Serial Control Clock
Serial Control Strobe
Lock Detect Out
Receive Data Flag
Figure 1. System Block Diagram for Interfacing to the MSP430 Microcontroller
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SWRS022B − MARCH 2004 − REVISED AUGUST 2004
functional block diagram
1, 2
LPF_OUT
LEARN / HOLD
SLC_CAP
IF_IN1,2
LPF_IN
MIX_OUT
44, 43
35
37
36
39
34
LPF Amplifier
Limiter
Mixer
LNA_IN1, LNA_IN2
RFIN
47
CER_DIS
Ceramic
Discriminator
10.7-MHz Ceramic
or Discrete IF FIlter
LNA
Data Slicer
Quadrature
Demodulator
OOK
Switch
RSSI
33
Bit Synchronizer
and
Data Clock
27
41
23
Band-gap
DET_OUT
45
8
/ACounter
Brownout
Detector
18
20
/Div. CTRL
6
/N Prescaler
Serial
Interface
19
26
21
/BCounter
32/33
RX_DATA
DCLK
RSSI_OUT
RX_FLAG
CLOCK
DATA
STROBE
STDBY
MODE
22
Lock
Detect
LOCK_DETECT
PA
Output
Divider
1, 2, 3
PFD
CPs
/Ref
2...255
VCO
VCO_TUNE
13
15 CP_OUT
Loop Filter
Terminal Functions
TERMINAL
NAME
4
NO.
CER_DIS
35
CLOCK
18
CP_GND
14
CP_OUT
15
CP_VCC
16
DATA
20
I/O
DESCRIPTION
Connect to external ceramic discriminator
I
Serial interface clock signal input
Charge pump ground
O
Charge pump output
Charge pump supply voltage
I
Serial interface data signal input
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
32
XTAL
Switch
30
XTAL_SW
4
XTAL
PA_OUT
31
TX_DATA
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
O
Data clock output
NAME
NO.
DCLK
27
DEM_GND
38
DEM_VCC
40
DET_OUT
45
DGND
28
Digital ground
DVDD
17
Digital power supply
GND
42
IF_IN1
44
I
Limiter amplifier noninverting input
IF_IN2
43
I
Limiter amplifier inverting input
LEARN/HOLD
39
I
Data slicer switch. Controls data slicer reference level
LNA_IN1
1
I
LNA noninverting input
LNA_IN2
2
I
LNA inverting input
LNA_VCC
3
LOCK_DETECT
22
LPF_IN
LPF_OUT
MIX_GND
46
MIX_OUT
47
MIX_VCC
48
MODE
NC
Demodulator ground
Demodulator supply voltage
O
Brownout detector output; active high
Substrate ground
LNA power supply
O
PLL lock detect signal, active high
37
I
Low-pass filter amplifier input
36
O
Low-pass filter amplifier output
21
Mixer ground
O
Mixer supply voltage
I
24, 25
PA_GND1
5
PA_GND2
7
PA_OUT
4
Mixer output
Mode select input
No connect
Power amplifier ground
Power amplifier ground
O
Power amplifier output
PA_VCC
6
RSSI_OUT
41
O
RSSI output signal
RX_DATA
33
O
Demodulated digital (FSK or OOK) RX data
RX_FLAG
23
O
Receive data flag
SLC_CAP
34
I/O
External capacitor for data slicer
STDBY
26
I
Standby input signal; active low
STROBE
19
I
Serial interface strobe signal
TX_DATA
32
I
Buffered TX data input
VCO_BYPASS
11
I
VCO bypass; connect to ground through a 100-pF capacitor
VCO_GND1
8
VCO_GND2
12
VCO_TUNE
13
Power amplifier supply voltage
VCO ground
VCO ground
I
Tuning voltage for the integrated VCO
VCO_VCC
9
VCO supply voltage
VCO_VCC2
10
VCO core supply voltage
XTAL
30
I/O
XTAL_SW
31
I
XTAL_VCC
29
Connection to an external crystal reference
Connecting to external capacitor, which sets the frequency deviation of the transmitted signal
Oscillator supply voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SWRS022B − MARCH 2004 − REVISED AUGUST 2004
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 to 4.5 Vdc
Input voltage, logic signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 to 4.5 Vdc
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
ESD protection, human body model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog supply voltage
2.2
3.6
V
Digital supply voltage
2.2
3.6
V
Operating free-air temperature
−40
85
°C
dc electrical characteristics, VCC = 2.7 V, TA = 25°C
supply current
PARAMETER
TEST CONDITIONS
Standby current
RX current, receive chain inactive. Bit synchronizer and data clock
inactive. PLL, VCO, dividers, and reference active
RX current, receive chain active. PLL, VCO, dividers, and reference
active. Bit synchronizer and data clock inactive
RX current, receive chain active. PLL, VCO, dividers, and reference
active. Bit synchronizer and data clock active
6
POST OFFICE BOX 655303
MIN
TYP
MAX
STDBY low
0.6
4
315-MHz band
12
15
433-MHz band
11
14
868-MHz band
10
12
915-MHz band
10
12
315-MHz band
20
26
433-MHz band
19
25
868-MHz band
18
23
915-MHz band
18
23
315-MHz band
20
26
433-MHz band
19
25
868-MHz band
18
23
915-MHz band
18
23
• DALLAS, TEXAS 75265
UNIT
µA
mA
mA
mA
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
dc electrical characteristics, VCC = 2.7 V, TA = 25°C (continued)
supply current (continued)
PARAMETER
TYP
MAX
315-MHz band
TEST CONDITIONS
12
15
433-MHz band
11
14
868-MHz band
10
12
915-MHz band
10
12
0-dB attenuation
315-MHz band
37
43
10-dB attenuation
315-MHz band
30
20-dB attenuation
315-MHz band
29
0-dB attenuation
433-MHz band
36
10-dB attenuation
433-MHz band
29
20-dB attenuation
433-MHz band
28
0-dB attenuation
868-MHz band
35
10-dB attenuation
868-MHz band
28
20-dB attenuation
868-MHz band
27
0-dB attenuation
915-MHz band
35
10-dB attenuation
915-MHz band
28
20-dB attenuation
915-MHz band
27
TX current, PA disabled. PLL, VCO, dividers, and reference active
TX current‡, PA enabled. PLL, VCO, dividers,
reference, and data clock active
MIN
UNIT
mA
42
40
mA
40
‡ The TX current consumption is dependent upon the external PA matching circuit. The matching network is normally designed to achieve the
highest output power at the 0-dB attenuation setting. Changing the external matching components to optimize the output power for other
attenuation settings alters the typical current consumption from the typical values noted.
digital interface
PARAMETER
VIH
VIL
High-level input voltage
VOH
VOL
High-level output voltage
TEST CONDITIONS
MIN
TYP
VDD−0.4
0
Low-level input voltage
IOH = 0.5 mA
IOL = 0.5 mA
Low-level output voltage
MAX
VDD
0.4
VDD−0.4
V
V
V
0.4
Digital input leakage current
UNIT
V
µA
<0.01
ac electrical characteristics, VCC = 2.7 V, TA = 25°C
receiver (LNA, mixer, limiter, demod, LPF amplifier, data slicer, VCO, and PLL)
PARAMETER
TEST CONDITIONS
MIN
TYP
RX wake-up time
MAX
1
BER, FSK
315 MHz, 433 MHz,
868 MHz, 915 MHz,
IF = 10.7 MHz, BW = 280 kHz
FSK deviation: ±32 kHz
Bit rate: 19.2 kbit/s
−103 < PRFIN (dBm) < − 30
10−3
BER, OOK
315 MHz, 433 MHz,
868 MHz, 915 MHz,
IF = 10.7 MHz, BW = 280 kHz
ON-OFF ratio: 50 dB
Bit rate: 9.6 kbit/s
−103 < PRFIN (dBm) < − 30
10−3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
ms
7
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
ac electrical characteristics, VCC = 2.7 V, TA = 25°C
LNA/mixer, 304−316 MHz
PARAMETER
TEST CONDITIONS
Frequency range
MIN
TYP
MAX
UNIT
304
315
316
dB
Conversion gain
21
SSB noise figure
Includes external matching network
dB
6.5
dB
Input 1-dB compression point
−31
dBm
Input IP3
−21
dBm
LNA/mixer, 430−450 MHz
PARAMETER
TEST CONDITIONS
Frequency range
MIN
TYP
MAX
UNIT
430
433
450
MHz
Conversion gain
21
SSB noise figure
Includes external matching network
dB
6.5
dB
Input 1-dB compression point
−31
dBm
Input IP3
−21
dBm
LNA/mixer, 868−870 MHz
PARAMETER
TEST CONDITIONS
Frequency range
MIN
TYP
MAX
UNIT
868
869
870
MHz
Conversion gain
19
dB
6.5
dB
Input 1-dB compression point
−31
dBm
Input IP3
−20
dBm
SSB noise figure
Includes external matching network
LNA/mixer, 902−928 MHz
PARAMETER
TEST CONDITIONS
Frequency range
MIN
TYP
MAX
UNIT
902
915
928
MHz
Conversion gain
18
dB
6.5
dB
Input 1-dB compression point
−31
dBm
Input IP3
−19
dBm
SSB noise figure
Includes external matching network
IF/limiter amplifier
PARAMETER
TEST CONDITIONS
MIN
Frequency
TYP
MAX
10.7
Voltage gain
Noise figure
IF frequency = 10.7 MHz
UNIT
MHz
86
dB
4
dB
VCO/output divider
MIN
TYP
MAX
UNIT
Frequency range: 315-MHz band
PARAMETER
Low-side injection, A<1:0> = 11
304
315
316
MHz
Frequency range: 433-MHz band
High-side injection, A<1:0> = 10
430
433
450
MHz
Frequency range: 868-MHz band
High-side injection, A<1:0> = 01
868
869
870
MHz
Frequency range: 915-MHz band
Low-side injection, A<1:0> = 01
902
915
928
MHz
Closed loop phase noise
TEST CONDITIONS
Frequency offset = 50 kHz
−77
Frequency offset = 200 kHz
−90
Tuning voltage
8
0.1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
dBc/Hz
VCC at
terminal 10
V
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued)
RSSI
PARAMETER
TEST CONDITIONS
MIN
Dynamic range
TYP
MAX
70
Rise time
RL = 100 kΩ,
CL = 10 pF
RSSI output current
dB
2
Slope
RL = 100 kΩ, CL = 10 pF
UNIT
4
µs
20
mV/dB
30
µA
impedances and loads
PARAMETER
TEST CONDITIONS
LNA_IN
MIN
TYP
MAX
UNIT
See Figure 4
MIX_OUT{
IF_IN{
Differential
1400
Ω
2600
Ω
See
Figure 10
PA_OUT
† Does not include external matching network.
transmitter (XTAL, PLL, VCO, and PA), 315-MHz band
PARAMETER
TEST CONDITIONS
TX frequency range
A<1:0> = 11
Output power†
MIN
TYP
MAX
UNIT
304
315
316
MHz
0-dB attenuation
8
10-dB attenuation
−2
20-dB attenuation
−12
Disabled, B<3> = 0
Off‡
−80
dBm
−80
Second harmonic
−25
dBc
Third harmonic
−30
dBc
32
kHz
Frequency deviation§
FSK
Power ON-OFF ratio
OOK, 0-dB mode
Data rate
75
dB
FSK
64
OOK
10
kbit/s
† Matched to 50 Ω using external matching network.
‡ Not selectable with PA attenuation bits A< 7 : 6 >, B< 7 : 6 >, or with B<3>. Measured while the TRF6903 device is in RX mode.
§ Dependent upon external circuitry.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SWRS022B − MARCH 2004 − REVISED AUGUST 2004
ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued)
transmitter (XTAL, PLL, VCO, and PA), 433-MHz band
PARAMETER
TEST CONDITIONS
TX frequency range
A<1:0> = 10
Output power†
MIN
TYP
MAX
UNIT
430
433
450
MHz
0-dB attenuation
8
10-dB attenuation
−2
20-dB attenuation
−12
Disabled, B<3> = 0
Off‡
−80
dBm
−80
Second harmonic
−25
dBc
Third harmonic
−30
dBc
32
kHz
Frequency deviation§
FSK
Power ON-OFF ratio
OOK, 0-dB mode
Data rate
75
dB
FSK
64
OOK
10
kbit/s
† Matched to 50 Ω using external matching network.
‡ Not selectable with PA attenuation bits A< 7 : 6 >, B< 7 : 6 >, or with B<3>. Measured while the TRF6903 device is in RX mode.
§ Dependent upon external circuitry.
transmitter (XTAL, PLL, VCO, and PA), 868-MHz band
PARAMETER
TEST CONDITIONS
TX frequency range
A<1:0> = 11
0-dB attenuation
Output power†
MIN
TYP
MAX
UNIT
868
869
870
MHz
8
10-dB attenuation
−2
20-dB attenuation
−12
Disabled, B<3> = 0
Off‡
−80
dBm
−80
Second harmonic
−25
dBc
Third harmonic
−30
dBc
32
kHz
75
dB
Frequency deviation§
FSK
Power ON-OFF ratio
OOK, 0-dB mode
Data rate
FSK
64
OOK
10
† Matched to 50 Ω using external matching network.
‡ Not selectable with PA attenuation bits A< 7 : 6 >, B< 7 : 6 >, or with B<3>. Measured while the TRF6903 device is in RX mode.
§ Dependent upon external circuitry.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
kbit/s
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
ac electrical characteristics, VCC = 2.7 V, TA = 25°C (continued)
transmitter (XTAL, PLL, VCO, and PA), 915-MHz band
PARAMETER
TEST CONDITIONS
TX frequency range
A<1:0> = 11
Output power†
MIN
TYP
MAX
UNIT
902
915
928
MHz
0-dB attenuation
8
10-dB attenuation
−2
20-dB attenuation
−12
Disabled, B<3> = 0
Off‡
−80
dBm
−80
Second harmonic
−25
dBc
Third harmonic
−30
dBc
±32
kHz
Frequency deviation§
FSK
Power ON-OFF ratio
OOK, 0-dB mode
Data rate
75
dB
FSK
64
OOK
10
kbit/s
† Matched to 50 Ω using external matching network.
‡ Not selectable with PA attenuation bits A< 7 : 6 >, B< 7 : 6 >, or with B<3>. Measured while the TRF6903 device is in RX mode.
§ Dependent upon external circuitry.
XTAL
PARAMETER
TEST CONDITIONS
Frequency range
MIN
TYP
9.5
MAX
UNIT
20
MHz
MAX
UNIT
brownout detector
PARAMETER
Voltage threshold, Vdet
TEST CONDITIONS
Set by B<2:1>
TYP
2.2
Voltage steps (∆V)
2.8
200
Number of steps
Output level
MIN
V
mV
4
Connected to typical input port of microcontroller
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CMOS
11
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
timing data for serial interface
PARAMETER
MIN
TYP
MAX
UNIT
20
MHz
f(CLOCK)
tw(CLKHI)
Clock frequency
Clock high-time pulse width, clock high
20
ns
tw(CLKLO)
tsu(D)
Clock low-time pulse width, clock low
20
ns
0
ns
th(D)
td(CLKLO)
Hold time, data valid after CLOCK ↑
10
ns
Delay time of CLOCK low before STROBE high
20
ns
tw(STROBEHI)
tw(STROBELO)
STROBE high-time pulse width, STROBE high
20
ns
STROBE low-time pulse width, STROBE low
20
ns
Setup time, data valid before CLOCK ↑
Data
Valid
DATA
Data
Change
MSB
MSB
LSB
t su(D) t
h(D)
t w(CLKHI)
t d(CLKLO)
Start of
Next Word
CLOCK
t w(STROBEHI)
t w(CLKLO)
STROBE
Clock Disabled
Shift in Data
Clock Enabled
Note: Most significant bit (MSB) clocked in first to the synthesizer.
Figure 2. Timing Data for Serial Interface
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
−V
H
−V
L
tw(STROBELOW)
tr
tf
−V
H
−V
L
Store Data
Strobe Enabled
−V
H
−V
L
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
timing data for DCLK, TX_DATA, RX_FLAG, and RX_DATA
PARAMETER
MIN
td(DG)
tsu(r)
Delay time, rising edge of DCLK to transition of RX_DATA
th(r)
td(FK)
Hold time, RX_DATA valid after DCLK ↑
MAX
UNIT
3
ns
2
ns
0.4/fc{
0.4/fc{
Setup time, RX_DATA valid before DCLK ↑
Delay time, rising edge of RX_FLAG before DCLK ↑
tsu(TX)
th(TX)
† After clock recovered
TYP
Setup time, TX_DATA valid before DCLK ↑
100
ns
Hold time, TX_DATA valid after DCLK ↑
100
ns
Receive Deglitch Mode
RX_DATA
Output
td(DG)
DCLK
Output
TDGK =
f
1
DG
Receive Clock Recovery Mode or Self Train Mode
tsu(r)
RX_DATA
Output
th(r)
DCLK
Output
TCRK
RX_FLAG
Output
(Valid Only in
Self Train Mode)
td(FK)
0.87
1.13
≤ TCRK ≤
fc
fc
tRXF = TCRK
NOTE: RX_DATA is latched at the falling edge of DCLK.
Transmit
tsu(TX)
th(TX)
TX_DATA
Input
DCLK
Output
1
TSK =
fc
NOTE: TX_DATA is latched at the rising edge of DCLK.
Figure 3. Timing Data for DCLK, TX_DATA, RX_FLAG, and RX_DATA
It can be seen from the timing diagram that in the clock recovery or self train mode, the data transitions
(high-to-low or low-to-high) on the RXDATA pin are timed to coincide with the falling edge of DCLK. Any
microcontroller using the TRF6903 can then latch RXDATA on the rising edge of DCLK. For more details, see
the data clock section.
POST OFFICE BOX 655303
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13
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
timing data for DCLK, TX_DATA, RX_FLAG, and RX_DATA (continued)
In high data rate systems (> 38K bps), designers need to be aware of the latency between the rising edge of
DCLK and the time the RXDATA logic value is sampled by the microcontroller. This latency needs to be less
than half the RXDATA pulse width to prevent bit errors.
If transmit capture mode is selected (by setting bit 13 in word E), the data transitions (high-to-low or low-to-high)
on the TXDATA pin are timed to coincide with the falling edge of DCLK. Any microcontroller using the TRF6903
can then latch TXDATA on the rising edge of DCLK. For more details, see the data clock section.
low-noise amplifier (LNA)/RF mixer
The LNA has differential inputs. The off-chip input matching network has the dual task of matching a 50-Ω
connector (or antenna, switch, filter, etc.) to the differential inputs and providing a 180-degree phase shift
between the inputs at terminals 1 and 2. The differential input impedance of the LNA is approximately 500 Ω
in parallel with 0.7 pF. The predicted noise figure of the LNA and input matching circuit is 2.5 dB. The cascaded
noise figure for the LNA/mixer is listed in the specifications.
The mixer offers good linearity (high IP3). An external matching network is required to transform the output
impedance of the mixer (1.4 kΩ) to the input impedance of the IF filter (typically 330 Ω).
↑1 U
CH1 S11
1
0.5
2
5
CAL
OFS
0
0.2
0.5
1
2
5
10
CPL
−5
FIL
1k
−0.5
−2
−1
START 300 MHz
STOP 1000 MHz
Figure 4. Typical LNA Input Impedance (S11) at Device Terminals LNA_IN1,2
IF amplifier/limiter
The IF amplifier has differential inputs to its first stage. The limiting amplifier provides 68 dB of gain. An external
impedance matching network is required between the IF filter output at terminal 47 and the IF amplifier inputs
at terminals 43 and 44.
RSSI
The received signal strength indicator (RSSI) voltage at terminal 41 is proportional to the log of the
down-converted RF signal at the IF limiting amplifier input. The RSSI circuit is temperature compensated. It is
useful for detecting interfering signals, transceiver handshaking, and RF channel selection. In some
applications, the RSSI circuitry alone can be used as a demodulator for amplitude-shift keying (ASK) or on-off
keying (OOK) modulation with an output at the RSSI_OUT terminal. In OOK mode, the received signal is also
fed from the RSSI circuitry to the input of the post-detection LPF amplifier. In this mode, received data is output
at the RX_DATA terminal according to the RXM field.
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POST OFFICE BOX 655303
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demodulator
The quadrature demodulator decodes digital frequency shift keying (FSK) modulation. An external ceramic
discriminator or an equivalent discrete circuit is required at terminal 35. The demodulator is optimized for use
with a ceramic discriminator. Thus, the use of a packaged ceramic discriminator is recommended for best
performance. Internal resistors can be programmed with D<14:12> to tune the demodulator center frequency.
The recommended default setting for the demodulator tuning bits is D<14:12> = 110. The resonant frequency
of the discrete-component discriminator can be calculated from the inductor and capacitor values used in the
circuit. A parallel resistor may be added to reduce the quality factor (Q) of the tank circuit, depending on the
application.
When OOK modulation is selected, the received signal from the RSSI circuitry is connected directly to the
post-detection LPF amplifier, therefore bypassing the quadrature demodulator.
ƒ res +
1
2p ǸLC
External Tank
35
L
R
C
Figure 5. Optional External Discrete Demodulator Tank
post-detection amplifier/low-pass filter
The post-detection amplifier operates as a low-pass transimpedance amplifier. The external low-pass filter
circuit must be optimized for the data rate. The 3-dB corner frequency of the low-pass filter should be greater
than twice the data rate. Various low-pass filter designs use two to five components and may be first- or
second-order designs. Simple 2-element filter component values and 3-dB bandwidths are contained in Table 1.
f
3dB
+
1
2p R2(C2 ) C1)
R2
C2
37
External Low-Pass Filter
36
C1
2 pF
Internal Low-Pass Amplifier
Figure 6. Post-Detection Amplifier/Low-Pass Filter
POST OFFICE BOX 655303
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SWRS022B − MARCH 2004 − REVISED AUGUST 2004
post-detection amplifier/low-pass filter (continued)
Table 1. Various Post-Detection Amplifier/Low-Pass Filter
3-dB Bandwidth and Corresponding Component Values for FSK Operation
f3dB (kHz)
10
20
30
60
R2 (kΩ)
220
220
220
220
C2 (pF)
68
33
22
10
NOTE: For OOK operation, it is recommended that R2 be set to 27 kΩ and C2 is not placed.
data slicer and bit synchronizer
The data slicer is a comparator circuit for received digital (FSK and OOK) data. The data slicer output voltage
depends on the difference between the received signal and a reference voltage (at the sample-and-hold (S&H)
capacitor) used as a decision threshold. During the learn mode, the S&H capacitor connected to terminal 34
is charged up to the average dc voltage of a training sequence of alternating ones and zeroes; this establishes
the reference voltage to be used as a decision level before a sequence of actual data is received in the hold
mode. During long data transmissions, more training sequences may be necessary to recharge the S&H
capacitor.
If the modulation scheme is dc-free (Manchester coding) or constant-dc, the TRF6903 may be operated
continuously in the learn mode and no training sequence is necessary before the transmission of a data string.
However, the S&H capacitor voltage may be incorrect during power up or after long periods of inactivity (no data
transmission); a learning sequence before each data transmission is recommended.
The comparator is a CMOS circuit that does not load the S&H capacitor. Leaving the transmission gate
(LEARN/HOLD switch) open (in hold mode) during periods of inactivity, such as during standby, may be useful
in maintaining the capacitor reference voltage. However, the reference voltage gradually discharges over time
due to leakage current.
The time constant for charging the S&H capacitor is determined by its capacitance and an internal 51-kΩ
resistor. A slow data rate requires a larger S&H capacitor (longer time constant). The value of the S&H capacitor,
Csh, can be calculated with the following equation:
S & H Cap +
5
Number of training Bits
; Farad
51k Data Rate (Hz)
Where the data rate in Hz is the fundamental frequency (in Hz) of the base band waveform.
Low-Pass Amplifier
LPF Out
39
51 kΩ
Comparator
Bit Synchronizer
and
Data Clock
33
27
23
34
Csh{
LEARN/HOLD
{External Sample-and-Hold Capacitor
Figure 7. Data Slicer and Bit Synchronizer
The received data and data clock output modes are determined by field RXM according to Table 3. When RXM,
E<15:14> is set to 00, the raw data from the data slicer is output at terminal 33, RX_DATA. No synchronization
or data recovery is performed and the receiver can be used in an asynchronous mode. When RXM, E<15:14>,
is set to 01, received data is first passed through a deglitching filter. These modes are useful for the reception
of data whose baud rate is nonstandard.
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POST OFFICE BOX 655303
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data slicer and bit synchronizer (continued)
When RXM is set to enable recovered data, RXM E<15:14> = 10 or 11, the integrated bit synchronizer
determines the preprogrammed data rate as determined by the crystal frequency and the values of D1, D2, and
D3, and performs data recovery. Glitch-free, recovered data is then output at terminal 33, RX_DATA, and the
corresponding data clock is output at terminal 27, DCLK.
The preprogrammed bit rate can be calculated based on the following equation:
Bit rate (kbps) +
crystal frequency (kHz)
+
D1 D2 D3
D1
Fx
D2
D3
+ f c (kHz)
where
D1 = 1, 5, 6, or 8
D2 = 1, 2, 4, 8, 16, 32, 64, or 128
D3 = 15 or 16
data clock
When enabled, RXM = 10 or 11, the data clock circuitry provides as an output at terminal 27, DCLK, a data clock
based on a programmable bit rate. The bit rate is programmable via variables D1, D2, and D3 and is always
relative to the master clock (XTAL) frequency, Fx. Table 2 shows common bit rates (kbps) vs selected crystal
frequencies (MHz) and the respective settings of D1, D2, and D3.
Table 2. Common Bit Rates, Corresponding Crystal Frequencies, and Values of D1, D2, and D3
D1, D2, AND D3 MULTIPLIERS FOR COMMON CRYSTAL VALUES (CRYSTAL FREQUENCIES IN MHZ)
BIT RATE
(kbps)
9.8304
0.6
8x128x16
12.288
14.7456
0.9
16.384
19.6608
8x128x16
1
6x128x16
1.024
5x128x15
1.2
8x64x16
8x128x16
8x128x15
5x128x16
1.8
6x128x16
8x128x16
8x64x16
2
6x64x16
2.048
5x64x15
2.4
8x32x16
8x64x16
8x64x15
5x64x16
3.6
5x128x15
6x64x16
8x64x16
8x32x16
4
6x32x16
4.096
5x32x15
4.8
8x16x16
8x32x16
8x32x15
5x32x16
7.2
5x64x15
6x32x16
8x32x16
8x16x16
8
6x16x16
8.192
5x16x15
9.6
8x8x16
8x16x16
8x16x15
5x16x16
14.4
5x32x15
6x16x16
8x16x16
8x8x16
16
6x8x16
16.384
5x8x15
19.2
8x4x16
8x8x16
8x8x15
5x8x16
28.8
5x16x15
6x8x16
8x8x16
8x4x16
32
6x4x16
32.768
5x4x15
38.4
8x2x16
8x4x16
8x4x15
5x4x16
57.6
5x8x15
6x4 x16
8x4x16
8x2x16
64
65.536
15.72864
6x2x16
8x2x16
5x2x15
8x2x15
POST OFFICE BOX 655303
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5x4x15
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SWRS022B − MARCH 2004 − REVISED AUGUST 2004
data clock (continued)
Table 2. Common Bit Rates, Corresponding Crystal Frequencies, and Values of
D1, D2, and D3 (continued)
D1, D2, AND D3 MULTIPLIERS FOR COMMON CRYSTAL VALUES (CRYSTAL FREQUENCIES IN MHZ)
BIT RATE
(kbps)
9.8304
12.288
14.7456
76.8
8x1x16
5x2x16
6x2x16
115.2
15.72864
16.384
19.6608
8x2x16
8x1x16
128
6x1x16
8x1x16
There are several receive modes, from raw slicer output to clock recovery and training sequence recognition.
The receive logic is controlled by the RXM, TWO, and TCOUNT fields. The RXM, E<15:14>, field determines
the receive mode as indicated in Table 3. These modes are described in more detail below.
Table 3. Clock Recovery and Receive Data Modes Selected by RXM
RXM
RECEIVE MODE
RX_DATA
00
Raw data
Data direct from data
slicer
Inactive; held low
DCLK
Inactive; held low
RX_FLAG
01
Deglitch
Deglitched data
Active; clock
synchronous to
deglitched data
Inactive; held low
10
Clock recovery
Deglitched data;
synchronous to
bit-rate clock at
DCLK
Active; synchronous
bit-rate clock
Inactive; held low
11
Self train
Deglitched data;
synchronous to
bit-rate clock at
DCLK
Active; synchronous
bit-rate clock
Active; set high at
first received bit that
is not part of a
predetermined
training sequence
In Raw Data mode, the data slicer output is fed directly to the RX_DATA terminal, and the DCLK and RX_FLAG
terminals are held low.
In Deglitch mode, the data slicer output is passed through the internal deglitch filter. This filter samples the slicer
output at a rate fDG, where
f
DG
+
Fx
D1
D2
The filter output is high if five or more of the last seven samples were high, and low if two or less of the last seven
samples were high. Otherwise, the filter holds its previous value. The deglitched data is applied to the RX_DATA
terminal, and the over-sampled deglitch filter clock is passed on to the DCLK terminal. Data will appear on the
RX_DATA terminal a few gate delays after the rising edge of DCLK. The RX_FLAG terminal is held low.
In Clock Recovery mode, the edges of the deglitched data are used to synchronize a bit-rate clock to the data.
As long as the consecutive number of ones or zeros in the data stream, NCB, meets the condition:
N
CB
t 250000
D
B
were ∆B is the error between the transmit bit rate and the receiver bit-rate clock in ppm.
The output data is synchronous with the bit-rate clock. The deglitched data is routed to the RX_DATA terminal
and the synchronized bit-rate clock appears at DCLK. The RX_FLAG terminal is held low. The data transition
is timed to coincide with the falling edge of DCLK, so that the external microcontroller using the TRF6903 can
latch RX_DATA on the rising edge of DCLK with plenty of setup and hold margin. If no data edges have been
observed since the last reset, then DCLK is held low until an edge is seen.
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data clock (continued)
In Self Train mode, the TRF6903 receiver not only performs clock recovery, but also looks for the end of a training
sequence. The TWO, E<12>, field determines the pattern of the training sequence. If TWO is low, the training
sequence is assumed to be alternating ones and zeros; if TWO is high, the training sequence is assumed to
be alternating pairs of ones and zeros. RX_DATA and DCLK output are the same as in Clock Recovery mode.
However, if a minimum number of training bits have been observed, then the RX_FLAG terminal is asserted
high for one clock period (after which it returns low) at the first bit that is not part of the training sequence. The
timing of RX_FLAG is a few gate delays after the rising edge of DCLK. The minimum number of training bits
is four times the unsigned binary value of TCOUNT, E<11:7>, plus two if TWO = 0 or plus three if TWO = 1,
according to the equation:
TBmin = (4 x TCOUNT) + TWO + 2
The clock recovery and training sequence recognition circuits are all designed to reset/clear internally with no
user action required. However, they can manually be reset/cleared by use of the NRX bit, C<5>.
When active, DCLK is synchronized to the received data. The rising edge of the data clock is intended to be
located at the middle of the received recovered data bit, thus enhancing the synchronization ability of the
microcontroller and reducing the need for extensive signal processing in the microcontroller.
main divider
The main divider is composed of a 5-bit A-counter and a 9-bit B-counter and a prescaler. The A-counter controls
the divider ratio of the prescaler, which divides the VCO signal by either 33 or 32. The prescaler divides by 33
until the A-counter reaches its terminal count and then divides by 32 until the B-counter reaches terminal count,
whereupon both counters reset and the cycle repeats. The total divide-by-N operation is related to the 32/33
prescaler by:
NTOTAL = 33 x A + 32 x (B – A)
where 0 ≤ A ≤ 31 and 31 ≤ B ≤ 511 or, NTOTAL = A + 32B
Thus, the N-divider has a range of 992 ≤ NTOTAL ≤ 16383
PLL
The phase-locked loop is the radio frequency synthesizer for the TRF6903. It is used to generate the transmit
signal and as the local oscillator for the receive mixer. The signal (FX) from a reference crystal oscillator (XO)
is divided by an integer factor R down to FR. The minimum frequency resolution, and thus, the minimum channel
spacing, is FR.
FR = FX ÷ R where 1 ≤ R ≤ 256
The phase-locked loop is an integer-N design. The voltage-controlled oscillator (VCO) signal is divided by an
integer factor N to get a frequency at the phase detector input.
FPD = FVCO ÷ N
The phase detector compares the divided VCO signal to the divided crystal frequency and implements an error
signal from two charge pumps. The error signal corrects the VCO output to the desired frequency.
As is in any integer-N PLLs, the VCO output has spurs at integer multiples of the reference frequency (nFR).
In applications requiring contiguous frequency channels, the reference frequency is often chosen to be equal
to the channel spacing, thus, channel spacing = FR = FX ÷ R. When the PLL is locked, the LOCK_DETECT
terminal is high.
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SWRS022B − MARCH 2004 − REVISED AUGUST 2004
PLL (continued)
With the addition of an output divider for multiband operation, the actual output frequency, Fout, is given by:
F
F
N + A ) 32B F
F out + VCO + X N + F
R P
R
P
P
P
R
where FR = FPD under locked conditions. The actual minimum channel spacing is:
F BR
R+ X
P
P
where P = 1, 2, 3 and is set by A<1:0>.
F
oscillator circuit and reference divider
The reference divider reduces the frequency of the external crystal (FX) by an 8-bit programmable integer
divisor, R, to an internal reference frequency (FR) used for the phase-locked loop. See Figure 8. The choice of
internal reference frequency also has implications for lock time, maximum data rate, noise floor, and loop-filter
design. The crystal frequency can be tuned using the F word to control internal trimming capacitors, which are
placed in parallel with the crystal. These offset a small frequency error in the crystal. In an FSK application, an
additional capacitor is placed in parallel (through terminal 31) with the external capacitor that is connected in
series with the crystal, thus, changing the load capacitance as the transmit data switch (TX_DATA, terminal 32)
is toggled. The change in load capacitance pulls the crystal off-frequency by the total frequency deviation.
Hence, the 2-FSK frequency, set by the level of TX_DATA and the external capacitor, can be represented as
follows:
ƒ out1 + TX_DATA Low (XTAL switch closed) ƒ out2 + TX_DATA High (XTAL switch open)
Note that the frequencies ƒout1 and ƒout2 are centered about the frequency ƒcenter = (ƒout1 + ƒout2)/2. When
transmitting FSK, ƒcenter is considered to be the effective carrier frequency and any receiver local oscillator (LO)
should be set to the same ƒcenter frequency ± the receiver’s IF frequency (ƒIF) for proper reception and
demodulation.
For the case of high-side injection, the receiver LO would be set to ƒLO = ƒcenter + ƒIF. Using high-side injection,
the received data at terminal 33, RX_DATA, would be inverted from the transmitted data applied at terminal 32,
TX_DATA. Conversely, for low-side injection, the receiver LO would be set to ƒLO = ƒcenter − ƒIF. Using low-side
injection, the received data would be the same as the transmitted data. The data polarity invert bit PI, A<4>,
can be used to invert the data at terminal 33, RX_DATA, when high-side injection is being used.
In addition, when the TRF6903 is placed in receive mode, it is recommended that the D<19> bit be kept high
to keep the XTAL switch closed. In this manner, the actual LO frequency injected into the mixer is ƒout1 = ƒLO.
If D<19> is set low, the the receiver LO would be offset, resulting in poor receiver sensitivity.
31
30
Fx
VCC
Crystal
Oscillator
Circuit
÷R
Reference
Divider
2...255
FR
FPD
External Crystal
PhaseFrequency
Detector
15
External
Loop
Filter
VCO
Charge Pumps
÷N
Main Divider
A, B Counters
32/33
992 ≤ N ≤ 16383
External
Cap for
FSK
Fvco
Output
Divider
P = 1, 2, 3
Fout
Figure 8. TRF6903 PLL and Output Divider
20
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phase detector and charge pumps
The phase detector is a phase-frequency design. The phase-frequency detector gain is given by:
KP = I(CP)/2π
where, I(CP) is the peak charge pump current. The peak charge pump current is programmable with A<3:2> in
three steps: 250 µA, 500 µA, and 1000 µA.
loop filter
The loop filter must be carefully chosen for proper operation of the TRF6903. The loop filter as shown in Figure 9
is typically a second- or third-order passive design and in FSK operation should have a bandwidth wide enough
to allow the PLL to relock quickly as the external crystal frequency is pulled off-center during modulation. The
loop filter should also be wider than the data modulation rate. These requirements should be balanced with
making the loop narrow enough in consideration of the reference frequency. In OOK the VCO frequency is not
changed during data modulation, so the filter bandwidth may be narrower than the modulation bandwidth. Filters
can be calculated using standard formulas in reference literature. Some third-order filter examples are shown
in Table 4.
1
C3R3
s) 1
C3R3
1 ) sC2R2
F(s) +
s(C1 ) C2 ) sC1C2R2)
R3
lcp
CP_OUT
Vtune
13
C3
15
C1
C2
VCO_TUNE
R2
VCO_VCC
External-Loop Filter
Figure 9. Third-Order Loop Filter and Transfer Function
Table 4. Loop Filter Component Values For Various Data Rates at a Reference Frequency of 409.6 kHz,
0.5-mA Charge Pump Current
Bit rate − kbps
Data rate − kHz
Manchester coding
1.024
2.048
4.096
8.192
16.384
19.2
32.768
65.536
NRZ coding
2.048
4.096
8.192
16.384
32.768
38.4
65.536
131.072
Fundamental freq of BB
Loop filter component
(selected to nearest
standard value)
1.024
2.048
4.096
8.192
16.384
19.2
32.768
65.536
C1, nF
47
12
2.7
0.68
0.18
0.12
0.043
0.01
C2, nF
1800
430
100
27
6.8
5.1
1.8
0.47
C3, nF
27
6.8
1.5
0.39
0.1
0.075
0.027
0.0068
R2, kΩ
0.39
0.75
1.5
3
5.7
6.8
12
24
R3, kΩ
0.75
1.5
3
5.7
12
15
22
47
−3−dB bandwidth, kHz (approximate)
1.28
2.56
5.12
10.24
20.48
24
40.96
81.92
VCO
The voltage-controlled oscillator (VCO) produces an RF output signal with a frequency that is dependent upon
the dc-tuning voltage at terminal 13. The tank circuit is passive and has integrated varactor diodes and
inductors. The open-loop VCO gain is approximately 100 MHz/V.
A <1:0> is used to set the output divider ratio for operation within the 315-MHz, 433-MHz, 868-MHz, or 915-MHz
bands.
When the STDBY terminal is high, the reference, PLL, VCO, and dividers are powered up. When STDBY is low,
these blocks are powered down.
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SWRS022B − MARCH 2004 − REVISED AUGUST 2004
power amplifier
The power amplifier has three programmable attenuation states as determined by A<7:6> and B<7:6>: full
power (0-dB attenuation), 10-dB attenuation, and 20-dB attenuation. This adjustment feature allows the user
to fine-tune the device for optimal output power. The power amplifier can be enabled/disabled during transmit
by bit B<3>, PARXED. During receive, the transmit power amplifier is powered down but the VCO and PLL are
still operating. During ASK or OOK operation, the TX_DATA signal turns the power amplifier on and off according
to the transmit data incident at terminal 32.
↑1 U
CH1 S22
1
0.5
2
5
CAL
OFS
0
0.2
0.5
1
2
5
10
CPL
−5
FIL
1k
−0.5
−2
−1
START 300 MHz
STOP 1000 MHz
Figure 10. Typical PA Output Impedance (S22) at Device Terminal PA_OUT
brownout detector
The brownout detector provides an output voltage to indicate a low supply voltage. This may be used to signal
the need to change transmit power to conserve battery life, or for system power down. The brownout detector
threshold is set with the B word. Four different thresholds are available.
serial control interface
The TRF6903 is controlled through a serial interface; there are five 24-bit control words (A, B, C, D, E) which
set the device state. The A and B words are almost identical, and provide configuration settings for two modes,
designated 0 and 1, which are commonly used to configure the transmit and receive states. The transmit and
receive states can then be rapidly selected using MODE (terminal 21). The C word sets the reference dividers,
the power amplifier bias, and contains various reset bits. The E word contains the bit-rate select, data clock
control bits, and the power amplifier bias control registers. The D word is used to trim the external crystal
frequency and tune the demodulator.
The register address is the composite of bits 23, 22, 1, and 0 of the 24 bits written to the serial interface. For
some words, certain bits of the address are don’t cares and are noted as XX. This flexible addressing scheme
allows backward compatibility with the TRF6901, and because of this flexibility, the data length of each register
varies from 15 bits to 22 bits.
Normal (write) operation of the serial interface is to clock in 24 bits through the CLOCK and DATA terminals.
DATA values are clocked into the 24-bit serial interface shift register on the rising edge of CLOCK. The 24-bit
value is decoded and written into the appropriate data register on the rising edge of STROBE.
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PRINCIPLES OF OPERATION
register description
!
"#$
%#
!&
!
"#$
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)*+$
,,+
!%#-
-
% %
%
%#*
%
%
#"23"4
%#
!)
"#
",
53"4
",1("
,,+#*
! '
(
"../
'
-0/
NOTE: r = reserved. All reserved bits should be set low (0) during normal operation.
NOTE: All bits indicated as 1 should be set high (1) during normal operation.
NOTE: All bits indicated as 0 should be set low (0) during normal operation.
ADDRESS
LOCATION
NO. OF
BITS
00xx
21 : 17
5
Main A divider coefficient (Mode 0)
00000
00xx
16 : 8
9
Main B divider coefficient (Mode 0)
001110000
00xx
7:6
2
Controls the PA attenuation (Mode 0)
10
00xx
5
1
Enables transmit/receive path (Mode 0)
0
00xx
4
1
Receive data polarity invert bit
0
00xx
3:2
2
Controls charge pump peak current
00
00xx
1:0
2
Output divider coefficient; band select
01xx
21 : 17
5
Main A divider coefficient (Mode 1)
00000
01xx
16 : 8
9
Main B divider coefficient (Mode 1)
001110000
01xx
7:6
2
Controls the PA attenuation (Mode 1)
10
01xx
5
1
Enables transmit/receive path (Mode 1)
0
01xx
4
1
Controls modulation scheme (FSK or OOK)
0
01xx
3
1
Enables or disables the power amplifier while in transmit mode
or the receive chain while in receive mode
0
01xx
2:1
2
Sets threshold for the brownout detector
00
01xx
0
1
Enables brownout detector
0
1000
21 : 14
8
Reference divider coefficient
1001
21 : 20
2
Bit-rate divider D1
11
1001
19 : 17
3
Bit-rate divider D2
010
1001
16
1
Bit-rate divider D3
0
1001
15 : 14
2
Receive mode select
00
1001
13
1
Transmit capture mode select
0
1001
12
1
RX training sequence pattern select
0
1001
11 : 7
5
Determines the minimum number of training bits
11x0
19
1
Controls the position of the XTAL switch during FSK reception
0
11x0
18 : 16
3
Tunes the XTAL frequency by using an internal capacitor bank
000
11x0
15
1
PFD reset
11x0
14 : 12
3
Tunes the resonant frequency of the external demodulation
tank circuit
11x0
11
1
Controls the position of the XTAL switch during OOK operation
DESCRIPTION
DEFAULT VALUE
10
01000000
00100
1
000
0
NOTE: x = don’t care
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
PRINCIPLES OF OPERATION
At power on/startup, all of the TRF6903 register contents are as per the default values.
Address 00XX (A-Word):
Word A is a 22-bit data register comprising seven fields. The main A-divider coefficient (mode 0), A<21:17>,
is the 5-bit divider ratio of the A counter when the MODE terminal is low. The main B-divider coefficient
(mode 0), A<16:8>, is the 9-bit value of the B counter when the MODE terminal is low. A <21:17> and A
<16:8> are unsigned binary values. PA0, A<7:6>, is the 2-bit PA attenuation setting when the MODE
terminal is low. TX/RX0, A<5>, is the TX/RX switch when the MODE terminal is low. PI, A<4>, is the data
polarity invert bit. When high, this bit causes the data slicer output to be inverted. CP Acc., A<3:2>, sets the
charge pump current. BND, A<1:0>, sets the output divider, which in turn determines the band of operation.
Terminal 21 (MODE) selects bits A< 21 : 5 > if low, or B< 21 : 5 > if high.
Main divider A< 21 : 17 >: 5-bit value for divider ratio of the A counter
Main divider A< 16 : 8 >: 9-bit value for divider ratio of the B counter
PA attenuation A< 7 : 6 >: 2 bits for setting the PA attenuation
A< 7 : 6 >
PA ATTENUATION
00
0 dB
01
10 dB
10
20 dB
11
Not defined
A<5 >: 1-bit TX/RX mode select
A< 5 >
TX/RX MODE
0
RX mode
1
TX mode
A<4 >: 1-bit data polarity invert bit
A<4 >
RX DATA POLARITY
0
Noninverted
1
Inverted
A<3: 2 >: 2 bits for setting the charge pump current
24
A<3 : 2 >
CP CURRENT
00
0.5 mA
01
1 mA
10
0.25 mA
11
Not defined
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
PRINCIPLES OF OPERATION
A<1:0>: 2-bit value to set the output divider and thus select the band of operation.
A<1:0 >
OUTPUT DIVIDER
RATIO, P
BAND OF
OPERATION
00
3
315 MHz
01
2
433 MHz
10
1
868 MHz or 915 MHz
11
1
868 MHz or 915 MHz
Address 01XX (B-Word):
Word B is a 22-bit data register comprising eight fields. The main A-divider coefficient (mode 1), B<21:17>,
is the 5-bit divider ratio of the A counter when the MODE terminal is high. The main B-divider coefficient
(mode 1), B<16:8>, is the 9-bit value of the B counter when the MODE terminal is high. B<21:17> and
B<16:8> are unsigned binary values. PA1, B<7:6>, is the 2-bit PA attenuation setting when the MODE
terminal is high. TX/RX1, B<5>, is the TX/RX switch when the MODE terminal is high. FSK/OOK, B<4>, sets
the modulation scheme for both TX and RX. Bit B<3> enables/disables the power amplifier while in transmit
mode and enables/disables the receive chain while in receive mode. The detector threshold, B<2:1>, is the
2-bit setting for the threshold voltage of the brownout detector. Det. Enable, B<0>, is the brownout detector
enable flag.
Terminal 21 (MODE) selects bits A< 21 : 5 > if low, or B< 21 : 5 > if high.
Main divider B< 21 : 17 >: 5-bit value for divider ratio of the A-counter
Main divider B< 16 : 8 >: 9-bit value for divider ratio of the B-counter
PA attenuation B< 7 : 6 >: 2 bits for setting the PA attenuation
B< 7 : 6 >
PA ATTENUATION
00
0 dB
01
10 dB
10
20 dB
11
Not defined
B<5 >: 1-bit TX/RX mode select
B< 5 >
TX/RX MODE
0
RX mode
1
TX mode
B<4 > 1-bit modulation select
B< 4 >
TX/RX MODULATION
0
OOK
1
FSK
NOTE: During OOK reception, the OOK switch is closed. During FSK reception, the OOK switch is open.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
PRINCIPLES OF OPERATION
B<3 >: 1-bit PA or receive chain enable/disable
B< 3 >
PA OR RECEIVE CHAIN
ENABLE/DISABLE
0
Disabled
1
Enabled
B<2 : 1 >: 2-bit value to set the threshold voltage for the brownout detector
B< 2 : 1 >
THRESHOLD VOLTAGE
00
2.2 V
01
2.4 V
10
2.6 V
11
2.8 V
B<0 >: 1 bit to enable brownout detector
B< 0 >
BROWNOUT DETECTOR
0
Off
1
On
Address 1000 (C-Word):
Word C is a 20-bit data register comprising four fields. The reference divider coefficient, C<21:14>, is the
8-bit divider ratio of the reference divider. The allowable reference divider range is 2 (C <21:14> =
00000010) through 255 (C <21:14> = 11111111).
Bits C<6> through C<2> are reserved and should be set to 0.
Address 1001 (E-Word):
Word E is a 20-bit data register comprising eight fields. The bit rate or bit frequency, used by the clock
recovery receive modes and the transmit synchronous mode is controlled by the BRA, E<21:20>, BRB,
E<19:17>, and BRC, E<16>, fields. These three fields control a sequence of dividers, D1 through D3, that
divide the reference (crystal) frequency, FX.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
PRINCIPLES OF OPERATION
E<21:20>: 2 bits to set D1 divider setting
E<21:20>
D1
00
1
01
5
10
6
11
8
E<19:17>: 3 bits to set D2 divider setting
E<19:17>
D2
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
E<16>: 1 bit to set D3 divider setting
E<16>
D3
0
16
1
15
RXM, E<15:14> controls the signals that appear at the RX_DATA and DCLK terminals. The definition of
RXM is contained in Table 3.
TXM, E<13>, sets the transmit capture mode. If TXM is low, the TX_DATA terminal controls the transmit
function asynchronously. If TXM is high, the bit-rate clock is output at DCLK and the transmit data at the
TX_DATA terminal is latched on the rising edge of DCLK, where DCLK is the bit-rate clock.
TWO, E<12>, sets the receive training sequence pattern. If TWO is high, the expected training sequence is
assumed to be alternating pairs of ones and zeroes. If TWO is low, the expected training sequence is
assumed to be alternating ones and zeroes.
TCOUNT, E>11:7>, determines the minimum number of training bits. The minimum number of training bits is
four times the unsigned binary value of TCOUNT, plus two if TWO = 0 or plus three if TWO = 1.
Bits E<6> through E<2> are reserved and should be set to 0.
Address 11X0 (D-Word):
Word D is a 21-bit data register comprising three fields. XTAL_Tune, D<18:16>, is used to fine tune the
crystal frequency by using an internal capacitor bank. PFD reset, D<15>, selects the source of the PFD
reset signal. Dem_Tune, D<14:12>, is a 3-bit value used to tune the demodulator time constant. Bit D<11>
controls the position of the XTAL switch during OOK operation.
D<19 >: 1-bit value to control the position of the XTAL switch during FSK reception, when B<4>=1 and
either A<5> or B<5> = 0. It is recommended to set this bit to 1 (XTAL switch closed). If D<19> is set to 0
(XTAL switch open), the LO frequency injected into the mixer is fouts = fLO + designed peak-peak
deviation. This results in the down-converted IF signal shifting higher (high-side injection) or lower
(low-side injection) from the IF center frequency (10.7 MHz) by an amount equal to the designed
peak-peak frequency deviation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
PRINCIPLES OF OPERATION
D<19 >
XTAL SWITCH DURING FSK
RECEPTION
TERMINAL 31
0
Unconnected (open)
High-Z
1
Connected (closed)
Shorted to ground internally
D<18 : 16 >: 3-bit value to fine-tune the XTAL frequency by using an internal capacitor bank.
D< 18:16 >
TYPICAL LOAD CAPACITANCE
000
13.23 pF
001
22.57 pF
010
17.9 pF
011
27.24 pF
100
15.56 pF
101
24.9 pF
110
20.23 pF
111
29.57 pF
D<15 >: 1-bit value to select the reset signal for the PFD
D<15 >
RESET SIGNAL
0
Derived from XTAL
1
Derived from prescaler
NOTE: The default setting for D<15> is 1.
D<14 : 12 >: 3-bit value to tune the resonant frequency of the external demodulator tank circuit. It can be
used to optimize the receiver performance. The recommended default setting is 110.
D<11>: 1-bit value to control position of the XTAL switch during OOK operation, when B<4> = 0.
D<11 >
XTAL SWITCH DURING OOK
OPERATION
TERMINAL 31
0
Unconnected (open)
High-Z
1
Connected (closed)
Shorted to ground internally
It is recommended that D<19> and D<11> be set to 0 during FSK reception and OOK operation.
Bits D<21>, D<20>, and D<10> through D<1> are reserved and should be set to 0.
operating modes
Controlled with terminal 26, STDBY
STDBY
OPERATING MODE
0
Power down of all blocks—programming mode
1
Operational mode and programming mode
Controlled with terminal 21, MODE
MODE
28
OPERATING MODE
0
Enable A-word
1
Enable B-word
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
PRINCIPLES OF OPERATION
Controlled with terminal 39, LEARN/HOLD
LEARN/HOLD
OPERATING MODE
0
Selects data slicer decision level to HOLD
1
Selects data slicer decision level to LEARN
The transmit/receive mode is controlled by the TX/RX0, A<5>, TX/RX1, B<5>, and PARXED, B<3>, fields
and the MODE and STDBY terminals.
A<5>
B<5>
B<3>
MODE
STDBY
OPERATING MODE
X
X
X
X
0
Off, programming mode; SPI enabled
0
X
0
0
1
Receive mode 0, RX chain disabled. Reference, PLL, VCO and
dividers enabled
0
X
1
0
1
Receive mode 0, RX chain enabled. Reference, PLL, VCO and
dividers enabled
1
X
0
0
1
Transmit mode 0, PA disabled. Reference, PLL, VCO and dividers
enabled
1
X
1
0
1
Transmit mode 0, PA enabled. Reference, PLL, VCO and dividers
enabled
X
0
0
1
1
Receive mode 1, RX chain disabled. Reference, PLL, VCO and
dividers enabled
X
0
1
1
1
Receive mode 1, RX chain enabled. Reference, PLL, VCO and
dividers enabled
X
1
0
1
1
Transmit mode 1, PA disabled. Reference, PLL, VCO and dividers
enabled
X
1
1
1
1
Transmit mode 1, PA enabled. Reference, PLL, VCO and dividers
enabled
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
APPLICATION INFORMATION
BPF1
MuRata
SFECS10M7EA00−R0
BW = 330 kHz
3
1
C3
2
100 pF
C4
120 pF
L1
4.7 µ H
J1
L2
C6
C7
DEM_VCC
MIX_VCC
DET_OUT
C5
82 pF
4.7 µ H
LRN/HOLD
82 pF
RSSI
C1
R3
220 k Ω
22 pF
C21
C8
1
2
LNA_VCC
J2
C9
L5
4
9
10
37
RX_DATA 33
RX_DATA
U1
TRF6903
C19
XTAL 30
Reference
Generator
1, 2, 3
Divider
29
VCO_TANK2
14
15
16
26
DVDD
17
18
19
R2
20
21
22
23
MIX_VCC
LNA_VCC
24
RX_FLAG
LOCK_DETECT
MODE
DATA
STROBE
CLOCK
DVDD
C13
DCLK
STDBY
VCC
R1
XTAL_VCC
25
CP_VCC
CP_OUT
VCO_TUNE
12
13
C18
22 pF
Crystek
017119
27
Bit Synchronizer
and
Data Clock
PLL
C12
24 pF
XTAL1
28
VCO_VCC
VCO_VCC
TX_DATA
XTAL_SW 31
11 VCO_BYPASSVCO
C14
2200 pF
TX_DATA 32
8
C11
100 pF
LPF_IN
LEARN/
HOLD 38
39
PA_OUT
PA_VCC
VCO_VCC
40
SLC_CAP 34 C20
Data
Slicer
7
PA_VCC1
CDSCB10M7GA119−R0
CER_DIS 35
6
C10
42
RSSI_
OUT 41
IF_IN2 43
IF_IN1 44
45
LNA
5
PA_VCC2
DIS 1
10.7 MHz
MuRata
LPF_OUT 36
PA
L4
RSSI
3
TX_OUT
C25
DET_OUT
J4
46
L3
MIX_OUT 47
48
RX_IN+
CP_VCC
R4 10 Ω
PA_VCC2
DEM_VCC
C17
0.1 µ F
VCO_VCC
C16
0.1 µ F
XTAL_VCC
C15
0.1 µ F
CP_VCC
R5 10 Ω
PA_VCC1
C2
NOTE: See Table 5 for component selection for band of operation.
Figure 11. Typical TRF6903 FSK Application Schematic
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.1 µ F
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
APPLICATION INFORMATION
Table 5. Component Selection for Band of Operation, FSK
315 MHz
Rx
LNA Matching
Network
Tx
PA Matching
Network
PLL
Loop Filter
433 MHz
868 MHz
915 MHz
Component
Value
Component
Value
Component
Value
Component
Value
C6
15 pF
C6
8.2 pF
C6
2.7 pF
C6
2.2 pF
C7
330 pF
C7
180 pF
C7
39 pF
C7
33 pF
C8
15 pF
C8
8.2 pF
C8
2.7 pF
C8
2.2 pF
L3
27 nH
L3
22 nH
L3
10 nH
L3
9.1 nH
C9
10 pF
C9
4.7 pF
C9
3.9 pF
C9
3.3 pF
C10
390 pF
C10
270 pF
C10
39 pF
C10
33 pF
L4
47 nH
L4
33 nH
L4
12 nH
L4
10 nH
L5
18 nH
L5
6.8 nH
L5
0Ω
L5
0Ω
C25
7.5 pF
C25
4.7 pF
C25
DNP
C25
DNP
C12
75 pF
C12
75 pF
C12
75 pF
C12
75 pF
C13
120 pF
C13
120 pF
C13
120 pF
C13
120 pF
C14
4700 pF
C14
5600 pF
C14
5600 pF
C14
5600 pF
R1
15 kΩ
R1
15 kΩ
R1
15 kΩ
R1
15 kΩ
R2
7.5 kΩ
R2
6.8 kΩ
R2
6.8 kΩ
R2
7.5 kΩ
NOTE: DNP = Do not place
NOTE: Loop filter components selected for 19.2 kbps Manchester or 38.4 kbps NRZ for each band. ICP = 0.5 mA,
Reference Frequency = 409.6 kHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
APPLICATION INFORMATION
BPF1
MuRata
SFECS10M7EA00−R0
BW = 330 kHz
3
1
C3
2
100 pF
C4
120 pF
L1
4.7 µ H
J1
L2
C6
C7
DEM_VCC
MIX_VCC
DET_OUT
C5
82 pF
4.7 µ H
LRN/HOLD
82 pF
RSSI
C1
R3
27 kΩ
C21
C8
1
2
LNA_VCC
J2
C9
L5
RSSI
37
LPF_OUT 36
LNA
CER_DIS 35
SLC_CAP 34 C20
3
4
TX_OUT
Data
Slicer
PA_OUT
5
C25
PA
6
PA_VCC
U1
TRF6903
VCO_VCC
9
10
XTAL1
28
VCO_TANK2
13
14
15
16
26
C14
DCLK
STDBY
DVDD
17
18
19
20
21
22
23
MIX_VCC
LNA_VCC
24
R2
RX_FLAG
LOCK_DETECT
MODE
DATA
STROBE
CLOCK
DVDD
VCC
R1
C13
27 pF
XTAL_VCC
25
CP_VCC
CP_OUT
VCO_TUNE
12
C12
C18
Crystek
017119
27
Bit Synchronizer
and
Data Clock
PLL
VCO_VCC
TX_DATA
29
VCO_VCC
11 VCO_BYPASSVCO
C11
100 pF
RX_DATA
XTAL 30
Reference
Generator
1, 2, 3
Divider
8
PA_VCC1
RX_DATA 33
XTAL_SW 31
7
C10
2200 pF
TX_DATA 32
L4
PA_VCC2
DNP
LPF_IN
LEARN/
HOLD 38
39
40
42
RSSI_
OUT 41
IF_IN2 43
IF_IN1 44
45
DET_OUT
J4
46
L3
MIX_OUT 47
48
RX_IN+
CP_VCC
R4 10 Ω
PA_VCC2
DEM_VCC
C17
0.1 µ F
VCO_VCC
C16
0.1 µ F
XTAL_VCC
C15
0.1 µ F
CP_VCC
R5 10 Ω
PA_VCC1
C2
NOTE: See Table 6 for component selection for band of operation.
Figure 12. Typical TRF6903 OOK Application Schematic With Ceramic IF Filter
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.1 µ F
SWRS022B − MARCH 2004 − REVISED AUGUST 2004
APPLICATION INFORMATION
Table 6. Component Selection for Band of Operation, OOK
315 MHz
Rx
LNA Matching
Network
Tx
PA Matching
Network
PLL
Loop Filter
433 MHz
868 MHz
915 MHz
Component
Value
Component
Value
Component
Value
Component
Value
C6
15 pF
C6
8.2 pF
C6
2.7 pF
C6
2.2 pF
C7
330 pF
C7
180 pF
C7
39 pF
C7
33 pF
C8
15 pF
C8
8.2 pF
C8
2.7 pF
C8
2.2 pF
L3
27 nH
L3
22 nH
L3
10 nH
L3
9.1 nH
C9
10 pF
C9
4.7 pF
C9
3.9 pF
C9
3.3 pF
C10
390 pF
C10
270 pF
C10
39 pF
C10
33 pF
L4
47 nH
L4
33 nH
L4
12 nH
L4
10 nH
L5
18 nH
L5
6.8 nH
L5
0Ω
L5
0Ω
C25
7.5 pF
C25
4.7 pF
C25
DNP
C25
DNP
C12
75 pF
C12
75 pF
C12
75 pF
C12
75 pF
C13
120 pF
C13
120 pF
C13
120 pF
C13
120 pF
C14
4700 pF
C14
5600 pF
C14
5600 pF
C14
5600 pF
R1
15 kΩ
R1
15 kΩ
R1
15 kΩ
R1
15 kΩ
R2
7.5 kΩ
R2
6.8 kΩ
R2
6.8 kΩ
R2
7.5 kΩ
NOTE: DNP = Do not place
NOTE: Loop filter components selected for 19.2 kbps Manchester or 38.4 kbps NRZ for each band. ICP = 0.5 mA,
Reference Frequency = 409.6 kHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TRF6903PT
ACTIVE
LQFP
PT
48
250
None
CU NIPDAU
Level-3-235C-168 HR
TRF6903PTR
ACTIVE
LQFP
PT
48
1000
None
CU NIPDAU
Level-3-235C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
1,45
1,35
Seating Plane
1,60 MAX
0°– 7°
0,75
0,45
0,10
4040052 / C 11/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MS-026
This may also be a thermally enhanced plastic package with leads conected to the die pads.
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