STMICROELECTRONICS TS924

TS924
Rail-to-rail High Output Current Quad Operational Amplifier
■
Rail-to-rail input and output
■
Low noise: 9nV/√Hz
■
Low distortion
■
High output current: 80mA
(able to drive 32Ω loads)
■
High-speed: 4MHz, 1.3V/µs
■
Operating from 2.7V to 12V
■
Low input offset voltage: 900µV max (TS924A)
■
ESD Internal protection: 3kV
■
Latch-up immunity
■
Macromodel included in this specification
N
DIP14
(Plastic Package)
D
SO-14
(Plastic Micropackage)
Description
The TS924 is a rail-to-rail quad BiCMOS
operational amplifier optimized and fully specified
for 3V and 5V operation.
P
TSSOP14
(Thin Shrink Small Outline Package)
High output current allows low load impedances to
be driven.
Pin connection (top view)
The TS924 exhibits a very low noise, low
distortion, low offset and high output current
capability making this device an excellent choice
for high quality, low voltage or battery operated
audio systems.
14 Output 4
Output 1 1
The device is stable for capacitive loads up to
500pF.
Inverting Input 1 2
-
-
13 Inverting Input 4
Non-inverting Input 1 3
+
+
12 Non-inverting Input 4
VCC + 4
11 VCC -
Non-inverting Input 2 5
+
+
10 Non-inverting Input 3
Inverting Input 2 6
-
-
9
Inverting Input 3
8
Output 3
Output 2 7
Applications
■
Headphone amplifier
■
Line driver, buffer
■
Piezoelectric speaker driver
■
■
Sound cards
Cordless telephones and portable
communication equipment
■
MPEG boards, multimedia systems,...
■
Instrumentation with low noise as key factor
November 2005
Rev 4
1/14
www.st.com
14
TS924
Order Codes
Part Number
Temperature
Range
Package
Packaging
DIP14
Tube
TS924IN
TS924IN
TS924AIN
TS924AIN
TS924ID/IDT
924I
SO-14
Tube or Tape & Reel
TS924AID/AIDT
924AI
TS924IPT
-40°C, +125°C
TS924AIPT
924I
TSSOP14
(Thin Shrink Outline Package)
Tape & Reel
SO-14 (automotive grade level)
Tube or Tape & Reel
924AI
TS924IYD/IYDT
924IY
TS924AIYD/AIYDT
924AIY
TS924IYPT
924IY
TSSOP14 (automotive grade level)
TS924IAIYPT
2/14
Marking
Tape & Reel
924AIY
TS924
1
Absolute Maximum Ratings
Absolute Maximum Ratings
Table 1.
Key parameters and their absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
Supply voltage (1)
14
V
Vid
Differential Input Voltage (2)
±1
V
VDD -0.3 to V CC+0.3
V
-65 to +150
°C
Maximum Junction Temperature
150
°C
Thermal Resistance Junction to Ambient
DIP14
103
SO14
66
TSSOP14
100
Vi
Tstg
Tj
Rthja
Input Voltage (3)
Storage Temperature
HBM: Human Body Model(4)
ESD
°C/W
3
kV
100
V
CDM: Charged Device Model
1
kV
Output Short Circuit Duration
see note(6)
MM: Machine Model(5)
Latch-up Immunity
200
mA
Soldering Temperature (10sec), leaded version
250
°C
Soldering Temperature (10sec), unleaded version
260
°C
1. All voltages values, except differential voltage are with respect to network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. If Vid > ±1V,
the maximum input current must not exceed ±1mA. In this case (Vid > ±1V) an input serie resistor must be
added to limit input current.
3. Do not exceed 14V.
4. Human body model, 100pF discharged through a 1.5kΩ resistor into pin of device.
5. Machine model ESD, a 200pF cap is charged to the specified voltage, then discharged directly into the IC with
no external series resistor (internal resistor < 5Ω), into pin to pin of device.
6. There is no short-circuit protection inside the device: short-circuits from the output to Vcc can cause excessive
heating. The maximum output current is approximately 80mA, independent of the magnitude of Vcc.
Destructive dissipation can result from simultaneous short-circuits on all amplifiers.
Table 2.
Operating conditions
Symbol
Parameter
VCC
Supply voltage
Vicm
Common Mode Input Voltage Range
Toper
Operating Free Air Temperature Range
Value
Unit
2.7 to 12
V
VDD -0.2 to VCC +0.2
V
-40 to +125
°C
3/14
Electrical Characteristics
2
Electrical Characteristics
Table 3.
VCC = +3V, VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless
otherwise specified)
Symbol
Vio
DVio
Parameter
Min.
Typ.
Input Offset Voltage - TS924
TS924A
Tmin. ≤ Tamb ≤ Tmax. - TS924
TS924A
Max.
Unit
3
0.9
5
1.8
mV
µV/°C
Input Offset Voltage Drift
2
Iio
Input Offset Current
Vout = Vcc/2
1
30
Iib
Input Bias Current
Vout = Vcc/2
15
100
VOH
High Level Output Voltage
RL= 100k
RL = 600Ω
RL = 32Ω
2.90
2.87
nA
nA
V
2.63
Low Level Output Voltage
RL= 10k
RL = 600Ω
RL = 32Ω
180
Avd
Large Signal Voltage Gain (Vout = 2Vpk-pk)
RL= 10k
RL = 600Ω
RL = 32Ω
200
35
16
Icc
Total Supply Current
no load, V out = Vcc/2
4.5
VOL
50
100
mV
V/mV
7
mA
GBP
Gain Bandwidth Product
RL = 600Ω
CMR
Common Mode Rejection Ratio
60
80
dB
SVR
Supply Voltage Rejection Ratio - V cc = 2.7 to 3.3V
60
85
dB
Output Short Circuit Current
50
80
mA
SR
Slew Rate
0.7
1.3
V/µs
φm
Phase Margin at Unit Gain - R L = 600Ω, CL =100pF
68
Degrees
Gm
Gain Margin - RL = 600Ω, CL =100pF
12
dB
en
Equivalent Input Noise Voltage - f = 1kHz
9
nV
-----------Hz
Io
THD
Cs
4/14
TS924
Total Harmonic Distortion
Vout = 2Vpk-pk, F = 1kHz, Av = 1, RL =600Ω
Channel Separation
4
0.005
120
MHz
%
dB
TS924
Electrical Characteristics
Table 4.
VCC = +5V, VDD = 0V, Vicm = VCC/2, Tamb = 25°C, RL connected to VCC/2 (unless
otherwise specified)
Symbol
Vio
DVio
Parameter
Min.
Typ.
Input Offset Voltage - TS924
TS924A
Tmin. ≤ Tamb ≤ Tmax. - TS924
TS924A
Max.
Unit
3
0.9
5
1.8
mV
µV/°C
Input Offset Voltage Drift
2
Iio
Input Offset Current
Vout = Vcc/2
1
30
Iib
Input Bias Current
Vout = Vcc/2
15
100
VOH
High Level Output Voltage
RL= 100k
RL = 600Ω
RL = 32Ω
4.90
4.85
nA
V
4.4
Low Level Output Voltage
RL= 10k
RL = 600Ω
RL = 32Ω
300
Avd
Large Signal Voltage Gain (Vout = 2Vpk-pk)
RL= 10k
RL = 600Ω
RL = 32Ω
200
40
17
Icc
Total Supply Current
no load, Vout = V cc/2
4.5
VOL
nA
50
120
mV
V/mV
7
mA
GBP
Gain Bandwidth Product
RL = 600Ω
CMR
Common Mode Rejection Ratio
60
80
SVR
Supply Voltage Rejection Ratio
Vcc = 3V to 5V
60
85
Output Short Circuit Current
50
80
mA
SR
Slew Rate
0.7
1.3
V/µs
φm
Phase Margin at Unit Gain
RL = 600Ω, CL =100pF
68
Gm
Gain Margin
RL = 600Ω, CL =100pF
12
en
Equivalent Input Noise Voltage
f = 1kHz
Io
THD
Cs
Total Harmonic Distortion
Vout = 2Vpk-pk, F = 1kHz, Av = 1, RL =600Ω
Channel Separation
4
9
MHz
dB
dB
Degrees
dB
nV
-----------Hz
%
0.005
120
dB
5/14
Electrical Characteristics
Figure 1.
TS924
Output short circuit current vs.
output voltage
Figure 2.
Output short circuit current vs.
output voltage
100
100
80
Output Short-Circuit Current (mA)
Output Short-Circuit Current (mA)
80
60
Sink
40
Vcc=0/12V
20
0
-20
-40
Source
-60
60
Sink
40
20
Vcc=0/3V
0
-20
-40
Source
-60
-80
-80
-100
0
-100
0
2
4
6
8
10
0,5
1
1,5
2
2,5
3
Output Voltage (V)
12
Output Voltage (V)
Figure 3.
Voltage gain and phase vs.
frequency
Figure 4.
Output short circuit current vs.
output voltage
100
C L=500pF
V CC=±1.5V
Phase
Gain
Output Short-Circuit Current (mA)
80
60
Sink
40
20
Vcc=0/5V
0
-20
-40
Source
-60
-80
-100
0
1
2
3
4
Output Voltage (V)
Figure 5.
Voltage gain & phase vs. frequency Figure 6.
RL =10κ
CL=100pF
VCC=±1.5V
Phase
Gain
6/14
THD + noise vs. frequency
RL =2k Vo=10Vpp
VCC =±6V Av= -1
5
TS924
Figure 7.
Electrical Characteristics
THD + noise vs. frequency
R L=2k Vo=10Vpp
V CC=±6V Av= 1
Figure 9.
THD + noise vs. Vout
RL=32Ω f=1kHz
V CC=±1.5V Av= -1
Figure 11. THD + noise vs. Vout
Figure 8.
THD + noise vs. frequency
RL=32Ω Vo=2Vpp
VCC =±1.5V Av= 10
Figure 10. THD + noise vs. frequency
RL=32Ω Vo=4Vpp
V CC=±2.5V Av= 1
Figure 12. THD + noise vs. Vout
RL=2kΩ f=1kHz
VCC=±1.5V Av= -1
7/14
Macromodel
TS924
3
Macromodel
3.1
Important note concerning this macromodel
Please consider following remarks before using this macromodel.
●
All models are a trade-off between accuracy and complexity (i.e. simulation time).
●
Macromodels are not a substitute to breadboarding; rather, they confirm the validity of a
design approach and help to select surrounding component values.
●
A macromodel emulates the NOMINAL performance of a TYPICAL device within
SPECIFIED OPERATING CONDITIONS (i.e. temperature, supply voltage, etc.). Thus the
macromodel is often not as exhaustive as the datasheet, its goal is to illustrate the main
parameters of the product.
●
Data issued from macromodels used outside of its specified conditions (Vcc, Temperature,
etc.) or even worse: outside of the device operating conditions (Vcc, Vicm, etc.) are not
reliable in any way.
In Section 3.3, the electrical characteristics resulting from the use of these macromodels are
presented.
3.2
Electrical characteristics from macromodelization
Table 5.
Electrical characteristics resulting from macromodel simulation at V CC = 3V,
VDD = 0V, R L, CL connected to VCC/2, Tamb = 25°C (unless otherwise specified)
Symbol
Conditions
Vio
Unit
0
mV
Avd
RL = 10kΩ
200
V/mV
ICC
No load, per operator
1.2
mA
-0.2 to 3.2
V
Vicm
8/14
Value
VOH
RL = 10kΩ
2.95
V
VOL
RL = 10kΩ
25
mV
Isink
VO = 3V
80
mA
Isource
VO = 0V
80
mA
GBP
RL = 600kΩ
4
MHz
SR
RL = 10kΩ, CL = 100pF
1
V/µs
φm
RL = 600kΩ
68
Degrees
TS924
3.3
Macromodel
Macromodel code
** Standard Linear Ics Macromodels, 1996.
** CONNECTIONS:
* 1 INVERTING INPUT
* 2 NON-INVERTING INPUT
* 3 OUTPUT
* 4 POSITIVE POWER SUPPLY
* 5 NEGATIVE POWER SUPPLY
.SUBCKT TS92X 1 2 3 4 5
*
.MODEL MDTH D IS=1E-8 KF=2.664234E-16 CJO=10F
*
* INPUT STAGE
CIP 2 5 1.000000E-12
CIN 1 5 1.000000E-12
EIP 10 5 2 5 1
EIN 16 5 1 5 1
RIP 10 11 8.125000E+00
RIN 15 16 8.125000E+00
RIS 11 15 2.238465E+02
DIP 11 12 MDTH 400E-12
DIN 15 14 MDTH 400E-12
VOFP 12 13 DC 153.5u
VOFN 13 14 DC 0
IPOL 13 5 3.200000E-05
CPS 11 15 1e-9
DINN 17 13 MDTH 400E-12
VIN 17 5 -0.100000e+00
DINR 15 18 MDTH 400E-12
VIP 4 18 0.400000E+00
FCP 4 5 VOFP 1.865000E+02
FCN 5 4 VOFN 1.865000E+02
FIBP 2 5 VOFP 6.250000E-03
FIBN 5 1 VOFN 6.250000E-03
* GM1 STAGE ***************
FGM1P 119 5 VOFP 1.1
FGM1N 119 5 VOFN 1.1
RAP 119 4 2.6E+06
RAN 119 5 2.6E+06
* GM2 STAGE ***************
G2P 19 5 119 5 1.92E-02
G2N 19 5 119 4 1.92E-02
R2P 19 4 1E+07
R2N 19 5 1E+07
**************************
VINT1 500 0 5
GCONVP 500 501 119 4 19.38
VP 501 0 0
GCONVN 500 502 119 5 19.38
VN 502 0 0
9/14
Macromodel
********* orientation isink isource
VINT2 503 0 5
FCOPY 503 504 VOUT 1
DCOPYP 504 505 MDTH 400E-9
VCOPYP 505 0 0
DCOPYN 506 504 MDTH 400E-9
VCOPYN 0 506 0
***************************
F2PP 19 5 poly(2) VCOPYP VP 0 0 0 0
F2PN 19 5 poly(2) VCOPYP VN 0 0 0 0
F2NP 19 5 poly(2) VCOPYN VP 0 0 0 0
F2NN 19 5 poly(2) VCOPYN VN 0 0 0 0
* COMPENSATION ************
CC 19 119 25p
* OUTPUT ***********
DOPM 19 22 MDTH 400E-12
DONM 21 19 MDTH 400E-12
HOPM 22 28 VOUT 6.250000E+02
VIPM 28 4 5.000000E+01
HONM 21 27 VOUT 6.250000E+02
VINM 5 27 5.000000E+01
VOUT 3 23 0
ROUT 23 19 6
COUT 3 5 1.300000E-10
DOP 19 25 MDTH 400E-12
VOP 4 25 1.052
DON 24 19 MDTH 400E-12
VON 24 5 1.052
.ENDS ;TS92X
10/14
TS924
*******
0.5
0.5
1.75
1.75
TS924
4
Package Mechanical Data
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK ® packages.
These packages have a Lead-free second level interconnect. The category of second level
interconnect is marked on the package and on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at:
www.st.com.
4.1
DIP14 Package
Plastic DIP-14 MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
1.39
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.055
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
15.24
0.600
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
1.27
0.130
2.54
0.050
0.100
P001A
11/14
Package Mechanical Data
4.2
TS924
SO-14 package
SO-14 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
0.1
0.003
0.064
b
0.35
0.46
0.013
b1
0.19
0.25
0.007
0.5
0.018
0.010
0.019
c1
45˚ (typ.)
D
8.55
E
5.8
e
8.75
0.336
6.2
0.228
1.27
e3
3.8
G
L
0.344
0.244
0.050
7.62
F
S
0.007
1.65
C
MAX.
0.068
0.2
a2
M
TYP.
1.75
0.300
4.0
0.149
4.6
5.3
0.181
0.208
0.5
1.27
0.019
0.050
0.68
0.157
0.026
8 ˚ (max.)
PO13G
12/14
TS924
4.3
Package Mechanical Data
TSSOP14 package
TSSOP14 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0089
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0˚
L
0.45
A
0.60
0.0256 BSC
8˚
0˚
0.75
0.018
8˚
0.024
0.030
A2
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080337D
13/14
Revision History
5
TS924
Revision History
Date
Revision
May 2001
1
First Release
May 2005
2
Modifications on AMR Table 1 on page 3 (explanation of Vid and Vi
limits, ESD MM and CDM values added, Rthja added)
July 2005
3
PPAP references inserted in the datasheet see Table on page 2.
4
– Package mechanical data modified
– TS924IYPT/TS924AYIPT PPAP reference inserted in Table on
page 2.
– Macromodel modified
Nov. 2005
Changes
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
14/14