ETC TSLW1401

TSLW1401
EXTENDED TEMPERATURE
128 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS024A – JUNE 2001
Optical Glass Window
128 × 1 Sensor-Element Organization
400 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
for 256 Gray-Scale (8-Bit) Applications
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 2 MHz
Single 5-V Supply
(TOP VIEW)
SI
CLK
AO
VDD
1
8
2
7
3
6
4
5
GND
GND
GND
GND
Description
The TSLW1401 linear sensor array consists of a 128 × 1 array of photodiodes, associated charge amplifier
circuitry, and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels.
The pixels measure 63.5 µm (H) by 55.5 µm (W) with 63.5-µm center-to-center spacing and 8-µm spacing
between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and
a clock.
Functional Block Diagram
Pixel 1
Pixel
2
Integrator
Reset
Pixel
3
VDD
4
Pixel
128
Analog
Bus
Output
Amplifier
_
+
3
Sample/
Output
RL
(External
Load)
AO
6,7
GND
Switch Control Logic
Hold
Q1
Q2
Q3
Q128
Gain
Trim
CLK
SI
2
128-Bit Shift Register
1
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Copyright 2001, TAOS Inc.
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 Plano, TX 75074 (972) 673-0759
1
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TAOS024A – JUNE 2001
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
AO
3
Analog output.
CLK
2
Clock. The clock controls charge transfer, pixel output, and reset.
GND
5,6,7,8
Ground (substrate). All voltages are referenced to the substrate.
SI
1
Serial input. SI defines the start of the data-out sequence.
VDD
4
Supply voltage. Supply voltage for both analog and digital circuits.
Detailed Description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog
switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the
integration time.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition,
SI must go low before the next rising edge of the clock. An internal signal, called Hold, is generated from the
rising edge of SI and transmitted to analog switches in the pixel circuit. This causes all 128 sampling capacitors
to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is
clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a
charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first
18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the
129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a
high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and
return the internal logic to a known state. A subsequent SI pulse may be presented as early as the 130th clock
pulse, thereby initiating another pixel output cycle.
AO is driven by a source follower that requires an external pulldown resistor. When the output is not in the output
phase, it is in a high-impedance state. The output is nominally 0 V for no light input and 2 V for a nominal
white-level output.
The voltage developed at analog output (AO) is given by:
Vout = Vdrk + (Re) (Ee)(tint)
where:
Vout
Vdrk
Re
Ee
tint
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/( µJ/cm2)
is the incident irradiance in µW/cm2
is integration time in seconds
The TSL1401 is intended for use in a wide variety of applications, including: image scanning, mark and code
reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical
linear and rotary encoding.
Copyright 2001, TAOS Inc.
2
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TSLW1401
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TAOS024A – JUNE 2001
Absolute Maximum Ratings†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Voltage range applied to any output in the high impedance or power-off state, VO . . . –0.3 V to VDD + 0.3 V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 mA to 25 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 115°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
Supply voltage, VDD
MIN
NOM
4.5
5
MAX
UNIT
5.5
V
Input voltage, VI
0
VDD
V
High-level input voltage, VIH
Low-level input voltage, VIL
2
VDD
V
Wavelength of light source, λ
Clock frequency, fclock
Sensor integration time, tint
Setup time, serial input, tsu(SI)
Hold time, serial input, th(SI) (see Note 1)
0
0.8
400
1000
nm
5
2000
kHz
0.0645
100
ms
20
ns
0
Operating free-air temperature, TA
V
ns
–25
115
°C
NOTE 1: SI must go low before the rising edge of the next clock pulse.
CLK
SI
Internal
Reset
18 Clock Cycles
Integration
Not Integrating
Integrating
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
129 Clock Cycles
AO
Hi-Z
Hi-Z
Figure 1. Timing Waveforms
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Copyright 2001, TAOS Inc.
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128 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS024A – JUNE 2001
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 565 nm, tint = 5 ms,
RL = 330 Ω, Ee = 15 µW/cm2 (unless otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
Ee = 15 µW/cm2,
tint = 5 ms,
λp = 565 nm
MIN
TYP
MAX
1.6
2
2.4
V
0
0.1
0.2
V
±4%
±7.5%
Vout
Analog output voltage (white, average over 128 pixels)
Vdrk
Analog output voltage (dark, average over 128 pixels)
PRNU
Pixel response nonuniformity
See Notes 3 & 4
Nonlinearity of analog output voltage
See Note 4
±0.4%
Output noise voltage
See Note 5
1
Re
Responsivity
Vsat
Analog output saturation voltage
SE
Saturation exposure
DSNU
Dark signal nonuniformity
IL
Image lag
IDD
Supply current
IIH
High-level input current
VI = VDD
IIL
Low-level input current
VI = 0
Ci
Input capacitance
see Note 2
λp = 565 nm
19
UNIT
FS
mVrms
25
32
V/
(µJ/cm 2)
3
3.5
V
88
136
nJ/cm 2
See Note 6
λp = 565 nm
All pixels
See Note 7
0.08
0.120
All except pixel 1
See Note 7
0.017
0.035
See Note 8
V
0.5%
2.5
4
mA
1
µA
1
µA
5
pF
NOTES: 2. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 565 nm.
3. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
4. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
5. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
6. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re.
7. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
8. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL V out (IL) V drk
V out (white) V drk
100
Timing Requirements (see Figure 1 and Figure 2)
MIN
tsu(SI)
Setup time, serial input (see Note 9)
th(SI)
Hold time, serial input (see Note 9 and Note 10)
tw
tr, tf
NOM
MAX
UNIT
20
ns
0
ns
Pulse duration, clock high or low
50
ns
Input transition (rise and fall) time
0
500
ns
NOTES: 9. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
10. SI must go low before the rising edge of the next clock pulse.
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
ts
Copyright 2001, TAOS Inc.
4
TEST CONDITIONS
Analog output settling time to ±1%
RL = 330 Ω,
CL = 50 pF
MIN
TYP
350
MAX
UNIT
ns
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TSLW1401
EXTENDED TEMPERATURE
128 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS024A – JUNE 2001
tw
1
2
128
129
5V
2.5 V
CLK
0V
tsu(SI)
SI
5V
50%
0V
th(SI)
ts
AO
ts
Pixel 1
Pixel 128
Figure 2. Operational Waveforms
TYPICAL CHARACTERISTICS
PHOTODIODE SPECTRAL RESPONSIVITY
1
TA = 25°C
Normalized Responsivity
0.8
0.6
0.4
0.2
0
300
400
500
600
700
800
900
1000 1100
λ – Wavelength – nm
Figure 3
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Copyright 2001, TAOS Inc.
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TSLW1401
EXTENDED TEMPERATURE
128 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS024A – JUNE 2001
TYPICAL CHARACTERISTICS
DARK SIGNAL NONUNIFORMITY
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
4
0.04
I DD– Supply Current – mA
Dark Signal Nonuniformity – V
0.06
0.03
0.02
3
2
1
0.01
0
–40
–20
0
20
40
60
80
100
TA – Free-Air Temperature – °C
0
–40
120
–20
20
60
100
0
40
80
TA – Free-Air Temperature – °C
Figure 4
Figure 5
ANALOG OUTPUT SATURATION VOLTAGE
vs
FREE-AIR TEMPERATURE
AVERAGE ANALOG OUTPUT VOLTAGE, WHITE
vs
FREE-AIR TEMPERATURE
1.2
Average Analog Output Voltage, White – V
Analog Output Saturation Voltage – V
3.28
3.26
3.24
3.22
3.20
3.18
3.16
–40
–20
0
40
80
20
60
TA – Free-Air Temperature – °C
100
120
1
0.8
0.6
0.4
VDD = 5 V
= 400 nm to 660 nm
0.2
0
–40
–20
0
20
40
60
80
100
TA – Free-Air Temperature – °C
Figure 6
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120
120
Figure 7
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TSLW1401
EXTENDED TEMPERATURE
128 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS024A – JUNE 2001
TYPICAL CHARACTERISTICS
Normalized Average Analog Output Voltage, Dark
AVERAGE ANALOG OUTPUT VOLTAGE, DARK
vs
FREE-AIR TEMPERATURE
4
VDD = 5 V
3.5
Normalized to 25C
tint = 5 ms
3
tint = 2.5 ms
2.5
tint = 1 ms
2
1.5
1
0.5
tint = 0.5 ms
0
40
50
60
80
100 110
70
90
TA – Free-Air Temperature – °C
120
Figure 8
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TAOS024A – JUNE 2001
MECHANICAL INFORMATION
The integrated circuit is mounted in a window frame package with a clear, flat glass cover.
5
6
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
1
2
3
4
5
6
7
8
SI
CLK
AO
VDD
GND
GND
GND
GND
7
8
4
3
2
1
SECTION ’A–A’
0.600 [15.240]
0.090 [2.286]
0.536 [13.614]
7
0.075 [1.905
0.375 [9.512]
0.150 [3.810]
0.060 [1.524]
0.040 [1.016]
A
0.550 [13.970]
C
L
0.325 [8.255]
0.260 [6.610]
NOTE B
0.010 [0.254]
(CHAMFER REF.)
Pin 1
A
C
L
0.020 [0.508]
0.020 [0.508]
0.135 [3.429]
0.025 [0.635]
0.115 [2.921]
0.100 [2.540]
(TYP. 3 PLCS.)
0.135 [3.425]
REF.
NOTES: A. All linear dimensions are in inches and parenthetically in [millimeters] ( ± 0.1 mm).
B. Pixel 1 typical location aligns on leading edge of pin 1 and 0.71 mm above package centerline.
C. Glass thickness nominally 1 mm with refraction index of 1.5186.
Figure 9. Packaging Configuration
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TSLW1401
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128 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS024A – JUNE 2001
PRODUCTION DATA — information in this document is current at publication date. Products conform to
specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard
warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this
document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised
to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems.
TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product
design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that
the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular
purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any
and all liability, including without limitation consequential or incidental damages.
TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR
USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY
RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY
UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK.
TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions
Incorporated.
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TSLW1401
EXTENDED TEMPERATURE
128 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS024A – JUNE 2001
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