Complies with Directive 2002/95/EC (RoHS) I. Product Overview TXC100 is a rugged, single chip OOK/ASK/FSK Transmitter IC in the 300-450 MHz frequency range. This chip is highly integrated and has all required RF functions including a complete PLL circuit and power amplifier, thus requiring very few external components. The TXC100 is feature rich and is very small in size with high output power and low current consumption and is ideal for various short range wireless applications in the industrial, automotive and consumer markets. 3x3mm package II. Key Features • • • • • • • • • • • • • Operating Frequency Range: 300-450 MHz Modulation Types: OOK/ASK/FSK Operation supply voltage: 2.1V - 3.6V High Date rate: ASK: 100 kbps FSK: 20 kbps Low current consumption: ASK mode: 7 mA typical FSK mode: 10 mA typical Low Stand by current: < 1 nA Adjustable Output power: -10dBm to +10dBm Adjustable FSK Shift Programmable Clock Output Very Low external component count Extended temperature range: -40°C to +125°C. Small Package: 3X3 mm 16-pin TQFN package Standard 13 inch reel, 2500 pieces III. Popular applications • • • • • • • • • • • • Electrical Characteristics Characteristics Operating Frequency Min fo 300 Typical Max Units 450 MHz OOK/ASK/ FSK Modulation Types ASK Data Rate 100 Kbps FSK Data Rate 20 Kbps Peak RF Output Power 10 Standby Current dBm 1 nA Vdc Supply Voltage Range VDD 2.1 3.6 Operating Temperature Ta -40 +125 Sym Min o C Crystal Parameters Characteristics Active RFID tags Automated Meter reading Wireless sensor nodes Home Automation Security systems Tire pressure monitoring Remote keyless entry Automobile Immobilizers Sports & Performance monitoring Wireless Toys Medical equipment Command & Control systems Sym Crystal Frequency fc Load Capacitance Cl Tolerance Tol Typical Max fo/32 MHz 10 30 Units pF ppm RF Monolithics, Inc. 4441 Sigma Road Dallas, Texas 75244 (800) 704-6079 toll-free in U.S. and Canada www.rfm.com Email: [email protected] 1 of 11 IV. TXC100 Block Diagram and Typical Application Circuit Mode TX Data Input Input VDD PA D0 D1 D2 11 12 13 2 Modulation Control 3 C5 C6 C7 6 Mode Select (ASK / FSK) RF Control Shape R1 7 C4 C1 XTAL1 14 REFEXT/XTAL2 XTAL DRV LOGIC C8 L1 Mixer 15 C3 C2 C9 PA Output Filter OSC PA 8 C10 CLK0 9 L2 /N CLK1 C16 /32 10 5 CLK C11 C12 BIAS 1 C13 PIN 4 ENABLE INPUT PIN 16 GND C14 C15 VCC Table 1: Component Values for Typical Application Circuit C1 C2 C33 C43 C5 C6 C7 C8 C9 C10¹ C11¹ C12¹ C13 C14 C15 C16¹ L1¹² L2¹² X1 315MHz Band 433MHz Band 100pF 100pF DNP DNP 1uF .01uF 220pF 100pF 680pF 15pF 22pF 15pF 1uF .01uF 220pF 2.2pF 27nH 22nH 9.84375MHz 100pF 100pF DNP DNP 1uF .01uF 220pF 100pF 680pF 6.8pF 1pF 6.8pF 1uF .01uF 220pF 1pF 22nH 18nH 13.5600MHZ ¹Matched to 50 Ohms ²Use wirewound inductors ONLY 3 Use for External Reference Input DNP - Do Not Populate 2 of 11 V. Pin Configuration BOTTOM VIEW Dev2 Xtal1 Xtal2/REF IN GND 3x3mm 13 14 15 16 Dev0 11 2 ModeSel Clk1 10 3 DataIN Clk0 9 4 Stdby 8 7 6 5 Clk Out VDD VDDPA 1 ES Out 12 PA Out Dev1 VI. Pin Description Pin Name Description 1 VDD VDD is the supply voltage for the PLL and Logic. Bypass as close as possible to pin with 1µF, .01µF, 220pf. Mode Select enables the chip to be set in ASK or FSK mode Low: ASK mode High: FSK mode ASK, FSK Mode Selection The Mode Select pin (2) sets the transmit mode of the device. A logic low sets the mode to ASK modulation. A logic high sets the device to FSK modulation. 2 ModeSel In ASK mode, data driven onto the DataIN pin (3) gates the internal power amplifier. A data “High” turns the power amplifier on and thus drives the RF signal to the antenna. A data “Low” turns off the power amplifier. In FSK mode, data driven onto the DataIN pin shifts the carrier frequency by the amount programmed through the DEV[2..0] pins (13,12,11). A data “Low” performs no shift. The frequency of a data “Low” in FSK mode is the same frequency of a data “High” in ASK mode. The FSK deviation is achieved by pulling the crystal frequency. See Crystal Reference section (pin 15) for more details. The maximum deviation for the 315MHz band and 433MHz band is approximately 55 kHz and 80 kHz, respectively. Data Input enables the turning on and off of the Power Amplifier in ASK mode and selection of high or low frequency in FSK mode. 3 DataIN Low (ASK mode): Power Amplifier off High (ASK mode): Power Amplifier on Low (FSK mode): Low frequency High (FSK mode): High frequency Standby enables selection of low power shutdown/standby mode Low or if left unconnected: Sets device in Standby mode High: Sets device in Ready for transmission mode 4 Stdby Note: Lowest current consumption achieved when all config pins at Logic Low. Standby Mode The Standby pin (4) sets the device in low power shutdown, pulling only 0.2nA. When the device is brought out of standby with a logic “High”, it is ready for operation within 200us. The Standby pin has an internal pull-down resistor so this pin can be pulled low or left unconnected. The 200us turn-on time is due to crystal start-up. An optimally matched crystal will minimize this turn-on time. See Crystal Reference section (pin 15) for details on crystal load matching. 3 of 11 Clock output is a buffered version of the crystal frequency which may be used to drive external logic or a microprocessor. The frequency is programmable thru pins 9 (Clk0) and 10(Clk1) as below: 5 ClkOut Clk0 0 1 0 1 Clk1 0 0 1 1 ClkOut 0 fc/4 fc/8 fc/16 NB: fc = (Crystal Frequency) 6 VDDPA Supply voltage for the Power amp. Bypass as close as possible to the pin with a .01µF and 220pf capacitor. Envelope-Shaping Output controls the on/off ramp time of the power amp in ASK mode. This reduces the spectral width of the output signal when modulated. Placing a small resistor in series with the output, as close as possible to the chip to minimize circuit parasitics, will enable control of output power. A potentiometer may be used to adjust the output power to the desired level. Bypass as close to the pin as possible with a 680pF and 220pF capacitor. 7 ESOut Note: By using the ESOUT pin there is approx a 0.6dB drop in max output power. Spectral Shaping/Output Power Adjust The ESOUT pin (7) can serve a dual function. Use of the ESOUT pin will allow for a softer turn-on/turn-off of the power amplifier resulting in reduced spectral spreading of the ASK signal. Inserting a series resistor between the ESOUT pin and the pull-up inductor will allow for adjustment of the carrier output power. Typically a resistance of 5K Ohms or less will allow adjustment down to -10dBm. The envelope-shaping resistor allows for a turn on / turn-off of the Power Amp in ASK mode. Power-Amplifier Output. - Requires a DC path to the supply voltage, thru a series inductor which can be part of the output matching network to an antenna 8 PAOut 10, 9 Clk[1..0] Power Amplifier The power amp is an open-drain, Class C amplifier with optimal impedance at PAOUT (pin 8) of about 250 Ohms. A matching network can optimize the output to drive typical 50 Ohm antennas. An output matching network with component values is shown in the Typical Application Circuit (section IV). Additionally, the matching network aids in suppressing carrier harmonics to aid in compliance testing. See description for Pin 5 Frequency Deviation configuration pins set the amount of deviation desired between data logic states in FSK mode. Frequency deviation is programmable through pins 13, 12, 11 as below: 13, 12, 11 FreqDev[2..0] DEV ∆ .125 x max .250 x max .375 x max .500 x max .625 x max .750 x max .875 x max max DEV 2 0 0 0 0 1 1 1 1 DEV 1 0 0 1 1 0 0 1 1 DEV 0 0 1 0 1 0 1 0 1 Note: Deviation values are approx for properly loaded crystal. Crystal characteristics and loading will differ with other manufacturers. 14 Xtal1 External Crystal input 1 presents a capacitance of 3pF to GND in ASK and FSK(DataIN=0V) mode. Additional circuit parasitics add to the package capacitance which increases the presented load to about 4.5pF. External Crystal input 2 presents a capacitance of 3pF to GND in ASK and FSK(DataIN=0V) mode. Additional circuit parasitics add to the package capacitance which increases the presented load to about 4.5pF. External Ref Input enables a custom frequency to be applied to obtain the desired transmit frequency. Unconnected Xtal1 input must be bypassed with a .01µF capacitor and additional .01µF series capacitance should be added into External Reference input. 15 Xtal2/REFIN Crystal Reference The crystal drive circuit in the TXC100 is designed to present a 3pF load to GND to the reference crystal. Including PCB parasitic capacitances, this increases to about 4.5pF. In ASK mode, the full 3pF load is applied to the crystal allowing it to oscillate at the desired frequency. In FSK mode, a portion of the 3pF load is removed in response to a data logic “High” applied to the DataIN (pin 2) and the programmed frequency deviation pins DEV[0..2] (13,12,11). For larger frequency deviations use a crystal with larger motional capacitance or reduce PCB parasitic capacitance as much as possible. NOTE: Use a crystal with the same load capacitance as that presented by the TXC100. If not, additional matching will be necessary to achieve the desired carrier frequency and the added matching will reduce the desired FSK deviation. Ground. Connect to system ground. 16 GND Note: The exposed ground pad is the power amp ground. It must be connected to system ground thru a low inductance path. 4 of 11 VII. Absolute Maximum Ratings Parameter Symbol Limit Values Unit Min Max Operating Temperature TO -40 +125 °C Junction Temperature TJ -40 +150 °C Storage Temperature TS -60 +150 °C Supply Voltage – Vdd to GND VS -0.3 +4 V -0.3 Vdd + 0.3 V All pins to GND Note: Maximum ratings must not be exceeded under any circumstances and can cause permanent damage to the IC VIII. DC Electrical Characteristic (Typical values taken at VDD = +3.0V, TA = +25°C, unless otherwise noted) Limit Values Characteristic Sym Notes Unit min Supply Voltage VDD typ 2.1 Test Conditions max 3.6 V Current Consumption Standby Supply ISTDBY IDD 1,4 0.2 1 TA = +25 deg C 120 300 700 1600 2.9 4.3 PA off, Data=0V (ASK) 7 10.7 50% duty cycle (ASK) 10.5 17.1 3.3 4.8 PA off, Data=0V (ASK) 7.3 11.4 50% duty cycle (ASK) 10 18.1 Data=+VDD (FSK and ASK) nA TA = +85 deg C TA = +125 deg C mA 315 Mhz Band Data=+VDD (FSK and ASK) 433 Mhz Band Digital Inputs Data Input Low VIL Data Input High VIH Max Input Current 0.25 VDD-0.25 II V V 15.5 20 µa 0.25 V Clkout, Load = 10pF V Clkout, Load = 10pF Digital Outputs Output Voltage Low VOL Output Voltage High VOH VDD-0.25 5 of 11 IX. AC Electrical Characteristic (Typical values taken at VDD = +3.0V, TA = +25°C, unless otherwise noted) Parameter Sym Notes min Limit Values typ max Unit Test Conditions PLL Performance VCO Gain KVCO 280 -75 -74 -98 -98 300 -40 -56 -52 -56 -65 Phase Noise Loop BW Reference Spur BW 2nd Harmonic 3rd Harmonic MHz/V dBc/Hz 315 Mhz Band 433 Mhz Band 315 Mhz Band 433 Mhz Band Freq Offset = 100kHz Freq Offset = 1MHz kHz dBc dBc dBc 315 Mhz Band 433 Mhz Band 315 Mhz Band 433 Mhz Band Crystal Frequency Range Tolerance Internal Load Capacitance Clock Output Frequency System Characteristics fREF CLKOUT Frequency Range 300 ∆dfVDD 12.2 10 5.3 160 300 20 100 55 80 35 31 27 25 -77 4 ∆dfTA TBD Output Power Start-up time Rise Time 4 tON tr Max Data Rate 5 5 5 Frequency Deviation (FSK) Transmit Efficiency η=POUT/(VDDxIDD) Power ON/OFF Ratio Frequency Stability vs. VDD Frequency Stability vs. Temp fRF/32 50 3 FXTAL/N 3 2 4 6.1 2.7 MHz ppm pF MHz 450 16.1 12.4 fundamental mode, AT Determined by CLK1 and CLK2 MHz dBm µs ns kbps kHz % dB kHz kHz TA = -40C, VDD = +3.6V into 50Ω matched TA = +25C, VDD = +3.0V load TA = +125C, VDD = +2.1V STDBY to Tx FSK (50% Duty Cycle) ASK (50% Duty Cycle) 315 Mhz Band DEV[2..0]=111 433 Mhz Band 315 Mhz Band CW 433 Mhz Band 315 Mhz Band 50% duty cycle 433 Mhz Band ASK Mode -40°C to +85°C Notes: 1. 10kHz, 50% duty cycle 2. Dependent on PCB parasitic trace capacitance and crystal parameters. 3. Dependent on crystal parameters. 4. Transmit Efficiency, RF Output Power, and Supply Current are heavily dependent on proper output matching and PCB layout. 5. No Envelope Shaping. 6 of 11 X. Typical Operating Characteristics Supply Voltage vs Supply Current Supply Voltage vs Supply Current 15 15 mA @ 433.92MHz mA @ 315MHz 14 14 13 Supply Current, mA Supply Current, mA 13 12 11 12 11 10 10 9 9 8 8 7 7 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 2 4 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 Supply Voltage, V Supply Voltage, V Supply Voltage vs Output Power Supply Voltage vs Output Power 13 14 dBm @ 433.92MHz dBm @ 315MHz 12 13 11 11 Output Power, dBm Output Power (Po), dBm 12 10 9 10 9 8 8 7 7 6 6 5 5 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Supply Voltage, V Output Power vs Supply Current 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 Output Power vs Supply Current 15 15 mA @ 315MHz mA @ 433.92MHz 14 14 13 13 12 Supply Current, mA Supply Current, mA 2.9 Supply Voltage, V 11 10 12 11 10 9 9 8 8 7 6 7 8 9 10 Output Power (Po), dBm 11 12 13 7 5 6 7 8 9 10 11 12 13 Output Power, dBm 7 of 11 Supply Voltage vs Modulation Supply Current Voltage vs Modulation Current 15 15 14 13 12 12 315MHz,ASK,50% DC 9 11 10 433.92MHz,ASK,50% DC 9 8 8 7 7 6 6 5 5 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Voltage, V 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 Supply Voltage, V Supply Current and Output Power vs ESout Resistor 16 Supply Current and Output Power vs ESout Resistor 12 16 10 15 8 14 8 13 6 13 6 12 4 12 4 11 2 10 0 12 f = 315MHz f = 433.92MHz 15 14 -2 8 -4 7 -6 6 -8 5 -10 4 -12 3 -14 2 0.1 1 10 100 Resistor, Ohms 1000 -16 10000 2 11 Supply Current, mA Current 9 10 Power (dBm) Power 10 0 Current (mA) 9 -2 8 -4 7 -6 6 -8 5 -10 4 -12 Output Power, dBm 2.1 2.2 Output Power, dBm 2 Supply Current, mA Current, mA 10 Supply Current, mA 13 11 433.92MHz,FSK,50% DC 14 315MHz,FSK,50% DC -14 3 2 0.1 1 10 100 1000 -16 10000 Resistor, Ohms 8 of 11 XI. Theory of Operation Introduction The TXC100 is a crystal-referenced transmitter designed to operate in the 315/433 MHz frequency spectrum. The carrier and crystal reference relation is given by: fC = fXTAL * 32 It is capable of supporting OOK/ ASK and FSK data transmissions at 100kbps and 20kbps, respectively. The output power is adjustable from -10dBm to +10dBm thru a resistor at the ESOUT (pin 7). The FSK frequency deviation is programmable with up to eight different deviation values. The IC also provides a buffered clock output of the reference crystal for use by an external processor. The clock output is also programmable. Frequency Synthesizer The frequency synthesizer is simply a Phase Locked Loop circuit with a loop bandwidth of 300 kHz. The PLL contains a phase detector, charge pump, VCO, integrated loop filter, ÷32 clock divider, and crystal oscillator drive circuit. The internal PLL is self contained and requires no external components for filtering or dividing. Only a reference crystal is needed. 50Ω Output Matching When properly matched, the TXC100 can output up to +12 dBm into a 50Ω load. The output is an open-drain configuration which requires a pull-up inductor for proper internal biasing. The pull-up inductance serves to provide biasing for the power amplifier and is a high frequency choke to reduce unwanted coupling back into the power supply. Maximum power transfer occurs when the output is closely matched to 250Ω. For best performance use wirewound inductors instead of chip inductors. Wirewound inductors provide lower insertion loss as opposed to chip inductors. See Typical Application Circuit (section IV) for topology and matching component values. PCB Layout Considerations PCB layout is critical to proper and consistent operation. Always use controlled impedance lines from the PAOUT (pin 8). For a .062” thick FR4 board a 50Ω impedance line is approximately .110” wide. Component spacing is critical as well. Keep all output matching components as close together as possible to minimize stray inductance and capacitance that can detune the matching network. Keep ground planes at least a board thickness away from the signal output leading to the antenna or RF connector. 9 of 11 Antenna Layout Considerations Most compact wireless designs have the need for a small, compact antenna. Typically, loop antennas are the ones of choice since they can be designed into tight spaces. Loop antenna design can become fairly lengthy and detailed discussion is beyond the scope of this datasheet. The object here is to provide a “rule of thumb” approach to achieve an appropriate starting point. Empirical data will provide the best path to take. The circumference of the antenna should be less than λ/4 so that the antenna appears inductive. For this, a series matching capacitor is used to tune out the inductance of the antenna, since the antenna appears inductive. The capacitor may be located at the feed point of the antenna or at the “grounded” end. The capacitor may be a variable type or several fixed values may be attempted until an optimal match is reached. The use of a good network analyzer is essential for proper matching and maximum power transfer. For additional information on antenna design see the Application Notes section of our website: http://www.rfm.com/corp/apnotes.htm. XII. Typical Test Circuit 10 of 11 Package Dimensions – 3x3mm 16-pin TQFN Package (all values in mm) TOP VIEW SEATING PLANE 3.00 BOTTOM VIEW SIDE VIEW 0.0~0.05 0.23 TYP. 0.5 TYP. PIN 1 Indicator 0.50 PIN # 1 0.5 TYP. 3.00 0.23 TYP. 1.50 0.40 0.25 0.75 MAX 1.50 0.40 4441 Sigma Road Dallas, Texas 75244 (800) 704-6079 toll-free in U.S. and Canada Email: [email protected] www.rfm.com www.wirelessis.com © 2005 RF Monolithics, Inc. TXC100 012706 11 of 11