ONSEMI UC384XBVD1G

UC3844B, UC3845B,
UC2844B, UC2845B
High Performance
Current Mode Controllers
The UC3844B, UC3845B series are high performance fixed
frequency current mode controllers. They are specifically designed for
Off−Line and dc−dc converter applications offering the designer a
cost−effective solution with minimal external components. These
integrated circuits feature an oscillator, a temperature compensated
reference, high gain error amplifier, current sensing comparator, and a
high current totem pole output ideally suited for driving a power
MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, a latch for single pulse metering, and a flip−flop
which blanks the output off every other oscillator cycle, allowing
output deadtimes to be programmed from 50% to 70%.
These devices are available in an 8−pin dual−in−line and surface
mount (SOIC−8) plastic package as well as the 14−pin plastic surface
mount (SOIC−14). The SOIC−14 package has separate power and
ground pins for the totem pole output stage.
The UCX844B has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX845B is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
Features
•
•
•
•
•
•
•
•
•
•
•
Pb−Free Packages are Available
Trimmed Oscillator for Precise Frequency Control
Oscillator Frequency Guaranteed at 250 kHz
Current Mode Operation to 500 kHz Output Switching Frequency
Output Deadtime Adjustable from 50% to 70%
Automatic Feed Forward Compensation
Latching PWM for Cycle−By−Cycle Current Limiting
Internally Trimmed Reference with Undervoltage Lockout
High Current Totem Pole Output
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
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PDIP−8
N SUFFIX
CASE 626
8
1
SOIC−8
D1 SUFFIX
CASE 751
8
1
SOIC−14
D SUFFIX
CASE 751A
14
1
PIN CONNECTIONS
Compensation
Voltage Feedback
Current Sense
RT/CT
1
8
2
7
3
6
4
5
(Top View)
Compensation
NC
Voltage Feedback
NC
Current Sense
NC
RT/CT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
Vref
VCC
Output
GN
D
Vref
NC
VCC
VC
Output
GND
Power Ground
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 16 of this data sheet.
 Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 3
1
Publication Order Number:
UC3844B/D
UC3844B, UC3845B, UC2844B, UC2845B
VCC
5.0V
Reference
Vref
8(14)
R
R
RT/CT
VCC
Undervoltage
Lockout
Vref
Undervoltage
Lockout
VC
7(11)
Output
6(10)
Oscillator
4(7)
Voltage
Feedback
Input
7(12)
Latching
PWM
Power
Ground
5(8)
2(3)
Output/
Compensation
Error
Amplifier
Current
Sense Input
3(5)
1(1)
GND
5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
Operating
Temperature Range
Package
Shipping†
UC384xBD
SOIC−14
55 Units/Rail
UC384xBDR2
SOIC−14
2500 Tape & Reel
UC3844BDR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
SOIC−8
98 Units/Rail
SOIC−8
(Pb−Free)
98 Units/Rail
SOIC−8
2500 Tape & Reel
SOIC−8
(Pb−Free)
2500 Tape & Reel
PDIP−8
50 Units/Rail
UC384xBNG
PDIP−8
(Pb−Free)
50 Units/Rail
UC2845BD
SOIC−14
55 Units/Rail
UC284xBDR2
SOIC−14
2500 Tape & Reel
UC2845BDR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
SOIC−8
98 Units/Rail
SOIC−8
2500 Tape & Reel
SOIC−8
(Pb−Free)
2500 Tape & Reel
Device
UC384xBD1
UC3844BD1G
TA = 0° to +70°C
UC384xBD1R2
UC384xBD1R2G
UC384xBN
UC2845BD1
TA = −25° to +85°C
UC284xBD1R2
UC284xBD1R2G
UC2844BN
PDIP−8
50 Units/Rail
UC384xBVD
SOIC−14
55 Units/Rail
UC3844BVDR2
SOIC−14
2500 Tape & Reel
SOIC−8
98 Units/Rail
UC384xBVD1R2
SOIC−8
2500 Tape & Reel
UC384xBVN
PDIP−8
50 Units/Rail
UC384xBVD1
TA = −40° to +105°C
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
x indicates either a 4 or 5 to define specific device part numbers.
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2
UC3844B, UC3845B, UC2844B, UC2845B
MAXIMUM RATINGS
Rating
Total Power Supply and Zener Current
Symbol
Value
Unit
(ICC + IZ)
30
mA
IO
1.0
A
Output Current, Source or Sink (Note 1)
Output Energy (Capacitive Load per Cycle)
W
5.0
J
Current Sense and Voltage Feedback Inputs
Vin
− 0.3 to + 5.5
V
Error Amp Output Sink Current
IO
10
mA
PD
RJA
862
145
mW
°C/W
PD
RJA
702
178
mW
°C/W
PD
RJA
1.25
100
W
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature
UC3844B, UC3845B
UC2844B, UC2845B
TA
Storage Temperature Range
Tstg
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package, SOIC−14 Case 751A
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
D1 Suffix, Plastic Package, SOIC−8 Case 751
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
N Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
°C
0 to + 70
− 25 to + 85
°C
− 65 to +150
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Maximum package power dissipation limits must be observed.
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
UC284XB
Characteristic
UC384XB, XBV
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C)
Vref
4.95
5.0
5.05
4.9
5.0
5.1
V
Line Regulation (VCC = 12 V to 25 V)
Regline
−
2.0
20
−
2.0
20
mV
Load Regulation (IO = 1.0 mA to 20 mA)
Regload
−
3.0
25
−
3.0
25
mV
Temperature Stability
TS
−
0.2
−
−
0.2
−
mV/°C
Total Output Variation over Line, Load, and Temperature
Vref
4.9
−
5.1
4.82
−
5.18
V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C)
Vn
−
50
−
−
50
−
V
Long Term Stability (TA = 125°C for 1000 Hours)
S
−
5.0
−
−
5.0
−
mV
ISC
− 30
− 85
−180
− 30
− 85
−180
mA
49
48
225
52
−
250
55
56
275
49
48
225
52
−
250
55
56
275
Output Short Circuit Current
OSCILLATOR SECTION
fOSC
Frequency
TJ = 25°C
TA = Tlow to Thigh
TJ = 25°C (RT = 6.2 k, CT = 1.0 nF)
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V)
fOSC/V
−
0.2
1.0
−
0.2
1.0
%
Frequency Change with Temperature (TA = Tlow to Thigh)
%
fOSC/T
−
1.0
−
−
0.5
−
Oscillator Voltage Swing (Peak−to−Peak)
VOSC
−
1.6
−
−
1.6
−
Discharge Current (VOSC = 2.0 V)
TJ = 25°C
TA = Tlow to Thigh (UC284XB, UC384XB)
TA = Tlow to Thigh (UC384XBV)
Idischg
7.8
7.5
−
8.3
−
−
8.8
8.8
−
7.8
7.6
7.2
8.3
−
−
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3844B, UC3845B
Thigh = + 70°C for UC3844B, UC3845B
= − 25°C for UC2844B, UC2845B
= + 85°C for UC2844B, UC2845B
= − 40°C for UC3844BV, UC3845BV
= +105°C for UC3844BV, UC3845BV
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3
V
mA
8.8
8.8
8.8
UC3844B, UC3845B, UC2844B, UC2845B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 4], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 5], unless otherwise noted.)
UC284XB
Characteristic
Symbol
Min
VFB
IIB
UC384XB, XBV
Typ
Max
Min
Typ
Max
Unit
2.45
2.5
2.55
2.42
2.5
2.58
V
−
− 0.1
−1.0
−
− 0.1
− 2.0
A
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V)
Input Bias Current (VFB = 5.0 V)
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V)
Unity Gain Bandwidth (TJ = 25°C)
Power Supply Rejection Ratio (VCC = 12 V to 25 V)
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V)
AVOL
65
90
−
65
90
−
dB
BW
0.7
1.0
−
0.7
1.0
−
MHz
PSRR
60
70
−
60
70
−
dB
mA
ISink
ISource
2.0
− 0.5
12
−1.0
−
−
2.0
− 0.5
12
−1.0
−
−
VOH
VOL
5.0
6.2
−
5.0
6.2
−
−
−
0.8
−
1.1
−
−
−
0.8
0.8
1.1
1.2
2.85
−
3.0
−
3.15
−
2.85
2.85
3.0
3.0
3.15
3.25
0.9
−
1.0
−
1.1
−
0.9
0.85
1.0
1.0
1.1
1.1
PSRR
−
70
−
−
70
−
dB
IIB
−
− 2.0
−10
−
− 2.0
−10
A
tPLH(In/Out)
−
150
300
−
150
300
ns
VOL
−
−
−
13
−
12
0.1
1.6
−
13.5
−
13.4
0.4
2.2
−
−
−
−
−
−
−
13
12.9
12
0.1
1.6
1.6
13.5
−
13.4
0.4
2.2
2.3
−
−
−
VOL(UVLO)
−
0.1
1.1
−
0.1
1.1
V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C)
tr
−
50
150
−
50
150
ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C)
tf
−
50
150
−
50
150
ns
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
(UC284XB, UC384XB)
(UC384XBV)
V
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 6 & 7)
(UC284XB, UC384XB)
(UC384XBV)
AV
Maximum Current Sense Input Threshold (Note 6)
(UC284XB, UC384XB)
(UC384XBV)
Vth
Power Supply Rejection Ratio
(VCC = 12 V to 25 V) (Note 6)
Input Bias Current
Propagation Delay (Current Sense Input to Output)
V/V
V
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
(ISink = 200 mA, UC284XB, UC384XB)
(ISink = 200 mA, UC384XBV)
High State (ISource = 20 mA, UC284XB, UC384XB)
(ISource = 20 mA, UC384XBV)
(ISource = 200 mA)
V
VOH
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA)
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX844B, BV
UCX845B, BV
Minimum Operating Voltage After Turn−On
UCX844B, BV
UCX845B, BV
Vth
V
VCC(min)
V
4. Adjust VCC above the Startup threshold before setting to 15 V.
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Thigh = + 70°C for UC3844B, UC3845B
Tlow = 0°C for UC3844B, UC3845B
= − 25°C for UC2844B, UC2845B
= + 85°C for UC2844B, UC2845B
= − 40°C for UC3844BV, UC3845BV
= +105°C for UC3844BV, UC3845BV
6. This parameter is measured at the latch trip point with VFB = 0 V.
7. Comparator gain is defined as: AV = V Output/Compensation
V Current Sense Input
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4
UC3844B, UC3845B, UC2844B, UC2845B
ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 8], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values
TA is the operating ambient temperature range that applies [Note 9], unless otherwise noted.)
UC284XB
Characteristic
UC384XB, XBV
Symbol
Min
Typ
Max
Min
Typ
Max
DC(max)
47
−
−
48
−
−
50
−
0
47
46
−
48
48
−
50
50
0
−
0.3
0.5
−
0.3
0.5
−
12
17
−
12
17
30
36
−
30
36
−
Unit
PWM SECTION
Duty Cycle
Maximum (UC284XB, UC384XB)
Maximum (UC384XBV)
Minimum
%
DC(min)
TOTAL DEVICE
Power Supply Current
Startup (VCC = 6.5 V for UCX845B,
Startup (VCC = 14 V for UCX844B, BV)
Operating (Note 8)
ICC
Power Supply Zener Voltage (ICC = 25 mA)
VZ
mA
V
8. Adjust VCC above the Startup threshold before setting to 15 V.
9. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Thigh = + 70°C for UC3844B, UC3845B
Tlow = 0°C for UC3844B, UC3845B
= − 25°C for UC2844B, UC2845B
= + 85°C for UC2844B, UC2845B
= − 40°C for UC3844BV, UC3845BV
= +105°C for UC3844BV, UC3845BV
% DT, PERCENT OUTPUT DEADTIME
50
R T, TIMING RESISTOR (k Ω)
75
VCC = 15 V
TA = 25°C
20
8.0
5.0
2.0
NOTE: Output switches at
1/2 the oscillator frequency
0.8
10 k
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
70
65
60
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
1
5
6
20 k
50 k 100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (kHz)
1.0 M
Figure 3. Output Deadtime
versus Oscillator Frequency
VCC = 15 V
AV = −1.0
TA = 25°C
VCC = 15 V
AV = −1.0
TA = 25°C
3.0 V
20 mV/DIV
2.5 V
4
55
Figure 2. Timing Resistor
versus Oscillator Frequency
2.55 V
2
7
50
10 k
1.0 M
3
1.CT = 10 nF
2.CT = 5.0 nF
3.CT = 2.0 nF
4.CT = 1.0 nF
5.CT = 500 pF
6.CT = 200 pF
7.CT = 100 pF
200 mV/DIV
80
2.5 V
2.0 V
2.45 V
0.5 s/DIV
1.0 s/DIV
Figure 4. Error Amp Small Signal
Transient Response
Figure 5. Error Amp Large Signal
Transient Response
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5
φ, EXCESS PHASE (DEGREES)
Vth , CURRENT SENSE INPUT THRESHOLD (V)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
UC3844B, UC3845B, UC2844B, UC2845B
0
1.2
30
1.0
60
0.8
90
0.6
20
120
0.4
0
150
0.2
180
10 M
0
100
VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 k
TA = 25°C
80
Gain
60
40
Phase
−20
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
1.0 M
VCC = 15 V
TA = 25°C
TA = 125°C
TA = −55°C
0
0
VCC = 15 V
−4.0
−8.0
−12
TA = −55°C
TA = 125°C
−16
−20
TA = 25°C
−24
0
20
40
60
80
100
Iref, REFERENCE SOURCE CURRENT (mA)
120
ÄÄÄÄ
ÄÄÄÄ
110
VCC = 15 V
RL ≤ 0.1 90
70
50
−55
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 9. Reference Short Circuit Current
versus Temperature
∆V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
Figure 8. Reference Voltage Change
versus Source Current
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
VCC = 12 V to 25 V
TA = 25°C
O
O
∆V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
8.0
Figure 7. Current Sense Input Threshold
versus Error Amp Output Voltage
ISC , REFERENCE SHORT CIRCUIT CURRENT (mA)
∆ Vref , REFERENCE VOLTAGE CHANGE (mV)
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
2.0
4.0
6.0
VO, ERROR AMP OUTPUT VOLTAGE (VO)
2.0 ms/DIV
2.0 ms/DIV
Figure 10. Reference Load Regulation
Figure 11. Reference Line Regulation
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6
125
0
TA = 25°C
−2.0
Source Saturation
(Load to Ground)
VCC = 15 V
80 s Pulsed Load
120 Hz Rate
VCC = 15 V
CL = 1.0 nF
TA = 25°C
90
%
TA = −55°C
3.0
TA = −55°C
2.0
TA = 25°C
Sink Saturation
(Load to VCC)
GND
800
200
400
600
IO, OUTPUT LOAD CURRENT (mA)
50 ns/DIV
Figure 12. Output Saturation Voltage
versus Load Current
Figure 13. Output Waveform
25
20
15
5
0
0
UCX844B
10
UCX845B
100 mA/DIV
ICC, SUPPLY CURRENT
VCC = 30 V
CL = 15 pF
TA = 25°C
ICC, SUPPLY CURRENT (mA)
0
10
%
20 V/DIV
1.0
0
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄÄ
ÄÄÄÄ
ÄÄÄ
ÄÄÄÄÄ
VCC
−1.0
V O , OUTPUT VOLTAGE
Vsat , OUTPUT SATURATION VOLTAGE (V)
UC3844B, UC3845B, UC2844B, UC2845B
10
100 ns/DIV
Figure 14. Output Cross Conduction
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
ÄÄÄÄ
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25°C
20
30
VCC, SUPPLY VOLTAGE (V)
40
Figure 15. Supply Current versus Supply Voltage
PIN FUNCTION DESCRIPTION
Pin
8−Pin
14−Pin
Function
1
1
Compensation
2
3
Voltage
Feedback
3
5
Current Sense
4
7
RT/CT
The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor
RT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible.
GND
This pin is the combined control circuitry and power ground.
6
10
Output
7
12
VCC
This pin is the positive supply of the control IC.
8
14
Vref
This is the reference output. It provides charging current for capacitor C T through resistor RT.
8
Power
Ground
11
VC
9
GND
2,4,6,13
NC
5
Description
This pin is the Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin. The output switches at one−half the oscillator frequency.
This pin is a separate power ground return that is connected back to the power source. It is used
to reduce the effects of switching transient noise on the control circuitry.
The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source
connection, it can reduce the effects of switching transient noise on the control circuitry.
This pin is the control circuitry ground return and is connected back to the powersource ground.
No connection. These pins are not internally connected.
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UC3844B, UC3845B, UC2844B, UC2845B
OPERATING DESCRIPTION
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when Pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the load
is removed, or at the beginning of a soft−start interval
(Figures 21, 22). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
comparator’s 1.0 V clamp level:
The UC3844B, UC3845B series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off−Line and dc−dc converter
applications offering the designer a cost−effective solution
with minimal external components. A representative block
diagram is shown in Figure 16.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates an internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. An internal flip−flop has been incorporated in the
UCX844/5B which blanks the output off every other clock
cycle by holding one of the inputs of the NOR gate high. This
in combination with the CT discharge period yields output
deadtimes programmable from 50% to 70%. Figure 2 shows
RT versus Oscillator Frequency and Figure 3, Output
Deadtime versus Frequency, both for given values of CT.
Note that many values of RT and CT will give the same
oscillator frequency but only one combination will yield a
specific output deadtime at a given frequency. The oscillator
thresholds are temperature compensated to within ±6% at
50 kHz. Also, because of industry trends moving the
UC384X into higher and higher frequency applications, the
UC384XB is guaranteed to within ±10% at 250 kHz.
In many noise−sensitive applications it may be desirable
to frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 18. For reliable locking, the
free−running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi−unit
synchronization is shown in Figure 19. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved to realize output deadtimes of greater than 70%.
Rf(min) ≈
3.0 (1.0 V) + 1.4 V
= 8800 0.5 mA
Current Sense Comparator and PWM Latch
The UC3844B, UC3845B operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the peak inductor current on a
cycle−by−cycle basis. The Current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
ground−referenced sense resistor RS in series with the
source of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared to a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
Pin 1 where:
Ipk =
V(Pin 1) − 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) =
1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in order
to keep the power dissipation of RS to a reasonable level. A
simple method to adjust this voltage is shown in Figure 20. The
two external diodes are used to compensate the internal diodes,
yielding a constant clamp voltage over temperature. Erratic
operation due to noise pickup can result if there is an excessive
reduction of the Ipk(max) clamp voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability (refer to Figure 24).
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 6). The
non−inverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is −2.0 A which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provided for external
loop compensation (Figure 29). The output voltage is offset
by two diode drops (≈1.4 V) and divided by three before it
connects to the inverting input of the Current Sense
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8
UC3844B, UC3845B, UC2844B, UC2845B
VCC
VCC
7(12)
36V
Vref
Reference
Regulator
8(14)
R
2.5V
RT
Vin
VCC
UVLO
Internal
Bias
R
+
−
3.6V
+
−
(See
Text)
VC
7(11)
Vref
UVLO
Output
Q1
Oscillator
CT
4(7)
6(10)
+ 1.0mA
S
Voltage
Feedback
Input 2(3)
Output/
Compensation 1(1)
2R
Q
R
R
Error
Amplifier
Power Ground
PWM
Latch
Current Sense
Comparator
GND
5(8)
Current Sense Input
1.0V
3(5)
5(9)
Pin numbers adjacent to terminals are for the 8−pin dual−in−line package.
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
= Sink Only Positive True Logic
Figure 16. Representative Block Diagram
Capacitor CT
Latch Set"
Input
Output/
Compensation
Current Sense
Input
Latch Reset"
Input
Output
Small RT/Large CT
Large RT/Small CT
Figure 17. Timing Diagram
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9
RS
UC3844B, UC3845B, UC2844B, UC2845B
Undervoltage Lockout
designer added flexibility in tailoring the drive voltage
independent of VCC. A Zener clamp is typically connected
to this input when driving power MOSFETs in systems
where VCC is greater than 20 V. Figure 23 shows proper
power and control ground connections in a current−sensing
power MOSFET application.
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX844B,
and 8.4 V/7.6 V for the UCX845B. The Vref comparator
upper and lower thresholds are 3.6 V/3.4 V. The large
hysteresis and low startup current of the UCX844B makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 30). The UCX845B is intended for lower voltage
dc−dc converter applications. A 36 V Zener is connected as
a shunt regulator from VCC to ground. Its purpose is to
protect the IC from excessive voltage that can occur during
system startup. The minimum operating voltage for the
UCX844B is 11 V and 8.2 V for the UCX845B.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has
short−circuit protection and is capable of providing in
excess of 20 mA for powering additional control system
circuitry.
Design Considerations
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse−width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 F) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise−generating components.
Output
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pulldown resistor.
The SOIC−14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. The separate VC supply input allows the
Vref
8(14)
8(14)
R
R
RA
Bias
RT
Bias
R
8
RB
5.0k
6
R
4
3
Osc
CT
4(7)
0.01
External
Sync
Input
Osc
+
5
2R
47
2(3)
EA
5.0k
2
R
5.0k
C
R
Q
S
MC1455
4(7)
+
7
2R
2(3)
EA
R
1
1(1)
1(1)
5(9)
To Additional
UCX84XBs
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of CT to go more than 300 mV below ground.
f Figure 18. External Clock Synchronization
1.44
(RA 2RB)C
RA
D(max) RA 2RB
Figure 19. External Duty Cycle Clamp and
Multi−Unit Synchronization
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10
5(9)
UC3844B, UC3845B, UC2844B, UC2845B
VCC
Vin
7(12)
5.0V Ref
8(14)
5.0V Ref
8(14)
R
Bias
+
−
Bias
R
R
+
−
7(11)
+
−
Osc
Q1
4(7)
Osc
4(7)
T
VClamp
+
R2
R
6(10)
2(3)
Q
Q
R
2R
R
EA
2(3)
1.0V
1(1)
3(5)
1(1)
RS
C
1.67
RR21 1 + 0.33x10
−3
5(9)
tSoft−Start ≈ 3600C in F
5(9)
VClamp ≈
EA
1.0M
5(8)
R
2R
R
Comp/Latch
1.0V
R1
S
1.0mA
S
1.0 mA
T
+
R1R1R2R2 Where: 0 ≤ VClamp ≤ 1.0 V
V
Ipk(max) Clamp
RS
Figure 20. Adjustable Reduction of Clamp Level
VCC
Figure 21. Soft−Start Circuit
Vin
VCC
Vin
VPin5 (12)
7(12)
RSIpkrDS(on)
rDM(on) RS
If: SENSEFET = MTP10N10M
RS = 200
5.0V Ref
5.0V Ref
8(14)
R
Bias
R
7(11)
+
−
+
S
G
Q1
T
VClamp
T
6(10)
2(3)
1.0V
R2
1.67
RR21 1
RS
1/4 W
Power Ground:
To Input Source
Return
Control Circuitry Ground:
To Pin (9)
Where: 0 ≤ VClamp ≤ 1.0 V
tSoft-Start In 1 VC
C R1R2
R1 R2
3VClamp
(8)
(5)
RS
5(9)
MPSA63
M
Comp/Latch
Comp/Latch
3(5)
VClamp ≈
R
5(8)
1(1)
R1
(10)
Q
Q
R
2R
R
EA
K
S
S
1.0 mA
D SENSEFET
(11)
+
−
Osc
4(7)
Then : VPin5 0.075Ipk
+
−
+
−
Virtually lossless current sensing can be achieved with the implementation
of a SENSEFET power switch. For proper operation during over−current
conditions, a reduction of the Ipk(max) clamp level must be implemented.
Refer to Figures 20 and 22.
V
Ipk(max) Clamp
RS
Figure 23. Current Sensing Power MOSFET
Figure 22. Adjustable Buffered Reduction of
Clamp Level with Soft−Start
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11
UC3844B, UC3845B, UC2844B, UC2845B
VCC
Vin
7(12)
5.0V Ref
+
−
7(11)
+
−
Q1
T
The addition of the RC filter will eliminate
instability caused by the leading edge spike
on the current waveform.
6(10)
S
5(8)
Q
R
3(5)
Comp/Latch
R
C
RS
Figure 24. Current Waveform Spike Suppression
Vin
VCC
IB
7(12)
+
Vin
0
5.0V Ref
−
+
−
Base Charge
Removal
C1
7(11)
+
−
Rg
Q1
Q1
6(10)
T
6(10)
S
Q
R
5(8)
5(8)
Comp/Latch
3(5)
3(5)
RS
RS
Series gate resistor Rg will damp any high frequency
parasitic oscillations caused by the MOSFET input
capacitance and any series wiring inductance in the
gate−source circuit.
The totem pole output can furnish negative base current
for enhanced transistor turn−off, with the addition of
capacitor C1.
Figure 25. MOSFET Parasitic Oscillations
Figure 26. Bipolar Transistor Drive
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12
UC3844B, UC3845B, UC2844B, UC2845B
Vin
VCC
7(12)
Isolation
Boundary
5.0V Ref
+
−
VGS Waveforms
+
−
7(11)
+
Q1
+
0
0
−
−
T
50% DC
6(10)
S
5(8)
Q
V(Pin1) − 1.4
Ipk =
R
3 RS
R
3(5)
Comp/Latch
C
RS
NS
25% DC
NNSp
NP
Figure 27. Isolated MOSFET Drive
8(14)
R
Bias
R
Osc
4(7)
+
1.0 mA
2(3)
2R
R
EA
1(1)
MCR
101
2N
3905
5(9)
2N
3903
The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The
simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.
Figure 28. Latched Shutdown
2.5V
From VO
Rd
+
1.0mA
Ri
2(3)
Cf
Rf
EA
2.5V
From VO
+
2R
Rp
R
Cp
Ri
Rd
Cf
1(1)
Rf ≥ 8.8k
1.0mA 2R
2(3)
Rf
EA
R
1(1)
5(9)
5(9)
Error Amp compensation circuit for stabilizing any current mode topology except
for boost and flyback converters operating with continuous inductor current.
Error Amp compensation circuit for stabilizing current mode boost
and flyback topologies operating with continuous inductor current.
Figure 29. Error Amplifier Compensation
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13
UC3844B, UC3845B, UC2844B, UC2845B
L1
MBR1635
4.7
+
MDA
202
4.7k
250
3300
pF
56k
115 Vac
T1
2200
+
1000
+
5.0V RTN
MUR110
1N4935
1N4935
+ 68
7(12)
+
5.0V Ref
8(14)
R
4(7)
T
+
6(10)
EA
150k
1N4937
MTP
4N50
1N5819
5(8)
1.0k
Comp/Latch
3(5)
1(1)
470pF
0.5
5(9)
T1 − Primary: 45 Turns #26 AWG
Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound
Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound
Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound
Core: Ferroxcube EC35−3C8
Bobbin: Ferroxcube EC35PCB1
Gap: ≈ 0.10" for a primary inductance of 1.0 mH
L1 − 15 H at 5.0 A, Coilcraft Z7156
L2, L3 − 25 H at 5.0 A, Coilcraft Z7157
Figure 30. 7 W Off−Line Flyback Regulator
Test
Conditions
Results
Vin = 95 Vac to 130 Vac
= 50 mV or ±0.5%
= 24 mV or ±0.1%
Load Regulation: 5.0 V
±12 V
Vin = 115 Vac, Iout = 1.0 A to 4.0 A
Vin = 115 Vac, Iout = 100 mA to 300 mA
= 300 mV or ±3.0%
= 60 mV or ±0.25%
Output Ripple:
Vin = 115 Vac
40 mVpp
80 mVpp
Vin = 115 Vac
70%
Line Regulation:
Efficiency
5.0 V
±12 V
5.0 V
±12 V
All outputs are at nominal load currents unless otherwise noted.
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14
+
12V/0.3A
+
−12V/0.3A
L3
Q
R
4.7k
680pF 2.7k
22
2(3)
100
pF
10
7(11)
+
−
S
18k
+
MUR110
Osc
1.0nF
1000
Bias
33k
10
±12V RTN
1N4937
+
−
R
+ L2
47
100
0.01
1000
5.0V/4.0A
UC3844B, UC3845B, UC2844B, UC2845B
Output Load Regulation
(Open Loop Configuration)
Vin = 15V
7(12)
UC3845B
+
IO (mA)
VO (V)
0
2
9
18
36
29.9
28.8
28.3
27.4
24.4
47
34V
8(14)
10k
Reference
Regulator
2.5V
VCC
UVLO
R
Internal
Bias
R
+
−
3.6V
+
−
1N5819
7(11)
Vref
UVLO
6(10)
15
10
Osc
4(7)
1.0nF
0.5mA
2(3)
S
2R
R
PWM
Latch
1.0V
R2
47
3(5)
Current Sense
Comparator
1(1)
+
Connect to
Pin 2 for
closed loop
operation.
5(8)
Q
R
Error
Amplifier
VO ≈ 2 (Vin)
+
T
+
1N5819
R1
R2
1
R1
VO = 2.5
5(9)
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor
may be required when using tantalum or other low ESR capacitors. The converter’s output can provide excellent line
and load regulation by connecting the R2/R1 resistor divider as shown.
Figure 31. Step−Up Charge Pump Converter
Vin = 15V
UC3845B
7(12)
Output Load Regulation
+
IO (mA)
VO (V)
0
2
9
18
32
−14.4
−13.2
−12.5
−11.7
−10.6
47
34V
8(14)
10k
Reference
Regulator
2.5V
R
VCC
UVLO
Internal
Bias
R
+
−
3.6V
+
−
Vref
UVLO
7(11)
6(10)
15
10
1N5819
VO ≈ −Vin
Osc
1.0nF
4(7)
T
+
0.5mA
2(3)
R
5(8)
Q
R
Error
Amplifier
1N5819
S
2R
1.0V
PWM
Latch
3(5)
Current Sense
Comparator
1(1)
5(9)
The capacitor’s equivalent series resistance must limit the Drive Output current to 1.0 A.
An additional series resistor may be required when using tantalum or other low ESR capacitors.
Figure 32. Voltage−Inverting Charge Pump Converter
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15
+
47
UC3844B, UC3845B, UC2844B, UC2845B
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
8
UC384xBN
AWL
YYWW
1
8
8
8
UC3844BVN
AWL
YYWW
UC3845BVN
FAWL
YYWW
1
1
UC2844BN
FAWL
YYWW
1
SOIC−8
D1 SUFFIX
CASE 751
8
8
384xB
ALYW
8
384xB
ALYWV
1
1
284xB
ALYW
1
SOIC−14
D SUFFIX
CASE 751A
14
14
UC384xBD
AWLYWW
1
14
UC384xBVD
AWLYWW
1
UC284xBD
AWLYWW
1
x
F
A
WL, L
YY, Y
WW, W
= 4 or 5
= Wafer Fab
= Assembly Location
= Wafer Lot
= Year
= Work Week
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16
UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
N
SEATING
PLANE
D
H
M
K
G
0.13 (0.005)
M
T A
M
B
M
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17
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10
0.030
0.040
UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
K
−Y−
G
C
N
X 45 DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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18
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 8 0.010
0.020
0.228
0.244
UC3844B, UC3845B, UC2844B, UC2845B
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
B
M
7
1
G
F
R X 45 C
−T−
SEATING
PLANE
0.25 (0.010)
M
T B
J
M
K
D 14 PL
S
A
S
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19
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
7
0.228 0.244
0.010 0.019
UC3844B, UC3845B, UC2844B, UC2845B
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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