TI UCC28231PWR

UCC28230
UCC28231
www.ti.com ................................................................................................................................................... SLUS814A – FEBRUARY 2008 – REVISED JUNE 2008
Advanced PWM Controller for Bus Converters
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable, Load Depended Off Time
Control
Frequency Controlled Start Up Allows Small
Output Inductor, Low Ripple and Constant
Current Start with Large Output Capacitor
Two 0.2-A Push-Pull Outputs Provide Matched
Control Signals D to External Drivers
Two Additional 1- D Outputs for Optimal Use
of Self-Driven or Control Driven Synchronous
Rectifiers
Unregulated, Fixed Volt-Second or Fixed
Frequency Modes set by User
Two, 1.5% Overall Accuracy Reference Voltage
Options: 5-V for UCC28230 and 3.3-V for
UCC28231
Resistor Programmable Switching Frequency
up to 1 MHz
Cycle-by-Cycle Current Limit Allows Parallel
Operation with Droop Based Current Sharing
Single External Capacitor sets Soft-Start and
Over Current Hiccup Mode Parameters with
Restart
Severe Short Circuit Hiccup with Restart or
Latch Off Protection Option by External
Resistor
Input Under Voltage Lock Out
Thermal Shutdown
Thermally Enhanced 3 mm × 2 mm SON-12
and TSSOP-14 Package Options
APPLICATIONS
•
•
Intermediate Bus Isolated Converters
DC-to-DC Transformers
DESCRIPTION
The UCC28230, UCC28231 PWM bus controllers are
optimized for use in high efficiency, high power
density, unregulated intermediate bus converters.
Topologies include push-pull, half-bridge and
full-bridge. External drivers, such as the UCC27200
120-V high-side/low-side drivers, can be used with
this controller.
Low cost, small size and highly efficient solutions are
provided by innovations such as:
• Start-up frequency control circuit allowing small
output inductor and the ability to start with large
intermediate bus capacitor.
• Load depended off-time control set by user.
Additional 1-D control outputs can be used for
primary winding clamping in self-driven output
synchronous rectifier applications or as drive signals
for the control-driven synchronous rectifier.
Cycle-by-cycle current limit prevents overstresses of
converter. If the over current condition causes less
than 80% duty cycle at the output, then after a
programmed time the controller proceeds into
periodical shutdown and restart hiccup mode.
The UCC28230 provides 5 V, and the UCC28231
provides 3.3-V precision reference voltages with 1.5%
overall accuracy and 10-mA output current. This
reference voltage can be used to supply
housekeeping circuit and/or microcontroller. The
precision reference voltage can also be used for
accurate setting of system parameters.
Other features include under-voltage lockout, thermal
shut down, programmable soft start, over-current
hiccup mode and short circuit protection with internal
restart by default that can be set into latch-off mode
by an external resistor.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
UCC28230
UCC28231
SLUS814A – FEBRUARY 2008 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com
TYPICAL APPLICATION DIAGRAMS
+
Vbias
UCC 27200
Vbias
UCC 27200
VDD
VDD
HB
HB
Vin
36 V to60V
HI
CT
HO
LI
HI
HO
HS
HS
LO
LO
LI
VSS
VSS
_
+
Vout
7 V to12 V
400W
_
Bias
Power
Supply
Vbias
VDD
VDD
UVLO
Comp.
VDD
Thermal
Shutdown
12
Interface
with
System
OS
Off Time
Control
Circuit
3
R3
R2
2
OST
CS
O1_ DIN
10
Short Circuit
Shutdown
O2_ DIN
8
6
Is
4
11
O2_D
Oscillator &
Start Up
Frequency
Control
RT
O1_D
Logic
Block
Cycle by
- Cycle Current
Limit
Vin
Reference
Generator
5V/3.3V
LDO
1
R1
Housekeeping
Micro
Controller
VDD
6.3 V rise
5.7 V fall
VREF
Vcc =5 V or 3.3V
EN
9
CLK
Soft Start &
Hiccup Current
Limit Circuit
GND
7
5
SS
Figure 1. Full-Bridge Bus Converter
+
UCC 27200
Vbias
VDD
HB
Vin
36V to 60V
CT
HO
HI
HS
LI
LO
VSS
+
_
Vout
7V to 12V
200W
Bias
Power
Supply
_
Vbias
UCC28230/1
VDD
V DD
UVLO
Comp.
12
Vcc =5V or 3.3V
Interface
with
System
EN
6.3 V rise
5.7 V fall
VREF
OS
Off Time
Control
Circuit
3
R3
Houskeeping
MicroController
R2
2
OST
CS
VDD
VDD
6
Short Circuit
Shutdown
O2_ DIN
Is
4
2
7
4
5
OUTB
INB
3
Logic
Block
Cycle by
- Cycle Current
Limit
RT
OUTA
INA
10
8
6
Vin
Reference
Generator
O1_ DIN
5V/3.3V
LDO
1
R1
Vbias
VDD
Thermal
Shutdown
Oscillator &
Start Up
Frequency
Control
O1_D
GND
11
UCC27324
O2_D
9
CLK
Soft Start &
Hiccup Current
Limit Circuit
GND
7
5
SS
Figure 2. Half-Bridge Bus Converter with Control-Driven Synchronous Rectifier
2
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PINOUT CONFIGURATION
ORDERING INFORMATION (1)
TEMPERATURE RANGE,
TA = TJ
REFERENCE VOLTAGE
TAPE and REEL QTY
.250
UCC28230DRNT
5V
3000
UCC28230DRNR
Plastic 12-pin SON (DRN)
250
UCC28231DRNT
3.3 V
3000
UCC28231DRNR
5V
250
UCC28230PW
2000
UCC28230PWR
5V
3.3 V
Plastic 14-pin TSSOP (PW)
3.3 V
(1)
(2)
PART NUMBER
5V
3.3 V
–55°C to +125°C
PACKAGE
(2)
250
UCC28231PW
2000
UCC28231PWR
The 12-pin SON (DRN) and 14-pin TSSOP packages use Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at
255-260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
The pad underneath the center of the IC is a thermal substrate. The PCB “thermal land” design for this exposed die pad should include
thermal vias that drop down and connect to one or more buried copper plane(s). This combination of vias for vertical heat escape and
buried planes for heat spreading allows the DRN to achieve its full thermal potential. This pad is also internally connected to GND pin.
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UCC28230
UCC28231
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range
(1) (2)
(unless otherwise noted)
PARAMETER
VDD (3)
VALUE
Input supply voltage range
O1_D, O2_D, O1_DIN, O2_DIN
HBM
CDM
UNIT
–0.3 to 20.0
–0.3 to VDD +0.3
Inputs voltages on OS, CS, SS, RT, OST
–0.3 to 6.3
Output voltage on VREF
–0.3 to 5.6
V
2k
ESD rating
500
Continuous total power dissipation
See Dissipation Rating Table
TJ
Operating virtual junction temperature range
–55 to +150
TA
Operating ambient temperature range
–55 to +125
Tstg
Storage Temperature
–65 to +150
Lead Temperature (Soldering, 10 sec.) PW Package
(1)
(2)
(3)
°C
+300
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
DISSIPATION RATINGS (1)
BOARD
PACKAGE
High-K (2)
DRN
θJC (°C/W)
JUNCTION TO
CASE
PW
(1)
(2)
2.71
θJA (°C/W)
JUNCTION TO
AMBIENT
θJP (°C/W)
JUNCTION TO PAD
θJB (°C/W)
JUNCTION TO
BOARD
70.66
15
37.66
97.65
2.07
These thermal data are taken at standard JEDEC test conditions and are useful for the thermal performance comparison of different
packages. The cooling condition and thermal impedance RθJA of practical design is specific.
The JEDEC test board JESD51-5 with direct thermal pad attach, 3-inch × 3-inch, 4-layer with 1-oz internal power and ground planes and
2-oz top and bottom trace layers (preliminary data based on modeling)
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
Supply voltage range
Operating junction temperature range
4
NOM
7
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–55
12
MAX
UNIT
17
V
125
°C
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): UCC28230 UCC28231
UCC28230
UCC28231
www.ti.com ................................................................................................................................................... SLUS814A – FEBRUARY 2008 – REVISED JUNE 2008
ELECTRICAL CHARACTERISTICS (1)
VDD = 12V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = –55°C to 125°C, RT = 49.9 kΩ connected to 4.4V supply to
set Fsw = 100 kHz (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Currents
IDDD(off)
Startup current
IDD
Operating supply current
VDD = 5.2 V
150
200
µA
1.5
2.5
mA
6.9
Under Voltage Lockout
Start threshold
5.9
6.3
Minimum operating voltage after start
5.3
5.7
6.2
0.55
0.6
0.75
Hysteresis
V
Soft Start (SS PIN, Figure 41, Figure 44)
ISS
Charge current
VSS_STD
Shutdown/restart/reset threshold
VSS_FP
Soft-start first pulse threshold
VSS_PU
Pull up threshold
VSS_CL
Clamp voltage
VSS = 0 V
–30
–25
–20
0.3
0.55
0.68
0.68
0.85
1.1
3.3
3.5
3.8
4.3
4.5
4.8
µA
V
Off-Time Programming (Figure 33)
TOFF5
Off time between O1_D and O2_D
UCC28230
32
40
50
TOFF3
Off time between O1_D and O2_D
UCC28231
30
40
53
TDT
Dead time between O1_D, O1_DIN and O2_D, O2_DIN
10
16
ΔTOFF
Off time matching
TOFFR5
Off time between O1_D and O2_D
UCC28230
32
40
50
TOFFR3
Off time between O1_D and O2_D
UCC28231
30
40
53
TDTREF
Dead time between O1_D, O1_DIN and O2_D, O2_DIN
10
16
ΔTOFFR
Off time matching
IHYST
Hysteresis current source
TOFFMAX
Maximum off time at low CS
OS = 8.45 kΩ, CS = 0.3 V, OST = 1 V
2
OS = 8.45 kΩ, CS = 0 V, OST = VREF
ns
2
µA
10
OS = 8.45 kΩ, OST = 1 V, CS = CSTH– 0.03
V
165
235
ns
Switching Frequency at O1_D and O2_D Outputs
FSWNOM
Nominal frequency
VSS = 4 V
FSWMAX
Maximum frequency
VSS = 1.8 V
92
100
108
425
550
675
4.925
5
5.075
3.25
3.3
3.35
–35
–25
–12
kHz
VREF Output Voltage
VREF5
VREF3
ISCC
(1)
VREF total output range
Short circuit current
UCC28230
UCC28231
0 ≤ IR ≤ 10 mA; VDD = from 7 V to 17 V,
–55°C ≤ TJ ≤ 125°C
VREF = 0 V
V
mA
Typical values for TA = 25°C
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 12V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = –55°C to 125°C, RT = 49.9 kΩ connected to 4.4V supply to
set Fsw = 100 kHz (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.515
V
Current Sense, Cycle-by-Cycle Current Limit With Hiccup, Short Circuit Protection With Latch Off
VCS_LIM
CS pin cycle-by-cycle threshold
0.48
0.5
TCS
CS to O1_D and O2_D propagation delay
Input pulse at CS from 0.3 V to 0.6 V with
0.03 V/ns slew rate
TBL
Leading edge blanking time by internal filter
Input pulse at CS from 0.3 V to 0.6 V with
0.03 V/ns slew rate
IDS
Discharge current to set cycle-by-cycle current limit duration
CS = 0.6 V, VSS = 4 V
(Figure 41)
15
20
25
µA
Hiccup OFF time threshold
3.1
3.4
3.7
V
IHCC
Discharge current to set Hiccup Mode OFF Time
(Figure 41, Figure 44)
1.9
2.5
3.1
µA
VCS_SC
CS pin short circuit protection threshold (Figure 44)
0.65
0.7
0.75
V
100
50
ns
Outputs O1_D, O2_D, O1_DIN, O2_DIN
Sink/Source peak current (2)
0.2
A
Rise time
CLOAD = 100 pF
12
25
Fall time
CLOAD = 100 pF
10
25
RSRC
Output source resistance
IOUT = 20 mA
10
20
35
RSINK
Output sink resistance
IOUT = 20 mA
5
15
30
Duty cycle matching
Pins 7 and 9 pulses matching at FSW = 100
kHz
35
ns
Ω
ns
Thermal Shutdown
Rising threshold (3)
150
160
170
Falling threshold (3)
130
140
150
Hysteresis
(2)
(3)
6
°C
20
Output sink/source peak current value, defined by equation IP = 100 pF × dV/dt where dV/dt is taken from the output rise and fall
switching waveforms. It is not tested in production. Characterization is available upon request.
Thermal shutdown is not tested in production. Characterization is available upon request
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FUNCTIONAL BLOCK DIAGRAMS
VDD
Thermal
Shutdown
UVLO
Comp.
VDD
VDD
12
EN
VDD
6.3V rise
5.7V fall
VREF
5V/3.3V
LDO
1
OS
R1
Off Time
Control
Circuit
3
R3
2
R2
Reference
Generator
OST
CS
O1_DIN
10
Short Circuit
Shutdown
O2_DIN
8
Is
6
CT
Oscillator &
Start Up
Frequency
Control
Vin RT
4
O1_D
Logic
Block
Cycle-byCycle Current
Limit
11
O2_D
9
CLK
Soft Start &
Hiccup Current
Limit Circuit
GND
7
5
SS
Figure 3. SON-12 Package
VDD
VDD
VDD
Thermal
Shutdown
UVLO
Comp.
14
EN
VDD
6.3V rise
5.7V fall
VREF
5V/3.3V
LDO
1
R1
OS
R3
R2
Off Time
Control
Circuit
3
2
OST
CS
Reference
Generator
O1_DIN
12
Short Circuit
Shutdown
O2_DIN
10
7
CT
Is
Logic
Block
Cycle-byCycle Current
Limit
NC
O2_D
4
Vin RT
5
AGND
Oscillator &
Start Up
Frequency
Control
O1_D
13
11
CLK
Soft Start &
Hiccup Current
Limit Circuit
GND
9
8
6
SS
Figure 4. TSSOP-14 Package
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TERMINAL FUNCTIONS
TERMINAL
DFN-12 TSSOP-14
PIN#
PIN#
8
NAME
I/O
FUNCTION
1
1
VREF
O
±1.5% accurate 5 V for UCC28230 and 3.3 V for UCC28231, 10-mA output reference voltage with
short circuit protection that can be used for fixed switching frequency setting and/or for
housekeeping microcontroller. Place decoupling capacitor in 1 µF to 2.2 µF range from this pin to
GND.
2
2
OST
I
Off time control threshold pin uses a resistor divider to set current level as percentage of current
limit threshold.
3
3
OS
I
Nominal off time TOFF and dead time TDT set pin. An external resistor connected between this pin
and GND sets the dead time and nominal off time.
4
NC
4
5
RT
5
6
SS
6
7
CS
8
AGND
Not connected pin, TSSOP-14 only.
I
Oscillator timing input pin. The external resistor which is connected between this pin and VIN sets
the oscillator frequency which varies with VIN. Tying the external resistor to VREF sets fixed
frequency operation independent of VIN.
Input to adjustable soft-start,and hiccup mode circuit. Place soft-start capacitor from this pin to
I/O GND. The internal charge/discharge current ISS and an external capacitor value set the soft-start
timing, duration of cycle-by-cycle current limit and controller turn-off time for hiccup mode operation.
I
Current sensing pin used for cycle-by-cycle current limit, short circuit protection and off time control.
Analog ground, TSSOP-14 only.
7
9
GND
8
10
O2_DIN
O
Ground pin connected to thermal pad. All signals are referenced to this node.
0.2-A sink/source switching output pin to an external driver providing 1-D pulse.
9
11
O2_D
O
0.2-A sink/source switching output pin to an external driver providing D pulse.
10
12
O1_DIN
O
0.2-A sink/source switching output pin to an external driver providing 1-D pulse.
11
13
O1_D
O
0.2-A sink/source switching output pin to an external driver providing D pulse.
12
14
VDD
I
Connect this pin to a 7-V to 17-V bias supply. Place a high quality at least 1-µF ceramic bypass
capacitor from this pin to GND.
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TYPICAL CHARACTERISTICS
Start-up Current IDDoff
Operating Supply Current IDD
over Temperature at VDD=5.2V
over Temperature at FSW=100kHz
1.60
165
160
1.55
I DD, mA
IDDoff,, µA
155
150
1.50
145
1.45
140
135
-55
-35
-15
5
25
45
65
85
105
1.40
-55
125
-35
-15
5
25
45
65
85
105
125
85
105
125
TJ-temperature, °C
TJ-temperature, °C
Figure 5.
Figure 6.
Under Voltage Lockout Hysteresis
over Temperature
Under Voltage Lockout Thresholds
over Temperature
0.70
6.7
0.68
6.3
UVLO Hysteresis, V
UVLO Thresholds, V
6.5
6.1
5.9
5.7
5.5
5.3
-55
-35
-15
5
25
45
65
85
105
125
0.64
0.62
-55
TJ-temperature, °C
Rising threshold
0.66
-35
-15
5
25
45
65
TJ-temperature, °C
Falling threshold
Figure 7.
Figure 8.
Soft Start Shutdown VSS_STD and First Pulse VSS_FP
Thresholds over Temperature
Soft Start Pull-up VSS_PU and Clamp Voltage VSS_CL
Thresholds over Temperature
1.00
5.00
V SS_PU , V SS_CL , V
V SS_STD , V SS_FP , V
0.90
0.80
0.70
0.60
0.50
4.50
4.00
3.50
0.40
0.30
-55
-35
-15
5
25
45
65
85
105
125
3.00
-55
-35
5
25
45
65
85
105
125
TJ-temperature, °C
TJ-temperature, °C
Soft Start Shutdown
-15
First Pulse Threshold
Figure 9.
Pull-up Threshold
Clamp Voltage
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
Off Time Matching ∆TOFF
Soft-Start Charge Current ISS
over Temperature
over Temperature
25.20
4.00
25.15
25.10
3.50
25.00
3.00
∆TOFF , ns
Iss, µA
25.05
24.95
24.90
24.85
24.80
-55
-35
-15
5
25
45
65
85
105
2.50
2.00
125
TJ-temperature, °C
1.50
1.00
-55
-35
-15
5
25
45
65
85
105
125
TJ - temperature, °C
Figure 11.
Figure 12.
UCC28231 Off Time T OFF and Dead Time T DT
over Temperature
UCC28230 Off Time TOFF and Dead Time TDT
over Temperature
50
50
40
TOFF , TDT , ns
TOFF , T DT , ns
40
30
30
20
20
10
-55
-35
-15
5
25
45
65
85
105
10
-55
125
-35
-15
Off Time
5
25
45
65
85
105
125
105
125
TJ - temperature, °C
TJ - temperature, °C
Dead Time
Off Time
Figure 13.
Dead Time
Figure 14.
Maximum Off Time TOFFMAX at Low VCS
over Temperature
Nominal Switching Frequency FSWNOM
over Temperature
220.00
101.00
210.00
F SWNOM , kHz
TOFFMAX , ns
100.50
200.00
190.00
99.50
180.00
170.00
-55
10
100.00
-35
-15
5
25
45
65
85
105
125
99.00
-55
-35
-15
5
25
45
65
TJ - temperature, °C
TJ - temperature, °C
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
Cycle-by-Cycle Current Limit Threshold
over Temperature
Maximum Switching Frequency FSWMAX
over Temperature
0.55
550.00
0.53
V CS_LIM , V
F SWMAX , kHz
540.00
530.00
520.00
0.51
0.49
0.47
510.00
500.00
-55
-35
-15
5
25
45
65
85
105
0.45
-55
125
-35
-15
5
25
TJ - temperature, °C
45
65
85
105
125
TJ-temperature, °C
Figure 17.
Figure 18.
UCC28231 Reference Voltage at V DD=12V
over Tem perature and Load Current
UCC28230 Reference Voltage at V DD=12V
over Tem perature and Load Current
5. 015
3. 305
VREF, V
VREF, V
5. 005
4. 995
3. 295
3. 285
4. 985
3. 275
4. 975
-55
-35
-15
5
25
45
65
85
105
-55
125
-35
-15
Iload=1mA
Iload=10mA
Iload=10uA
45
65
85
Iload=1mA
Figure 19.
105
125
Iload=10mA
Figure 20.
UCC28230 Reference Voltage at ILOAD=1m A
over Tem perature and Supply Voltage V DD
UCC28231 Reference Voltage at ILOAD=1m A
over Tem perature and Supply Voltage V DD
3. 306
5.006
3. 302
VREF, V
5.002
VREF, V
25
TJ - tem perature, °C
TJ - tem perature, °C
Iload=10uA
5
4.998
3. 298
3. 294
4.994
4.990
3. 290
-55
-35
-15
5
25
45
65
85
105
125
-55
-35
-15
Vdd=7V
Vdd=12V
5
25
45
65
85
105
125
TJ - tem perature, °C
TJ - tem perature, °C
Vdd=17V
Vdd=7V
Figure 21.
Vdd=12V
Vdd=17V
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
Output Source Resistance RSRC and Sink Resistance
Current Sense Propogation Delay TCS
RSINK over Temperature
over Temperature
30.0
115.00
25.0
R SCR , R SINK , O
TCS , ns
110.00
105.00
100.00
20.0
15.0
95.00
90.00
-55
10.0
-55
-35
-15
5
25
45
65
85
105
TJ - temperature, °C
12
-35
-15
125
5
25
45
65
85
105
125
TJ - temperature, °C
Source Resistance
Sink Resistance
Figure 23.
Figure 24.
Figure 25. O1_D and O2_D Duty Cycle Matching at VCS =
0.14 V and VOST = 1 V
Figure 26. O1_D and O2_D Duty cycle Matching at VCS =
0.0 V and VOST = 1 V
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TYPICAL CHARACTERISTICS (continued)
Figure 27. Output Waveforms During First Half Switching Cycle at VCS = 0.14 V and VOST = 1 V
Figure 28. Output Waveforms During Second Half Switching Cycle at VCS = 0.14 V and VOST = 1 V
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TYPICAL CHARACTERISTICS (continued)
Figure 29. Output Waveforms During First Half Switching Cycle at VCS = 0 V and VOST = 1 V
Figure 30. Output Waveforms During Second Half Switching Cycle at VCS = 0 V and VOST = 1 V
14
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DETAILED DESCRIPTION
Start-Up Protection Logic
Before the controller allows the start up, the following conditions must be met:
• VDD voltage exceeds rising UVLO threshold 6.3 V typical
• The reference voltage 5 V for UCC28230 or 3.3 V for UCC28231 is available
• Junction temperature is below the thermal shutdown threshold 130°C min
• The voltage at soft-start capacitor is not below 0.55 V typical
If all those conditions are met, an internal enable signal EN is generated that initiates the soft start process. The
duty cycle during the soft start is defined by the voltage at the SS pin or by cycle-by-cycle current limit circuit
depending on load conditions.
Internal Oscillator and Converter Switching Frequency
The oscillator frequency is set by an external resistor at RT pin (see Figure 3 and Figure 4). The oscillator
frequency FOSC is twice that of converter switching frequency FSW. The oscillator performs the following main
functions:
• Generates clock signal CLK to synchronize internal functional blocks
• By changing the switching frequency during the start up and cycle-by-cycle current limit, the oscillator limits
the current ripple at the output inductor allowing the use of small output inductor and start with large output
capacitor
Oscillator can operate in the following modes:
• Fixed volt-second mode of operation when the resistor RT is connected between VIN and RT pin. In this mode
the switching frequency increases in accordance to an input voltage rise
• Fixed switching frequency mode when the resistor RT is connected between VREF and RT pins.
The switching frequency of converter is defined as FSW(nom) = 1/TSW(nom) (see Figure 33). Equation 1 is used to
calculate the nominal switching frequency of the converter and its transformer.
FSW ( nom ) =
1
RT
+ 1.2 ´ TOFF
2500 ´ (VIN - 2.4 )
(1)
Where RT is in kΩ, VIN is in volts, TOFF is in ms and FSW(nom) is in kHz.
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In most applications, TOFF is set at about 40~50 ns, which can be neglected compared to the total oscillator
period. Therefore Equation 1 can be simplified as:
FSW ( nom ) = 2500 ´
(VIN - 2.4 )
RT
(2)
In this equation RT is in kΩ, VIN is in volts and FSW(nom) is in kHz.
Figure 31 shows how the nominal switching frequency of converter depends on value of resistor RT, and
Figure 32 shows how the switching frequency changes over the input voltage range in case of fixed volt-second
mode of operation. The TOFF is set to 40 ns for both figures.
800
1,000
900
700
(kHz)
700
Switching Frequency
Switching Frequency (kHz)
800
600
500
400
300
600
500
400
300
200
200
100
100
0
100
0
300
500
700
900
1100
36
40
44
Vin=36V
Vin=48V
48
52
56
60
Vin Voltage (V)
RT Resistance (kO)
Vin=60V
Figure 31. Nominal Switching Frequency of Converter vs
Resistor RT
RT=200kohm
RT=400kohm
RT=1,100kohm
Figure 32. Switching Frequency Variation Over the Input
Voltage for Fixed Volt-Second Mode of Operation
Fixed frequency mode of operation can be achieved by connecting the resistor RT between VREF and RT pins.
In such case the switching frequency is defined by the following Equation 3, where the impact of TOFF is
neglected as well.
FSW ( nom ) = 2500 ´
(VREF - 2.4 )
RT
(3)
In this equation the RT is in kΩ, VREF is in volts and FSW(nom) is in kHz.
16
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Output Signals
The UCC28230/1 has two push-pull outputs O1_D and O2_D that provide D pulse signals to external drivers.
The additional two outputs O1_DIN and O2_DIN provide 1-D output pulses with dead time between D and 1-D
pulses to avoid shoot-through currents. Such combination of outputs allows use of UCC28230/1 either with
self-driven synchronous rectifier, or with the control-driven synchronous rectifier in push-pull, half-bridge or
full-bridge configuration.
For the full-bridge self-driven rectifier configuration, outputs O1_D and O2_D control high-side MOSFETs while
outputs O1_DIN and O2_DIN control low-side MOSFETs thus shorting the primary winding during (1-D)
switching cycle. This avoids number of issues related to self-driven rectification such as start up disabling,
reverse current during parallel operation, tendency to oscillate during low duty cycles. The applications circuit for
this configuration is shown on Figure 1 and the output signal timing diagrams are shown in Figure 33.
TOFF
O1_D
O2_D
TOFF
TOFF
TOFF
TOUT_D
TDT
TDT
TSWNOM
O1_DIN
TDT
TDT
O2_DIN
TCLAMP
TCLAMP
TCLAMP
TCLAMP
Figure 33. D and (1-D) Output Pulses Providing Dead Time TDT in Each Leg and the Off Time TOFF
Between Upper FETs That Includes Some Overlapping Time TCLAMP.
In the steady state condition an unregulated bus converter operates at maximum duty cycle thus having
minimum overlapping TCLAMP of (1-D) outputs. During start up or cycle-by-cycle current limit, the duty cycle can
be very low, so (1-D) output pulses occupy most of the switching cycle time. This provides zero voltage clamping
of the transformer’s primary winding. The UCC28230/1 also includes an off-time control feature. This feature
allows user to increase off time TOFF when the converter output current is below a programmable current
threshold. This feature reduces switching losses of the synchronous rectifier at light load and it is described in
detail in Offtime Control Circuit section.
For the control driven half-bridge topology, the outputs O1_D and O2_D provide control pulses for the high-side
and low-side MOSFETs, while the outputs O1_DIN and O2_DIN can be used to drive the pulse transformers
providing control signals to the secondary-side MOSFET rectifiers as shown in Figure 2.
In case of full-bridge topology with the control-driven rectifier, the outputs O1_DIN and O2_DIN are used to
control primary low-side MOSFETs as well as the secondary-side rectifier MOSFETs.
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Start-Up Frequency Control Circuit
The start-up frequency control circuit addresses the need for bus converter to start at heavy load with a large
output capacitance. In the steady state condition bus converters operate with the minimum off time and as the
result, the output inductor current ripple is low. Therefore the output inductor value is able to be selected very low
to save the size and cost. During over current or soft start condition the duty cycle is controlled by the
cycle-by-cycle current limit circuit or by the voltage at soft-start capacitor. In this condition, the duty cycle D for
the output inductor can be anywhere between 0 and 1 causing significant output inductor current ripple that
reaches its maximum at duty cycle D = 0.5. The current limit circuit on primary side limits the peak current, not
the average current. The limiting of peak current with a large ripple causes the fold back characteristic of
converter output, which prevents the converter from ever reaching its nominal steady state output voltage.
The output inductor duty cycle is a ratio of output pulses TOUT_D at pins O1_D and O2_D to the half of switching
cycle TSW(nom), i.e. TOUT_D +TOFF (see Figure 33):
D=
TOUT _ D
TOUT _ D + TOFF
(4)
The start-up frequency control circuit changes the switching frequency during the start up or during the
cycle-by-cycle current limit to maintain the output inductor current ripple almost constant at any duty cycle D. This
allows an additional cost and size saving because the output inductor can be selected based on steady state
condition rather than the transient condition, which dictates significantly larger inductance value and size.
Examples of switching frequency changes over duty cycle variation for the selected nominal frequencies 100 kHz
and 450 kHz are shown in Figure 34. The plots are given for the nominal off time at 53 ns and 77 ns (right
column) and for no load off time at 196 ns, 209 ns accordingly. It is shown that the impact of nominal off time on
switching frequency is minimal. However the no load off time causes visible frequency reduction especially at
maximum frequency when the duty cycle D is around 0.5.
Switching Frequency Plots vs Duty Cycle for FSW(nom) Set at 100 kHz and 450 kHz at Different No Load and
Nominal TOFF Time Sets.
Fsw vs Duty Cycle, RT=1M tied to Vin,
Vost=1V, R3(OS)=15k, Toff=196ns, Vcs=0V
900
800
800
700
Fsw, kHz
900
700
Fsw,
Fsw vs Duty Cycle, RT=1M tied to Vin,
Vost=1V, R3(OS)=15k, Toff=53ns, Vcs=0.4V
600
500
600
500
400
300
200
400
100
300
0
200
0
10
20
30
100
40
50
60
70
80
90
100
Duty Cycle, %
0
Vin=48V
0
10
20
30
40
50
60
70
80
90
Vin=36V
Vin=72V
Vin=48V, RT=287K
100
Duty Cycle, %
Vin=48V
Vin=36V
Vin=72V
Vin=48V, RT=287K
Figure 34.
18
Figure 35.
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Fsw vs Duty Cycle at Lout, RT=1M tied to Vin,
Vost=1V, R3(OS)=30k, Toff=209ns, Vcs=0V
900
900
800
800
700
700
600
600
Fsw, kHz
Fsw, kHz
Fsw vs Duty Cycle, RT=1M tied to Vin,
Vost=1V, R3(OS)=30k, Toff=77ns, Vcs=0.4V
500
400
300
500
400
300
200
200
100
100
0
0
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
Duty Cycle, %
Vin=48V
Vin=36V
Vin=72V
40
50
60
70
80
90
100
Duty Cycle, %
Vin=48V, RT=287K
Vin=48V
Vin=36V
Figure 36.
Vin=72V
Vin=48V, RT=287K
Figure 37.
To avoid jittering during the fast duty cycle change and reduce sensitivity to noise, the transfer function of
switching frequency of the converter to the duty cycle has 20-kHz bandwidth well below the switching frequency.
The maximum switching frequency FSW(max) of converter is given by:
FSW ( m ax) @ FSW ( nom ) + 375 kHz
(5)
Where TOFF affect is neglected as well and the frequency is in kHz. TOFF has more affect on switching frequency
FSW at very high frequency. One can see how TOFF affects FSW(max) in Figure 34.
The relation between switching frequency FSW and duty cycle D in Figure 34 can be best described by:
FSW
ì
FSW ( nom )
D < 0.1 or D > 0.9
ï
0 .4 £ D £ 0 .6
Ȓ
FSW (max)
ïF
î SW (max) ´ D ´ ( 1 - D ) 0.1 £ D < 0.4 or 0.6 < D £ 0.9
(6)
Knowing the maximum switching frequency FSW(max) at D = 0.5 and the ratio of peak output inductor current to
the nominal load current KL = IL(max)/IO, allows calculate the output inductor value by using the following
Equation 7.
LO =
VIN ´ D ´ ( 1 - D )
NTR ´ 4 ´ FSW (max) ´ ( KL - 1) ´ IO
(7)
In this equation NTR is transformer turns ratio from primary winding to the secondary. The selection of KL
depends on the average output inductor current IL(ch) that needs to be provided during the start up to charge the
output capacitor and supply the load. To ensure that the converter starts the following condition needs to be met.
I L (m ax) £ 2 ´ I L ( ch )
(8)
How IL(ch) needs to be defined is described in the following section.
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Soft Start
The soft-start pin SS is multi-function pin used for the following operations:
• Soft start with the duty cycle graduate increase from zero to its maximum value of almost 100%
• Setting cycle-by-cycle over current hiccup mode conditions
• On/off control for the converter
• Indicator of severe short circuit condition
The soft-start duration is defined by an external capacitor connected between SS pin and ground and the internal
charge current that has typical value of 25 µA. During soft start, the duty cycle of controller is determined by the
voltage at SS pin. Below the 0.85-V threshold, there are no switching pulses at the outputs. Pulling the soft-start
pin externally below or above 0.55-V typical threshold can be used for the on/off control. When the soft-start
voltage is rising from 0.85 V up to 2.85 V and there is no current limit condition, the duty cycle applied to the
output inductor is increasing accordingly from 0 to 1. The external capacitor CSS value can be defined by the
Equation 9:
CSS =
TSS ´ 25 m A
( 2.85V - 0.85V )
(9)
For example, if the soft-start time TSS is selected 10 ms, then the soft-start capacitor CSS is equal to 125 nF and
the closest available standard value100 nF can be selected. Notice, that the output pulses do not appear until the
voltage at soft start capacitor reaches 0.85 V. An additional typical soft start delay caused by this can be
calculated by the Equation 10:
TDEL =
CSS ´ 0.85V
25 m A
(10)
For the CSS = 100 nF the calculated delay is 3.4 ms.
20
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The Equation 9 and Equation 10 use typical values for calculations. If the output capacitor of the bus converter is
large and the soft-start time is selected relatively short, then the converter should deliver large charge current to
the output capacitor to provide the required soft start time. This current might hit the current limit threshold and
the soft-start time can be longer than expected. Figure 38 provides an estimation of the required average charge
current from the converter to charge the output capacitor within predetermined soft-start time. To avoid tripping of
the current limit comparator, the current limit threshold should be set above the required average charge current
with the additional current required by the load, half of the output inductor current ripple and the magnetizing
current of the transformer. The average output inductor charge current IOUT during the cycle-by-cycle current limit
can be described by the following equation:
IOUT = IO(lim) -
NTR ´ VIN ´ D VIN ´ D ´ ( 1 - D )
4 ´ Lm ´ FSW 4 ´ NTR ´ LO ´ FSW
(11)
Here IO(lim) is the output current limit and Lm is magnetizing inductance. The IO(lim) is always less or equal to IL(max)
to avoid saturation of the output inductor. The output voltage VO over output current IOUT is as follows
VO =
(VIN - IOUT ´ RPR / NTR ) ´ D
- IOUT ´ RSEC
NTR
(12)
Where RPR is the equivalent resistance on primary side and RSEC is the equivalent resistance on secondary side.
3
Required primary current, A
1 .10
100
10
1
0.1
0.01
0.1
1
Soft start time, ms
10
Cout=100uF
Cout=1000uF
Cout=10000uF
Figure 38. Estimated Average Primary-Side Charge Current From the Converter Required to Charge the
Output Capacitor of Specified Value Within Required Soft-Start Time
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Figure 39 shows the output voltage as function of the average load current limited by the cycle-by-cycle current
limit threshold after substituting (9) into (10). These plots are generated for the following conditions: VIN = 48 V,
NTR = 5, LO= 0.1 µH, Lm = 75 µH, IO(lim) = 73 A, Rpr = 25 mΩ and RSEC = 4 mΩ at FSW= 100 kHz, 200 kHz and
400 kHz. This fold back type of behavior limits the start-up capability of unregulated IBC. One can see that at
100-kHz switching frequency and 0.5 duty cycle (i.e., VO ≈ 5 V), only about 11.5 A average current is available to
charge the output capacitor while at 400 kHz, the charge current can be as high as 60 A. The plots in Figure 39
show the required average charge current reflected to the primary side of the converter with NTR = 5:1 for
different output capacitor values depending on the selected soft-start time, which do not count extra current
drawn by the load itself. Therefore the significant output inductor current ripple not only can trip the peak current
mode control current limit circuit to reduce the average output inductor current available to charge the output
capacitor, but also can cause the hiccup or latch off of the converter to prevent it from starting at all. Increasing
the current limit threshold to allow the normal start up of the converter can cause potential overstress if for some
reason the load exceeds its nominal current during the steady state operation.
Without frequency control circuit, the module operates only at 100 kHz. At 100 kHz the secondary charge current
available is only 11.5 A, which is only 2.3 A if reflected to the primary side (NTR = 5). The 2.3-A current is able to
charge the 10000-µF output capacitor within 10 ms provided that there is no additional load current applied.
Cycle-by-cycle current limit
12
10
Vout, V
8
6
4
2
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Iout, A
100kHz
200kHz
400kHz
Vout Steady State (top)
Figure 39. Output Voltage at Cycle-by-Cycle Current Limit
22
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With the frequency control circuit, the start up switching frequency is 400 kHz. At 400-kHz, 60-A charge current is
available, which is 12 A if reflected to the primary side. Assuming as in previous case 2.3 A portion of this current
is used to charge the 10000-µF output capacitor within 10 ms, the remaining 9.7 A on primary side allows extra
48.5-A current to supply the load itself on the secondary side. Figure 40 shows a design example using the
startup frequency control of UCC28230 to start up with 30-A constant load current and 10900-µF output
capacitor.
Using SS pin and soft-start capacitor to set cycle-by-cycle over-current hiccup mode is described further in
Cycle-by-Cycle Current Limit section and Short Circuit Protection section.
Figure 40. Start up at 30-A Constant Current Load With CO = 10900 µF
Current Sensing
The current sensing pin CS is used for the following functional blocks:
• Cycle-by-cycle current limit
• Adjustable off-time control
• Short circuit protection
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Cycle-by-Cycle Current Limit and Short Circuit Protection
The cycle-by-cycle current limit provides peak current limit on primary side when the load current exceeds its
predetermined threshold. For peak current mode control, certain leading edge blanking time is needed to prevent
the controller from false tripping due to switching noise. In order to save external RC filter for the blanking time,
an internal 50-ns filter at CS input is provided. With the 50-ns delay from the input of the current sense
comparator to the outputs, the total propagation delay TCS from CS pin to outputs is about 100 ns. An external
RC filter is still needed if the power stage requires more blanking time. The 0.5-V ±3% cycle-by-cycle current limit
threshold is optimized for efficient current transformer based sensing. The duration when a converter operates at
cycle-by-cycle current limit depends on the value of soft-start capacitor and how severe is the over current
condition. The soft-start capacitor value also determines the so called hiccup mode off-time duration. These are
achieved by the internal discharge current IDS (Equation 13) and IHCC (see Figure 41) at SS pin.
I DS = (- 25 ´ (1 - D ) + 5 )m A
(13)
When the output inductor duty cycle D at cycle-by-cycle current limit is above 80%, the converter operates as the
current source and does not enter into hiccup mode at all. This allows parallel operation of converters using
droop current sharing technique. At more severe over current condition, the duty cycle D becomes lower and Ids
becomes large enough to initiate hiccup mode with periodical restart. The behaviour of the converter at different
modes and related soft-start capacitor charge/discharge currents are shown in Figure 41.
SS pin,
Volts
SS Clamp Voltage
Soft-Start
4.5
Normal
Operation
Cycle-byCycle I lim.
Off Time before restart
SoftRestart
25μA
Pull Up Thresh. 3.5
Dmax Thresh. 2.85
(for reference)
Iss=25μA
Fast Pull Up Ids=(-25x(1-D)+5)μA
by
1kΩ Switch
Ihcc=-2.5μA
Outp. Enbl. Thresh. 0.85
SS ShDn. Thresh. 0.55
0
Output Pulses, D
t
Figure 41. Timing Diagram of Soft-Start Voltage VSS at Different Modes of Operation Defined by Voltage
Thresholds and Related Soft-Start Capacitor Charge/Discharge Currents
The largest discharge current is at the duty cycle close to zero as 20 µA. This current sets the shortest operation
time during the cycle-by-cycle current limit which is defined as:
TCL( on ) =
CSS ´ (4.5V - 3.5V )
20 m A
(14)
Thus, if the soft-start capacitor CSS = 100 nF is selected, then the TCL(on) time will be 5 ms.
To calculate the hiccup off time TCL(off) before the restart, Equation 15 needs to be used:
TCL( off ) =
24
CSS ´ (3.5V - 0.55V )
2 .5 m A
(15)
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With the same soft-start capacitor value 100 nF, the off time before the restart is going to be 118 ms. Notice, that
if the over current condition happens before the soft-start capacitor voltage reaches the 3.5-V threshold during
start up, the controller limits the current but the soft-start capacitor continues to be charged. As soon as the 3.5-V
threshold is reached, the soft-start voltage is quickly pulled up to the 4.5-V threshold by an internal 1-kΩ RDS(on)
switch and the cycle-by-cycle current limit duration timing starts by discharging the soft-start capacitor.
Depending on specific design requirements, the user can override default parameters by applying external
charge or discharge currents to the soft-start capacitor. Figure 42 shows the operation of a full-bridge system at
cycle-by-cycle current limit. The waveforms include drain-source voltages of synchronous rectifiers and voltage at
CS pin. The whole cycle-by-cycle current limit and hiccup operation is shown in Figure 43. In this example the
cycle-by-cycle current limit lasts about 25 ms followed by 150 ms of off time.
Figure 42. Cycle-by-Cycle Current Limit
Figure 43. Hiccup Mode with Cycle-by-Cycle Current Limit at IOUT = 60 A
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In the event of a severe short circuit condition, the current sense voltage will exceed the short circuit threshold
set at 0.7 V min. At this point the controller shuts down the converter with propagation time 100 ns and pulls the
soft start pin up to the 4.5-V threshold. (see Figure 44).
SS pin,
Volts SoftStart
SS Clamp Voltage 4.5
SoftRestart
Off Time before restart
Fast Pull Up by
1kΩ Switch
The second current limit threshold0.7V
is hit at CS pin indicating short circuit
Iss=25µA
Outp. Enbl. Thresh. 0.85
SS ShDn. Thresh. 0.55
0
Ihcc= -2.5µA
Output Pulses, D
Figure 44. Timing Diagram for the Soft-Start Capacitor Voltage VSS During Short Circuit Protection
At this condition the soft-start voltage is forcibly pulled up even if the soft-start charge is not completed. After
that, the soft-start capacitor is discharged by 2.5-µA current until its voltage reaches the 0.55 V in order to
resume the soft-start cycle again. The duration of off time before the restart is defined by Equation 16:
TCL( off ) =
CSS ´ (4.5V - 0.55V )
2 .5 m A
(16)
With the same soft-start capacitor value 100 nF, the off time before the restart is going to be about 158 ms.
Similar to the over current condition, the hiccup mode with the restart can be override by user if a pull-up resistor
is connected between the SS and VREF pins. If the pull-up current provided by the resistor exceeds 2.5 µA, then
the controller remains in the latch-off mode. In this case, an external soft-start capacitor value should be
calculated with the additional pull-up current taken into account. The latch-off mode can be reset externally if the
soft-start capacitor forcibly discharged below 0.55 V or the VDD voltage is lowered below the UVLO threshold.
26
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Off-Time Control Circuit
The off time control circuit provides optimal off time between O1_D and O2_D outputs depending on the load
current condition. The UCC28230/1 implements the off time control approach based on step function with
hysteresis (see Figure 45).
Off-time control is an important feature to address an optimal operation of self-driven synchronous rectifier over
the whole load current range. In self-driven rectifier applications, the turn-on and off time of the synchronous
FETs is defined by the current of output inductor and its polarity. Some additional energy is also provided from
the magnetizing inductance of a power transformer but it may not be sufficient for the fast switching. Therefore,
at light load the off-time should be longer than at full load to allow previously conducting rectifier MOSFET to be
completely turned off before the next switching half-cycle. This ensures the rectifier MOSFET having enough
time to turn off before the primary-side MOSFET forces it to turn off. The turn off of the rectifier MOSFET, while
still conducting, results in a current surge followed by a significant voltage spike which lowers the efficiency and
reliability of converter.
TOFFMAX at light load = 5x TOFF with Off Time Control
Threshold set to 20% of IMAX
TOFF
TDT
T CLAMP
Hysteresis = IHYST x R1 x R2/(R1+R2)
Off Time Control Threshold
(Set by resister divider R1/R2 from
Pin VREF to pin OST and to GND)
TDT
TCLAMP
TDT
0
TOFF≈2.5×TDT at heavy load
(set by resister R3 from
pin OS to GND)
Iout
Ensures
no cross
conduction at
light load
Provides
minimum diode
conduction over
wide range of
load conditions
Figure 45. The Off Time Change as Function of Load Current
Usually there is no direct access to the load current of bus converters, so the primary current sensing is used to
replicate load current changes (see Figure 45). The largest part of the primary current is the load current on
secondary side of power transformer reflected into the primary side in accordance to transformer’s turn ratio. The
primary current includes not only the reflected load current, but also magnetizing current. However, for the most
practical applications the accuracy of solution with magnetizing current included is sufficient because in this
application the magnetizing current is only small percentage of overall current. With this assumption, the voltage
at pin CS can be defined as:
VCS = IOUT ´
RCS ´ WCT ( pr ) ´ W PT (sec)
W PT ( pr ) ´ WCT (sec)
(17)
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Where IOUT is the output inductor current, RCS is the current sense resistor, WPT(pr) and WPT(sec) are the primary
and secondary number of turns of power transformer windings and the WCT(pr) and WCT(sec) are the primary and
secondary number of turns of current transformer windings.
UCC28230/1 uses OS pin and OST pin to program the nominal off time TOFF and the output current threshold
where the off time steps up to the new value TOFF(max). The dead time Td and nominal off time TOFF are set by
resistor R3 between OS pin and GND (Figure 3, Figure 4 and Figure 50). Figure 46 shows how to choose R3
resistance to achieve the dead time Td and nominal off time TOFF for both UCC28230 and UCC28231. For
example, if a 40ns nominal TOFF is needed, the resistor value should be 8.45kΩ, and Td is about 17ns for
UCC28230 and 15ns for UCC28231. 15 kΩ R3 at OS pin sets TOFF to 50 ns and Td to 23 ns for UCC28230, with
TOFF as 47 ns and Td as 19 ns for UCC28231. Based on Figure 46, one can tell that TOFF is about 2.2 to 2.64
times of Td for UCC28230, and 2.25 to 2.75 times of Td for UCC28231.
Figure 25 through Figure 30 from Typical Waveforms show the output switching waveforms including rise and fall
time and off time TOFF1, TOFF2 for each half switching cycle and dead time Td1, Td2, Td3 and Td4 for each half
switching cycle.
Off time and dead time selection based on the resistor R3 value.
UCC28230 Off Time TOFF and Dead Time TD vs ROS
UCC28230 Off Time TOFF and Dead Time TD vs ROS
100
350
90
80
250
TOFF and T
D (ns)
TOFF and T
D (ns)
300
200
150
100
70
60
50
40
30
20
50
10
0
0
0
15
30
45
60
75
90
105
120
135
0
150
5
10
15
Off Time
20
25
30
35
ROS (kΩ)
ROS (kΩ)
Off Time
Dead Time
Figure 46.
Dead Time
Figure 47.
UCC28231 Off Time TOFF and Dead Time TD vs ROS
UCC28231 Off Time TOFF and Dead Time TD vs ROS
300
100
90
80
TOFF and T
D (ns)
TOFF and T
D (ns)
250
200
150
100
70
60
50
40
30
20
50
10
0
0
0
20
40
60
80
100
120
140
160
180
200
0
5
10
ROS (kΩ)
Off Time
20
25
30
35
40
45
50
55
60
ROS (kΩ)
Dead Time
Figure 48.
28
15
Off Time
Dead Time
Figure 49.
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The next step is to set the output current threshold below that the off time changes to its maximum value. This
threshold is defined as:
VOST = VREF ´
R2
R1 + R 2
(18)
The increase of off time at light load condition is provided by the increasing of overlapping time TCLAMP of
O1_DIN and O2_DIN outputs (see Figure 33). This ensures the faster turning off of the rectifier MOSFETs when
the primary winding is clamped. The dead time between the switching of primary MOSFETs in each leg remains
the same over the load current, which is still proportional to nominal off time as shown in Figure 46.
5V for UCC28230,
3.3V for UCC28231
VREF
1
OS
R1
TOFF set
circuit
3
To Logic Block
R3
2
R2
OST
I HYST = 10µ A
Iprim
CS
6
Is
X 10
filtering
RCS
CT
Cycle-by-Cycle
Current Limit
Figure 50. The Off-Time Control Circuit Using Comparator With Hysteresis
Selecting optimal hysteresis is important to avoid oscillation. UCC28230/31 provides the flexibility of
programming the hysteresis with internal 10-µA current IHYST and the values of external resistors R1 and R2 (see
Figure 50). Equation 19 shows how to choose the hysteresis.
Vhyst = Ihyst ´
R1´ R 2
R1 + R 2
(19)
In some cases, the disabling of off-time control circuit is needed, which can be done by simply connecting OST
pin to GND or to VREF. Connecting OST pin to the VREF is characterized in the electrical table and is the
preferable way to maintain fixed off time set by resistor R3.
The load dependent dead time will cause a slight change in output duty cycle at the programmed transition point
from light load to heavy load and vice-versa. This slight change in duty cycle corresponds to a slight change in
output voltage.
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APPLICATION INFORMATION
DESIGN EXAMPLE
1
V
0
Two design examples are provided to show how to design an intermediate bus converter with UCC28230/1.
Design Example 1 provides a concise step-by-step design. Its design specifications, schematics and test results
are illustrated on efficiency, power dissipation and output voltage regulation. Design Example 2 is to show an
industry standard quarter brick module design with 12-layer boards and embedded magnetic parts. Its design
specifications, schematics, and test results are provided.
Figure 51. Design Example of IBC Using UCC28230 Controller Device
30
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Design Goals
This example illustrates the design process and component selection for an intermediate bus converter using
UCC28230. The target design is a 300-W full bridge converter with narrowed input voltage range in a close to
quarter brick form factor with open-loop control for the telecom applications in intermediate bus architecture. Its
specifications are shown in Table 1.
Table 1. 300W IBC Specifications
PARAMETER
MIN
43
TYP
MAX
UNIT
48
53
VDC
Input voltage
VIN
Output voltage
VOUT
Output power
POUT
300
W
Output load current
IOUT
30
A
Load capacitance
COUT
Switching frequency
FSW
Over power limit
PLIMIT
Efficiency at full load
η (VIN = 48 V)
9.6
10,000
125
150%
96%
Isolation
Turns-ratio
µF
kHz
1500
NPRI : NSEC
V
5:1
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Recommended PCB Device Layout
The device programming components should be placed as close as possible to the device. The power ground
should be separated from the signal ground and connected only at one point at device pin 8 and 9 for TSSOP
package. For SON package there is only one ground pin available, pin 7. In this case, pin 7 is used to replace
the connection of pin 8 and pin 9 of TSSOP. The following takes TSSOP as the example. For SON, a similar
arrangement on the layout should be made. Capacitors for bias decoupling (C5), reference voltage decoupling
(C6), and soft start (C9), should be placed right across the signal ground and pins 14, 1 and 6, respectively. All
programming resistors, R2, R3, R5, and R7 should be placed next to the device pins they should be connected
to minimize their EMI noise reception. See Figure 52 for a recommended component layout and placement. PCB
design considerations of other circuit part are discussed later in the relevant part design.
Figure 52.
Figure 53.
32
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Programming the UCC28230
Switching frequency: R7 Equation 3
R 7 = RT = K 1´
(VREF - K 2 )
( 5 - 2 .4 )
= 2500 ´
= 52 k W Þ 52.3 k W
fSW
125
(20)
Soft-start time: C9
Considering power on with maximum 10,000-µF load capacitors, soft-start time may need be adjusted and if
soft-start time is determined as 25 ms, then based on Equation 9
C9 = CSS =
TSS ´ K 3
25 ´ 25 m A
=
= 0.27 m F Þ 0.33 m F
( K 4 - K 5 ) ( 2.85V - 0.85V )
(21)
Multilayer ceramic capacitor (X7R or X5R) should be used.
Dead time set-up resistor, R5
Assuming Td = 20 ns, based on Figure 46
R 5 = 13 k W Þ 15 k W
(22)
Off-time adjustment threshold and hysteresis resistors: R2 and R3
TOFF is set up at 10% of rated load, VOST = 0.5V, with hysteresis VHYST = 100 mV. Based on Equation 18 and
Equation 19, kΩ
VOST
R3
=
R 2 (VREF - VOST )
R3 =
Vhyst
Ihyst
(23)
æ
ö
V OST
´ ç1+
÷
è VREF - VOST ø
(24)
Solution to the above two equations yields R2 = 99.9 kΩ, and R3 = 11.1 kΩ.
VDD decoupling capacitor: C5 High quality low ESR and low ESL such as multilayer ceramic capacitor (X7R or
X5R) with a value between 0.1 to 1.0 µF should be used.
VREF decoupling and stability capacitor: C6
High quality low ESR and low ESL such as multilayer ceramic capacitor (X7R or X5R) with a value between 1.0
to 2.2 µF should be used .
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Current Sensing
Power stage design shows primary DC current maximum value is determined
IP ( rms ) =
PLIMIT
450
=
= 10 .5 (with 20 % m arg in ) Þ 12 .6 A
VIN (min)
43
(25)
If pick up a current transformer with turns ratio of 100:1, R4 is determined as 5.11Ω with current sense threshold
at 150% of rated power.
Current sensing plays a critical role to achieve several features of UCC28230 including over current protection
and off time adjustment. Usually the sensing element cannot be placed next to the device. In such a case, it is
strongly recommended to route the PCB with Kelvin connection from the current sensing output device (R4) to
the IC (Pin 7) as shown in Figure 54. A small RC filter (R8 and C10) is required to attenuate possible high
frequency noise. A small capacitor, C8, can also be added to get further filtering effect while usually it is not
needed.
Figure 54.
34
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Power Stage
Transformer:
The design goal shows a 300-W transformer with turns ratio 5:1. To make the design close to the telecom typical
applications, planar magnetic core is used with windings using PCB traces.
Primary MOSFETs
In steady state, the primary MOSFET's duty cycle is about 50%. At minimum input voltage 43 V, maximum
450-W power, and 96% efficiency, their current rating can be determined as
ID( rms ) =
PLIMIT
450
0 .5
a
´
=
´
= 7 .7 A
h
43 0 .96
VIN (min)
(26)
α = duty cycle of MOSFETS
Their voltage rating is determined as 53 V. After considering 20% margin, current and voltage rating should be 9
A and 80 V, respectively.
Primary MOSFET drivers
The UCC28230 of 0.2-A MOSFET driving capability requires external MOSFET drivers. One good option is to
use UCC27200 for U1 and U3. Gate resistors (1.0 Ω) of R16-19 are suggested to add in and attenuate possible
parasitic ringing. UCC27200 is designed for half bridge application with 2-A driving capability. Each UCC27200
should have its own VDD high quality decoupling and driving energy capacitor (typical value 1.0 µF) of low ESR
and low ESL. Its boost strap capacitor value of 0.1µF can be selected.
Secondary MOSFETs
In steady state, the secondary MOSFETs have their duty about 50%. At minimum input voltage 43 V, maximum
450-W power, transformer turns ratio 5:1, their current rating can be determined as:
ID( rms ) =
PLIMIT
450
´ a ´ Nt =
´ 0.5 ´ 5 = 52.3 A
43
VIN(min)
(27)
Their voltage rating can be determined as:
VDS =
VIN (max)
Nt
´2 =
53
´ 2 = 21 .2 V
5
(28)
After considering potential parasitic ringing, 40-V MOSFETs may be used.
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Output Inductor
The output inductor value is determined by the start-up condition with supposed maximum peak-to-peak ripple
current. The ripple current is a function of input voltage, duty cycle, switching frequency and transformer turns
ratio. At start, a highest ripple should occur at about 0.5 duty cycle and maximum input voltage when the
switching frequency should be designed in accordance with the top flat area shown in Figure 34. A typical ripple
current can be initially taken around 90% of the maximum output current from steady state operation.
L2 =
D ´ ( 1 - D ) ´ VIN
0.5 ´ ( 1 - 0.5 ) ´ 53
=
= 106 nH
2 ´ n ´ fsw ´ I pk - pk 2 ´ 5 ´ 500 ´ 103 ´ 25
(29)
The inductor value is then determined to be 100 nH.
Test Results
97.00%
96.00%
Efficiency
95.00%
94.00%
43Vin
48Vin
53Vin
93.00%
92.00%
91.00%
90.00%
5
10
15
20
25
30
35
Load Current A
Figure 55. Efficiency
36
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15.000
14.000
13.000
12.000
Power Loss W
11.000
10.000
9.000
43V
8.000
48V
7.000
53V
6.000
5.000
4.000
3.000
2.000
1.000
0.000
0.00
5.00
10.00
15.00
20.00
25.00
30.00
35.00
Load Current A
Figure 56. . Power Dissipation
11.000
Output Voltage V
10.500
10.000
43Vin
9.500
48Vin
53Vin
9.000
8.500
8.000
0
5
10
15
20
25
30
35
Load Current A
Figure 57. Load regulation
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11V
11V
Design Example 2
Figure 58.
38
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This design consists of a 350 watt 6:1 bus converter in an industry standard quarter brick package, utilizing the
UCC28230 PWM Bus Controller, UCC27201 High Voltage High-Side Low-Side Drivers and a 12-layer PCB with
embedded magnetic parts. This design features low profile construction representative of typical isolated dc-to-dc
construction in a quarter brick form factor. Typical efficiency above 97% is achieved with this design. By using
the UCC28230 PWM Bus Controller allows optimum duty cycle control for both light load and full load. The
unique feature of sampling the primary transformer current and controlling the dead time provides reduced no
load/ light load power dissipation by increasing the dead time to minimize output synchronous rectifier cross
conduction, yet reducing the dead time at higher output loads to achieve maximum power transfer to the load. As
with all self driven synchronous rectifiers, transformer design is critical. Minimal leakage inductance to reduce
ringing on the MOSFETs and minimize or eliminate snubbers along with optimum coupling of the output
secondary winding with the gate drive winding for precise timing of the turn on and off of the synchronous
rectifiers. This is required to reduce the amount of conduction of the internal intrinsic diode of the MOSFETs.
350-W IBC Specifications
PARAMETER
MIN
TYP
MAX
UNIT
48
60
VDC
Input voltage
VIN
Output voltage
VOUT
36
Output power
POUT
350
W
Output load current
IOUT
45
A
Load capacitance
COUT
Switching frequency
FSW
Over power limit
PLIMIT
Efficiency at full load
η (VIN = 48V)
8.0
10,000
165
150%
96%
Isolation
Turns-ratio
µF
kHz
1500
V
NPRI : NSEC
6:1
Test Results
UCC28230 IBC Efficiency
99
97
Efficiency %
95
36.0V
93
48.0V
91
60.0V
89
87
85
4.5
9
13.5
18
22.5
27
31.5
36
40.5
45
Load Current A
Figure 59. Efficiency
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UCC28230 REFERENCE Power Dissipation
20.0
18.0
16.0
Pd - Watts
14.0
12.0
36.0V
10.0
48.0V
8.0
60.0V
6.0
4.0
2.0
0.0
0
5
10
15
20
25
30
35
40
45
Iout()-Amps
Figure 60. Power Dissipation
UCC28230 REFERENCE Load Regulation
12.000
10.000
Vout - V
8.000
36.0V
48.0V
6.000
60.0V
4.000
2.000
0.000
0
5
10
15
20
25
30
35
40
45
Iout()-Amps
Figure 61. Load Regulation
40
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PACKAGE MATERIALS INFORMATION
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31-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
UCC28230DRNR
SON
DRN
12
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
2.3
3.3
0.85
4.0
12.0
Q1
UCC28230DRNT
SON
DRN
12
250
330.0
12.4
2.3
3.3
0.85
4.0
12.0
Q1
UCC28231DRNR
SON
DRN
12
3000
330.0
12.4
2.3
3.3
0.85
4.0
12.0
Q1
UCC28231DRNT
SON
DRN
12
250
330.0
12.4
2.3
3.3
0.85
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Jul-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28230DRNR
SON
DRN
12
3000
340.5
338.1
20.6
UCC28230DRNT
SON
DRN
12
250
340.5
338.1
20.6
UCC28231DRNR
SON
DRN
12
3000
340.5
338.1
20.6
UCC28231DRNT
SON
DRN
12
250
340.5
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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