UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 8-Pin High-Performance Resonant Mode Controller FEATURES 1 • • • • • • • • • • • • Variable Switching Frequency Control Programmable Minimum Switching Frequency With 4% Accuracy (3% accuracy at temperature range: -20°C to 105°C) Programmable Maximum Switching Frequency Programmable Dead Time for Best Efficiency Programmable Soft-Start Time Easy ON/OFF Control Over-Current Protection Over-Temperature Protection Bias Voltage UVLO and OVP Integrated Gate Driver With 0.4-A Source and 0.8-A Sink Capability Operating Temperature Range: –40°C to 125°C SOIC 8-Pin Package APPLICATIONS • • • • • 100-W to 1-kW Power Supplies LCD, Plasma and DLP TVs Adaptors, Computing and ATX Power Supplies Home Audio Systems Electronic Lighting Ballasts DESCRIPTION The UCC25600 high performance resonant mode controller is designed for dc-to-dc applications utilizing resonant topologies, especially the LLC half bridge resonant converter. This highly integrated controller implements frequency modulation control and complete system functions in only an 8-pin package. Switching to the UCC25600 will greatly simplify the system design, layout and improve time to market, all at a price point lower than competitive 16-pin device offerings. The internal oscillator supports the switching frequencies from 30 kHz to 350 kHz. This high accuracy oscillator realizes the minimum switching frequency limiting with 4% tolerance, allowing the designer to avoid "over design" of the power stage and, thus, further reducing overall system cost. The programmable dead time enables zero-voltage switching with minimum magnetizing current. This will maximize system efficiency across a variety of applications. The programmable soft-start timer maximizes design flexibility demanded by the varied requirements of end equipments utilizing a half bridge topology. By incorporating 0.4-A source and 0.8-A sink driving capability, a low cost, reliable gate driver transformer is a real option. The UCC25600 delivers complete system protection functions including over current, UVLO, bias supply OVP and over temperature protection. TYPICAL APPLICATION DIAGRAM * * * Vs 8 5 7 6 GD1 OC GD2 RT UCC25600 VCC DT GND SS 3 2 1 4 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2009, Texas Instruments Incorporated UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE UCC25600D 8-Pin SOIC -40°C to 125°C ABSOLUTE MAXIMUM RATINGS (1) (2) (3) (4) over operating free-air temperature range (unless otherwise noted) PARAMETER LIMIT UNIT Supply voltage, VCC 22 Voltage, GD1, GD2 Gate drive current – continuous, GD1, GD2 +/- 25 Current, RT -5 Current, DT -0.7 Operating junction temperature, TJ −40 to 125 Storage temperature, TSTG −65 to 150 Lead temperature (10 seconds) (1) (2) (3) (4) V -0.5 to VCC + 0.5 mA °C 260 These are stress limits. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability. All voltages are with respect to GND. All currents are positive into the terminal, negative out of the terminal. In normal use, terminals GD1 and GD2 are connected to an external gate driver and are internally limited in output current. ELECTROSTATIC DISCHARGE (ESD) PROTECTION PARAMETER RATING Human Body Model (HBM) UNIT 2,000 Charged Device Model (CDM) V 500 DISSIPATION RATINGS PACKAGE THERMAL IMPEDANCE, JUNCTION-TO-AMBIENT 8-Pin SOIC (1) (2) 150°C/watt TA = 25°C POWER RATING (1) (2) 667 mW TA = 85°C POWER RATING (1) 267 mW (1) Thermal resistance is a strong function of board construction and layout. Air flow will reduce thermal resistance. This number is only a general guide. Thermal resistance calculated with a low-K methodology. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER MINIMUM VCC input voltage from a low-impedance source MAXIMUM UNIT 11.5 18.0 RT resistance 1 8.666 DT resistance 3.3 39 SS capacitor 0.01 1 2 Submit Documentation Feedback V kΩ µF Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, −40°C < TA < 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 4.7 kΩ, RDT = 16.9 kΩ, CVCC = 1 µF, (unless otherwise noted) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Bias Supply (VCC) 1 1.5 2.5 5 7.5 100 400 Measured at VCC rising 9.9 10.5 11.1 UVLO turn-off threshold Measured at VCC falling 8.9 9.5 10.1 UVLO hysteresis Measured at VCC 0.7 1 OVP turn-off threshold Measured at VCC rising 18 20 22 OVP turn-on threshold Measured at VCC falling 16 18 20 OVP hysteresis Measured at VCC 1.5 2 2.5 Dead time RDT = 16.9 kΩ 390 420 450 FSW(min) Minimum switching frequency at GD1, GD2 -40°C to 125°C 40.04 41.70 43.36 -20°C to 105°C 40.45 41.70 42.95 KICO Switching frequency gain/I (RT) RRT = 4.7 kΩ, IRT = 0 to 1 mA 60 80 100 Hz/µA 50 ns VUVLO VOVP VCC current, disabled SS = 0 V VCC current, enabled SS = 5 V, CGD1 = CGD2 = 1 nF VCC current, UVLO VCC = 9 V UVLO turn-on threshold 1.3 mA µA V Dead Time (DT) TDT ns Oscillator GD1, GD2 on time mismatching FSW_BM FSW(start) -50 Switching frequency starting burst mode SS = 5 V 300 350 400 Switching frequency to come out of burst mode SS = 5 V 280 330 380 -40°C to 125°C 122 142.5 162 -20°C to 105°C 125 142.5 160 Switching frequency at soft start kHz kHz External Disable/Soft Start ISS Enable threshold Measure at SS rising 1.1 1.2 1.3 Disable threshold Measured at SS falling 0.85 1 1.1 Disable hysteresis Measured at SS 0.15 Disable prop. delay Measured between SS (falling) and GD2 (falling) 250 500 750 Source current on ISS pin VSS = 0.5 V -225 -175 -125 Source current on ISS pin VSS = 1.35 V -5.5 -5 -4.5 0.35 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 V ns µA 3 UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, −40°C < TA < 125°C, TJ = TA, VCC = 12 V, GND = 0 V, RRT = 4.7 kΩ, RDT = 16.9 kΩ, CVCC = 1 µF, (unless otherwise noted) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Peak Current Limit VOC1(off) Level 1 over current threshold – VOC rising 0.9 1 1.1 VOC2(off) Level 2 over current latch threshold – VOC rising 1.8 2.0 2.2 VOC1(on) Level 1 over current threshold – VOC falling 0.5 0.6 0.7 Td_OC Propagation delay 60 200 500 ns IOC OC bias current VOC = 0.8 V 200 nA GD1, GD2 output voltage high IGD1, IGD2 = −20 mA GD1, GD2 on resistance high IGD1, IGD2 = −20 mA GD1, GD2 output voltage low IGD1, IGD2 = 20 mA GD1, GD2 on resistance low IGD1, IGD2 = 20 mA Rise time GDx 1 V to 9 V, CLOAD = 1 nF Fall time GDx 9 V to 1 V, CLOAD = 1 nF 12 25 GD1, GD2 output voltage during UVLO VCC = 6 V, IGD1, IGD2 = 1.2 mA -200 V Gate Drive 9 11 V 12 30 Ω 0.08 0.2 V 4 10 Ω 18 35 0.5 1.75 ns V Thermal Shutdown 4 Thermal shutdown threshold 160 Thermal shutdown recovery threshold 140 Submit Documentation Feedback °C Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 DEVICE INFORMATION 8-Pin SOIC, Top View DT 1 8 GD1 RT 2 7 VCC OC 3 6 GND SS 4 5 GD2 TERMINAL FUNCTIONS TERMINAL NAME DT NO. 1 DESCRIPTION I/O I This pin sets the dead time of high-side and low-side switch driving signals. Connect a resistor to ground. With internal 2.25-V voltage reference, the current flowing through the resistor sets the dead time. To prevent shoot through when this pin is accidentally short to ground, the minimum dead time is set to 120 ns. Any dead time setting less than 120 ns will automatically have 120-ns dead time. RT 2 I The current flowing out of this pin sets the frequency of the gate driver signals. Connect the opto-coupler collector to this pin to control the switching frequency for regulation purpose. Parallel a resistor to ground to set the minimum current flowing out of the pin and set the minimum switching frequency. To set the maximum switching frequency limiting, simply series a resistor with the opto-coupler transistor. This resistor sets the maximum current flowing out of the pin and limits the maximum switching frequency. OC 3 I Over-current protection pin. When the voltage on this pin is above 1 V, gate driver signals are actively pulled low. After the voltage falls below 0.6 V, the gate driver signal recovers with soft start. When OC pin voltage is above 2 V, the device is latched off. Bringing VCC below UVLO level resets the overcurrent latch off. SS 4 I Soft-start pin. This pin sets the soft-start time of the system. Connect a capacitor to ground. Pulling this pin below 1 V will disable the device to allow easy ON/OFF control. The soft-start function is enabled after all fault conditions, including bias supply OV, UVLO, over-current protection and over-temperature protection. GD1 8 O GD2 5 O High-side and low-side switch gate driver. Connect gate driver transformer primary side to these two pins to drive the half bridge. GND 6 - Ground. VCC 7 - Bias Supply. Connect this pin to a power supply less than 20 V. Parallel a 1-µF capacitor to ground to filter out noise. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 5 UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com Block Diagram 2.25V T J 160oC/140oC DT + TSD Thermal ShutDown 1 OV + 10.5V 9.5V Dead time generator RDT 20V 18V UVLO + 7 VCC 2.5V Feed back RT 2 Ic 8 GD1 OSC Vss UVLO OV Q OC TSD SET VCC D 5 GD2 FAULT Q CLR 5uA 6 GND GD_Stop 6V 170uA OC OC SS 3 + 1V Vss 4 OC_latch Css + + 2V 1.2V/1V FAULT S R 6 SET CLR Q Q Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 TYPICAL CHARACTERISTICS At VCC = 12 V, RRT = 4.7 kΩ, RDT = 16.9 kΩ, VSS = 5 V, VOC = 0 V; all voltages are with respect to GND, TJ = TA = 25°C, unless otherwise noted. BIAS SUPPLY CURRENT vs BIAS SUPPLY VOLTAGE SWITCHING FREQUENCY vs RT CURRENT 350 Fsw - Switching Frequency - kHz Ivcc - Bias Supply Current - mA 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 300 250 200 150 100 -40 °C OC Open 0.2 25 °C 50 0.1 125 °C 0 0 6 7 8 9 10 11 12 13 14 0 1 2 Vvcc - Bias Supply Voltage - V 3 4 5 IRT - RT Current - mA Figure 1. Figure 2. DEAD TIME vs DT CURRENT DEAD TIME vs DT RESISTOR 1000 1000 - 40 °C 900 900 25 °C 800 125 °C DT - Dead Time - DT - Dead Time - 800 700 600 500 400 700 600 500 400 300 300 200 200 100 100 0 0 0 100 200 300 400 500 600 700 -40 °C 25 °C 125 °C 0 5 10 15 20 25 30 35 40 45 RDT - DT Resistor - kOhm IDT - DT Current - uA Figure 3. Figure 4. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 7 UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) GATE DRIVE FALLING; VCC=15V 10 0.8 1.4 14 0.7 1.2 12 0.6 10 Gate Drive Voltage 0.5 1 8 0.8 6 0.6 4 0.4 2 0 -2 0 100 200 300 400 500 Gate Drive Source Current 8 6 0.3 4 0.2 0.2 2 0.1 0 0 0 -0.2 600 -2 0 200 400 600 -0.1 1000 800 Time - ns Time - ns Figure 5. Figure 6. OC PROPAGATION DELAY vs TEMPERATURE UVLO THRESHOLD vs TEMPERATURE 300 12 UVLO On Threshold - VCC Rising UVLO Off Threshold -VCC Falling UVLO Threshold - 250 Propagation Delay - ns 0.4 Gate Drive Current - A Gate Drive Voltage - V 12 16 Gate Drive Voltage - V Gate Drive Voltage Gate Drive Sink Current 14 1.6 Gate Drive Current - A 16 GATE DRIVE RISING; VCC=15V 200 150 11 10 100 9 50 0 8 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 Tj - Junction Temperature - °C Figure 7. 8 0 20 40 60 80 100 120 140 Tj - Junction Temperature - °C Figure 8. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 TYPICAL CHARACTERISTICS (continued) VCC OVER VOLTAGE THRESHOLD vs TEMPERATURE OVER CURRENT THRESHOLD vs TEMPERATURE 2.5 OVP Off Threshold - VCC Rising 21 Voc Over Current Threshold - V VCC Over Voltage Threshold - V 22 OVP On Threshold -VCC Falling 20 19 18 2 OC Off Threshold - Voc Rising OC On Threshold - Voc Falling 1.5 OC Latch Threshold - Voc Rising 1 0.5 17 16 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 Tj - Junction Temperature - °C 0 20 40 60 80 100 120 140 Tj - Junction Temperature - °C Figure 9. Figure 10. ON TIME MISMATCH vs SWITCHING FREQUENCY On Time Mismatch - ns 100 80 60 40 20 0 0 50 100 150 200 250 300 350 Switching Frequency - kHz Figure 11. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 9 UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com APPLICATION INFORMATION Principal of Operation The soft-switching capability, high efficiency and long holdup time make the LLC resonant converter attractive for many applications, such as digital TV, ac/dc adapters and computer power supplies. Figure 12 shows the schematic of the LLC resonant converter. Cr Lr n:1:1 Lm Figure 12. LLC Resonant Converter The LLC resonant converter is based on the Series Resonant Converter (SRC). By utilizing the transformer magnetizing inductor, zero-voltage switching can be achieved over a wide range of input voltage and load. As a result of multiple resonances, zero-voltage switching can be maintained even when the switching frequency is higher or lower than resonant frequency. This simplifies the converter design to avoid the zero-current switching region, which can lead to system damage. The converter achieves the best efficiency when operated close to its resonant frequency at a nominal input voltage. As the switching frequency is lowered the voltage gain is significantly increased. This allows the converter to maintain regulation when the input voltage falls low. These features make the converter ideally suited to operate from the output of a high-voltage boost PFC pre-regulator, allowing it to hold up through brief periods of ac line-voltage dropout. Due to the nature of resonant converter, all the voltages and currents on the resonant components are approximately sinusoidal. The gain characteristic of LLC resonant converter is analyzed based on the First Harmonic Approximation (FHA), which means all the voltages and currents are treated as sinusoidal shape with the frequency same as switching frequency. According to the operation principle of the converter, the LLC resonant converter can be draw as the equivalent circuit as shown in Figure 13. Cr Vge Lr Lm Re Voe Figure 13. LLC Resonant Converter Equivalent Circuit 10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 In this equivalent circuit, the Vge and Voe are the fundamental harmonics of the voltage generated by the half bridge and the voltage on the transformer primary side, respectively. These voltages can be calculated through Fourier analysis. The load resistor Re is the equivalent resistor of the load, and it can be calculated as: Re = 8 2 n R p2 (1) Based on this equivalent circuit, the converter gain at different switching frequencies can be calculated as: jw Lm Re Vo jw Lm + Re = jw Lm Re 1 VDC / 2 + + jw Lr jw Lm + Re jwCr (2) In this equation VDC/2 is the equivalent input voltage due to the half bridge structure. Table 1. Circuit Definition Calculations NORMALIZED GAIN M= Vo VDC / 2 RESONANT FREQUENCY f0 = 1 2p Lr Cr NORMALIZED FREQUENCY QUALITY FACTOR Qe = Lr / Cr Re fn = f f0 INDUCTOR RATIO Ln = Lm Lr Following the definitions in Table 1, the converter gain at different switching frequencies can be written as: M= Ln f n 2 Ln f n 2 + ( f n - 1)( f n + 1 + jf n LnQe ) (3) Because of the FHA, this gain equation is an approximation. When the switching frequency moves away from the resonant frequency, the error becomes larger. However, this equation can be used as the design tool. The final results need to be verified by the time based simulation or hardware test. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 11 UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com From Equation 3, when switching frequency is equal to resonant frequency, fn = 1 and converter voltage gain is equal to 1. Converter gain at different loads and inductor ratio conditions are shown in Figure 14 through Figure 17. M vs ƒn M vs ƒn 2 2 Ln = 1 Ln = 5 Qe = 0.1 Qe = 0.2 Qe = 0.5 Qe = 1 Qe = 2 Qe = 5 1.5 Qe = 0.1 Qe = 0.2 Qe = 0.5 Qe = 1 Qe = 2 Qe = 5 1.5 M M 1 1 0.5 0.5 0 0.1 0.5 1 1.5 0 0.1 2 0.5 1 fn 1.5 2 fn Figure 14. Figure 15. M vs ƒn M vs ƒn 2 2 Qe = 0.1 Qe = 0.2 Qe = 0.5 Qe = 1 Qe = 2 Qe = 5 Ln = 10 1.5 Ln = 20 1.5 Qe = 0.1 Qe = 0.2 Qe = 0.5 Qe = 1 Qe = 2 Qe = 5 M M 1 1 0.5 0.5 0 0.1 0.5 1 1.5 2 0 0.1 fn 0.5 1 1.5 2 fn Figure 16. Figure 17. Based on its theory of operation the LLC resonant converter is controlled through Pulse Frequency Modulation (PFM). The output voltage is regulated by adjusting the switching frequency according to the input and output conditions. Optimal efficiency is achieved at the nominal input voltage by setting the switching frequency close to the resonant frequency. When the input voltage droops low the switching frequency is decreased to boost the gain and maintain regulation. The UCC25600 resonant half-bridge controller uses variable switching frequency control to adjust the resonant tank impedance and regulate output voltage. This 8-pin package device integrates the critical functions for optimizing the system performance while greatly simplifying the design and layout. 12 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 Adjustable Dead Time Resonant half-bridge converter relies on the resonant tank current at MOSFETs turn-off to achieve soft switching and reduce switching loss. Higher turn-off current provides more energy to discharge the junction capacitor, while it generates more turn-off loss. Smaller turn-off current reduces turn-off loss, but it requires longer time to discharge MOSFETs junction capacitors and achieve soft switching. By choosing an appropriate dead time, turn-off current is minimized while still maintaining zero-voltage switching, and best system performance is realized. In UCC25600, dead time can be adjusted through a single resistor from DT pin to ground. With internal 2.25-V voltage reference, the current flow through the resistor sets the dead time. td = 20ns + Rdt ´ 24ns / k W (4) To prevent shoot through when DT pin accidentally connects to ground, a minimum 120-ns dead time is inserted into the two gate driver outputs. Any dead-time setting less than 120-ns, will be limited to 120-ns. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 13 UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com Oscillator With variable switching frequency control, UCC25600 relies on the internal oscillator to vary the switching frequency. The oscillator is controlled by the current flowing out of RT pin. Except during soft start, the relationship between the gate signal frequency and the current flowing out of RT pin can be represented as: fS = 1 1 » I RT ´ 83Hz / m A 2 6ns ´1A + 150ns I RT (5) Since the switching frequency is proportional to the current, by limiting the maximum and minimum current flowing out of RT pin, the minimum and maximum switching frequency of the converter could be easily limited. As shown in Figure 18, putting a resistor from RT pin to ground limits the minimum current and putting a resistor in series with the opto-coupler limits the maximum current. UCC25600 Maximum frequency limiting RT R1 Minimum frequency limiting R2 Figure 18. Maximum and Minimum Frequency Setting for UCC25600 The frequency limiting resistor can be calculated based on following equations. I f max = I f min = 6ns 1 - 150ns 2 f max (6) 6ns 1 - 150ns 2 f min (7) æ 1 1 ö I f max = 2.5V ç + ÷ è R1 R2 ø I f min = 14 (8) 2.5V R2 (9) Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 Soft Start During start up and fault recovery conditions, soft start is always implemented to prevent excessive resonant tank current and ensure Zero-Voltage Switching (ZVS). During soft start, the switching frequency is increased. The soft-start time can be programmed by placing a capacitor from SS pin to ground. The soft-start pin also serves as an ON/OFF control pin of the device. By actively pulling the SS pin below 1 V, the device is disabled. When the pull down is removed, SS pin voltage is increased because of internal charging current. Once SS pin becomes above 1.2 V, the device starts to generated gate-driver signal and enters soft-start mode. The time sequence of soft start is shown in Figure 19. 4V 1.2V Vss Gate driver t ss _ delay t ss Figure 19. Soft-Start Sequence To prevent a long delay between the ON command and apperance of a gate driver signal, the SS pin current is set as two different levels. When SS pin voltage is below 1.2 V, its output current is 175 µA. This high current could charge the soft-start pin capacitor to 1.2 V in a short period of time, and reduces the time delay. This time delay can be calculated using following equation: tSS _ delay = 1.2V CSS 175m A (10) The switching frequency during soft start is determined by both the current flowing out of the RT pin and the voltage on SS pin. The switching frequency can be calculated based on the following equation: fS = 1 2 1 6ns ´1A I RT V æ ö + ç1.81mA - SS ÷ 2 .2 k W ø è + 150ns (11) After SS pin voltage reaches 4 V, soft-start period is finished and switching frequency becomes the same as demanded by the RT pin current. The time used to charge SS pin from 1.2 V to 4 V is defined as soft-start time and can be calculated as: tSS = 2.8V CSS 5m A (12) To ensure reliable operation, the gate drivers restart with GD2 turning high. This prevents uncertainty during system start up. Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 15 UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com Burst-Mode Operation During light load condition, the resonant converter tends to increase its switching frequency and maintain the output voltage regulation. However, due to ringing caused by transformer parasitic capacitor and the rectification-diode-junction capacitors, the energy could be directly transferred to the load through these capacitors. When this power becomes more than the load requires, output voltage become higher than the regulation level. In this case, further increasing the switching frequency will not help the situation because energy transfer to the load is not through the power stage itself. To prevent output over voltage during this condition, the UCC25600 includes the burst-mode operation function. When the control loop demands switching frequency higher than 350 kHz, the gate driver is disabled and the power stage stops switching. When the output voltage drops, the control loop begins to demand switching frequency less than 330 kHz, the gate driver recovers and the power stage begins to deliver power again. This allows output voltage to be regulated. This burst mode can be easily disabled by limiting the maximum switching frequency to less than 350 kHz. In this way, the control loop will never demand a switching frequency higher than 350kHz and burst mode operation will not occur. 16 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 UCC25600 www.ti.com ............................................................................................................................................. SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 Over-Current Protection To prevent power stage failure under excessive load current condition, the UCC25600 includes an over-current protection function. With a dedicated OC pin, the power stage is shut down when OC pin voltage is above 1 V. Once the OC pin voltage becomes lower than 0.6 V, the gate driver recovers with soft start. To enhance system safety, the UCC25600 latches up the whole system when OC pin becomes above 2 V. Bring VCC below UVLO level to reset the device. The current can be indirectly sensed through the voltage across resonant capacitor by using the sensing network shown in Figure 20. Lr From half bridge TR Lm Rs D2 To OC Cp Rp Cs D1 Cr Figure 20. Current Sensing for LLC Resonant Converter The general concept of this sensing method is that, ac voltage across the resonant capacitor is proportional to load current. According to the FHA model, peak voltage of the ac component on the resonant capacitor can be calculated as: VCr _ pk = jf L Q + 1 4 nVo n n2 e p f n Ln (13) Therefore, the resonant capacitor voltage reaches its maximum value at the minimum switching frequency and maximum load. According to this equation, the current sensing network components can be calculated. Due to the nature of FHA, the final circuit parameters need to be verified through actual hardware test. Calculated Current Sensing Network Components NAME FUNCTION DESIGN EQUATION 2 Transfer ac voltage across resonant capacitor into current source Rs = CS Blocking dc voltage on resonant capacitor Cs = RP Load resistor of the current source Rp = CP Filter capacitor Cp = RS VCr _ pk (max ) 2 PRs (max) 10 Rs f min Rs p VCr _ pk (max ) 10 R p f min Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 17 UCC25600 SLUS846A – SEPTEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................. www.ti.com Gate Driver Half-bridge resonant converter is controlled by the nearly 50% duty cycle variable frequency square wave voltage. This allows the half bridge to be easily driven by the gate-driver transformer. Compared with a half-bridge driver device, a gate-driver transformer provides a simple and reliable solution, which: • Eliminate the need for gate driver power supply • Enable simplified layout • Preventing shoot through due to the transformer coupling • No latch up The UCC25600 integrates two-gate drivers with 0.4-A source and 0.8-A sink capability to directly drive the gate driver transformer. For LLC resonant converter, it is critical for the gate-driver signal to be precisely symmetrical. Otherwise, the resonant tank operation will be asymmetrical. The load current distribution will be unbalanced for the output rectifiers, which in turn requires over design of the power stages and thermal management. In UCC25600, the gate-driver outputs are precisely trimmed to have less than 50 ns mismatch. Although the gate-driver signal is quite symmetrical, it is still recommended to insert the dc blocking capacitor in the gate-driver transformer primary side to prevent transformer saturation during fast transients. VCC Connect a regulated bias supply to VCC pin. When VCC becomes above 10.5 V the device is enabled and after all fault conditions are cleared the gate driver starts with soft start. When VCC drops below 9.5 V, the device enters UVLO protection mode and both gate drivers are actively pulled low. When VCC rises above 20 V the device enters VCC over-voltage protection mode and the device is disabled with both gate drivers actively pulled low. VCC over-voltage protection will recover with soft start when VCC voltage returns below 18 V. Over-Temperature Protection UCC25600 continuously senses its junction temperature. When its junction temperature rises above 160°C the device will enter over-temperature protection mode with both gate drivers actively pulled low. When junction temperature drops below 140°C, gate driver restarts with soft start. 18 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): UCC25600 PACKAGE OPTION ADDENDUM www.ti.com 23-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty UCC25600D ACTIVE SOIC D 8 UCC25600DR ACTIVE SOIC D UCC25600DRG4 ACTIVE SOIC D 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Mar-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC25600DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.4 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Mar-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC25600DR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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