UCC1919 UCC2919 UCC3919 application INFO available 3V to 8V Hot Swap Power Manager FEATURES DESCRIPTION • Precision Fault Threshold The UCC3919 family of Hot Swap Power Managers provide complete power management, hot swap, and fault handling capability. The UCC3919 features a duty ratio current limiting technique, which provides peak load capability while limiting the average power dissipation of the external pass transistor during fault conditions. The UCC3919 has two reset modes, selected with the TTL/CMOS compatible L/R pin. In one mode, when a fault occurs the IC repeatedly tries to reset itself at a user defined rate, with user defined maximum output current and pass transistor power dissipation. In the other mode the output latches off and stays off until either the L/R pin is reset or the shutdown pin is toggled. The on board charge pump circuit provides the necessary gate voltage for an external N-channel power FET. • Charge Pump for Low RDSON High Side Drive • Differential Sense Inputs • Programmable Average Power Limiting • Programmable Linear Current Control • Programmable Fault Time • Fault Output Indicator • Manual and Automatic Reset Modes • Shutdown Control w/Programmable Softstart • Undervoltage Lockout • Electronic Circuit Breaker Function BLOCK DIAGRAM VDD CSP 13 OVERLOAD COMPARATOR VDD OVERCURRENT COMPARATOR 12 50mV – + + 1.5v 10 GATE 7 FLT UVLO 200mV 1 DRIVER VDD UVLO + IMAX CAP + – + CSN 4 – LINEAR CURRENT AMPLIFIER + 14 CHARGE PUMP VDD 36µA IBIAS 1X 2 1X UVBIAS SET DOMINANT S Q R Q FLT SD PL 9 + CT 1.5V – 0.5V + S R GND S Q R Q Q 11 RESET DOMINANT 1.2µA SD Note: Pins shown for 14-pin package. 07/99 FLT Q 8 – UVBIAS 5 6 LR SD UDG-98123 UCC1919 UCC2919 UCC3919 CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS DIL-14, (Top View) N, J Packages VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 10V Pin Voltage (All pins except CAP and GATE). . . . . . –0.3V to VDD + 0.3V Pin Voltage (CAP and GATE) . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 15V PL Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5mA to –10mA IBIAS Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 3mA Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of package. IMAX 1 14 CSP IBIAS 2 13 VDD N/C 3 12 CSN CAP 4 11 GND L/R 5 10 GATE SD 6 9 PL FLT 7 8 CT SOIC-16, TSSOP-16 (Top View) D or PW Package IMAX 1 16 CSP IBIAS 2 15 VDD N/C 3 14 CSN CAP 4 13 GND L/R 5 12 GATE SD 6 11 PL N/C 7 10 N/C FLT 8 9 CT ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 5V, TA = 0°C to 70°C for the UCC3919, –40°C to 85°C for the UCC2919 and –55°C to 125°C for the UCC1919. All voltages are with respect to GND. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Supply Supply Current Shutdown Current VDD = 3V 0.5 1 mA VDD = 8V 1 1.5 mA SD = 0.2V 1 7 µA Undervoltage Lockout Minimum Voltage to Start 2.35 2.75 3 V Minimum Voltage after Start 1.9 2.25 2.5 V Hysteresis 0.25 0.5 0.75 V 25°C, referred to CSP 1.47 1.5 1.53 V Over Temperature Range, referred to CSP 1.44 1.5 1.56 V 1 2 IBIAS Output Voltage, (0 A < IOUT < 15 A) Maximum Output Current 2 mA UCC1919 UCC2919 UCC3919 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 5V, TA = 0°C to 70°C for the UCC3919, –40°C to 85°C for the UCC2919 and –55°C to 125°C for the UCC1919. All voltages are with respect to GND. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Current Sense Over Current Comparator Offset Referred to CSP, 3V ≤VDD ≤ 8V –55 –50 –45 mV Linear Current Amplifier Offset VIMAX = 100mV, Referred to CSP, 3V ≤VDD ≤ 8V –120 –100 –80 mV VIMAX = 400mV, Referred to CSP, 3V ≤VDD ≤ 8V –440 –400 –360 mV VIMAX = 100mV, Referred to CSP, 3V ≤VDD ≤ 8V –360 –300 –240 mV CSN Input Common Mode Voltage Range Referred to VDD, 3V ≤VDD ≤ 8V, (Note 1) –1.5 0.2 V CSP Input Common Mode Voltage Range Referred to VDD, 3V ≤VDD ≤8V, (Note 1) 0 0.2 V Overload Comparator Offset Input Bias Current CSN 1 5 µA Input Bias Current CSP 100 200 µA Current Fault Timer CT Charge Current VCT = 1V –56 –35 –16 µA CT Discharge Current VCT = 1V 0.5 1.2 1.9 µA On Time Duty Cycle in Fault IPL = 0 1.5 3 6 % CT Fault Threshold 1.0 1.5 1.7 V CT Reset Threshold 0.25 0.5 0.75 V –1 0 1 µA –1.0 –1.4 –1.9 V IPL = –1.5mA, Referred to VDD –0.5 –1.8 –2.2 V IPL = –250µA 0.25 0.5 1 % IPL = –1.5mA 0.05 0.1 0.2 % 0.8 V IMAX Input Bias Current VIMAX = 100mV, Referred to CSP Power Limiting Section Voltage on PL On Time Duty Cycle in Fault IPL = –250µA, Referred to VDD SD and L/R Inputs Input Voltage Low Input Voltage High 2 L/R Input Current SD Internal Pulldown Impedance V µA 1 3 6 100 270 500 k FLT Output Output Leakage Current VDD = 5V 10 µA Output Low Voltage IOUT = 10mA 1 V –0.25 mA FET GATE Driver and Charge Pump Peak Output Current VCAP = +15V, VGATE = 10V Peak Sink Current VGATE = 5V –3 –1 20 Fault Delay mA 100 300 VDD = 3V, Average IOUT = 1µA 8 10 12 V VDD = 8V, Average IOUT = 1µA 12 14 16 V Charge Pump UVLO Minimum Voltage to Start VDD = 3V 6.5 7.5 V VDD = 8V 6.5 8 V Charge Pump Source Impedance VDD = 5V, Average IOUT = 1µA 50 100 Maximum Output Voltage Note 1: Guaranteed by design. Not 100% tested in production. 3 150 nS kΩ UCC1919 UCC2919 UCC3919 PIN DESCRIPTIONS CAP: A capacitor is placed from this pin to ground to filter the output of the on board charge pump. A .01µF to 0.1µF capacitor is recommended . stable with up to .001µF of capacitance. The bypass must be to CSP, since the bias voltage is generated with respect to CSP. Resistor R2 (Figure 4) should be greater than 50k to minimize the effect of the finite input impedance of the IBIAS pin on the IMAX threshold. CSN: The negative current sense input signal. CSP: The positive current sense input signal. IMAX: Used to program the maximum allowable sourcing current. The voltage on this pin is with respect to CSP. If the voltage across the shunt resistor exceeds this voltage the linear current amplifier lowers the voltage at GATE to limit the output current to this level. If the voltage across the shunt resistor goes more than 200mV beyond this voltage, the gate drive pin GATE is immediately driven low and kept low for one full off time interval. CT: Input to the duty cycle timer. A capacitor is connected from this pin to ground, setting the off time and the maximum on time of the overcurrent protection circuits. FLT: Fault indicator. This open drain output will pull low under any fault condition where the output driver is disabled. This output is disabled when the IC is in low current standby mode. L/R: Latch/Reset. This pin sets the reset mode. If L/R is low and a fault occurs the device will begin duty ratio current limiting. If L/R is high and a fault occurs, GATE will go low and stay low until L/R is set low. This pin is internally pulled low by a 3µA nominal pulldown. GATE: The output of the linear current amplifier. This pin drives the gate of an external N-channel MOSFET pass transistor. The linear current amplifier control loop is internally compensated, and guaranteed stable for output load (gate) capacitance between 100pF and .01µF. In applications where the GATE voltage (or charge pump voltage) exceeds the maximum Gate-to-Source voltage ratings (VGS) for the external N-channel MOSFET, a Zener clamp may be added to the gate of the MOSFET. No additional series resistance is required since the internal charge pump has a finite output impedance of 100k typical. PL: Power Limit. This pin is used to control average power dissipation in the external MOSFET. If a resistor is connected from this pin to the source of the external MOSFET, the current in the resistor will be roughly proportional to the voltage across the FET. As the voltage across the FET increases, this current is added to the fault timer charge current, reducing the on time duty cycle from its nominal value of 3% and limiting the average power dissipation in the FET. GND: The ground reference for the device. SD: Shutdown pin. If this pin is taken low, GATE will go low, and the IC will go into a low current standby mode and CT will be discharged. This TTL compatible input must be driven high to turn on. IBIAS: Output of the on board bias generator internally regulated to 1.5V below CSP. A resistor divider between this pin and CSP can be used to generate the IMAX voltage. The bias circuit is internally compensated, and requires no bypass capacitance. If an external bypass is required due to a noisy environment, the circuit will be VDD: The power connection for the device. APPLICATION INFORMATION nal MOSFET will be turned off. It will either be latched off (until the power to the circuit is cycled, the L/R pin is taken low, or the SD pin is toggled), or will retry after a fixed off time (when CT has discharged to 0.5V), depending on whether the L/R pin is set high or low by the user. The equation for this current threshold is simply: The UCC3919 monitors the voltage drop across a high side sense resistor and compares it against three different voltage thresholds. These are discussed below. Figure 1 shows the UCC3919 waveforms under fault conditions. Fault Threshold IFAULT = The first threshold is fixed at 50mV. If the current is high enough such that the voltage on CSN is 50mV below CSP, the timing capacitor CT begins to charge at about 35µA if the PL pin is open. (Power limiting will be discussed later). If this threshold is exceeded long enough for CT to charge to 1.5V, a fault is declared and the exter- 0 .05 (1) R SENSE The first time a fault occurs, CT is at ground, and must charge 1.5V. Therefore: t FAULT = t ON (sec) = 4 CT (µF ) • 1.5 35 (2) UCC1919 UCC2919 UCC3919 APPLICATION INFORMATION In the retry mode, the timing capacitor will already be charged to 0.5V at the end of the off time, so all subsequent cycles will have a shorter ton time, given by: t FAULT ≅ t ON (sec) = CT (µF ) reduces the voltage on GATE to control the external MOSFET in a constant current mode. During this time CT is charging, as described above. If this condition lasts long enough for CT to charge to 1.5V, a fault will be declared and the MOSFET will be turned off. The IMAX current is calculated as follows: (3) 35 Note that these equations for ton are without the power limiting feature (RPL pin open). The effects of power limiting on ton will be discussed later. IMAX = CT µF 1. 2 (4) Overload Threshold There is a third threshold which, if exceeded, will declare a fault and shutdown the external MOSFET immediately, without waiting for CT to charge. This “Overload” threshold is 200mV greater than the IMAX threshold (again, this is with respect to CSP). This feature protects the circuit in the event that the external MOSFET is on, with a load current below IMAX, and a short is quickly applied across the output. This allows hot-swapping in cases where the UCC3919 is already powered up (on the backplane) and capacitors are added across the output bus. In this case, the load current could rise too quickly for the linear amplifier to reduce the voltage on GATE and limit the current to IMAX. If the overload threshold is reached, the MOSFET will be turned off quickly and a fault declared. A latch is set so that CT can be charged, guaranteeing that the MOSFET will remain off for the same period as defined above before retrying. The overload current is: Shutdown Characteristics When the SD pin is set to TTL high (above 2V) the UCC3919 is guaranteed to be enabled. When SD is set to a low TTL (below 0.8V) the UCC3919 is guaranteed to be disabled, but may not be in ultra low current sleep mode. When SD is set to 0.2V or less, the UCC3919 is guaranteed to be disabled and in ultra low current sleep mode. See Fig. 1. 1.e-02 1.e-03 ICC 1.e-04 1.e-05 1.e-06 IOVERLOAD = 1.e-07 0.25 0.5 0.75 1 VSD 1.25 1.5 1.75 VCSP – VIMAX + 0 . 2 0.2 = IMAX + R SENSE R SENSE (6) Note that IOVERLOAD may be much greater than IMAX, depending on the value of RSENSE. 1.e-08 0 (5) Note that if the voltage on the IMAX pin is programmed to be less than 50mV below CSP, then the UC3919 will control the MOSFET in a constant current mode all the time. No fault will be declared and the MOSFET will remain on because IMAX is less than IFAULT. The off time in the retry mode is set by CT and an internal 1.2µA sink current. It is the time it takes CT to discharge from 1.5V to 0.5V. The equation for the off time is therefore: t OFF (sec) = VCSP – VIMAX R SENSE 2 Power Limiting Figure 1. Typical Shutdown Current A power limiting feature is included which allows the power dissipated in the external MOSFET to be held relatively constant during a short, for different values of input voltage. This is accomplished by connecting a resistor from the output (source of the external MOSFET) to PL. When the output voltage drops due to a short or overload, an internal bias current is generated which is equal to: IMAX Threshold The second threshold is programmed by the voltage on IMAX (measured with respect to the CSP pin). This controls the maximum current, IMAX, that the UCC3919 will allow to flow into the load during the MOSFET on time. A resistive divider connected between IBIAS and CSP generates the programming voltage. When the drop across the sense resistor reaches this voltage, a linear amplifier IPL ≅ 5 (VIN – VOUT – VPL ) RPL (7) UCC1919 UCC2919 UCC3919 APPLICATION INFORMATION (cont.) PDISS = IMAX • VIN • 0 .033 This current is used to help charge the timing capacitor in the event that the load current exceeds IFAULT. (A simplified schematic of the circuit internal to the UCC3919 is shown in Figure 2.) The result is that the on time of the MOSFET during current limit is reduced as the input voltage is increased. This reduces the effective duty cycle, holding the average power dissipated constant. Calculating CT(min) for a Given Load Capacitance without Power Limiting To guarantee recovery from an overload when operating in the retry mode, there is a maximum total output capacitance which can be charged for a given tON (fault time) before causing a fault. For a worst case situation of a constant current load below the fault threshold, CT(min) for a given output load capacitance (without power limiting) can be calculated from: VDD VDD UCC3919 POWER LIMIT 1X 1X CT (min) = SD TO GATE FLT IPL TO LOAD Figure 2. Power limiting circuit. It can be seen that power limiting will only occur when IPL is > 0 (it cannot be negative). For power limiting to begin to occur, the voltage drop across the MOSFET must be greater than VDD-VPL or 1.4V(typ). CT (min) = CT • ∆V IPL + 35 • 10 −6 where V = 1V (9) PDISS = IMAX • VIN • 1. 2 • 10 −6 IPL + 35 • 10 (13) 28 • 10 3 Estimating CT(min) When Using Power Limiting If power limiting is used, the calculation of CTmin for a given COUT becomes considerably more complex, especially with a resistive load. This is because the CT charge current becomes a function of VOUT, which is changing with time. The amount of capacitance that can be charged (without causing a fault) when using power limiting will be significantly reduced for the same value CT, due to the shorter ton time. The graph in Figure 4 illustrates the effect of RPL on the average MOSFET power dissipation into a short. The equation for the average power dissipation during a short is: PDISS = VIN −COUT • RL • n 1 − IMAX • RL Note that in the latch mode (or when first turning on in the retry mode), since the timing capacitor is not recovering from a previous fault, it is charging from 0V rather than 0.5V. This allows up to 50% more load capacitance without causing a fault. (8) The on time using RPL is defined as: t ON = (12) For a resistive load of value RL and an output cap COUT, CTmin can be smaller than in the constant current case, and can be estimated from: UGD-98124 VIN − VOUT ≥1. 4V VIN • COUT • 35 • 10 −6 IMAX − ILOAD A larger load capacitance or a smaller CT will cause a fault when recovering from an overload, causing the circuit to get stuck in a continuous hiccup mode. To handle larger capacitive loads, increase the value of CT. The equation can be easily re-written, if desired, to solve for COUT(max) for a given value of CT. CT RPL PL (11) −6 , or (10) IMAX • VIN • t ON t ON + t OFF The charge current contribution from the power limiting circuit is defined as: If PL is left unconnected, the power limiting feature will not be exercised. In the retry mode, the duty cycle during a fault will be nominally 3%, independent of input voltage. The average power dissipation in the external MOSFET with a shorted output will be proportional to input voltage, as shown by the equation: IPL ≅ 6 (VIN − VOUT RPL − VPL ) (14) UCC1919 UCC2919 UCC3919 APPLICATION INFORMATION (cont.) UDG-97073 t0: Normal condition - Output current is nominal, output voltage is at positive rail, VCC. goes low, the FET turns off allowing no output current to flow, VOUT discharges to GND. t1: Fault control reached - Output current rises above the programmed fault value, CT begins to charge with 35µA + IPL. t4: Retry - CT has discharged to 0.5V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT increases. t2: Maximum current reached - Output current reaches the programmed maximum level and becomes a constant current with value IMAX. t3 to t5: Illustrates <3% duty cycle depending upon RPL selected. t6 = t4 t7: Fault released, normal condition - return to normal operation of the circuit breaker t3: Fault occurs - CT has charged to 1.5V, fault output Figure 3. Typical Timing Diagram 7 UCC1919 UCC2919 UCC3919 APPLICATION INFORMATION (cont.) Constant Current Load IPL (avg ) ≅ 2 POWER DISSIPATION (Watts) For a constant current load, the output capacitor will charge linearly. During that time: (VIN − VPL ) (15) 2 • RPL • VIN Modifying equation (12) yields: VIN • COUT CT (min) ≅ 2 (16) (VIN − VPL ) −6 • + 35 • 10 2 • RPL • VIN IMAX − ILOAD VOUT (t ) = IMAX • RLOAD 24.9K 0.2 20K 0.15 15K 0.1 10K 0.05 1 2 3 4 VDD (Volts) 5 6 Figure 4. MOSFET average short circuit power dissipation vs. VIN for values of RPL. Determining CT(min) for a resistive load is more complex. First, the expression for the output voltage as a function of time is: RPL= 0.25 0 Resistive Load T START − R LOAD • COUT 1 − e For IMAX=7A 0.3 TSTART = (18) VIN − RLOAD • COUT • n 1 − IMAX • RLOAD (17) Assuming that the device is operating in the retry mode, where CT is charging from 0.5V to just below 1.5V in time t, CT is defined as: Solving for TSTART when VOUT = VIN yields: CT = ICT • dt = ICT • dt Where dV ICT = (IPL + 35 • 10 −6 ) (19) CIN VIN R1 4.99k 1 IMAX R2 100k CSP 14 VDD 13 2 IBIAS CSN 12 3 N/C GND 11 4 CAP GATE 10 5 L/R PL 9 0.01Ω 0.01µF 6 SD 7 FLT RPL 10k VOUT CT 0.01µF CT COUT RLOAD 8 UDG-98137 Figure 5. Application circuit. 8 UCC1919 UCC2919 UCC3919 APPLICATION INFORMATION (cont.) For a worst case 5A constant current load: COUT(max) ≅ 27µF. Substituting equation (15) into (19) yields: 2 (VIN − VPL ) −6 CT (min) = + 35 • 10 • dt 2 • RPL • VIN (20) With L/R grounded, the part will operate in the retry or “hiccup” mode. The values shown for CT and RPL will yield a nominal duty cycle of 0.32% and an off time of 8.3ms. With a shorted output, the average steady state power dissipation in Q1 will be less than 100mW over the full input voltage range. This yields the following expression for CT(min) for a resistive load with power limiting. By substituting the value calculated for TSTART in equation (18) for dt, CT(min) is determined. 2 (VIN • VPL ) −6 CT (min) = + 35 • 10 • TSTART 2 • RPL • VIN If power limiting is disabled by opening RPL, then: (21) t FAULT = t ON sec = PDISS (shorted ) = Example The example in Figure 5 shows the UCC3919 in a typical application. A low value sense resistor and N-channel MOSFET minimize losses. With the values shown for R1, R2, and RS, the overcurrent fault will be 5A nominal. Linear current limiting (IMAX) will occur at 7.14A and the overload comparator will trip at 27A. The calculations are shown below. IFAULT = IMAX = 0.05 0.05 = = 5A R S 0.01 0.2 0.2 = 714 . A+ = 27.14A RS 0.01 IPL (typ ) (output shorted ) = THERMAL CONSIDERATIONS In normal operation, with a steady state load current below IFAULT, the power dissipation in the external MOSFET will be: (23) PDISS = RDS ON • ILOAD 2 (24) TJ = TA + (PDISS • θ JA ) IPL + 35 • 10 = 0.01 • 10 375 µA θ JA + θ JC + θCS + θ SA (33) (27) Where JC is the MOSFET’s thermal resistance from junction to case, θCS is the thermal resistance from case to sink, and θSA is the thermal resistance of the heatsink to ambient. (28) The calculated TJ must be lower than the MOSFET’s maximum junction temperature rating, therefore: −6 = 27 µs IMAX • VIN • t ON t ON + t OFF 714 . • 5 • 27 µs = 0.12W = 27 µs + 8.33 • 10 −3 PDISS ( shorted ) = (32) Where TA is the ambient temperature and θJA is the MOSFET’s thermal resistance from junction to ambient. If the device is on a heatsink, then the following equation: (26) t ON ( shorted ) = (31) The junction temperature of the MOSFET can be calculated from: (25) 5 − 1.6 = = 340µA 10k −6 714 . • 5 • 287 • 10 −6 = 1. 2W (withVIN = 5V ) 287 • 10 −6 + 8.33 • 10 −3 For a worst case 5A constant current load: COUT(max) ≅ 120µF. With the value shown for RPL: CT (30) Steady State Conditions CT µF 0.01 TOFF (sec) = = = 8.33 ms 1. 2 1. 2 VIN − VPL RPL IMAX • VIN • t ON t OFF + t ON (29) For a worst case 1Ω resistive load: COUT(max) ≅ 220µF. (22) VCSP − VIMAX 1.5 • R1 = = 714 . A ( RS R1 + R 2) • R S IOVERLOAD = IMAX + = CT µF • 1 = 287 µs 35 θ JA < For a worst case 1Ω resistive load: COUT(max) ≅ 47µF. 9 TJ (max) − TA PDISS (34) UCC1919 UCC2919 UCC3919 APPLICATION INFORMATION This effective transient thermal impedance, when multiplied by the pulse power, will give the transient temperature rise of the die. To keep the junction temperature below the maximum rating, the following must be true: Transient Thermal Impedance During a fault condition in the retry mode, the average MOSFET power dissipation will generally be quite low due to the low duty cycle, as defined by: IMAX • VIN • t ON (35) (w/output shorted) PDISS (avg ) = t ON + t OFF θ JC (trans ) = However, the pulse power in the MOSFET during tON, with the output shorted, is: (36) Safety Recommendations In choosing tON for a given VIN, IMAX, and duty cycle it is important to consult the manufacturer’s transient thermal impedance curves for the MOSFET to make sure the device is within its safe operating area. These curves provide the user with the effective thermal impedance of the device for a given time duration pulse and duty cycle. Note that some of the impedance curves are normalized to one, in which case the transient impedance values must be multiplied by the DC (steady state) thermal resistance, θJC. Although the UCC3919 is designed to provide system protection for all fault conditions, all integrated circuits can ultimately fail short. for this reason, if the UCC3919 is intended for use in safety critical applications where UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series with the device. The UCC3919 will prevent the fuse from blowing for virtually all fault conditions, increasing system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device. For duty cycles not shown in the manufacturer’s curves, the transient thermal impedance for any duty cycle and ton time (given a square pulse) can be estimated from [1]: θ JC (trans ) = (D • θ JC ) + (1 − D ) • θ SP where D is the duty cycle: PDISS (pulse ) (38) If necessary, the junction temperature rise can be reduced by reducing ton (using a smaller value for CT), or by reducing the duty cycle using the power limiting feature already discussed. Note that in either case, the amount of load capacitance, COUT, that can be charged before causing a fault, will also be reduced. (In the latch mode, tOFF will be the time between a fault and the time the device is reset.) PDISS ( pulse ) = IMAX • VIN (w/output shorted) TJ (max) − TC References [1] (37) t ON . t ON + t OFF and θSP is the single pulse thermal impedance given in the transient thermal impedance curves for the time duration of interest (tON). Note that these are absolute numbers, not normalized. If the given single pulse impedance is normalized, it must first be multiplied by θJC before using in the equation above. UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 10 International Rectifier, HEXFET Power MOSFET Designer’s Manual, Application Note 949B, Current Ratings, Safe Operating Area, and High Frequency Switching Performance of Power HEXFETs, pp.1553-1565, September 1993. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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