UCC1570 UCC2570 UCC3570 Low Power Pulse Width Modulator FEATURES DESCRIPTION • Low Power BiCMOS Process The UCC1570 family of pulse width modulators is intended for application in isolated switching supplies using primary side control and a voltage mode feedback loop. Made with a BiCMOS process, these devices feature low startup current for efficient off-line starting with a bootstrapped low voltage supply. Operating current is also very low; yet these devices maintain the ability to drive a power MOSFET gate at frequencies above 500kHz. • 85µA Start-up Current • 1mA Run Current • 1A Peak Gate Drive Output • Voltage Feed Forward Voltage feedforward provides fast and accurate response to wide line voltage variation without the noise sensitivity of current mode control. Fast current limiting is included with the ability to latch off after a programmable number of repetitive faults has occurred. This allows the power supply to ride through a temporary overload, while still shutting down in the event of a permanent fault. Additional versatility is provided with a maximum duty cycle clamp programmable within a 20% to 80% range and line voltage sensing with a programmable window of allowable operation. • Programmable Duty Cycle Clamp • Optocoupler Interface • 500kHz Operation • Soft Start • Fault Counting Shutdown • Fault Latch Off or Automatic Restart BLOCK DIAGRAM CLK CLOCK GENERATOR FREQ 11 4.5V RAMP VALLEY 1V VFWD 6 10 I3 5V GENERATOR SLOPE 7 S RAMP LATCH I3 RAMP 10 1V 12 VREF 13 GND R 15V 10 I4 13/9V ISET 9 I4 4V HIGH LINE 4V RAMP PEAK 3 VCC LOW LINE S 1V FEEDBK 8 I4 PWM PWM LATCH CURRENT LIMIT CURLIM 2 I4 0.2V SD CLK R R SD 1 4V SHUTDOWN 0.6V 04/99 OUT RD SOFTST 14 COUNT 4 SHUTDOWN LATCH 5 PGND UCC1570 UCC2570 UCC3570 ABSOLUTE MAXIMUM RATINGS CONNECTION DIAGRAMS Supply Voltage (Limit Supply Current to 20mA) . . . . . . . Self Limiting at 15V Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20mA Analog Inputs (CURLIM, VFWD, FEEBK) . . . . . . . . . . . . . . 6V Programming Current ISLOPE, IISET . . . . . . . . . . . . . . . . . –1mA Output Current IOUT DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±180mA Pulse (0.5ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1.2A DIL-14 (TOP VIEW) N or J Package Note: All voltages are with respect to GND. Currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of package. PLCC-20 (TOP VIEW) Q Package SOIC-14 (TOP VIEW) D Package ORDERING INFORMATION UCC1570J UCC2570D UCC2750N UCC3570D UCC3570N UCC3570Q Temperature Range –55°C to +125°C –40°C to +85°C 0°C to +70°C Package Ceramic Dip SOIC Plastic Dip SOIC Plastic Dip PLCC ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0 to 70°C for the UCC3570, TA= –40 to 85°C for the UCC2570, TA=–55 to 125°C for the UCC1570, RISET=100k, RSLOPE=121k, CFREQ=180pF, CRAMP=150pF, VCC=11V and TA=TJ. PARAMETER Reference VREF Line Regulation Load Regulation Short Circuit Current VCC Vth (On) Vth (Off) Hysteresis VCC IVCC Start IVCC Run TEST CONDITIONS Min Typ Max Units VCC =10 to 13V, IVREF = 0 to 2mA 4.9 5 2 2 10 5.1 10 10 50 V mV mV mA 12 8 3 13.5 13 9 4 15 85 1 10 5 16 150 1.5 V V V V µA mA VCC = 10 to 13V IVREF = 0 to 2mA VREF = 0 IVCC = 10mA VCC = 11V, VCC Comparator Off VCC Comparator On 2 UCC1570 UCC2570 UCC3570 ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for TA = 0 to 70°C for the UCC3570, TA= –40 to 85°C for the UCC2570, TA=–55 to 125°C for the UCC1570, RISET=100k, RSLOPE=121k, CFREQ=180pF, CRAMP=150pF, VCC=11V and TA=TJ. PARAMETER TEST CONDITIONS Line Sense Vth High Line Comparator Vth Low Line Comparator lib (VFWD) Oscillator Frequency Ramp Generator IRAMP/ISLOPE –IRAMP/IISET Peak Ramp Voltage Valley Ramp Voltage ISET Voltage Level Soft Start Saturation ISOFTST/IISET Pulse Width Modulator lib(FEEDBK) FEEDBK Typ Max Units 3.9 0.96 4 1 0 4.1 1.04 ±100 V V nA 90 100 110 kHz 9 9 3.8 0.95 0.95 10 10 4 1 1 11 11 4.2 1.05 1.05 A/A A/A V V V 0.8 25 1 100 1.2 mV A/A 0.9 3.8 0 1 4 ±100 1.1 4.2 nA V V 180 500 0 200 600 ±100 220 700 nA mV mV 4 0 1 4.2 100 1.2 V mV A/A 0.4 0.4 20 1 1 100 V V ns VCC = 11V, VCC Comparator Off Zero Duty Cycle Maximum Duty Cycle, (Note 1) Current Limit lib(CURLIM) Vth Current Limit Vth Shutdown Fault Counter Vth Vsat ICOUNT/IISET Output Driver Vsat High Vsat Low Rise/Fall Time Min 3.8 0.8 IOUT = –100mA IOUT = 100mA COUT = 1nF, (Note 1) Note 1: This parameter guaranteed by design but not 100% tested in production. PIN DESCRIPTIONS VFWD: Voltage Feed Forward and Line Sense pin. Connect to input DC line using a resistive divider. VCC: Chip supply voltage pin. Bypass to PGND with a low ESL/ESR 0.1µF capacitor plus a capacitor for gate charge storage. Lead lengths must be minimum. SLOPE: Program the charging current for RAMP with a resistor from this pin to GND. This pin will follow VFWD. PGND: Ground pin for the output driver. Keep connections less than 2cm. Carefully maintain low impedance path for high current return. FEEDBK: Input to the pulse width modulator comparator. Drive this pin with an optocoupler to GND and a resistor to VREF. Modulation input range is from 1V to 4V. OUT: Gate drive output pin. Connect to the gate of a power MOSFET with a resistor greater than 2Ω. Keep connection lengths under 2cm. ISET: A resistor from this pin to GND programs RAMP discharge current, FREQ current, SOFTST current, and COUNT current. 3 UCC1570 UCC2570 UCC3570 PIN DESCRIPTIONS (cont.) GND: Analog ground. Connect to a low impedance ground plane containing all analog low current returns. RAMP: Ramp Pin. Connect a capacitor to GND. Rising slope is programmed by current in SLOPE. This slope is compared to FEEDBK for pulse width modulation. The falling slope is programmed by the current in ISET and used to limit maximum duty cycle. SOFTST: Soft start pin. Program with a capacitor to GND. COUNT: Program the time that fault events will be tolerated before shutdown occurs with a capacitor and resistor to GND. FREQ: Oscillator pin. Program the frequency with a capacitor to GND. VREF: Precision 5V reference, and bypass point for internal circuitry. Bypass this pin with a 1µF minimum capacitor to GND. CURLIM: Current Limit Sense pin. Terminates OUT gate drive pulse for inputs over 0.2V. Enables fault counting function (COUNT). For inputs over 0.6V, the shutdown latch is activated. APPLICATION INFORMATION (Note: Refer to Typical Application for external component names.) All the equations given below should be considered as first order approximations with final values determined empirically for a specific application. Output Inhibit During normal operation, OUT is driven high at the start of a clock period and back low when RAMP either crosses FEEDBK or equals 4V. If, however, any of the following occur, OUT is immediately driven low for the remainder of the clock period: Power Sequencing VCC normally connects through a high impedance (R5) to the rectified line, with an additional path(R6) to a low voltage, bootstrap on the winding power transformer. VFWD normally connects to a divider (R1 and R2) from the rectified line. For circuit activation, all of the following considerations are required: 1. VFWD is outside the range of 1V to 4V 2. CURLIM is greater than 0.2V 3. FEEDBK or SOFTST is less than 1V Normal output pulses will not resume until the beginning of the next clock period in which none of the above conditions exist. 1. VFWD between 1V and 4V 2. VCC has been under 9V (to reset the shutdown latch) Current Limiting CURLIM is monitored by two internal comparators. The current limit comparator threshold is 0.2V. If the current limit comparator is triggered, OUT is immediately driven low and held low for the remainder of the clock cycle, providing pulse-by-pulse overcurrent control for excessive loads. This comparator also causes CF to be charged for the remainder of the clock cycle. The charging current is 3. VCC over 13V At this time, the circuit will activate. IVCC will increase from its start up value of 85µA to its run value of 1mA. The capacitor on SOFTST is charged with a current determined by: –I SOFTST = 1V . R4 –ICOUNT = When SOFTST rises above 1V, output pulses will begin and IVCC will further rise to a level dictated by gate charge requirements asIVCC ≈ 1mA + QTfs. With output pulses, the low voltage bootstrap winding should now power the controller. If VCC falls below 9V, the controller will turn off and the start sequence will reset and retry. 1V . R4 If repetitive cycles are terminated by the current limit comparator causing COUNT to rise above 4V, the shutdown latch is set. The COUNT integration delay feature will be bypassed by the shutdown comparator which has a 0.6V threshold. The shutdown comparator immediately sets the shutdown latch. RF in parallel with CF resets the COUNT integrator following transient faults. RF must be (4 • R 4) . greater than (1 − D MAX ) VCC Clamp An internal shunt regulator clamps VCC so that it will not exceed 15V. 4 UCC1570 UCC2570 UCC3570 APPLICATION INFORMATION (cont.) Choose R4 between 20k and 200k and CR greater than 50pF. In order to have a pulse at OUT in the next clock period, RAMP must fall to 1V prior to the end of the current period. If it does not, OUT will remain low for the entire next clock period. Latched Shutdown If CURLIM rises above 0.6V, or COUNT rises to 4V, the shutdown latch will be set. This will force OUT low, discharge SOFTST and COUNT, and reduce IVCC to approximately 1mA. When, and if, VCC falls below 9V, the shutdown latch will reset and IVCC will fall to 85µA, allowing the circuit to restart. If VCC remains above 9V, an alternate restart will occur if VFWD is momentarily reduced below 1V. External shutdown commands from any source may be added into either the COUNT or CURLIM pins. Voltage Feedforward The +dV/dt on RAMP is made proportional to line voltage. The slope is: dV VFWD = 10 • dt (R 3 • C R ) Deadtime Control where VFWD is line voltage scaled by R1 and R2. Therefore, a changing line voltage will accomplish an immediate proportionate pulse width change without any action from the feedback amplifier. This will result in constant volt-second drive to the power transformer providing both international voltage operation, and excellent dynamic line regulation. VFWD is intended to operate over a 4:1 range (1V to 4V) with undervoltage and overvoltage sensors designed to drive OUT low if this range is exceeded. Choose R3 between 20k and 200k. The voltage waveform on RAMP has independently controlled rising and falling edges. At the start of the clock period, RAMP is at 1V and rises to 4V. It then discharges back to 1V and awaits the next clock period. OUT can only be high during the rising part of the waveform, while it is positively blanked off during the falling portion. Setting the –dV/dt slope by R4 from ISET to GND establishes a minimum deadtime as: td = 0. 3 • R 4 • C R Figure 1. UCC1570 typical application. 5 UCC1570 UCC2570 UCC3570 APPLICATION INFORMATION (cont.) be able to sink (4 • I4) with at a voltage less than the 3.5V upper threshold of the oscillator. It must also be able to source 36 • I4 at a voltage greater than the 1.5V lower threshold of the oscillator. As long as FREQ is held high, the output is guaranteed to be low. Frequency Set A capacitor from FREQ to GND will determine a constant clock frequency. Frequency is: F = 1. 8 R 4 ( • CT ) Gate Drive Output If required, frequency can be trimmed down from the above equation by the addition of RT from FREQ to GND. The reduction in frequency is a function of the ratio of RT/R4. RT should be greater than 2.4 • R4 for reliable operation. The UCC1570 is capable of 1A peak output current. Bypass VCC with at least 0.1µF directly to PGND. Use a capacitor with low equivalent series resistance and inductance. The connection from OUT to the MOSFET gate should have a 2Ω or greater damping resistor and the length should be minimized. A low impedance connection must be established between the MOSFET source (or the ground side of the current sense resistor), the VCC bypass capacitor and PGND. PGND should then be connected by a single path (shown as RGND in the application) to GND. External synchronization can be accomplished by coupling a narrow pulse to a resistor inserted in series with the ground side of CT. The value should be less than R4/200 and the synchronizing pulse width should be less than 5% of the oscillator period. External synchronization can also be accomplished by driving FREQ with an CMOS inverter. The inverter must CLOCK FEEDBK RAMP OUT HIGH VIN FAULT VIN LOW VIN Figure 2. Ramp and PWM waveforms. 6 UCC1570 UCC2570 UCC3570 APPLICATION INFORMATION (cont.) Figure 3. Clock generator. Figure 4. External clock synchronization. Figure 5. Frequency dependence on RT/ R4 ratio. 7 UCC1570 UCC2570 UCC3570 APPLICATION INFORMATION (cont.) UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 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