D SCSI SPI-2, SPI-3, SPI-4,
D
D
D
D
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
{DISCNCT1
{DISCNCT2
L21–
L21+
L20–
L20+
L19–
L19+
DIFSENS
DIFFB
L18–
L18+
L17–
L17+
L16–
L16+
L12+
L12–
L13+
L13–
L1+
L1–
L2+
L2–
L3+
L3–
L4+
L4–
L14+
L14–
L15+
L15–
PTRMPWR
REG
SGND
PGND
LVD
L10–
L10+
L11–
L11+
PM PACKAGE
(TOP VIEW)
L24+
L24–
L23+
L23–
L9+
L9–
L8+
L8–
L7+
L7–
L6+
L6–
L5+
L5–
D
D
Ultra160, Ultra320 Compliance
Smallest Footprint
Lowest Channel
L25–
Capacitance, 2 pF
L25+
Less than 0.5-pF Capacitance
L26–
Differential Between Pairs
L26+
2.7 V to 5.25 V Operation
L27–
Differential Failsafe Bias
L27+
64-Pin Low Profile QFP
STRMPWR
L22+
L22–
SLUS386B – FEBRUARY 2000 – REVISED APRIL 2001
{For the UCC5647, Pin 47 is DISCNCT1 and Pin 48 is DISCNCT2.
description
The UCC5646 is a twenty-seven line active terminator for low-voltage-differential (LVD) SCSI networks. This
LVD SCSI-only design allows the user to reach peak bus performance, while reducing system cost. The device
is designed as an active Y-terminator to improve the frequency response of the LVD SCSI Bus. Designed with
a 2-pF (typical) channel capacitance, the UCC5646 allows for minimal bus loading for a maximum number of
peripherals. With the UCC5646, the designer is able to comply with the Ultra2, Ultra3, Ultra160 and Ultra320
specifications. The UCC5646 also provides a much-needed system migration path for the ever improving SCSI
system standards.
This device is available in the 64-pin low-profile QFP package for ease of layout use.
Single-ended (SE) and high-voltage differential (HVD) SCSI drivers are not supported.
AVAILABLE OPTIONS
DISCONNECT
STATUS
TA
0°C to 70°C
REGULAR
PACKAGED DEVICES†
LOW PROFILE QFP
(PM)
UCC5646PM
REVERSE
UCC5647PM
† The PM package is available taped and reeled. Add TR suffix to
device type (e.g. UCC5646PMTR) to order quantities of 1000
devices per reel.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '! !"# %! &*)' '$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
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1
SLUS386B – FEBRUARY 2000 – REVISED APRIL 2001
block diagram
DIFSENS
40
–15mA≤ ISOURCE ≤ –5mA
50µA ≤ ISINK ≤ 200µA
*FOR THE UCC5647 PIN 47 IS DISCNCT1 AND PIN 48 IS DISCNCT2.
REF 1.3V
1.3V +/– 0.1V
2.15 V
DIFFB
+
HPD
39
12
LVD
+
STRMPWR
7
PTRMPWR
8
*DISCNCT1
*DISCNCT2
48
47
0.6V
SE
125
REF
1.25V
L10
L1
SOURCE/SINK
REGULATOR
L27
L9
52
– +
+56mV
MODE
ALL SWITCHES
SE
LVD
HVD
DISCNCT
OPEN
DOWN
OPEN
OPEN
22
L1–
21
L1+
5
L27–
6
L27+
52
+ –
+56mV
125
52
– +
+56mV
52
+ –
+56mV
10
11
9
SGND
PGND
REG
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†‡
Input voltage VIN (STRMPWR, PTRMPWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Signal line input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 5 V
Regulator output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 A
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals. Consult
Packaging Section of the Databook for thermal limitations and considerations of packages. All voltages are referenced to GND.
2
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SLUS386B – FEBRUARY 2000 – REVISED APRIL 2001
electrical characteristics over recommended operating free-air temperature range,
xTRMPWR = 2.7 V to 5.25 V, TA = 0_C to 70_C, DISCNCT1 = DISCNCT2 = 0 V for UCC5646,
DISCNCT1 = DISCNCT2 = open for UCC5647, TA = TJ, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
xTRMPWR Supply Current Section
LVD mode
xTRMPWR supply current
Disabled terminator
65
mA
500
µA
1.25 V Regulator Section
1.25 V regulator
0.5 V ≤ VCM ≤ 2.0 V,
Regulator source current
VREG = 0 V
Regulator sink current
VREG = 3.0 V
240
300
1.3 V regulator
–5mA ≤ IDIFSENS ≤ 50 µA
1.2
1.3
1.4
V
Short-circuit source current
VDIFSENS = 0 V
–5
–8
–15
mA
Short-circuit sinkcurrent
VDIFSENS = 2.75 V
50
200
µA
See Note 1
1.15
1.25
1.35
V
–300
–240
mA
mA
1.3 V (DIFSENS) Regulator Section
Differential Termination Section (Applies to each line pair 1–27)
Differential bias voltage
100
125
mV
Differential impedance
100
105
110
Ω
1.15
1.25
1.35
V
110
140
165
Ω
10
400
nA
3
pF
Common-mode bias voltage
L+ and L– shorted together
Common-mode impedance
L+ and L– shorted together,
See Note 2
SE measurement to GND,
See Note 3
Disconnected Termination Section
Output leakage current
Output capacitance
Disconnect Control (DISCNCT1) or (DISNCNT2) and DIFFB Input Section
DISCNCT threshold voltage
0.8
DISCNCT input current
VDISCNCT = 0 V and 2.0 V
DIFFB SE to LVD threshold voltage
DIFFB LVD to HPD threshold voltage
0 V ≤ VDIFFB ≤ 2.75 V,
DIFFB Input current
1.5
–30
2.0
V
–10
µA
V
0.5
0.6
0.7
1.9
2.05
2.2
V
10
µA
–4
mA
–10
Low-Voltage Differential (LVD) Status Bit Section
Source current
VLOAD = 2.4 V
Sink current
VLOAD = 0.4 V
–6
2
5
140
155
mA
Thermal Shutdown Section
Thermal shutdown threshold
For increasing temperature
Thermal shutdown hysteresis
10
170
_C
_C
NOTE 1: VCM is applied to all L+ and L– lines simultaneously.
2.0 V * 0.5 V
, VCM(max) = 2.0 V, VCM(min) = 0.5 V
+
CM
I
*I
VCM (max)
VCM (max)
NOTE 3: Ensured by design, not production tested.
NOTE 2: Z
ƪ
ƫ
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SLUS386B – FEBRUARY 2000 – REVISED APRIL 2001
pin descriptions
STRMPWR: 2.7 V to 5.25 V power supply for all circuitry except the 1.25-V regulator.
SGND: Ground reference for all circuitry except the 1.25-V regulator.
PTRMPWR: 2.7 V to 5.25 V power supply for the 1.25-V regulator.
PGND: Ground reference for the 1.25-V regulator.
REG: Output of the internal 1.25-V regulator; must be connected to a 4.7-µF bypass capacitor and a
high-frequency, low-ESR 0.01-µF capacitor to GND.
DIFSENS: Drives the SCSI bus DIFF SENSE line to 1.3 V to detect what types of devices are tied to the bus.
DIFFB: DIFF SENSE input pin. Connect through a 20-kΩ resistor to DIFSENS and through a 0.1-µF capacitor
to GND. Input to comparators that detect what type of drives are connected to the SCSI bus.
DISCNCT1: Disconnect one controls termination lines 10–27 (control and low byte).
DISCNCT2: Disconnect two controls termination lines 1–9 (high byte).
LVD: TTL compatible status bit indicating when low-voltage-differential voltage is present on DIFFB.
L1– thru L27–: Negative lines for the SCSI bus.
L1+ thru L27+: Positive lines for the SCSI bus.
4
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SLUS386B – FEBRUARY 2000 – REVISED APRIL 2001
UCC5646
L1+ 21
21 L1+
L1– 22
22 L1–
Termpower
7 STRMPWR
L9+ 60
60 L9+
L9– 59
59 L9–
4.7 µ F
12 LVD
L10+ 14
14 L10+
L10– 13
13 L10–
CONTROL AND
LOW BYTE
37 L18+
L18– 38
38 L18–
L19+ 41
41 L19+
L19– 42
42 L19–
0.01 µF
L27+ 6
6 L27+
L27– 5
5 L27–
DIFSENS 40
8
48
40
HIGH SIDE
PGND 11
DIFSENS
SGND 10
REG
DIFFB
DIFFB
REG
9
39
39
9
4.7 µ F
50 kΩ
0.01 µ F
DISCNCT2 47
HIGH SIDE
10 SGND
PTRMPWR
CONTROL AND
LOW BYTE
DATA (8)
+ PARITY LINES
11 PGND
7
DISCNCT1
L18+ 37
DISCNCT2
STRMPWR
4.7 µ F
DATA (8)
+ PARITY LINES
48 DISCNCT1
47
Termpower
CONTROL LINES (9)
8 PTRMPWR
0.01 µF
UCC5646
50 kΩ
4.7 µF
4.7 µF
4.7 µ F
0.01µ F
UDG–98202
Figure 1. Typical Application Diagram
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SLUS386B – FEBRUARY 2000 – REVISED APRIL 2001
6
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Copyright 2001, Texas Instruments Incorporated