MICROSEMI UFT12630

LTC1264-7
Linear Phase, Group Delay
Equalized, 8th Order
Lowpass Filter
U
DESCRIPTIO
FEATURES
■
■
■
■
■
■
■
Steeper Roll-Off Than Bessel Filters
High Speed: fC ≤ 200kHz
Phase Equalized Filter in a 14-Pin Package
Phase and Group Delay Response Fully Tested
Transient Response Exhibits 5% Overshoot and
No Ringing
65dB THD or Better Throughout a 100kHz Passband
No External Components Needed
UO
APPLICATI
■
■
■
S
The LTC1264-7 is a clock-tunable monolithic 8th order
lowpass filter with linear passband phase and flat group
delay. The amplitude response approximates a maximally
flat passband and exhibits steeper roll-off than an equivalent 8th order Bessel filter. For instance, at twice the cutoff
frequency the filter attains 28dB attenuation (vs 12dB for
Bessel), while at three times the cutoff frequency the filter
attains 55dB attenuation (vs 30dB for Bessel). The cutoff
frequency of the LTC1264-7 is tuned via an external TTL or
CMOS clock.
The clock-to-cutoff frequency ratio of the LTC1264-7 can
be set to 25:1 (pin 10 to V +) or 50:1 (pin 10 to V –).
Data Communication Filters
Time Delay Networks
Phase Matched Filters
When the filter operates at clock-to-cutoff frequency ratio
of 25:1, the input is double-sampled to lower the risk of
aliasing.
The LTC1264-7 is optimized for speed. Depending on the
operating conditions, cutoff frequencies between 200kHz
and 250kHz can be obtained. (Please refer to the Passband
vs Clock Frequency graphs.)
The LTC1264-7 is pin-compatible with the LTC1064-X
series.
UO
TYPICAL APPLICATI
4-Level PAM Eye Diagram
200kHz Linear Phase Lowpass Filter
8V
14
2
13
3
12
4
LTC1264-7
11
5
10
6
9
7
8
–8V
fCLK = 5MHz
8V
VOUT
1V/DIV
VIN
1
1264-7 TA01
NOTE: THE POWER SUPPLIES SHOULD BE BYPASSED BY A
0.1µF CAPACITOR CLOSE TO THE PACKAGE AND ANY PRINTED
CIRCUIT BOARD ASSEMBLY SHOULD MAINTAIN A DISTANCE
OF AT LEAST 0.2 INCHES BETWEEN ANY OUTPUT OR INPUT
PIN AND THE fCLK LINE.
500ns/DIV
1264-7 TA02
fCLK = 5MHz
fC = 200kHz
1
LTC1264-7
W W
W
AXI U
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ABSOLUTE
RATI GS (Note 1)
Total Supply Voltage (V + to V –) .......................... 16.5V
Power Dissipation............................................. 400mW
Burn-In Voltage ................................................... 16.5V
Voltage at Any Input ..... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V)
Storage Temperature Range ............... – 65°C to 150°C
Operating Temperature Range
LTC1264-7C ...................................... – 40°C to 85°C
LTC1264-7M ................................... – 55°C to 125°C
Lead Temperature (Soldering, 10 sec)................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
NC 1
16 OUT (C)
NC
1
14 OUT (C)
VIN
2
13 NC
VIN 2
15 NC
GND
3
12 V –
GND 3
14 V –
V+
4
11 fCLK
NC
5
10 25/50
LP (A)
6
9
VOUT
RIN (A)
7
8
NC
J PACKAGE
14-LEAD CERAMIC DIP
LTC1264-7CN
LTC1264-7CJ
LTC1264-7MJ
V+
LTC1264-7CS
13 NC
4
NC 5
12 fCLK
NC 6
11 25/50
10 NC
LP (A) 7
VOUT
9
RIN (A) 8
N PACKAGE
14-LEAD PLASTIC DIP
ORDER PART
NUMBER
TOP VIEW
S PACKAGE
16-LEAD PLASTIC SOL
TJMAX = 150°C, θJA = 65°C/W (J )
TJMAX = 110°C, θJA = 65°C/W (N )
TJMAX = 110°C, θJA = 85°C/W
ELECTRICAL CHARACTERISTICS
VS = ±7.5V, RL = 10k, TA = 25°C, fCUTOFF = 100kHz or 50kHz, fCLK = 2.5MHz, TTL or CMOS level (maximum clock rise or fall
time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise specified.
PARAMETER
Passband Gain
Gain at 0.50 fCUTOFF (Note 3)
Gain at 0.75 fCUTOFF
Gain at fCUTOFF
Gain at 2.0 fCUTOFF
Gain with fCLK = 20kHz
Gain with fCLK = 400kHz, VS = ±2.375V
Gain with fCLK = 4MHz
Phase Factor (F )
Phase = 180° – F (f/fC)
(Note 1)
Phase Nonlinearity
(Note 1)
2
CONDITIONS
0.1Hz ≤ f ≤ 0.25 fCUTOFF
fTEST = 25kHz, (f CLK / fC) = 25:1
fTEST = 50kHz, (f CLK / fC) = 25:1
fTEST = 25kHz, (f CLK / fC) = 50:1
fTEST = 75kHz, (f CLK / fC) = 25:1
fTEST = 100kHz, (f CLK / fC) = 25:1
fTEST = 50kHz, (f CLK / fC) = 50:1
fTEST = 200kHz, (f CLK / fC) = 25:1
fTEST = 100kHz, (f CLK / fC) = 50:1
fTEST = 200Hz, (f CLK / fC) = 50:1
fTEST = 8kHz, (fCLK / fC) = 25:1
fTEST = 16kHz, (f CLK / fC) = 25:1
fTEST = 160kHz, VIN = 1VRMS
(fCLK / fC) = 25:1, TA = 0°C to 70°C
(fCLK / fC) = 25:1
(f CLK / fC) = 25:1, f ≤ fCUTOFF
(f CLK / fC) = 50:1, f ≤ fCUTOFF
(f CLK / fC) = 25:1, f ≤ fCUTOFF
(f CLK / fC) = 50:1, f ≤ fCUTOFF
(f CLK / fC) = 25:1, f ≤ fCUTOFF
(f CLK / fC) = 50:1, f ≤ fCUTOFF
(f CLK / fC) = 25:1, f ≤ fCUTOFF
(f CLK / fC) = 50:1, f ≤ fCUTOFF
●
●
●
●
●
●
●
●
MIN
TYP
MAX
UNITS
– 0.50
– 0.50
– 0.65
– 1.5
– 3.7
– 4.5
– 34
– 34
– 0.7
– 0.2
– 3.5
– 0.10
0.50
0.20
0.30
0.1
–1.9
– 2.3
– 20
– 27
0.1
0.5
– 1.4
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
– 0.15
–1.0
– 3.0
– 3.0
– 28
– 30
– 0.3
0.15
– 2.70
0.00 ±1.0
3.0
●
407 ± 2
388 ± 2
●
●
392
374
423
414
±1.0
±1.0
●
●
± 2.0
± 2.0
dB
dB
Deg
Deg
Deg
Deg
%
%
%
%
LTC1264-7
ELECTRICAL CHARACTERISTICS
VS = ±7.5V, RL = 10k, TA = 25°C, fCUTOFF = 100kHz or 50kHz, fCLK = 2.5MHz, TTL or CMOS level (maximum clock rise or fall
time ≤ 1µs) and all gain measurements are referenced to passband gain, unless otherwise specified.
PARAMETER
Group Delay (td)
td = (F / 360)(1/fC);
(Note 2, 3)
Group Delay Ripple
(Note 2)
Input Frequency Range
(Table 9, 10)
Maximum fCLK
Clock Feedthrough
Wideband Noise
(1Hz ≤ f < fCLK)
Input Impedance
Output DC Voltage Swing
(Note 4)
Output DC Offset
(fCLK = 1MHz)
Output DC Offset TempCo
Power Supply Current
(fCLK = 1MHz)
CONDITIONS
(f CLK / fC) = 25:1, f ≤ fCUTOFF
(f CLK / fC) = 50:1, f ≤ fCUTOFF
(f CLK / fC) = 25:1, f ≤ fCUTOFF
(f CLK / fC) = 50:1, f ≤ fCUTOFF
(f CLK / fC) = 25:1, f ≤ fCUTOFF
(f CLK / fC) = 50:1, f ≤ fCUTOFF
(f CLK / fC) = 25:1, f ≤ fCUTOFF
(f CLK / fC) = 50:1, f ≤ fCUTOFF
(f CLK / fC) = 25:1
(f CLK / fC) = 50:1
VS = Single 5V (GND = 2V)
VS = ±5V
VS = ±7.5V
25:1, ±7.5V, f = fCLK
VS = Single 5V
VS = ±5V
VS = ±7.5V
MIN
TYP
11.3
21.6
10.9
20.8
●
●
11.7
22.9
±1.0
±1.0
±2.0
±2.0
●
●
<fCLK
<fCLK /2
2
3
5
120
140 ± 5%
160 ± 5%
175 ± 5%
50
±1.0
±2.3
±3.8
±100
±100
±200
±200
11
30
VS = ±2.375V
VS = ±5V
VS = ±7.5V
25:1, VS = ±5V
50:1, VS = ±5V
25:1, VS = ±5V
50:1, VS = ±5V
VS = ±2.375V
MAX
±2.0
±3.0
●
●
75
±220
±220
22
22
23
26
28
32
±8
●
VS = ±5V
14
●
VS = ±7.5V
17
●
±2.375
Power Supply Range
180
fCLK = 2.5MHz
(fCLK /fC) = 25:1
90
PHASE (DEG)
The ● denotes specifications which apply over the full operating temperature range.
Note 1: Input frequencies, f, are linearly phase shifted through the filter as long as f ≤ fC;
fC = cutoff frequency.
Figure 1 curve (A) shows the typical phase response of an LTC1264-7 operating at
fCLK = 2.5MHz, fC = 100kHz. An endpoint straight line, curve (B), depicts the ideal linear
phase response of the filter. It is described by: phase shift = 180° – F (f/fC); f ≤ fC.
F is arbitrarily called the “phase factor” expressed in degrees. The phase factor together
with the specified deviation from the ideal straight line allows the calculation of the phase
at a given frequency. Note, the maximum phase nonlinearity, Figure 1, occurs at the vicinity
of f = 0.25 fC and = 0.75 fC. Example: The phase shift at 70kHz of the LTC1264-7 shown in
Figure 1 is: phase shift = 180° – 407° (70kHz/100kHz) ± nonlinearity
=–
104.9° ± 1% or –104.9° ± 1.05°.
Note 2: Group delay and group delay deviation are calculated from the measured phase
factor and phase deviation specifications.
Note 3: The filter cutoff frequency is abbreviated as fCUTOFF or fC.
Note 4: The AC swing is typically 9VP-P, 5.6VP-P, 1.8VP-P with ± 7.5V, ±5V, ±2.5V supply
respectively. For more information refer to the THD + Noise vs Input graphs.
UNITS
µs
µs
µs
µs
%
%
%
%
kHz
kHz
MHz
MHz
MHz
µVRMS
µVRMS
µVRMS
µVRMS
kΩ
V
V
V
mV
mV
µV/°C
µV/°C
mA
mA
mA
mA
mA
mA
V
0
B
–90
A
–180
–270
–360
0 10 20
30 40 50 60 70 80 90 100
FREQUENCY (kHz)
LTC1264-7 F01
Figure 1. Phase Response in the Passband (Note 1)
3
LTC1264-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
10
–10
VS = ±7.5V
(fCLK /fC) = 25:1
450
–20
70°C
–40
50:1
–50
25:1
–60
25°C
430
420
0°C
410
–70
–80
400
10
100
FREQUENCY (kHz)
1000
410
0°C
400
380
370
390
1
25°C
420
390
–90
–100
70°C
430
PHASE FACTOR
–30
VS = ±7.5V
(fCLK /fC) = 50:1
440
440
PHASE FACTOR
GAIN (dB)
450
460
VS = ±7.5V
fCLK = 1MHz
TA = 25°C
0
Phase Factor vs fCLK
(Typical Unit)
Phase Factor vs fCLK
(Typical Unit)
Gain vs Frequency
0
3
2
fCLK (MHz)
1
5
4
1264-7 G01
0
3
2
fCLK (MHz)
1
1264-7 G02
Phase Factor vs fCLK (Min and
Max Representative Units)
425
VS = ±7.5V
(fCLK /fC) = 25:1
TA = 25°C
445
440
VS = ±5V
(fCLK /fC) = 25:1
TA = 25°C
420
PHASE FACTOR
PHASE FACTOR
435
430
425
420
415
415
410
405
410
405
400
400
395
395
0
1
3
2
fCLK (MHz)
4
5
0
0.5
1.0
1.5
2.0
fCLK (MHz)
2.5
3
180
2
135
2
135
1
90
1
90
0
45
0
45
0
–45
–2
–3
–90
PHASE
–135
VS = ±7.5V
fCLK = 2.5MHz
fC = 100kHz
(fCLK /fC) = 25:1
–3
–5
–6
–270
–7
10 20 30 40 50 60 70 80 90 100 110
FREQUENCY (kHz)
–7
1264-7 G06
–90
PHASE
–135
–4
–180
–6
0
–45
–2
–225
–5
GAIN
–1
VS = ±7.5V
fCLK = 2.5MHz
fC = 50kHz
(fCLK /fC) = 50:1
5
–180
–225
–270
10 15 20 25 30 35 40 45 50 55
FREQUENCY (kHz)
1264-7 G07
PHASE (DEG)
GAIN
–1
GAIN (dB)
180
PHASE (DEG)
GAIN (dB)
Passband Gain and Phase
3
–4
4
3.0
1264-7 G05
1264-7 G04
Passband Gain and Phase
5
1264-7 G03
Phase Factor vs fCLK (Min and
Max Representative Units)
450
4
LTC1264-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Passband Gain vs fCLK
Passband Gain vs fCLK
5
3
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
VS = ±7.5V
(fCLK /fC) = 50:1
TA = 25°C
4
3
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
E. fCLK = 5MHz
2
1
GAIN (dB)
GAIN (dB)
2
5
0
–1
–2
–3
C
D E
0
–1
–5
–5
100
FREQUENCY (kHz)
1000
B
C D E
100
FREQUENCY (kHz)
1000
10
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
Gain vs Frequency
10
0
–10
2
–20
–20
1
–30
–30
GAIN (dB)
–1
GAIN (dB)
0
–10
–40
–50
–60
–2
B
A
C
–3
–70
–4
–80
10
100
FREQUENCY (kHz)
VS = ±7.5V
fCLK = 5MHz
(fCLK /fC) = 25:1
TA = 25°C
5
0
4
–10
3
B
C
–80
GAIN (dB)
1
0
–1
B
C
FREQUENCY (kHz)
–5
B
–1
A. TA = 70°C
B. TA = –40°C
–2
VS = SINGLE 5V
fCLK = 2MHz
(fCLK /fC) = 25:1
AGND = 2V
–4
–5
100
10
200
FREQUENCY (kHz)
1264-7 G14
A
0
D
–4
200
1
–3
A
–3
100
10
2
–2
VS = SINGLE 5V
(fCLK /fC) = 25:1
AGND = 2V
TA = 25°C
–70
–90
A. fCLK = 0.5MHz
B. fCLK = 1MHz
C. fCLK = 2MHz
1000
Maximum Passband vs
Temperature
A. fCLK = 0.5MHz
B. fCLK = 1.0MHz
C. fCLK = 1.5MHz
D. fCLK = 2.0MHz
VS = SINGLE 5V
(fCLK /fC) = 25:1
AGND = 2V
TA = 25°C
2
–30
100
FREQUENCY (kHz)
1264-7 G13
GAIN (dB)
A
–60
10
Passband Gain vs fCLK
10
–50
–90
1000
1264-7 G12
Gain vs fCLK
–40
VS = ±5V
fCLK = 3MHz
(fCLK /fC) = 25:1
TA = 25°C
–80
1264-7 G11
–20
–50
–70
100
FREQUENCY (kHz)
10
1000
–40
–60
–90
–5
1000
1264-7 G10
Gain vs Frequency
0
100
FREQUENCY (kHz)
1264-7 G09
10
3
B
–5
Passband Gain vs fCLK at 85°C
4
A
–4
10
5
GAIN (dB)
0
–1
–3
1264-7 G08
VS = ±5V
(fCLK /fC) = 25:1
1
–2
A
–3
–4
10
GAIN (dB)
2
1
–4
A. fCLK = 4MHz
B. fCLK = 5MHz
3
–2
B
A
VS = ±7.5V
(fCLK /fC) = 25:1
4
GAIN (dB)
VS = ±7.5V
(fCLK /fC) = 25:1
TA = 25°C
4
Passband Gain vs fCLK at 85°C
5
1264-7 G15
1
10
FREQUENCY (kHz)
100
1264-7 G16
5
LTC1264-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Gain vs fCLK
10
–10
3
2
C
GAIN (dB)
B
–40
–50
–60
–70
–80
–90
10
VS = SINGLE 5V
(fCLK /fC) = 50:1
AGND = 2V
TA = 25°C
0
–1
B
A
C
D
5
10
–4.0
100
1
VS = ±7.5V
(fCLK /fC) = 25:1
TA = 25°C
–40
–50
–55
30
B
20
C
D
D
5
10
0
0
VS = ±5V
VIN = 1VRMS
fCLK = 1MHz
(fCLK /fC) = 25:1
(5 REPRESENTATIVE UNITS)
–45
40
C
10
VS = ±7.5V
(fCLK /fC) = 50:1
TA = 25°C
A
50
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
THD (dB)
B
50
THD vs Frequency
Delay vs fCLK
A. fCLK = 1MHz
B. fCLK = 2MHz
C. fCLK = 3MHz
D. fCLK = 4MHz
10
FREQUENCY (kHz)
1264-7 G19
60
DELAY (µs)
DELAY (µs)
–3.5
1264-7 G18
Delay vs fCLK
15
VS = SINGLE 5V
fCLK = 2MHz
(fCLK /fC) = 50:1
AGND = 2V
FREQUENCY (kHz)
30
20
A. TA = 70°C
B. TA = –40°C
–2.0
–2.5
1264-7 G17
A
–1.0
–1.5
–3.0
FREQUENCY (kHz)
25
B
–3
–5
200
A
0
–2
–4
100
0.5
– 0.5
1
GAIN (dB)
A
A. fCLK = 0.5MHz
B. fCLK = 1.0MHz
C. fCLK = 1.5MHz
D. fCLK = 2.0MHz
VS = SINGLE 5V
(fCLK /fC) = 50:1
AGND = 2V
TA = 25°C
4
–20
GAIN (dB)
1.0
5
A. fCLK = 0.5MHz
B. fCLK = 1MHz
C. fCLK = 2MHz
0
–30
Maximum Passband vs
Temperature
Passband Gain vs fCLK
–60
–65
–70
–75
–80
–85
20 40 60
80 100 120 140 160 180 200 220
INPUT FREQUENCY (kHz)
–90
10 20 30
1264-7 G20
THD vs Frequency
THD vs Frequency
THD + Noise vs Input
–40
–55
–50
–55
THD (dB)
–60
VS = SINGLE 5V
VIN = 0.5VRMS
fCLK = 500kHz
(fCLK /fC) = 25:1
AGND = 2V
(5 REPRESENTATIVE UNITS)
–45
–65
–70
–60
–45
–50
THD + NOISE (dB)
VS = ±7.5V
VIN = 1VRMS
fCLK = 2.5MHz
(fCLK /fC) = 25:1
(5 REPRESENTATIVE UNITS)
–50
–65
–70
–80
–85
–85
–90
–90
–90
0.1
6
B
–70
–85
–75
–80
1
10
20
FREQUENCY (kHz)
1264-7 G23
A
–65
–80
100
A. VS = ±5V
B. VS = ±7.5V
–60
–75
10
FREQUENCY (kHz)
fIN = 1kHz
fCLK = 1MHz
(fCLK /fC) = 25:1
–55
–75
1
50
1264-7 G22
–40
–45
10
FREQUENCY (kHz)
1264-7 G21
–40
THD (dB)
1
40 50 60 70 80 90 100 110
INPUT FREQUENCY (kHz)
1264-7 G24
1
INPUT AMPLITUDE (VRMS)
5
1264-7 G25
LTC1264-7
U W
TYPICAL PERFOR A CE CHARACTERISTICS
THD + Noise vs Input
–40
A
A. PIN 3 AT 2.5V
B. PIN 3 AT 2V
PHASE DIFFERENCE (DEG)
THD + NOISE (dB)
–50
–55
–60
–65
–70
–75
–80
–85
VS = SINGLE 5V
fCLK = 500kHz
fIN = 1kHz
–90
50m
48
5
B
PHASE DIFFERENCE BETWEEN
ANY TWO UNITS (SAMPLE OF
50 REPRESENTATIVE UNITS)
VS ≥ ±5V
fCLK ≤ 2.5MHz
(fCLK /fC) = 25:1 OR 50:1
TA = 0°C TO 70°C
4
3
2
1
fCLK = 1MHz
40
36
32
28
24
–55°C
25°C
125°C
20
16
12
8
4
0.1
INPUT AMPLITUDE (VRMS)
1
0
0
0
0.2
0.6
0.8
0.4
FREQUENCY (fCUTOFF/FREQUENCY)
1264-7 G26
GAIN (dB)
1.0
0 2
4 6 8 10 12 14 16 18 20 22 24
TOTAL POWER SUPPLY VOLTAGE (V)
1264-7 G28
1264-7 G27
Table 1. Passband Gain and Phase
VS = ±7.5V, (fCLK / fC) = 25:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 1MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
44
POWER SUPPLY CURRENT (mA)
–45
Power Supply Current vs Power
Supply Voltage
Phase Matching vs Frequency
Table 2. Passband Gain and Phase
VS = ±7.5V, (fCLK / fC) = 50:1, TA = 25°C
PHASE (DEG)
0.064
0.064
0.058
– 0.639
– 2.741
180.00
81.14
–19.18
–120.63
– 221.78
FREQUENCY (kHz)
fCLK = 1MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
fCLK = 2MHz (Typical Unit)
0.000
20.000
40.000
60.000
80.000
– 0.006
– 0.006
– 0.164
– 0.958
– 3.003
180.00
79.42
– 22.13
–124.09
– 225.01
fCLK = 3MHz (Typical Unit)
0.000
30.000
60.000
90.000
120.000
– 0.067
– 0.067
– 0.287
– 0.944
– 2.545
fCLK = 4MHz (Typical Unit)
0.000
40.000
80.000
120.000
160.000
fCLK = 5MHz (Typical Unit)
0.000
50.000
100.000
150.000
200.000
GAIN (dB)
PHASE (DEG)
– 0.048
– 0.048
– 0.351
– 1.253
– 3.348
180.00
84.51
– 10.87
– 105.53
– 199.61
fCLK = 2MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
– 0.008
– 0.008
– 0.237
– 1.105
– 3.238
180.00
83.39
– 13.09
– 108.91
– 204.09
180.00
77.49
– 25.54
– 128.51
– 230.19
fCLK = 3MHz (Typical Unit)
0.000
15.000
30.000
45.000
60.000
0.044
0.044
– 0.065
– 0.863
– 3.022
180.00
81.04
– 18.64
– 118.48
– 217.67
– 0.031
– 0.031
– 0.078
– 0.332
– 1.275
180.00
75.23
– 30.06
– 135.27
– 239.76
fCLK = 4MHz (Typical Unit)
0.000
20.000
40.000
60.000
80.000
0.071
0.071
0.039
– 0.664
– 2.755
180.00
78.04
– 25.06
– 128.54
– 231.42
0.073
0.073
0.365
0.686
0.521
180.00
71.77
– 37.11
– 146.19
– 255.85
fCLK = 5MHz (Typical Unit)
0.000
25.000
50.000
75.000
100.000
0.089
0.089
0.141
– 1.437
– 2.421
180.00
74.36
– 32.41
– 139.33
– 246.01
7
LTC1264-7
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TYPICAL PERFOR A CE CHARACTERISTICS
Table 3. Passband Gain and Phase
VS = ±5V, (fCLK / fC) = 25:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 1MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
GAIN (dB)
Table 4. Passband Gain and Phase
VS = ±5V, (fCLK / fC) = 50:1, TA = 25°C
PHASE (DEG)
0.081
0.081
0.071
– 0.631
– 2.732
180.00
80.94
– 19.54
– 121.10
– 222.28
FREQUENCY (kHz)
fCLK = 1MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
fCLK = 2MHz (Typical Unit)
0.000
20.000
40.000
60.000
80.000
– 0.016
– 0.016
– 0.211
– 0.968
– 2.864
180.00
78.78
– 23.21
– 125.42
– 226.47
fCLK = 3MHz (Typical Unit)
0.000
30.000
60.000
90.000
120.000
– 0.006
– 0.006
– 0.044
– 0.369
– 1.507
180.00
76.07
– 28.54
– 133.27
– 237.35
fCLK = 1MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
0.032
0.032
– 0.249
– 1.135
– 3.225
180.00
84.60
– 10.65
– 105.20
– 199.22
fCLK = 2MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
0.101
0.101
– 0.043
– 0.864
– 3.021
180.00
82.47
– 15.45
– 113.28
– 210.54
fCLK = 3MHz (Typical Unit)
0.000
15.000
30.000
45.000
60.000
0.125
0.125
0.043
– 0.753
– 2.987
180.00
77.88
– 25.31
– 128.74
– 231.29
0.161
0.161
0.166
– 0.515
– 2.598
180.00
81.47
– 18.52
– 119.79
– 220.82
FREQUENCY (kHz)
fCLK = 0.5MHz (Typical Unit)
0.000
2.500
5.000
7.500
10.000
0.125
0.125
0.043
– 0.706
– 2.781
180.00
80.23
– 20.75
– 122.53
– 223.59
GAIN (dB)
PHASE (DEG)
GAIN (dB)
PHASE (DEG)
0.075
0.075
– 0.217
– 1.108
– 3.198
180.00
84.79
– 10.40
– 105.10
– 199.26
fCLK = 1MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
0.114
0.114
– 0.122
– 0.988
– 3.111
180.00
83.96
– 11.88
– 107.02
– 201.63
0.174
0.174
0.066
– 0.744
– 2.949
180.00
81.36
– 17.84
– 117.12
– 215.79
0.232
0.232
0.219
– 0.599
– 3.031
180.00
75.98
– 29.26
– 134.63
– 239.09
fCLK = 1.5MHz (Typical Unit)
0.000
15.000
30.000
45.000
60.000
0.061
0.061
– 0.096
– 0.741
– 2.432
180.00
78.49
– 23.82
– 126.47
– 228.12
fCLK = 1.5MHz (Typical Unit)
0.000
7.500
15.000
22.500
30.000
fCLK = 2MHz (Typical Unit)
0.000
20.000
40.000
60.000
80.000
0.151
0.151
0.321
0.203
– 0.838
180.00
75.03
– 31.15
– 137.86
– 244.58
fCLK = 2MHz (Typical Unit)
0.000
10.000
20.000
30.000
40.000
8
PHASE (DEG)
Table 6. Passband Gain and Phase
VS = Single 5V, (fCLK /fC) = 50:1, TA = 25°C
Table 5. Passband Gain and Phase
VS = Single 5V, (fCLK /fC) = 25:1, TA = 25°C
FREQUENCY (kHz)
fCLK = 0.5MHz (Typical Unit)
0.000
5.000
10.000
15.000
20.000
GAIN (dB)
LTC1264-7
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PI FU CTIO S
Power Supply Pins (4, 12)
The V + (pin 4) and the V – (pin 12) should each be
bypassed with a 0.1µF capacitor to an adequate analog
ground. The filter’s power supplies should be isolated
from other digital or high voltage analog supplies. A low
noise linear supply is recommended. Using a switching
power supply will lower the signal-to-noise ratio of the
filter. The supply during power-up should have a slew rate
less than 1V/µs. When V + is applied before V – and V – is
allowed to go above ground, a signal diode should clamp
V – to prevent latch-up. Figures 2 and 3 show typical
connections for dual and single supply operation.
Clock Input Pin (11)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 7 shows the clock’s low and high
level threshold values for a dual or single supply operation.
A pulse generator can be used as a clock source provided
the high level ON time is greater than 0.1µs. Sine waves are
not recommended for clock input frequencies less than
100kHz, since excessively slow clock rise or fall times
generate internal clock jitter (maximum clock rise or fall
time ≤ 1µs). The clock signal should be routed from the
right side of the IC package and perpendicular to it to avoid
coupling to any input or output analog signal path. A 200Ω
resistor between clock source and pin 11 will slow down
the rise and fall times of the clock to further reduce charge
coupling (Figures 2 and 3).
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, pin 3 should be connected to the analog
ground plane. For single supply operation pin 3 should be
biased at 1/2 supply and should be bypassed to the analog
ground plane with at least a 1µF capacitor (Figure 3). For
single 5V operation at the highest fCLK of 2MHz, pin 3
should be biased at 2V. This minimizes passband gain and
phase variations.
Ratio Input Pin (10)
The DC level at this pin determines the ratio of the clock
frequency to the cutoff frequency of the filter. Pin 10 at V +
gives a 25:1 ratio and pin 10 at V – gives a 50:1 ratio. For
single supply operation the ratio is 25:1 when pin 10 is at
V + and 50:1 when pin 10 is at ground. When pin 10 is not
tied to ground, it should be bypassed to analog ground
with a 0.1µF capacitor. If the DC level at pin 10 is switched
mechanically or electrically at slew rates greater than
1V/µs while the device is operating, a 10k resistor should
be connected between pin 10 and the DC source.
V–
VIN
1
14
2
13
3
12
4
V+
0.1µF
HIGH LEVEL
≥ 2.18V
≥ 1.45V
≥ 0.73V
≥ 7.80V
≥ 1.45V
LOW LEVEL
≤ 0.5V
≤ 0.5V
≤ – 2.0V
≤ 6.5V
≤ 0.5V
Analog Ground Pins (3, 5)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
200Ω
11
5
10
6
9
7
8
CLOCK SOURCE
V+
+
GND
DIGITAL SUPPLY
VOUT
1264-7 F02
Figure 2. Dual Supply Operation for an fCLK/fCUTOFF = 25:1
Table 7. Clock Source High and Low Threshold Levels
POWER SUPPLY
Dual Supply = ±7.5V
Dual Supply = ±5V
Dual Supply = ± 2.5V
Single Supply = 12V
Single Supply = 5V
LTC1264-7
0.1µF
VIN
14
2
13
3
12
11
200Ω
5
10
V+
6
9
7
8
4
V+
0.1µF
10k
10k
1
LTC1264-7
CLOCK SOURCE
+
GND
DIGITAL SUPPLY
+
1µF
VOUT
1264-7 F03
Figure 3. Single Supply Operation for an fCLK/fCUTOFF = 25:1
9
LTC1264-7
U
U
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PI FU CTIO S
Filter Input Pin (2)
The input pin is connected internally through a 50k resistor
tied to the inverting input of an op amp.
Filter Output Pins (9, 6)
Pin 9 is the specified output of the filter; it can typically
source 3mA and sink 1mA. Driving coaxial cables or
resistive loads less than 20k will degrade the total harmonic distortion of the filter. When evaluating the device’s
–
1k
+
LT1220
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W
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S I FOR ATIO
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pin (9). The clock feedthrough is tested with the
input pin (2) grounded and it depends on PC board layout
and on the value of the power supplies. With proper layout
techniques the values of the clock feedthrough are shown
in Table 8.
Table 8. Clock Feedthrough
25:1
100µVRMS
100µVRMS
120µVRMS
50:1
100µVRMS
400µVRMS
1000µVRMS
Note: The clock feedthrough at 25:1 is imbedded in the wideband
noise of the filter. Clock waveform is a square wave.
Any parasitic switching transients during the rise and fall
edges of the incoming clock are not part of the clock
feedthrough specifications. Switching transients have frequency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
10
Pins 7 and 14 should be connected together. In a printed
circuit board the connection should be done under the IC
package through a short trace surrounded by the analog
ground plane.
Pins 1, 5, 8 and 13 are not connected to any internal circuit
point on the device and should be preferably tied to analog
ground.
Figure 4. Buffer for Filter Output
VS
Single 5V
±5V
±7.5V
External Connection Pins (7, 14)
NC Pin (1, 5, 8, 13)
1264-7 F04
APPLICATI
distortion an output buffer is required. A noninverting
buffer, Figure 4, can be used provided that its input
common-mode range is well within the filter’s output
swing. Pin 6 is an intermediate filter output providing an
unspecified 6th order lowpass filter. Pin 6 should not be
loaded.
clock feedthrough, if bothersome, can be greatly reduced
by adding a simple R/C lowpass network at the output of
the filter pin (9). This R/C will completely eliminate any
switching transients.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and it is used to
determine the operating signal-to-noise ratio. Most of its
frequency contents lie within the filter passband and it
cannot be reduced with post filtering. For instance, the
LTC1264-7 wideband noise at ±5V supply is 160µVRMS,
145µVRMS of which have frequency contents from DC up
to the filter’s cutoff frequency. The total wideband noise
(µVRMS) is nearly independent of the value of the clock.
The clock feedthrough specifications are not part of the
wideband noise.
Speed Limitations
To avoid op amp slew rate limiting at maximum clock
frequencies, the signal amplitude should be kept below a
specified level as shown in Table 9.
LTC1264-7
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APPLICATI
S I FOR ATIO
Table 9. Maximum VIN vs VS and Clock
POWER SUPPLY
±7.5V
±5V
Single 5V
Aliasing
MAXIMUM fCLK
5.0MHz
4.5MHz
4.0MHz
≥ 3.5MHz
3.0MHz
≥ 3.0MHz
2.0MHz
MAXIMUM VIN
1.6VRMS (fIN ≥ 160kHz)
2.0VRMS (fIN ≥ 160kHz)
2.5VRMS (fIN ≥ 160kHz)
1.6VRMS (fIN ≥ 500kHz)
1.6VRMS (fIN ≥ 100kHz)
0.7VRMS (fIN ≥ 500kHz)
0.5VRMS (fIN ≥ 400kHz)
Transient Response
Aliasing is an inherent phenomenon of sampled data
systems and it occurs when input frequencies close to the
sampling frequency are applied. For the LTC1264-7 case
at 50:1, an input signal whose frequency is in the range of
fCLK ±10%, will be aliased back into the filter’s passband.
If, for instance, an LTC1264-7 operating with a 100kHz
clock and 2kHz cutoff frequency receives a 95kHz 10mV
input signal, a 5kHz 56µVRMS alias signal will appear at its
output. When the LTC1264-7 operates with a clock-tocutoff frequency of 25:1, aliasing occurs at twice the clock
frequency. Table 10 shows details.
2V/DIV
Table 10. Aliasing (fCLK = 100kHz )
10µs/DIV
INPUT = 10kHz ± 3V
fCLK = 2.5MHz
RATIO = 25:1
Figure 5.
ts
INPUT FREQUENCY
(VIN = 1VRMS,
fIN = fCLK ± fOUT)
(kHz)
25:1, fCUTOFF = 4kHz
OUTPUT LEVEL
(Relative to Input,
0dB = 1VRMS)
(dB)
OUTPUT FREQUENCY
(Aliased Frequency
fOUT = ABS [fCLK ± fIN])
(kHz)
175 (or 225)
180 (or 220)
185 (or 215)
190 (or 210)
195 (or 205)
50:1, fCUTOFF = 2kHz
–76
– 69
– 62
– 43
–7
25
20
15
10
5
75 (or 125)
80 (or 120)
85 (or 115)
90 (or 110)
95 (or 105)
99 (or 101)
–96
– 90
– 82
– 72
– 45
0
25
20
15
10
5
1
OUTPUT
INPUT
90%
50%
10%
Table 11. Transient Response of LTC Lowpass Filters
td
tr
0.36
±5%
fCUTOFF
2
SETTLING TIME (ts) =
±5%
f
(TO 1% of OUTPUT) CUTOFF
RISE TIME (tr) =
1.15
TIME DELAY (td) = GROUP DELAY ≈
fCUTOFF
(TO 50% OF OUTPUT)
1164-7 F06
LOWPASS FILTER
LTC1064-3 Bessel
LTC1164-5 Bessel
LTC1164-6 Bessel
DELAY
TIME*
(SEC)
0.50/fC
0.43/fC
0.43/fC
RISE SETTLING OVERTIME** TIME*** SHOOT
(SEC)
(SEC)
(%)
0.34/fC
0.80/fC
0.5
0.34/fC
0.85/fC
0
0.34/fC
1.15/fC
1
LTC1264-7 Linear Phase
LTC1164-7 Linear Phase
LTC1064-7 Linear Phase
1.15/fC
1.20/fC
1.20/fC
0.36/fC
0.39/fC
0.39/fC
2.05/fC
2.20/fC
2.20/fC
5
5
5
LTC1164-5 Butterworth
0.80/fC
0.48/fC
2.40/fC
11
LTC1164-6 Elliptic
LTC1064-4 Elliptic
LTC1064-1 Elliptic
0.85/fC
0.90/fC
0.85/fC
0.54/fC
0.54/fC
0.54/fC
4.30/fC
4.50/fC
6.50/fC
18
20
20
* To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5%
Figure 6.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC1264-7
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
J Package
14-Lead Ceramic DIP
0.200
(5.080)
MAX
0.290 – 0.320
(7.366 – 8.128)
0.785
(19.939)
MAX
0.005
(0.127)
MIN
14
12
13
11
10
9
8
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
(0.203 – 0.460)
0.220 – 0.310
(5.588 – 7.874)
0.025
(0.635)
RAD TYP
0° – 15°
1
0.385 ± 0.025
(9.779 ± 0.635)
0.038 – 0.068
(0.965 – 1.727)
0.100 ± 0.010
(2.540 ± 0.254)
0.014 – 0.026
(0.360 – 0.660)
2
3
4
5
6
7
0.098
(2.489)
MAX
0.125
(3.175)
MIN
J14 0392
N Package
14-Lead Plastic DIP
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.015
(0.380)
MIN 0.130 ± 0.005
(3.302 ± 0.127)
(
+0.635
8.255
–0.381
)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
0.260 ± 0.010
(6.604 ± 0.254)
0.009 – 0.015
(0.229 – 0.381)
+0.025
0.325 –0.015
0.770
(19.558)
MAX
0.065
(1.651)
TYP
0.075 ± 0.015
(1.905 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
0.125
(3.175)
MIN
S Package
16-Lead Plastic SOL
0.398 – 0.413
(10.109 – 10.490)
0.291 – 0.299
(7.391 – 7.595)
0.005
(0.127)
RAD MIN
0.010 – 0.029 × 45°
(0.254 – 0.737)
16
0.093 – 0.104
(2.362 – 2.642)
15
14
13
12
11
10
9
0.037 – 0.045
(0.940 – 1.143)
0° – 8° TYP
0.394 – 0.419
(10.007 – 10.643)
SEE NOTE
0.009 – 0.013
(0.229 – 0.330)
SEE NOTE
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.014 – 0.019
(0.356 – 0.482)
TYP
NOTE:
PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
1
2
3
4
5
6
7
8
SOL16 0392
12
Linear Technology Corporation
LT/GP 1292 10K REV 0
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977
 LINEAR TECHNOLOGY CORPORATION 1992