INTEGRATED CIRCUITS DATA SHEET UMA1021M Low-voltage frequency synthesizer for radio telephones Product specification Supersedes data of 1996 May 06 File under Integrated Circuits, IC17 1996 August 28 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M The device is designed to operate from 3 NiCd cells, in pocket phones, with low current and nominal 3 V supplies. FEATURES • Low phase noise The synthesizer operates at RF input frequencies up to 2.2 GHz, with a fully programmable reference divider. All divider ratios are supplied via a 3-wire serial programming bus. • Low current from 3 V supply • Fully programmable main divider • 3-line serial interface bus • Independent fully programmable reference divider, driven from external crystal oscillator Separate power and ground pins are provided to the analog (charge-pump) and digital circuits. The ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. VDD1 and VDD2 must also be at the same potential (VDD). VCC must be equal to or greater than VDD (e.g. VDD = 3 V and VCC = 5 V for wider VCO control voltage range). • Dual charge pump outputs • Hard and soft power-down control. APPLICATIONS • 900 MHz and 2 GHz mobile telephones The phase detector has two charge-pump outputs, CP and CPF, the latter of which is enabled directly at pin FAST. This permits the design of adaptive loops. The charge pump currents (phase detector gain) are fixed by an external resistance at pin ISET and via the serial interface. Only a passive loop filter is necessary; the charge pumps function within a wide voltage compliance range to improve the overall system performance. • Portable battery-powered radio equipment. GENERAL DESCRIPTION The UMA1021M BICMOS device integrates a prescaler, programmable dividers, and a phase comparator to implement a phase-locked loop. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS VDD digital supply voltage VDD1 = VDD2; VCC ≥ VDD VCC charge-pump supply voltage VCC ≥ VDD IDD + ICC supply current MIN. 2.7 TYP. − MAX. 5.5 UNIT V 2.7 − 5.5 V − 10 − mA ICC(pd) + IDD(pd) total supply current in power-down mode − 5 − µA fRF RF input frequency 300 − 2200 MHz fxtal crystal reference input frequency 3 − 35 MHz fPC phase comparator frequency − 200 − kHz Tamb operating ambient temperature −30 − +85 °C ORDERING INFORMATION TYPE NUMBER UMA1021M 1996 August 28 PACKAGE NAME SSOP20 DESCRIPTION plastic shrink small outline package; 20 leads; body width 4.4 mm 2 VERSION SOT266-1 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M BLOCK DIAGRAM VDD1 handbook, full pagewidth FAST 14 1 VDD2 VCC 4 18 UMA1021M 2 FAST CHARGE PUMP CPF BAND GAP 3 CP 6 ISET CHARGE PUMP 20 PHASE COMPARATOR RFI 19 LOCK 16 MAIN DIVIDER WITH PRESCALER REFERENCE DIVIDER XTALA XTALB 15 POL PON 8 13 9 12 SERIAL INTERFACE 11 10 7 5 17 MBG366 VSS1 VSS2 VSS3 GND(CP) Fig.1 Block diagram. 1996 August 28 3 E DATA CLK Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M PINNING SYMBOL PIN DESCRIPTION FAST 1 enable input for fast charge-pump output CPF CPF 2 fast charge-pump output CP 3 normal charge-pump output VDD2 4 power supply 2 VSS3 5 ground 3 RFI 6 2 GHz main divider input VSS2 7 ground 2 POL 8 digital input to select polarity of power-on inputs (PON and sPON): POL = 0 for active LOW and POL = 1 for active HIGH handbook, halfpage FAST 1 20 LOCK CPF 2 19 ISET CP 3 18 VCC VDD2 4 17 GND(CP) VSS3 5 RFI 6 15 XTALB VSS2 7 14 VDD1 PON 9 power-on input VSS1 10 ground 1 CLK 11 programming bus clock input DATA 12 programming bus data input E 13 programming bus enable input POL 8 13 E VDD1 14 power supply 1 PON 9 12 DATA XTALB 15 complementary crystal frequency input from TCXO; if not used should be decoupled to ground XTALA 16 crystal frequency input from TCXO; if not used should be decoupled to ground GND(CP) 17 ground for charge-pump VCC 18 supply for charge-pump ISET 19 external resistor from this pin to ground sets the charge-pump currents LOCK 20 out-of-lock detector output 16 XTALA UMA1021M VSS1 10 11 CLK MBG365 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION Reference divider Main divider The reference divider is clocked by the differential signal between pins XTALA and XTALB. If only one of these inputs is used, the other should be decoupled to ground. The applied input signal(s) should be AC-coupled. The circuit operates with levels from 50 up to 500 mV (RMS) and at frequencies from 3 to 35 MHz. Any divide ratios from 8 to 2047 inclusive can be programmed. The main divider is clocked at pin RFI by the RF signal which is AC-coupled from an external VCO. The divider operates with signal levels from 50 to 225 mV (RMS), and at frequencies from 300 MHz to 2.2 GHz. It consists of a fully programmable bipolar prescaler followed by a CMOS counter. Any divide ratios from 512 to 131071 inclusive can be programmed. 1996 August 28 4 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M During normal operation, E should be kept HIGH. Only the last 21 bits serially clocked into the device are retained within the programming register. Additional leading bits are ignored, and no check is made on the number of clock pulses. The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new programmed data even during power-down. Phase detector The phase detector is driven by the output edges of the main and reference dividers. It produces current pulses at pins CP and CPF whose amplitudes are programmed. The pulse duration is equal to the difference in time of arrival of the edges from the two dividers. If the main divider edge arrives first, CP and CPF sink current. If the reference divider edge arrives first, CP and CPF source current. When the synthesizer is powered-on, the presence of a TCXO signal at the reference divider input and a VCO signal at the main divider input is required for correct programming. The currents at CP and CPF are programmed via the serial bus as multiples of a reference current set by an external resistor connected between pin ISET and VSS (see Table 3). CP remains active except in power-down. CPF is enabled via input pin FAST which is synchronized with respect to the phase detector to prevent output current pulses being interrupted. By appropriate connection to the loop filter, dual bandwidth loops can be designed; short time constant during frequency switching (FAST mode) to speed-up channel changes, and low bandwidth in the settled state to improve noise and breakthrough levels. Data format The leading bits (dt16 to dt0) make up the data field, while the trailing four bits (ad3 to ad0) are the address field. The UMA1021M uses 4 of the 16 available addresses. These are chosen for compatibility with other Philips Semiconductors radio telephone ICs. The data format is shown in Table 1. The first bit entered is dt16, the last bit is ad0. For the divider ratios, the first bits entered (PM16 and PR10) are the most significant (MSB). The trailing address bits are decoded on the rising edge of E. This produces an internal load pulse to store the data in the addressed latch. To avoid erroneous divider ratios, the load pulse is not allowed during data reads by the frequency dividers. This condition is guaranteed by respecting a minimum E pulse width after data transfer. Additional circuitry is included to ensure that the gain of the phase detector remains linear even for small phase errors. Out-of-lock detector The out-of-lock detector is enabled (disabled) via the serial interface by setting bit OOL HIGH (LOW). An open drain transistor drives the output pin LOCK (pin 20). It is recommended that the pull-up resistor from this pin to VDD is chosen to be of sufficient value to keep the sink current in the LOW state to below 400 µA. When the out-of-lock detector is enabled, LOCK is HIGH if the error at the phase detector input is less than approximately 25 ns, otherwise LOCK is LOW. If the out-of-lock detector is disabled, LOCK remains HIGH. The test register (address 0000) does not normally need to be programmed. However if it is programmed, all bits in the data field should be set to logic 0. Power-down mode The synthesizer is on when both the input signals PON and the programmed bit sPON are active. The ‘active’ level for these two signals is chosen at pin POL (see Table 2). When turned on, the dividers and phase detector are synchronized to avoid random phase errors. When turned off, the phase detector is synchronized to avoid interrupting charge-pump pulses. For synchronisation functions to work correctly on power-up or power-down (using either hardware or software programming), the presence of TCXO and VCO signals is required to drive the appropriate divider inputs. The UMA1021M has a very low current consumption in the power-down mode. Serial programming bus A simple 3-line unidirectional serial bus is used to program the circuit. The 3 lines are DATA, clock (CLK) and enable (E). The data sent to the device is loaded in bursts framed by E. Programming clock edges and their appropriate data bits are ignored until E goes active LOW. The programmed information is loaded into the addressed latch when E returns HIGH. 1996 August 28 5 Bit allocation; note 1 1996 August 28 X X X X X X OOL(3) X dt11 dt12 CR0 X X dt8 dt7 Test bits(2) dt9 PR10(4) sPON(3) dt6 X X X X X dt5 dt4 dt3 dt2 dt1 reference divider coefficient main divider coefficient CR1 dt10 DATA FIELD REGISTER BIT ALLOCATION PR0 PM0 X dt0 0 0 0 0 ad3 6 1 1 1 0 X 1 X 0 sPON 0 1 0 1 0 0 1 1 V SET 1. ISET = -------------- ; reference current for charge pumps. R SET CR0 CR1 ICPF 8 × ISET 16 × ISET 12 × ISET 16 × ISET 2 × ISET 2 × ISET 1 × ISET 1 × ISET on off off off off on SYNTHESIZER STATE ICP Fast and normal charge pumps current ratio (note 1) 0 X 0 X 1 0 1 0 0 1 PON POL Power-on programming 0 0 0 0 ad1 16 : 1 12 : 1 8:1 4:1 ICPF : ICP UMA1017M UMA1017M UMA1017M UMA1019M/UMA1019AM UMA1019M/UMA1019AM UMA1019M/UMA1019AM COMPATIBILITY 1 1 0 0 ad2 ADDRESS 1 0 1 0 ad0 LAST IN Low-voltage frequency synthesizer for radio telephones Note Table 3 Table 2 4. PM16 is the MSB of the main divider coefficient; PR10 is the MSB of the reference divider coefficient. 3. Bit sPON = software power-up for synthesizer (see Table 2); OOL = Out-Of-Lock (1 = enabled). 2. The test register (address 0000) should not be programmed with any other values except all zeros for normal operation. X X dt15 dt14 dt13 1. X = don’t care. Notes X PM16(4) X dt16 FIRST IN Table 1 Philips Semiconductors Product specification UMA1021M Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD digital supply voltage −0.3 +5.5 V VCC charge-pump supply voltage −0.3 +5.5 V VCC − VDD difference in voltage between VCC and VDD −0.3 +5.5 V Vn voltage at pins 6, 8, 9 and 11 to 13 −0.3 VDD + 0.3 V voltage at pins 1, 2, 3, 15, 16, 19 and 20 −0.3 VCC + 0.3 V ∆VGND difference in voltage between any of GND(CP), VSS1, VSS2, and VSS3 (these pins should be connected together) −0.3 +0.3 V Ptot total power dissipation − 150 mW Tstg storage temperature −55 +125 °C Tamb operating ambient temperature −30 +85 °C Tj(max) maximum junction temperature − 150 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. This device meets class 2 ESD test requirements [Human Body Model (HBM)], in accordance with “MIL STD 883C - method 3015”. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1996 August 28 PARAMETER thermal resistance from junction to ambient in free air 7 VALUE UNIT 120 K/W Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M CHARACTERISTICS All values refer to the typical measurement circuit of Fig.5; VDD1 = VDD2 = 2.7 to 5.5 V; VCC = 2.7 to 5.5 V; Tamb = 25 °C; unless otherwise specified. Characteristics for which only a typical value is given are not tested. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply; pins 4, 14 and 18 VDD digital supply voltage VDD1 = VDD2; VCC ≥ VDD 2.7 VCC charge pump supply voltage VCC ≥ VDD IDD1 + IDD2 synthesizer digital supply current VDD = 5.5 V ICC charge pump supply current ICC(pd) + IDD(pd) total supply current in power-down mode − 5.5 V 2.7 − 5.5 V − 7 9.5 mA VCC = 5.5 V; RSET = 5.6 kΩ − 3 3.8 mA logic levels 0 V or VDD − 5 50 µA 300 − 2200 MHz 50 − 225 mV 512 − 131071 RF main divider input; pin 6 fRF RF input frequency VRF(rms) AC-coupled input signal level (RMS value) Rm main divider ratio Zi input impedance (real part) fRF = 1 GHz − 1 − kΩ fRF = 2 GHz − 60 − Ω Ci typical pin input capacitance fRF = 1 GHz − 1 − pF fRF = 2 GHz − 1 − pF Rs = 50 Ω Synthesizer reference divider input; pins 15 and 16 fxtal crystal reference input frequency 3 − 35 MHz Vxtal(rms) sinusoidal input signal level between pins 15 and 16 (RMS value) 50 − 500 mV Rref reference division ratio 8 Zi input impedance (real part) fxtal = 13 MHz − 10 − kΩ Ci typical pin input capacitance fxtal = 13 MHz − 1.5 − pF − 2000 − kHz 5.6 − 12 kΩ − 1.2 − V 2047 Phase detector fPCmax maximum loop comparison frequency Charge pump current setting resistor input; pin 19 RSET external resistor connected between pin 19 and ground VSET regulated voltage at pin 19 1996 August 28 RSET = 5.6 kΩ 8 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones SYMBOL PARAMETER UMA1021M CONDITIONS MIN. TYP. MAX. UNIT Charge pump outputs; pins 2 and 3; RSET = 5.6 kΩ Iocp(err) charge pump output current error Imatch sink-to-source current matching ILIcp charge pump off leakage current VCP/CPF charge pump voltage compliance VCP/CPF = 1⁄ V 2 CC −25 − +25 % − ±5 − % nA −5 ±1 +5 0.4 − VCC − 0.4 V Phase noise N900 synthesizer’s contribution to close-in phase noise of 900 MHz RF signal at 1 kHz offset (GSM) fxtal = 13 MHz; Vxtal = 0 dBm; fPC = 200 kHz − −88 − dBc/Hz N1800 synthesizer’s contribution to close-in phase noise of 1.8 GHz RF signal at 1 kHz offset (DCS1800) fxtal = 13 MHz; Vxtal = 0 dBm; fPC = 200 kHz − −82 − dBc/Hz Interface logic input signal levels; pins 1, 8, 9, 11, 12 and 13 VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V VIL LOW level input voltage −0.3 − 0.3VDD V Ibias input bias current −5 − +5 µA Ci input capacitance − 2 − pF − − 0.4 V − 25 − ns logic 1 or logic 0 Lock detect output signal; pin 20; open-drain output VOL LOW level output voltage tOOL phase error threshold for out-of-lock detector 1996 August 28 Isink < 0.4 mA 9 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M SERIAL BUS TIMING CHARACTERISTICS VDD = VCC = 3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT Serial programming clock; CLK tr input rise time − 10 40 ns tf input fall time − 10 40 ns Tcy clock period 100 − − ns 40 − − ns Enable programming; E tSTART delay to rising clock edge tEND delay from last falling clock edge −20 − − ns tW(min) minimum inactive pulse width 4000(1) − − ns tSU;E enable set-up time to next clock edge 20 − − ns Register serial input data; DATA tSU;DAT input data to clock set-up time 20 − − ns tHD;DAT input data to clock hold time 20 − − ns Note 1. The minimum pulse width (tW(min)) can be smaller than 4 µs provided all the following conditions are fulfilled: 447 a) Main divider input frequency f RF > ------------------- . t W ( min ) 3 b) Reference divider input frequency f xtal > ------------------- . t W ( min ) tSU;DAT handbook, full pagewidth tHD;DAT tf Tcy tr tEND tSU;E CLK DATA MSB LSB ADDRESS E tSTART MGD565 Fig.3 Serial bus timing diagram. 1996 August 28 10 tW(min) Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M APPLICATION INFORMATION handbook, full pagewidth power amplifier transmit data PLL SPLITTER VCO LPF transmit mixer MAIN DIVIDER PHASE COMPARATOR duplex filter REFERENCE DIVIDER TCXO UMA1021M low noise amplifier MBG369 to demodulation 1st mixer 2nd mixer Fig.4 Typical application block diagram. 1996 August 28 11 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones handbook, full pagewidth UMA1021M positive supply 12 Ω positive supply 1 20 2 19 3 18 4 17 (1) 100 nF (1) (1) (1) 12 Ω (1) 1 nF 18 Ω 18 Ω 1 nF out 56 Ω 1 nF 18 Ω positive supply 12 Ω 100 nF 5 6 15 7 14 8 13 9 12 10 11 12 Ω VCC VTCXO GND Vcont fosc 16 UMA1021M 12 Ω 100 nF 1 nF 100 nF control RF VCO 5.6 kΩ 1 nF 100 nF to 1st mixer 1 kΩ 1 kΩ 3-wire bus (1) Values depend on application. Fig.5 Typical test and application diagram. 1996 August 28 12 1 kΩ MBG367 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm D SOT266-1 E A X c y HE v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0 1.4 1.2 0.25 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-04-05 95-02-25 SOT266-1 1996 August 28 EUROPEAN PROJECTION 13 o Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 August 28 14 Philips Semiconductors Product specification Low-voltage frequency synthesizer for radio telephones UMA1021M DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 647021/1200/03/pp16 Date of release: 1996 August 28 Document order number: 9397 750 01062