DATA SHEET COMPOUND TRANSISTOR µPA104 HIGH FREQUENCY NPN TRANSISTOR ARRAY FEATURES • 9 GHz CONFIGURABLE TRANSISTOR BASED OR/NOR CIRCUITRY • OUTSTANDING hFE LINEARITY • TWO PACKAGE OPTIONS: µPA104B: Studded ceramic package provides superior thermal dissipation µPA104G: Reduced circuit size due to 14-pin plastic SOP package for surface mounting • EXCELLENT FOR ANALOG ADDITIONS & FORMATION OF 2-INPUT OR/NOR GATES DESCRIPTION AND APPLICATIONS The µPA104 is a user-configurable, Si bipolar transistor array for formation of high speed OR/NOR gates. Its internal transistor configuration and external connection options allow the user considerable flexibility in its application. Its high gain bandwidth product (fT = 9 GHz) make it applicable for electro-optical, signal processing, cellular telephone systems, instrumentation, and high speed gigabit logic circuits. ORDERING INFORMATION PART NUMBER PACKAGE µPA104B-E1 14-pin ceramic package µPA104G-E1 14-pin plastic SOP (225 mil) ABSOLUTE MAXIMUM RATINGS (TA = +25 °C) SYMBOLS PARAMETERS UNITS RATINGS VCBO* Collector to Base Voltage V 15 VCEO* Collector to Emitter Voltage V 6 VEBO* Emitter to Base Voltage V 2.5 IC * Collector Current mA 40 PT Power Dissipation µPA104B µPA104G mW mW 650 350 Junction Temperature µPA104B µPA104G °C °C 200 125 Storage Temperature µPA104B µPA104G °C °C –55 to +200 –55 to +125 TJ TSTG * Absolute maximum ratings for each transistor. Caution electro-static sensitive devices The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. P10709EJ2V0DS00 (2nd edition) Date Published October 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1995, 1999 µPA104 PACKAGE DIMENSIONS (UNIT: mm) µPA104B 14 PIN CERAMIC PACKAGE φ 0.8 TOP VIEW 0.35 6.2 1.27 5.0 MAX. 4.5 MIN. 2. 7 SIDE VIEW MAX. 0.08 2.3 MIN. φ 1.6 BOTTOM VIEW 1.8 3.0 µPA104G 14 PIN PLASTIC SOP (225 mil) 14 8 detail of lead end +7° 3° –3° 1 7 10.2 ± 0.26 6.55 ± 0.2 4.38 ± 0.1 1.49 1.1 ± 0.16 0.6 ± 0.2 1.42 MAX 1.27 0.40 +0.10 –0.05 +0.10 0.15 –0.05 0.10 0.10 M 0.1 ± 0.1 1.59 +0.21 –0.20 NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. See connection diagram for description of leads. 2 Data Sheet P10709EJ2V0DS00 µPA104 ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 ˚C µPA104B, µPA104G common) SYMBOLS PARAMETERS AND CONDITIONS UNITS MIN. TYP. MAX. ICBO Collector Cutoff Current at VCB = 5 V, IE = 0 (Q1 thru Q6) µA 1.0 IEBO Emitter Cutoff Current at VEB = 1 V, IC = 0 (Q4 thru Q6) µA 1.0 hFE Direct Current Amplification at VCE = 3 V, IC = 5 mA (Q4 and Q6) CCB Collector to Base Capacitance at V CB = 3 V, f = 1 MHz (Q3, Q5, Q6) CEB CCS fT 40 100 250 pF 0.9 1.8 Emitter to Base Capacitance at VEB = 0, f = 1 MHz (Q4 thru Q6) pF 1.4 2.8 Collector/Substrate Capacitance, V CS = 3 V, f = 1 MHz (Q3, Q5, Q6) pF 1.4 2.8 GHz 9.0 Gain Bandwidth Product* at VCE = 3 V, IC = 10 mA * Measured by installing a single transistor in a Micro-X package: the value shown is a reference value. CONNECTION DIAGRAM (Top View) µPA104B 14 13 12 11 10 9 8 6 7 Q6 Q5 Q1 Q2 Q3 SUB Q4 2 1 3 4 5 µPA104G 14 13 12 11 10 9 Q5 8 Q6 Q1 Q2 Q3 Q4 1 2 3 4 5 6 7 Note: Substrate should be connected to the lowest voltage point in order to prevent latch-up. Data Sheet P10709EJ2V0DS00 3 µPA104 TYPICAL PERFORMANCE CHARACTERISTICS (TA = +25 °C) COLLECTOR CURRENT vs. BASE TO EMITTER VOLTAGE COLLECTOR CURRENT vs. COLLECTOR TO EMITTER VOLTAGE 10 200 100 8 Collector Current, IC (mA) Collector Current, IC (mA) 100 80 60 6 40 4 IB = 20 µ A 2 50 20 10 5 2 1 0.5 VCE = 3 V 0 0 0.1 1 2 3 4 5 Collector to Emitter Voltage, VCE (V) 0 DC CURRENT GAIN vs. COLLECTOR CURRENT GAIN BANDWIDTH PRODUCT vs. COLLECTOR CURRENT 12 Gain Bandwidth Product, fT (GHz) DC Current Gain, hFE 1000 200 VCE = 3 V 100 50 20 10 0.5 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Base to Emitter Voltage, VBE (V) 1 2 5 10 20 Collector Current, IC (mA) 50 VCE = 5 V 10 8 3V 6 1V 4 1 2 5 10 20 Collector Current, IC (mA) GAIN AND NOISE FIGURE OF INDIVIDUAL TRANSISTOR 20 8 Gain (dB) GAIN 6 10 4 NF 0 4 1 2 5 10 20 50 100 Collector Current, IC (mA) Data Sheet P10709EJ2V0DS00 2 0 Noise Figure, NF (dB) VCC = 3 V f = 1 GHz 50 µPA104 TYPICAL APPLICATION A B OR A+B A B VCC (+2 V) 100 Ω 115 Ω 300 Ω OR 50 Ω VBB (–1.6 V) 100 Ω 50 KΩ 47 Ω 50 KΩ 1.5 KΩ 2.8 KΩ VEE (–3.2 V) +1.1 V IN 50 % t++ 50 % t–– tf tR +0.3 V OUT (OR) 50 % 50 % 90 % 10 % tf = 500 psec. tR = 750 psec. t++ = 500 psec. t–– = 250 psec. The application circuits and their parameters are for references only and are not intended for use in actual design-in's. Data Sheet P10709EJ2V0DS00 5 µPA104 NOTES ON CORRECT USE (1) Observe precautions for handling because of electro-static sensitive devices. (2) Form a ground pattern as wide as possible to maintain the minimum ground impedance (to prevent undesired oscillation). (3) Design circuits connected Sub pin to the lowest voltage to prevent latch-up. (4) Design circuits as each pin voltage difference within 15 V maximum. RECOMMENDED SOLDERING CONDITIONS This product should be soldered in the following recommended conditions. Other soldering methods and conditions than the recommended conditions are to be consulted with our sales representatives. µPA104G Soldering process Soldering conditions Recommended condition symbol Infrared ray reflow Package peak temperature: 235 °C, Hour: within 30 s. (more than 210 °C), Time: 2 times, Limited days: no.Note IR35-00-2 VPS Package peak temperature: 215 °C, Hour: within 40 s. (more than 200 °C), Time: 2 times, Limited days: no.Note VP15-00-2 Wave soldering Soldering tub temperature: less than 260 °C, Hour: within 10 s. Time: 1 time, Limited days: no.Note WS60-00-1 Pin part heating Pin area temperature: less than 300 °C, Hour: within 3 s./pin Limited days: no.Note µPA104B Soldering process Soldering conditions Infrared ray reflow Peak package’s surface temperature: 230 °C or below, Reflow time: 10 seconds or below (210 °C or higher), Number of reflow process: 1, Exposure limit*: None Partial heating method Terminal temperature: 260 °C or below, Flow time: 10 seconds or below, Exposure limit*: None Symbol Note It is the storage days after opening a dry pack, the storage conditions are 25 °C, less than 65 % RH. Caution The combined use of soldering method is to be avoided (However, except the pin area heating method). For details of recommended soldering conditions for surface mounting, refer to information document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E). 6 Data Sheet P10709EJ2V0DS00 µPA104 [MEMO] Data Sheet P10709EJ2V0DS00 7 µPA104 NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. 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