DATA SHEET MOS FIELD EFFECT TRANSISTOR μ PA2757GR SWITCHING N-CHANNEL POWER MOS FET PACKAGE DRAWING (Unit: mm) DESCRIPTION The μ PA2757GR is Dual N-channel MOS Field Effect 8 Transistors designed for switching application. 5 1 : Source 1 2 : Gate 1 7, 8 : Drain 1 FEATURES 3 : Source 2 4 : Gate 2 5, 6 : Drain 2 • Low on-state resistance RDS(on)1 = 36.0 mΩ MAX. (VGS = 10 V, ID = 3.0 A) RDS(on)2 = 50.0 mΩ MAX. (VGS = 4.5 V, ID = 3.0 A) • Built-in G-S protection diode 0.05 MIN. • Small and surface mount package (Power SOP8) ORDERING INFORMATION PART NUMBER LEAD PLATING μ PA2757GR-E1-AT Note μ PA2757GR-E2-AT Note Pure Sn 4.4 5.37 MAX. 0.8 +0.10 –0.05 QG = 10 nC TYP. (VGS = 10 V) 6.0 ± 0.3 4 0.15 1.8 MAX. • Low gate charge 1.44 1 0.5 ± 0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 PACKING Tape 2500 p/reel 0.12 M PACKAGE Power SOP8 Note Pb-free (This product does not contain Pb in the external electrode and other parts.) EQUIVALENT CIRCUIT (1/2 circuit) Drain Body Diode Gate Gate Protection Diode Remark Source The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. Caution This product is electrostatic-sensitive device due to low ESD capability and should be handled with caution for electrostatic discharge. VESD ± 600 V TYP. (C = 100 pF, R = 1.5 kΩ) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G18206EJ2V0DS00 (2nd edition) Date Published November 2007 NS Printed in Japan The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. 2006, 2007 μ PA2757GR ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 30 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V ID(DC) ±5.0 A ID(pulse) ±20 A PT1 1.7 W PT2 2.0 W Tch 150 °C Drain Current (DC) (TC = 25°C) Drain Current (pulse) Note2 Note1 Total Power Dissipation (1 unit) Note2 Total Power Dissipation (2 units) Note2 Channel Temperature Tstg −55 to +150 °C Single Avalanche Current Note3 IAS 5 A Single Avalanche Energy Note3 EAS 2.5 mJ Storage Temperature <R> <R> Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1% 2 2. Mounted on ceramic substrate of 2000 mm × 1.6 mmt 3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V <R> 2 Data Sheet G18206EJ2V0DS μ PA2757GR ELECTRICAL CHARACTERISTICS (TA = 25°C. All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT 10 μA ±10 μA 2.5 V Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V Gate Leakage Current IGSS VGS = ±16 V, VDS = 0 V VGS(off) VDS = 10 V, ID = 1 mA 1.0 | yfs | VDS = 10 V, ID = 3 A 2.0 RDS(on)1 VGS = 10 V, ID = 3.0 A 28.5 36.0 mΩ RDS(on)2 VGS = 4.5 V, ID = 3.0 A 36.0 50.0 mΩ Input Capacitance Ciss VDS = 10 V, 400 pF Output Capacitance Coss VGS = 0 V, 80 pF Reverse Transfer Capacitance Crss f = 1 MHz 50 pF Turn-on Delay Time td(on) VDD = 15 V, ID = 3 A, 7 ns Rise Time tr VGS = 10 V, 4 ns Turn-off Delay Time td(off) RG = 10 Ω 21 ns Fall Time tf 5 ns Total Gate Charge QG ID = 5 A, 10 nC Gate to Source Charge QGS VDD = 24 V, 1.5 nC QGD VGS = 10 V 2.7 nC VF(S-D) IF = 5 A, VGS = 0 V 0.86 V Reverse Recovery Time trr IF = 5 A, VGS = 0 V, 20 ns Reverse Recovery Charge Qrr di/dt = 50 A/μs 16 nC Gate to Source Cut-off Voltage Forward Transfer Admittance Note Drain to Source On-state Resistance Note Gate to Drain Charge Body Diode Forward Voltage Note S Note Pulsed <R> TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω VGS RL Wave Form RG PG. VDD VGS 0 VGS 10% 90% VDD VDS 90% BVDSS IAS 90% VDS VGS 0 VDS 10% 0 10% Wave Form VDS ID τ VDD Starting Tch τ = 1 μs Duty Cycle ≤ 1% td(on) tr ton td(off) tf toff TEST CIRCUIT 3 GATE CHARGE D.U.T. IG = 2 mA PG. 50 Ω RL VDD Data Sheet G18206EJ2V0DS 3 μ PA2757GR TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.5 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 120 100 80 60 40 20 Mounted on ceramic substrate of 2 2000 mm x 1.6 mmt 2 units 2 1 unit 1.5 1 0.5 0 0 0 20 40 60 80 0 100 120 140 160 20 40 60 80 100 120 140 160 TA - Ambient Temperature - °C TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA 100 ID - Drain Current - A ID(pulse) 10 PW ID(DC) 1i 0 DC d it e m Li V ) ) n 0 i o 1 S( = D R GS (V 1 0.1 1i = m 20 0 s i m 1i 0 μs 0 m s i s i Po w er D is si p Mounted on ceramic substrate of at io n Li m it e d 2000 mm2 x 1.6 mmt, 1 unit TA = 25°C Single pulse 0.01 0.01 0.1 1 10 100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - °C/W 1000 4 Rth(ch-A) = 73.5°C/Wi 100 10 1 Mounted on ceramic substrate of 2000 mm2 x 1.6 mmt, 1 unit TA = 25°C Single pulse 0.1 100 μ 1m 10 m 100 m 1 PW - Pulse Width – s Data Sheet G18206EJ2V0DS 10 100 1000 μ PA2757GR DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 25 100 VGS = 10 V 15 ID - Drain Current - A ID - Drain Current - A 20 VDS = 10 V Pulsed 10 4.5 V 10 5 1 TA = 150°C 75°C 25°C −25°C 0.1 0.01 0.001 Pulsed 0 0.0001 0.5 1 1.5 0 1 3 4 VGS - Gate to Source Voltage - V GATE TO SOURCE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 2.5 2 1.5 1 0.5 VDS = 10 V ID = 1 mA 0 -50 0 50 100 10 1 0.1 −25°C 25°C 75°C TA = 150°C 0.01 0.001 100 μ 150 1m 100 Pulsed 80 VGS = 4.5 V 40 10 V 20 0 1 10 100 m 1 10 100 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT 60 10 m VDS = 10 V Pulsed ID - Drain Current - A Tch - Channel Temperature - °C RDS(on) - Drain to Source On-state Resistance - mΩ 2 VDS - Drain to Source Voltage - V | yfs | - Forward Transfer Admittance - S VGS(off) - Gate to Source Cut-off Voltage - V 0 100 ID - Drain Current - A ID = 3.0 A Pulsed 80 60 40 20 0 0 5 10 15 20 VGS - Gate to Source Voltage - V Data Sheet G18206EJ2V0DS 5 μ PA2757GR CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 1000 ID = 3.0 A Pulsed 80 60 VGS = 4.5 V 40 10 V 20 0 50 100 150 100 Crss VGS = 0 V f = 1 MHz 10 100 Tch - Channel Temperature - °C SWITCHING CHARACTERISTICS DYNAMIC INPUT/OUTPUT CHARACTERISTICS td(off) VDS - Drain to Source Voltage - V VDD = 15 V VGS = 10 V RG = 10 Ω tf 10 td(on) tr 1 12 25 10 VDD = 24 V 15 V 6V 20 8 15 6 VGS 10 5 4 2 VDS ID = 5 A 0 1 10 100 0 0 ID - Drain Current - A 2 4 6 8 10 12 QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 100 10 VGS = 4.5 V 0V 1 0.1 0.01 Pulsed 0.001 trr - Reverse Recovery Time - ns 100 IF - Diode Forward Current - A 1 30 0.1 10 VGS = 0 V di/dt = 50 A/μs 1 0 0.5 1 1.5 VF(S-D) - Source to Drain Voltage - V 6 0.1 VDS - Drain to Source Voltage - V 100 td(on), tr, td(off), tf - Switching Time - ns Coss 10 0.01 0 -50 Ciss 0.1 1 10 IF - Diode Forward Current - A Data Sheet G18206EJ2V0DS 100 VGS - Gate to Source Voltage - V 100 Ciss, Coss, Crss - Capacitance - pF RDS(on) - Drain to Source On-state Resistance - mΩ DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE μ PA2757GR TAPE INFORMATION There are two types (-E1, -E2) of taping depending on the direction of the device. Reel side Draw-out side −E1 TYPE −E2 TYPE MARKING INFORMATION A2757 Lot code 1 pin mark Pb-free plating marking RECOMMENDED SOLDERING CONDITIONS The μ PA2757GR should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Soldering Method Infrared reflow Soldering Conditions Maximum temperature (Package's surface temperature): 260°C or below Recommended Condition Symbol IR60-00-3 Time at maximum temperature: 10 seconds or less Time of temperature higher than 220°C: 60 seconds or less Preheating time at 160 to 180°C: 60 to 120 seconds Maximum number of reflow processes: 3 times Maximum chlorine content of rosin flux (percentage mass): 0.2% or less Partial heating Maximum temperature (Pin temperature): 350°C or below P350 Time (per side of the device): 3 seconds or less Maximum chlorine content of rosin flux: 0.2% (wt.) or less Caution Do not use different soldering methods together (except for partial heating). Data Sheet G18206EJ2V0DS 7 μ PA2757GR • The information in this document is current as of November, 2007. The information is subject to change without notice. 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