NEC UPD161401

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD161401
256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
DESCRIPTION
The µPD161401 is an LCD controller/driver with RAM and is capable of driving a full-dot LCD. It can display 256
colors on an RGB-STN color LCD. This LCD controller/driver can drive a full-dot LCD of up to 101 × 80 pixel with a
single chip.
FEATURES
• LCD driver with on-chip display RAM
• Logic power supply operation from +1.8 V to +3.6 V
• Internal booster circuit: x 2 to x 7 selectable
• Dot display RAM: (101 x 80) x 8 bits
• 8 (R, G)/4 (B) grayscales selectable from 17 levels
• Full-dot output: 303 segment lines and 80 common lines
• Serial interface (SI, SCL) or 8-/16-bit parallel data input (i80 or M68 system interface)
• On-chip voltage divider resistor
• Selectable bias value: 1/9 to 1/5
• Selectable duty ratio: 1/80, 1/72 and 1/64 (main duty)
• On-chip oscillator
ORDERING INFORMATION
Part Number
Package
µPD161401W/P
Wafer/Chip (supports COF)
Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
S15726EJ2V0DS00 (2nd Edition)
Data Published June 2002 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
2001
µPD161401
CONTENT
1. BLOCK DIAGRAM ................................................................................................................................... 5
2. PIN CONFIGURATION (Pad Layout) ..................................................................................................... 6
3. PIN FUNCTIONS...................................................................................................................................... 12
3.1 Power Supply Pins...........................................................................................................................................12
3.2 Logic Circuit Pins ............................................................................................................................................13
3.3 Driver Pins ........................................................................................................................................................15
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS.................................... 16
5. FUNCTIONAL DESCRIPTION................................................................................................................. 17
5.1 CPU Interface ....................................................................................................................................................17
5.1.1
Selecting interface type...........................................................................................................................17
5.1.2
Parallel interface .....................................................................................................................................17
5.1.3
Serial interface........................................................................................................................................19
5.1.4
Chip select ..............................................................................................................................................19
5.1.5
Accessing display data RAM and internal registers ................................................................................19
5.2 Display Data RAM ............................................................................................................................................21
5.2.1
Display data RAM ...................................................................................................................................21
5.2.2
X address circuit .....................................................................................................................................21
5.2.3
Y address circuit .....................................................................................................................................23
5.2.4
Column address circuit ...........................................................................................................................24
5.2.5
Common scan circuit ..............................................................................................................................25
5.2.6
Display data latch circuit .........................................................................................................................28
5.2.7
Arbitrary address area access (window access mode (WAS)) ...............................................................28
5.3 Screen Processing...........................................................................................................................................30
5.3.1
Blink/reverse display circuit.....................................................................................................................30
5.3.2
Example of setting blink area..................................................................................................................33
5.4 Oscillator ..........................................................................................................................................................33
5.5 Display Timing Generator ...............................................................................................................................35
5.6 Power Supply Circuit .......................................................................................................................................37
5.6.1
Power supply circuit ................................................................................................................................37
5.6.2
Booster circuit .........................................................................................................................................37
5.6.3
Voltage regulator circuit ..........................................................................................................................39
5.6.4
Level voltage control by operational amplifier .........................................................................................42
5.6.5
Application example of power supply circuit ...........................................................................................44
5.7 Driving LCD ......................................................................................................................................................48
5.7.1
2
Full-dot pulse modulation........................................................................................................................48
Data Sheet S15726EJ2V0DS
µPD161401
5.7.2
Grayscale palette....................................................................................................................................51
5.7.3
Setting of display size .............................................................................................................................52
5.7.4
Setting of LCD N-line inversion and M-line shift......................................................................................52
5.7.5
Reverse driving between frames ............................................................................................................54
5.8 Display Mode....................................................................................................................................................55
5.8.1
Selecting display mode ...........................................................................................................................55
5.8.2 Screen scrolling .......................................................................................................................................58
5.8.3 Scroll setting examples ............................................................................................................................59
5.9 Reset .................................................................................................................................................................61
6. COMMANDS ............................................................................................................................................ 63
6.1 Control Register 1 (R0)....................................................................................................................................64
6.2 Control Register 2 (R1)....................................................................................................................................65
6.3 Reset Command Register (R3) .......................................................................................................................66
6.4 X Address Register (R4) ..................................................................................................................................66
6.5 Y Address Register (R5) ..................................................................................................................................66
6.6 MIN.·X Address Register (R7) .........................................................................................................................67
6.7 MAX.·X Address Register (R8) ........................................................................................................................67
6.8 MIN.·Y Address Register (R9) .........................................................................................................................67
6.9 MAX.·Y Address Register (R10) ......................................................................................................................68
6.10 Display Memory Access Register (R12).......................................................................................................68
6.11 Main Duty Setting Register (R14) .................................................................................................................69
6.12 Main Duty N-line Inversion Register (R15)...................................................................................................69
6.13 Main Duty M-line Shift Register (R16) ..........................................................................................................70
6.14 Sub-duty Setting Register (R17) ...................................................................................................................71
6.15 Sub-duty N-line Inversion Register (R18) ....................................................................................................72
6.16 Sub-duty M-line Shift Register (R19)............................................................................................................73
6.17 COM Scanning Address Setting Register (R21)..........................................................................................74
6.18 Sub-duty Start Address Register (R22)........................................................................................................77
6.19 Scroll Fixed Area Position Register (R23) ...................................................................................................78
6.20 Scroll Fixed Area Width Register (R27) .......................................................................................................78
6.21 Scroll Step Number Register (R31) ..............................................................................................................79
6.22 Blink/Reverse Setting Register (R37)...........................................................................................................80
6.23 Complementary Color Blink X Address Register (R38) ..............................................................................80
6.24 Complementary Color Blink Start Line Address Register (R39)................................................................81
6.25 Complementary Color Blink End Line Address Register (R40) .................................................................81
6.26 Complementary Color Blink Data Memory Register (R41) .........................................................................82
6.27 Specified Color Blink X Address Register (R42) .........................................................................................82
6.28 Specified Color Blink Start Line Address Register (R43) ...........................................................................83
6.29 Specified Color Blink End Line Address Register (R44) ............................................................................83
6.30 Specified Color Blink Data Memory Register (R45) ....................................................................................84
6.31 Specified Color Setting Register (R46) ........................................................................................................84
Data Sheet S15726EJ2V0DS
3
µPD161401
6.32 Reverse X Address Register (R47) ...............................................................................................................84
6.33 Reverse Start Line Address Register (R48) .................................................................................................85
6.34 Reverse End Line Address Register (R49) ..................................................................................................85
6.35 Reverse Data Memory Access Register (R50).............................................................................................86
6.36 Power System Control Register 1 (R52) ......................................................................................................87
6.37 Power System Control Register 2 (R53) ......................................................................................................88
6.38 Power System Control Register 3 (R54) ......................................................................................................89
6.39 Power System Control Register 4 (R55) ......................................................................................................90
6.40 Power System Control Register 5 (R56) ......................................................................................................91
6.41 Main Electronic Volume Register (R57) .......................................................................................................92
6.42 Sub-electronic Volume Register (R58).........................................................................................................92
6.43 RAM Test Mode Setting Register (R61)........................................................................................................93
6.44 Driving Mode Select Register (R64) .............................................................................................................93
6.45 Main R Grayscale Data Registers (R65 to R72) ...........................................................................................94
6.46 Main G Grayscale Data Registers (R73 to R80) ...........................................................................................95
6.47 Main B Grayscale Data Registers (R81 to R84) ...........................................................................................96
6.48 Sub R Grayscale Data Registers (R85 to R92).............................................................................................97
6.49 Sub G Grayscale Data Registers (R93 to R100) ..........................................................................................98
6.50 Sub B Grayscale Data Registers (R101 to R104).........................................................................................99
7. µPD161401 REGISTER LIST ................................................................................................................ 100
8. POWER SEQUENCE............................................................................................................................. 102
8.1 Power ON Sequence (with Internal Power Supply, Power ON → Display ON) ........................................103
8.2 Power OFF Sequence (with Internal Power Supply) ...................................................................................105
8.3 Power ON Sequence (with External Driving Power Supply, Power ON → Display ON)...........................106
8.4 Power OFF Sequence (with External Driving Power Supply).....................................................................107
8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF .................................................................108
8.6 Flow of VOUT and VLCD Voltages in Display Output and HALT/Standby Modes.........................................109
9. USING RAM TEST MODE ..................................................................................................................... 110
10. ELECTRICAL SPECIFICATIONS........................................................................................................ 111
11. CPU INTERFACE (Reference Example)............................................................................................ 120
4
Data Sheet S15726EJ2V0DS
µPD161401
1. BLOCK DIAGRAM
SEG1
SEG303
O1
O80
Common driver
Segment driver
Common timing
generator
Segment gray-scale control
IFM0
IFM1
/CS1
CS2
/RD(E)
/WR(R,/W)
D15 to D8
Display data latch
D7(SI)
Graphic control
D6(SCL)
D5 to D0
RS
/DISP
I/O
buffer
Display data RAM
101 x 8 x 80 bits
Blink & Inverse data RAM
303 bits
TOUT15 to TOUT0
M,/S
FR
FRSYNC
Logic Control Circuit
DOF
TSTRTST
TSTVIHL
TPWR0, TPWR1
Data
control
Data
register
Gray-scale
control
Register
Command
decorder
OSCIN1
OSCIN2
OSCOUT
OSCSYNC
Address
control
VDD1
VDD2
Oscillator
circuit
VSS
Timing generator
C1 +, C1 DC/DC
converter
D/A
converter
Op amp.
LCD voltage generator
C5 +
, C5 -
VOUT VOUT2
Remark
VRS IRS
VR
AMPOUTM AMPOUTS
VLCD
VLC1
VLC2
VLC3
VLC4
/xxx is an active-low signal.
Data Sheet S15726EJ2V0DS
5
µPD161401
2. PIN CONFIGURATION (Pad Layout)
• µPD161401W/P
Chip size: 2.57 x 16.05 mm2
Chip thickness: 485 µm (TYP.)
713
M1
D
u
m
m
y O80
D
u
m
m
O41 y
672
671
Dummy
1
SEG303
SEG302
SEG301
Y
SEG194
SEG193
Dummy
SEG192
SEG191
X
I/O side
SEG3
SEG2
SEG1
Dummy
317
360
M2
318
6
D O40
u
m
m
y
O1 D
u
m
m
y
Data Sheet S15726EJ2V0DS
359
µPD161401
Details of pad and alignment mark
Pad type
A type
Pad size (Al): 39 x 71 µm2 TYP.
Bump size : 33 x 65 µm2 TYP.
Bump height: 17 µm TYP.
B type
Pad size (Al): 93 x 71 µm2 TYP.
Bump size: 87 x 65 µm2 TYP.
Bump height: 17 µm TYP.
Alignment mark (unit: µm)
X
Y
M1
−1140.00
7560.00
M2
−1140.00
−7560.00
Shape of mark (unit: µm)
Mark center
80φ (M1)
75φ (M2)
Data Sheet S15726EJ2V0DS
7
µPD161401
Table 2−
−1 Pad Layout (1/4)
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
8
Pad Name
DUMMY
VSS
VSS
VSS
VOUT
VOUT
VOUT
VOUT2
VOUT2
VOUT2
VSS
VSS
VSS
C5−
C5−
C5−
C5+
C5+
C5+
C4−
C4−
C4−
C4+
C4+
C4+
C3−
C3−
C3−
C3+
C3+
C3+
C2−
C2−
C2−
C2+
C2+
C2+
C1−
C1−
C1−
C1+
C1+
C1+
VSS
VSS
VSS
TPWR1
TPWR1
TPWR1
TPWR0
TPWR0
TPWR0
VRS
VRS
VRS
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD1
VDD1
VDD1
VSS
VSS
VSS
Pad
Type
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Layout [µm]
X
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
Y
7230.00
7105.00
7060.00
7015.00
6970.00
6925.00
6880.00
6835.00
6790.00
6745.00
6700.00
6655.00
6610.00
6565.00
6520.00
6475.00
6430.00
6385.00
6340.00
6295.00
6250.00
6205.00
6160.00
6115.00
6070.00
6025.00
5980.00
5935.00
5890.00
5845.00
5800.00
5755.00
5710.00
5665.00
5620.00
5575.00
5530.00
5485.00
5440.00
5395.00
5350.00
5305.00
5260.00
5215.00
5170.00
5125.00
5080.00
5035.00
4990.00
4945.00
4900.00
4855.00
4810.00
4765.00
44720.00
4675.00
4630.00
4585.00
4540.00
4495.00
4450.00
4405.00
4360.00
4315.00
4270.00
4225.00
4180.00
4135.00
4090.00
4045.00
Pad
No.
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Pad Name
VSS
VSS
VSS
M, /S
M, /S
M, /S
VDD1
VDD1
VDD1
IFM0
IFM0
IFM0
VSS
VSS
VSS
IFM1
IFM1
IFM1
VDD1
VDD1
VDD1
IRS
IRS
IRS
VSS
VSS
VSS
/CS1
/CS1
/CS1
CS2
CS2
CS2
VDD1
VDD1
VDD1
/DISP
/DISP
/DISP
RS
RS
RS
VSS
VSS
VSS
/WR (R, /W)
/WR (R, /W)
/WR (R, /W)
/RD (E)
/RD (E)
/RD (E)
VDD1
VDD1
VDD1
D15
D15
D15
D14
D14
D14
D13
D13
D13
VSS
VSS
VSS
D12
D12
D12
D11
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Layout [µm]
X
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
Data Sheet S15726EJ2V0DS
Y
4000.00
3955.00
3910.00
3865.00
3820.00
3775.00
3730.00
3685.00
3640.00
3595.00
3550.00
3505.00
3460.00
3415.00
3370.00
3325.00
3280.00
3235.00
3190.00
3145.00
3100.00
3055.00
3010.00
2965.00
2920.00
2875.00
2830.00
2785.00
2740.00
2695.00
2650.00
2605.00
2560.00
2515.00
2470.00
2425.00
2380.00
2335.00
2290.00
2245.00
2200.00
2155.00
2110.00
2065.00
2020.00
1975.00
1930.00
1885.00
1840.00
1795.00
1750.00
1705.00
1660.00
1615.00
1570.00
1525.00
1480.00
1435.00
1390.00
1345.00
1300.00
1255.00
1210.00
1165.00
1120.00
1075.00
1030.00
985.00
940.00
895.00
Pad
No.
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
Pad Name
D11
D11
D10
D10
D10
VSS
VSS
VSS
D9
D9
D9
D8
D8
D8
VSS
VSS
VSS
D7
D7
D7
D6
D6
D6
D5
D5
D5
VSS
VSS
VSS
D4
D4
D4
D3
D3
D3
D2
D2
D2
VSS
VSS
VSS
D1
D1
D1
D0
D0
D0
VSS
VSS
VSS
FRSYNC
FRSYNC
FRSYNC
FR
FR
FR
DOF
DOF
DOF
OSCSYNC
OSCSYNC
OSCSYNC
VSS
VSS
VSS
OSCIN1
OSCIN1
OSCIN1
VSS
VSS
Pad
Type
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Pad Layout [µm]
X
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
Y
850.00
805.00
760.00
715.00
670.00
625.00
580.00
535.00
490.00
445.00
400.00
355.00
310.00
265.00
220.00
175.00
130.00
85.00
40.00
-5.00
-50.00
-95.00
-140.00
-185.00
-230.00
-275.00
-320.00
-365.00
-410.00
-455.00
-500.00
-545.00
-590.00
-635.00
-680.00
-725.00
-770.00
-815.00
-860.00
-905.00
-950.00
-995.00
-1040.00
-1085.00
-1130.00
-1175.00
-1220.00
-1265.00
-1310.00
-1355.00
-1400.00
-1445.00
-1490.00
-1535.00
-1580.00
-1625.00
-1670.00
-1715.00
-1760.00
-1805.00
-1850.00
-1895.00
-1940.00
-1985.00
-2030.00
-2075.00
-2120.00
-2165.00
-2210.00
-2255.00
µPD161401
Table 2−
−1 Pad Layout (2/4)
Pad
Pad Name
No.
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
VSS
OSCIN2
OSCIN2
OSCIN2
VSS
VSS
VSS
OSCOUT
OSCOUT
OSCOUT
VSS
VSS
VSS
TSTRTST
TSTRTST
TSTRTST
TSTVIHL
TSTVIHL
TSTVIHL
TOUT15
TOUT15
TOUT15
TOUT14
TOUT14
TOUT14
TOUT13
TOUT13
TOUT13
TOUT12
TOUT12
TOUT12
TOUT11
TOUT11
TOUT11
TOUT10
TOUT10
TOUT10
TOUT9
TOUT9
TOUT9
TOUT8
TOUT8
TOUT8
TOUT7
TOUT7
TOUT7
TOUT6
TOUT6
TOUT6
TOUT5
TOUT5
TOUT5
TOUT4
TOUT4
TOUT4
TOUT3
TOUT3
TOUT3
TOUT2
TOUT2
TOUT2
TOUT1
TOUT1
TOUT1
TOUT0
TOUT0
TOUT0
VSS
VSS
VSS
Pad
Pad Layout [µm]
Pad
Type
X
No.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
Y
-2300.00
-2345.00
-2390.00
-2435.00
-2480.00
-2525.00
-2570.00
-2615.00
-2660.00
-2705.00
-2750.00
-2795.00
-2840.00
-2885.00
-2930.00
-2975.00
-3020.00
-3065.00
-3110.00
-3155.00
-3200.00
-3245.00
-3290.00
-3335.00
-3380.00
-3425.00
-3470.00
-3515.00
-3560.00
-3605.00
-3650.00
-3695.00
-3740.00
-3785.00
-3830.00
-3875.00
-3920.00
-3965.00
-4010.00
-4055.00
-4100.00
-4145.00
-4190.00
-4235.00
-4280.00
-4325.00
-4370.00
-4415.00
-4460.00
-4505.00
-4550.00
-4595.00
-4640.00
-4685.00
-4730.00
-4775.00
-4820.00
-4865.00
-4910.00
-4955.00
-5000.00
-5045.00
-5090.00
-5135.00
-5180.00
-5225.00
-5270.00
-5315.00
-5360.00
-5405.00
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
Pad Name
VSS
VSS
VSS
VSS
VSS
VSS
VR
VR
VR
AMPOUTM
AMPOUTM
AMPOUTM
VSS
VSS
VSS
AMPOUTS
AMPOUTS
AMPOUTS
VSS
VSS
VSS
VLCD
VLCD
VLCD
VLC1
VLC1
VLC1
VLC2
VLC2
VLC2
VLC3
VLC3
VLC3
VLC4
VLC4
VLC4
DUMMY
DUMMY
O40
O39
O38
O37
O36
O35
O34
O33
O32
O31
O30
O29
O28
O27
O26
O25
O24
O23
O22
O21
O20
O19
O18
O17
O16
O15
O14
O13
O12
O11
O10
O9
Pad
Pad Layout [µm]
Pad
Type
X
No.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1060.00
-935.00
-890.00
-845.00
-800.00
-755.00
-710.00
-665.00
-620.00
-575.00
-530.00
-485.00
-440.00
-395.00
-350.00
-305.00
-260.00
-215.00
-170.00
-125.00
-80.00
-35.00
10.00
55.00
100.00
145.00
190.00
235.00
280.00
325.00
370.00
415.00
460.00
Data Sheet S15726EJ2V0DS
Y
-5450.00
-5495.00
-5540.00
-5585.00
-5630.00
-5675.00
-5720.00
-5765.00
-5810.00
-5855.00
-5900.00
-5945.00
-5990.00
-6035.00
-6080.00
-6125.00
-6170.00
-6215.00
-6260.00
-6305.00
-6350.00
-6395.00
-6440.00
-6485.00
-6530.00
-6575.00
-6620.00
-6665.00
-6710.00
-6755.00
-6800.00
-6845.00
-6890.00
-6935.00
-6980.00
-7025.00
-7150.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
Pad Name
O8
O7
O6
O5
O4
O3
O2
O1
DUMMY
DUMMY
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
Pad
Pad Layout [µm]
Type
X
A
A
A
A
A
A
A
A
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
505.00
550.00
595.00
640.00
685.00
730.00
775.00
820.00
945.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
Y
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7080.00
-6955.00
-6910.00
-6865.00
-6820.00
-6775.00
-6730.00
-6685.00
-6640.00
-6595.00
-6550.00
-6505.00
-6460.00
-6415.00
-6370.00
-6325.00
-6280.00
-6235.00
-6190.00
-6145.00
-6100.00
-6055.00
-6010.00
-5965.00
-5920.00
-5875.00
-5830.00
-5785.00
-5740.00
-5695.00
-5650.00
-5605.00
-5560.00
-5515.00
-5470.00
-5425.00
-5380.00
-5335.00
-5290.00
-5245.00
-5200.00
-5155.00
-5110.00
-5065.00
-5020.00
-4975.00
-4930.00
-4885.00
-4840.00
-4795.00
-4750.00
-4705.00
-4660.00
-4615.00
-4570.00
-4525.00
-4480.00
-4435.00
-4390.00
-4345.00
-4300.00
9
µPD161401
Table 2−
−1 Pad Layout (3/4)
Pad
Pad Name
No.
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
10
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
Pad
Pad Layout [µm]
Pad
Type
X
No.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
Y
-4255.00
-4210.00
-4165.00
-4120.00
-4075.00
-4030.00
-3985.00
-3940.00
-3895.00
-3850.00
-3805.00
-3760.00
-3715.00
-3670.00
-3625.00
-3580.00
-3535.00
-3490.00
-3445.00
-3400.00
-3355.00
-3310.00
-3265.00
-3220.00
-3175.00
-3130.00
-3085.00
-3040.00
-2995.00
-2950.00
-2905.00
-2860.00
-2815.00
-2770.00
-2725.00
-2680.00
-2635.00
-2590.00
-2545.00
-2500.00
-2455.00
-2410.00
-2365.00
-2320.00
-2275.00
-2230.00
-2185.00
-2140.00
-2095.00
-2050.00
-2005.00
-1960.00
-1915.00
-1870.00
-1825.00
-1780.00
-1735.00
-1690.00
-1645.00
-1600.00
-1555.00
-1510.00
-1465.00
-1420.00
-1375.00
-1330.00
1285.00
-1240.00
-1195.00
-1150.00
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
Pad Name
SEG131
SEG132
SEG133
SEG134
SEG135
SEG136
SEG137
SEG138
SEG139
SEG140
SEG141
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
SEG152
SEG153
SEG154
SEG155
SEG156
SEG157
SEG158
SEG159
SEG160
SEG161
SEG162
SEG163
SEG164
SEG165
SEG166
SEG167
SEG168
SEG169
SEG170
SEG171
SEG172
SEG173
SEG174
SEG175
SEG176
SEG177
SEG178
SEG179
SEG180
SEG181
SEG182
SEG183
SEG184
SEG185
SEG186
SEG187
SEG188
SEG189
SEG190
SEG191
SEG192
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
SEG193
Pad
Pad Layout [µm]
Pad
Type
X
No.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
Data Sheet S15726EJ2V0DS
Y
-1105.00
-1060.00
-1015.00
-970.00
-925.00
-880.00
-835.00
-790.00
-745.00
-700.00
-655.00
-610.00
-565.00
-520.00
-475.00
-430.00
-385.00
-340.00
-295.00
-250.00
-205.00
-160.00
-115.00
-70.00
-25.00
20.00
65.00
110.00
155.00
200.00
245.00
290.00
335.00
380.00
425.00
470.00
515.00
560.00
605.00
650.00
695.00
740.00
785.00
830.00
875.00
920.00
965.00
1010.00
1055.00
1100.00
1145.00
1190.00
1235.00
1280.00
1325.00
1370.00
1415.00
1460.00
1505.00
1550.00
1595.00
1640.00
1685.00
1730.00
1775.00
1820.00
1865.00
1910.00
1955.00
2000.00
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
Pad Name
SEG194
SEG195
SEG196
SEG197
SEG198
SEG199
SEG200
SEG201
SEG202
SEG203
SEG204
SEG205
SEG206
SEG207
SEG208
SEG209
SEG210
SEG211
SEG212
SEG213
SEG214
SEG215
SEG216
SEG217
SEG218
SEG219
SEG220
SEG221
SEG222
SEG223
SEG224
SEG225
SEG226
SEG227
SEG228
SEG229
SEG230
SEG231
SEG232
SEG233
SEG234
SEG235
SEG236
SEG237
SEG238
SEG239
SEG240
SEG241
SEG242
SEG243
SEG244
SEG245
SEG246
SEG247
SEG248
SEG249
SEG250
SEG251
SEG252
SEG253
SEG254
SEG255
SEG256
SEG257
SEG258
SEG259
SEG260
SEG261
SEG262
SEG263
Pad
Pad Layout [µm]
Type
X
Y
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
2045.00
2090.00
2135.00
2180.00
2225.00
2270.00
2315.00
2360.00
2405.00
2450.00
2495.00
2540.00
2585.00
2630.00
2675.00
2720.00
2765.00
2810.00
2855.00
2900.00
2945.00
2990.00
3035.00
3080.00
3125.00
3170.00
3215.00
3260.00
3305.00
3350.00
3395.00
3440.00
3485.00
3530.00
3575.00
3620.00
3665.00
3710.00
3755.00
3800.00
3845.00
3890.00
3935.00
3980.00
4025.00
4070.00
4115.00
4160.00
4205.00
4250.00
4295.00
4340.00
4385.00
4430.00
4475.00
4520.00
4565.00
4610.00
4655.00
4700.00
4745.00
4790.00
4835.00
4880.00
4925.00
4970.00
5015.00
5060.00
5105.00
5150.00
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
µPD161401
Table 2−
−1 Pad Layout (4/4)
Pad
Pad Name
No.
Pad
Pad Layout [µm]
Pad
Type
X
Y
No.
701
702
703
704
705
706
707
708
709
710
711
712
713
631
632
633
634
635
636
637
638
639
640
641
642
643
SEG264
SEG265
SEG266
SEG267
SEG268
SEG269
SEG270
SEG271
SEG272
SEG273
SEG274
SEG275
SEG276
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
5195.00
5240.00
5285.00
5330.00
5375.00
5420.00
5465.00
5510.00
5555.00
5600.00
5645.00
5690.00
5735.00
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
SEG277
SEG278
SEG279
SEG280
SEG281
SEG282
SEG283
SEG284
SEG285
SEG286
SEG287
SEG288
SEG289
SEG290
SEG291
SEG292
SEG293
SEG294
SEG295
SEG296
SEG297
SEG298
SEG299
SEG300
SEG301
SEG302
SEG303
DUMMY
DUMMY
O41
O42
O43
O44
O45
O46
O47
O48
O49
O50
O51
O52
O53
O54
O55
O56
O57
O58
O59
O60
O61
O62
O63
O64
O65
O66
O67
O68
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
950.00
825.00
780.00
735.00
690.00
645.00
600.00
555.00
510.00
465.00
420.00
375.00
330.00
285.00
240.00
195.00
150.00
105.00
60.00
15.00
-30.00
-75.00
-120.00
-165.00
-210.00
-255.00
-300.00
-345.00
-390.00
5780.00
5825.00
5870.00
5915.00
5960.00
6005.00
6050.00
6095.00
6140.00
6185.00
6230.00
6275.00
6320.00
6365.00
6410.00
6455.00
6500.00
6545.00
6590.00
6635.00
6680.00
6725.00
6770.00
6815.00
6860.00
6905.00
6950.00
7075.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
Pad Name
O69
O70
O71
O72
O73
O74
O75
O76
O77
O78
O79
O80
DUMMY
Data Sheet S15726EJ2V0DS
Pad
Pad Layout [µm]
Type
X
A
A
A
A
A
A
A
A
A
A
A
A
B
-435.00
-480.00
-525.00
-570.00
-615.00
-660.00
-705.00
-750.00
-795.00
-840.00
-885.00
-930.00
-1055.00
Y
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
11
µPD161401
3. PIN FUNCTIONS
3.1 Power Supply Pins
Symbol
VDD1
Pin Name
Logic power supply
Pin No.
I/O
65 to 67, 77 to 79,
−
Supplies power to the logic circuit.
Description
62 to 64
−
Supplies power to the booster circuit.
2 to 4, 11 to 13, 44 to 46,
−
Ground pin for the logic and driver circuits.
−
Supply power to the driver (output pins of the internal
89 to 91,104 to 106,
122 to 124
VDD2
Booster circuit power
supply
VSS
Logic and driver
ground pin
56 to 61, 68 to 73,
83 to 85, 95 to 97,
113 to 115, 134 to 136,
146 to 148, 155 to 157,
167 to 169, 179 to 181,
188 to 190, 203 to 205,
209 to 211, 215 to 217,
221 to 223, 278 to 286,
293 to 295, 299 to 301
VOUT,
Driver power supply
VOUT2
5 to 7,
booster circuit). Connect a 1 µF capacitor between GND
8 to 10
and these pins. When the internal booster circuit is not
used, the driver power can be directly input to the VOUT pin.
At this time, leave VOUT2 open.
VLCD,
Driver reference
302 to 304,
VLC1 to VLC4
power supply
305 to 316
C1+, C1−
Booster capacitor
C2+, C2−
connection pin
−
Supply the reference power for driving the LCD. Connect a
capacitor between GND and these pins when an internal
bias is selected.
C3+, C3−
43 to 14
−
These pins are used to connect capacitors for the internal
booster circuit. Connect a 1 µF capacitor between the
corresponding (+) and (−) pins.
C4+, C4−
C5+, C5−
12
Data Sheet S15726EJ2V0DS
µPD161401
3.2 Logic Circuit Pins (1/3)
Symbol
/CS1,
Pin Name
Chip select
CS2
Pin No.
I/O
98 to 100,
Input
101 to 103
Description
These pins are chip select signal pins.
When /CS1 = L (CS2 = H), the chip is active, and data/command
can be input or output and I/O manipulated.
/RD (E)
Read (enable)
119 to 121
Input
When i80 system parallel data transfer is selected (/RD), read is
enabled by this signal. When this pin is L, data is output to the data
bus. When M68 system parallel data transfer is selected (E), this
pin inputs an enable signal that triggers data write or read.
But in the µPD161401, the data of the display access memory
register, the complementary color blink data memory register, the
specified color blink data memory register and the reverse data
memory access register (R12, R41, R45, R50) cannot be read.
/WR (R,/W)
Write (read/write)
116 to 118
Input
When i80 system parallel data transfer is selected (/WR), write is
enabled by this signal. Data is written at the rising edge of this
signal. When M68 system parallel data transfer is selected (R, /W),
this pin determines the data transfer direction, as follows:
0: Write
1: Read
IFM0,
Interface selection
IFM1
86 to 88,
Input
Selects an interface mode
80 to 82
I/O
IFM1
IFM0
L
L
Serial
Interface Mode
L
H
Setting prohibited
H
L
i80 series parallel
H
H
M68 series parallel
This is a bi-directional data bus connected to an 8- or 16-bit
D0 to D15
Data bus
187 to 182,
(SI)
(serial input)
178 to 170,
standard CPU bus.
(SCL)
(serial clock)
166 to 158,
When the serial interface mode is selected (IFM1, IFM0 = L, L), D7
154 to 149,
functions as a serial data input pin (SI), and D6 serves as a serial
145 to 137,
clock input pin (SCL). At this time, D0 to D5 and D8 to D15 go into a
133 to 125
high-impedance state.
When the 8-bit data bus is selected, only D0 to D7 are used, and D8
to D15 go into a high-impedance state. Data is input starting from its
higher byte, followed by the lower byte. If the chip is not selected,
all D0 to D15 go into a high-impedance state.
RS
Index register/data
command selection
110 to 112
Input
This pin is usually connected to the least significant bit of a
standard CPU address bus to identify whether data is an index
register or data/command.
RS = H: Indicates that D0 to D15 are data/command.
RS = L: Indicates that D0 to D15 are an index register.
Data Sheet S15726EJ2V0DS
13
µPD161401
(2/3)
Symbol
/DISP
Pin Name
Reset
Pin No.
I/O
Description
107 to 109
Input
Making /DISP low initializes the DISP flag in the control register 1
(R0) and turns OFF the display. When the serial interface is used,
the write counter is also initialized. Making /DISP high enables
writing. To light the display after it has been turned OFF by this pin,
make /DISP high and set the DISP flag to 1.
FR
Frame signal
194 to 196
I/O
This pin inputs or outputs a liquid crystal AC signal.
M,/S = H : Output
M,/S = L : Input
When two or more µPD161401s are used in master/slave mode,
the respective FR pins must be connected to each other.
FRSYNC
Frame sync signal
191 to 193
I/O
This pin inputs or outputs a liquid crystal AC sync signal.
M,/S = H : Output
M,/S = L : Input
When two or more µPD161401s are used in master/slave mode,
the respective FRSYNC pins must be connected to each other.
DOF
Display blink
197 to 199
I/O
This pin controls blinking of the LCD.
M,/S = H : Output
M,/S = L : Input
When two or more µPD161401s are used in master/slave mode,
the respective DOF pins must be connected to each other.
M,/S
Master/slave
74 to 76
Input
This pin selects master or slave mode. In the master mode, it
outputs a timing signal necessary for driving the LCD. In the slave
mode, this timing signal is input from an external source to
synchronize the LCD.
M,/S = H : Master mode
M,/S = L : Slave mode
The status of each pin, including this pin, and the power circuit is
as follows depending on the status of the M,/S pin.
IRS
VLCD adjustment
92 to 94
Input
M,/S
Power Circuit
FR
FRSYNC
DOF
H
Enabled
Output
Output
Output
L
Disabled
Input
Input
Input
This pin selects the resistor used to adjust the VLCD voltage level.
IRS = H: The internal resistor is used.
IRS = L: The internal resistor is not used.
The VLCD voltage level is adjusted by an external voltage divider
resistor connected to the VR pin.
This pin is enabled only when the master operation mode is
selected. If the slave mode is selected, this pin is fixed to H or L.
14
Data Sheet S15726EJ2V0DS
µPD161401
(3/3)
Symbol
OSCIN1
Pin Name
Pin No.
I/O
Description
Oscillation signal pin
206 to 208
Input
These pins are connected with a resistor inserted between OSCIN1
212 to 214
Input
OSCIN2
and OSCOUT, and between OSCIN2 and OSCOUT. When an external
oscillator is used, input a clock signal to the OSCIN pin and leave
OSCOUT
OSCSYNC
Display clock output
218 to 220
Output
200 to 202
Output
the OSCOUT pin open.
This pin outputs a clock for display. When using the µPD161401 in
the master or slave mode, refer to 5.4 Oscillator.
TOUT0 to
Test output
230 to 277
Output
TOUT15
TSTRTST,
Usually, leave these pins open.
Test input pin
TSTVIHL
TPWR0,
These pins are used when the µPD161401 is in the test mode.
224 to 226,
Input
227 to 229
Test input/output pin
TPWR1
These pins are used to set the µPD161401 in the test mode.
Usually, connect these pins to VSS.
50 to 52,
I/O
These pins are used to input/output test signals when the
µPD161401 is in the test mode. Usually, leave these pins open.
47 to 49
3.3 Driver Pins
Symbol
SEG1 to
Pin Name
Pin No.
I/O
Description
Segment
361 to 670
Output
These pins output segment signals.
Common
319 to 358,
Output
These pins output common signals.
SEG303
O1 to O80
673 to 712
VRS
Operational amplifier
53 to 55
Input
input
These are the input pins of the operational amplifier that adjusts
the LCD driving voltage. VRS is used to input the reference voltage
of the amplifier for LCD voltage adjustment. VR is used to connect
a feedback resistor for the operational amplifier.
The feedback resistor is connected between this pin and GND,
287 to 289
VR
AMPOUTM, or AMPOUTS. This pin is enabled only when the internal
divider resistor for VLCD voltage adjustment is not used (IRS = L).
When the internal divider resistor is used (IRS = H), this pin is not
used.
AMPOUTM
Operational amplifier
Output
290 to 292
These pins are the output pins of the operational amplifier that
adjusts the LCD driving voltage. The signals output by these pins
output
are connected to the LCD driving voltage adjuster resistor (refer to
5.6.3 Voltage regulator circuit) only when the internal resistor for
296 to 298
AMPOUTS
LCD voltage adjustment is not used (IRS = L). It is recommended
to connect a capacitor of 0.01 to 0.1 µF to these pins to stabilize
the output of the internal operational amplifier.
DUMMY
Dummy pin
1, 317, 318, 359,
−
These pins are not connected to the internal circuit.
360, 553 to 559,
671, 672, 713
Data Sheet S15726EJ2V0DS
15
µPD161401
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit type of each pin and recommended connection of unused pins are shown in the table below.
Symbol
Input Type
I/O
Recommended of Unused Pins
Note
/CS1
Schmitt-trigger A
Input
Connect this pin to VSS.
−
CS2
Schmitt-trigger A
Input
Connect this pin to VDD1.
−
/RD(E)
Schmitt-trigger A
Input
Connect to VDD1 (i80 system interface), or to VDD1 or VSS (serial
−
interface).
/WR(R,/W)
Schmitt-trigger A
Input
Connect to VDD1 or VSS (serial interface).
−
IFM1, IFM0
Schmitt-trigger A
Input
Mode setting pin
1
D0 to D5
Schmitt-trigger B
I/O
Leave open.
−
D6(SCL)
Schmitt-trigger B
I/O
−
−
D7(SI)
Schmitt-trigger B
I/O
−
−
D8 to D15
Schmitt-trigger B
I/O
Leave open.
−
RS
Schmitt-trigger A
Input
Register setting pin
2
/DISP
Schmitt-trigger C
Input
FR
Schmitt-trigger A
I/O
Connect to VDD1.
−
Leave open (in master mode, M,/S = H).
−
−
FRSYNC
Schmitt-trigger A
I/O
Leave open (in master mode, M,/S = H).
DOF
Schmitt-trigger A
I/O
Leave open (in master mode, M,/S = H).
−
M,/S
Schmitt-trigger A
Input
Mode setting pin
1
IRS
Schmitt-trigger A
Input
Mode setting pin
1
OSCIN1
Schmitt-trigger A
Input
Connect to VDD1 or VSS.
−
OSCIN2
Schmitt-trigger A
Connect to VDD1 or VSS.
−
OSCOUT
−
Output
Leave open (when an external clock is used).
−
OSCSYNC
−
Output
Leave open.
−
TOUT0 to
−
Output
Leave open.
−
Input
TOUT15
TSTRTST
Schmitt-trigger A
Input
Connect this pin to VSS (in normal operation mode).
−
TSTVIHL
Schmitt-trigger A
Input
Connect this pin to VSS (in normal operation mode).
−
TPWR
−
Leave open.
−
I/O
Notes 1. Connect this pin to VDD1 or VSS depending on the mode selected.
2. Input VDD1 or VSS output from the CPU to this pin depending on the mode selected.
Remark Schmitt-trigger A : Schmitt inverter
Schmitt-trigger B : Schmitt NAND
Schmitt-trigger C : Schmitt inverter (with delay circuit)
16
Data Sheet S15726EJ2V0DS
µPD161401
5. FUNCTIONAL DESCRIPTION
5.1 CPU Interface
5.1.1 Selecting interface type
The µPD161401 transfers data through an 8-bit bi-directional data bus (D7 to D0), a 16-bit bi-directional data bus (D15
to D0), or a serial data input (SI) pin. Interface type can be selected by making the IFM1,IFM0 pin high or low, as shown
in the following table.
IFM1
IFM0
Interface type
L
L
Serial data input
L
H
Setting Prohibited
H
L
i80 system CPU
H
H
M68 system CPU
Parallel data input or serial data input can be chosen as by setting the polarity of IFM1 terminal, as shown in the
following table.
IFM1
/CS1, CS2
RS
H: Parallel input
/CS1, CS2
RS
L: Serial input
/CS1, CS2
RS
/RD
/WR
D15 to D8
D7
D6
D5 to D0
/RD
/WR
D15 to D8
D7
D6
D5 to D0
Note1
Note1
Hi-ZNote2
SI
SCL
Hi-ZNote2
Notes 1. Fix these pins to the high or low level.
2. Hi-Z: High impedance
5.1.2 Parallel interface
When the parallel interface is selected (IFM = H), an 8-bit bi-directional data bus (D7 to D0) or 16-bit bi-directional data
bus (D15 to D0) can be selected by setting the BMOD flag of the control register 2 (R1) to 1 or 0. In addition, the
µPD161401 can be directly connected to an i80 or M68 system by making the IFM0 pin high or low as shown in the
following table.
IFM0
/CS1, CS2
H: M68 system CPU
/CS1, CS2
L: i80 system CPU
/CS1, CS2
RS
/RD
/WR
RS
E
R,/W
RS
/RD
/WR
BMOD
D15 to D8
D7 to D0
0
D15 to D8
D7 to D0
1
Hi-ZNote
D7 to D0
0
D15 to D8
D7 to D0
1
Hi-ZNote
D7 to D0
Note Hi-Z : High impedance (may be open)
Data Sheet S15726EJ2V0DS
17
µPD161401
The data bus signals are identified by the combination of the RS, /RD(E), /WR (R,/W) signals as shown in the
following table.
Common
M68
i80
Common
Data Bus
Function
RS
R,/W
E
/RD
/WR
BMOD
D15 to D8
D7 to D0
1
1
1
0
1
0
Note1
Note1
1
Hi-Z
OUT
1
0
1
1
0
0
Note2
IN
1
Hi-Z
IN
0
1
1
0
1
0
Hi-Z
OUT
1
Hi-Z
OUT
0
0
1
1
0
0
Hi-Z
IN
1
Hi-Z
IN
Hi-Z
Hi-Z
0/1
Other
Reads the register.
Writes the display data/register.
Prohibited
Writes the control index register.
−
Remark IN : Input status (cannot be open), OUT : Output status, Hi-Z : High impedance (may be open)
Notes1. In the µPD161401, the data of the display access memory register, the complementary color blink data
memory register, the specified color blink data memory register and the reverse data memory access
register (R12, R41, R45, R50) are read-prohibited. However, if R12 is selected, the data bus signals D15 to
D0 enter an output state. If another register is specified, the D15 to D8 signals become Hi-Z and the D7 to D0
signals enter an output state.
2. Only the display access memory register (R12) enters the input state. If another register is specified, the D15
to D8 signals become Hi-Z.
18
Data Sheet S15726EJ2V0DS
µPD161401
5.1.3 Serial interface
When the serial interface has been selected (IFM1, IFM0 = L, L), as long as the chip is in an active state (/CS1= L,
CS2 = H ), serial data input (SI) and serial clock input (SCL) can be received. Serial data is read in the order of D7, then
D6 to D0 at the rising edge of the serial clock input from the serial input pin. This data is converted to parallel data in
synchronization with the 8th rising edge of the serial clock. Serial input data is judged as display data/command data if
RS = H and an index if RS = L. The RS input is read every 8th rising edge of the serial clock after the chip becomes
active and is used for data discrimination.
Figure 5−1. Serial Interface Signal Chart
CS2 = "H"
/CS1
SI
SCL
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
RS
Remarks 1. If the chip is not in an active state, the shift register and counter are reset to their initial statuses.
2. The serial clock counter is reset by initialization from the /DISP pin.
3. Data cannot be read when using serial interface mode.
4. Care must be taken when performing SCL wiring to avoid effects from terminal radiation or external noise
caused by the wiring length. It is recommended to confirm operation using the actual equipment to be
used.
5.1.4 Chip select
The µPD161401 has chip select pins (/CS1 and CS2). The CPU parallel interface or Serial interface can be used only
when /CS1 = L (CS2 = H).
If the chip select pins are not active, the D0 to D15 pins go into a high-impedance state, and the RS, /RD, and /WR pins
do not become active.
5.1.5 Accessing display data RAM and internal registers
When the CPU accesses the µPD161401, the CPU only has to satisfy the requirement of the cycle time (tCYC) and can
transfer data at high speeds. Usually, it is not necessary for the CPU to take wait time into consideration.
When the CPU writes data to the µPD161401, no dummy data is necessary. When reading data, dummy data is not
necessary either. In the µPD161401, the data of the display access memory register, the complementary color blink
data memory register, the specified color blink data memory register and the reverse data memory access register
(R12, R41, R45, R50) cannot be read. Figure 5−
−2 illustrates as follows.
Data Sheet S15726EJ2V0DS
19
µPD161401
Figure 5−
−2. Writing and Reading
Writing
/WR
DATA
N
N+1
N+2
N+3
Reading (other than display memory access register)
/WR
/RD
DATA
Caution
IRn
IRn
Data
IRn + 1
IRn+1
Data
IR Address
Set #n
IRn Register
Data Read
IR Address
Set #n+1
IRn+1 Register
Data Read
Display access memory register, the complementary color blink data memory register, the
specified color blink data memory register and the reverse data memory access register (R12,
R41, R45, R50) cannot be read.
20
Data Sheet S15726EJ2V0DS
µPD161401
5.2 Display Data RAM
5.2.1 Display data RAM
This RAM stores dot data for display and consists of (101 × 80) × 8 bits. Any address of this RAM can be accessed by
specifying an X address and a Y address.
Display data D0 to D15 transmitted from the CPU corresponds to the pixels on the LCD (refer to Table 5−
−1). If the
µPD161401 is used in a multi-chip configuration, restrictions on display data transfer are relaxed and display setting
can be performed relatively freely.
The CPU writes data to the display RAM via I/O buffers. This write operation is performed independently of an
operation to read signals for driving the LCD. Therefore, even if the display data RAM is asynchronously accessed,
adverse effects such as flickering do not occur or the current LCD screen.
Table 5−
−1. Display Data RAM
MSB
D15
D14
D13
D12
Dot (R)
D11
D10
D9
Dot (G)
LSB
MSB
D8
D7
LSB
D6
Dot (B)
D5
D3
Dot (R)
D2
D1
Dot (G)
Pixel 1
LCD panel
D4
D0
Dot (B)
Pixel 2
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
Pixel 8
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
Pixel 8
00H
01H
02H
03H
04H
05H
06H
07H
5.2.2 X address circuit
An X address of the display data RAM is specified by using the X address register (R4) as shown in Figure 5−
−5.
If the X address increment mode (INC = 0: control register 2 (R1)) is used, the specified X address is incremented or
decremented by one each time display data is written. Whether the address is incremented or decremented is specified
by the XDIR flag of control register 2 (R1) as shown in Table 5−
−2.
In the increment mode, the X address is incremented up to 64H. If more display data is written, the Y address is
incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 00H.
In the decrement mode, the X address is decremented to 00H. If more display data is written, the Y address is
incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 64H.
When the 16-bit data bus is selected (BMOD = 0), only an even address can be specified. Moreover, when the 16-bit
data bus is selected, dummy data is required as shown in Figure 5−
−3.
Data Sheet S15726EJ2V0DS
21
µPD161401
Figure 5−
−3. About Dummy Data Required when the 16-bit Data Bus is Selected
· When an ADC = 0
101
pixel1
D15
D8 D7
D0
Dummy data
SEG1
SEG303
X address 00H 01H
64H
pixel 1
pixel 101
· When an ADC = 1
D8 D7
D15
SEG303
SEG1
pixel1
101
D0
Dummy data
X address
64H
00H 01H
pixel 1
22
pixel 101
Data Sheet S15726EJ2V0DS
µPD161401
5.2.3 Y address circuit
A Y address of the display data RAM is specified by using the Y address register (R5) as shown in Figure 5−
−5. If the
Y address increment mode (INC = 1: control register 2 (R1)) is used, the specified Y address is incremented or
decremented by one each time display is written. Whether the address is incremented or decremented is specified by
the YDIR flag of control register 2 (R1) as shown in Table 5−
−2.
In the increment mode, the Y address is incremented up to 4FH. If more display data is written, the X address is
incremented (XDIR = 0) or decremented (XDIR = 1), and the Y address returns to 00H.
In the decrement mode, the Y address is decremented to 00H. If more display data is written, the X address is
incremented (XDIR = 0) or decremented (XDIR = 1), and the Y address returns to 4FH.
The relationship between the setting of INC, XDIR, and YDIR of control register 2 (R1) and the address is as follows:
Table 5−
−2. Relationship between INC, XDIR, and YDIR, and Address
INC
Setting
0
The address is successively incremented or decremented in the X direction when data is accessed.
1
The address is successively incremented or decremented in the Y direction when data is accessed Note.
Note This setting cannot be used when the 16-bit parallel interface is used.
XDIR
Setting
0
Increments the X address (+1) when data is accessed.
1
Decrements the X address (−1) when data is accessed.
YDIR
Setting
0
Increments the Y address (+1) when data is accessed.
1
Decrements the Y address (−1) when data is accessed.
Table 5−
−3. Combination of INC, XDIR, and YDIR, and Address Direction
INC
0
1
XDIR
YDIR
Image of Address Scanning
0
0
A-1
0
1
A-2
1
0
A-3
1
1
A-4
0
0
B-1
0
1
B-2
1
0
B-3
1
1
B-4
Caution If the access direction is changed by using INC, XDIR, or YDIR, be sure to set the X address register
(R4) and Y address register (R5) before accessing the display RAM.
Data Sheet S15726EJ2V0DS
23
µPD161401
Y address register (R5)
D7
D6
D5
D4
D3
D2
D1
D0
YA6
YA5
YA4
YA3
YA2
YA1
YA0
YA6 to YA0
Sets a line address.
Figure 5−
−4. Combination of INC, XDIR, and YDIR, and Address Scanning Image
X address
00H
64H
00H
A-1
Y address
A-2
A-3
A-4
4FH
X address
64H
00H
Y address
00H
B-1
B-2
B-3
4FH
B-4
5.2.4 Column address circuit
When the contents of the display data RAM are displayed, column addresses are output to the SEG output pins as
shown in Figure 5−
−5.
The correspondence relationship between the column addresses of the display RAM and segment outputs can be
reversed by the ADC flag (segment driver direction select flag) of control register 1 (R0). This reduces the restrictions
on chip layout when the LCD module is assembled.
Table 5−
−4. Relationship between Column Address of Display RAM and Segment Output
SEG Output
24
SEG1
SEG303
ADC
0
000H
→
Column address
→
12EH
(D1)
1
12EH
←
Column address
←
000H
Data Sheet S15726EJ2V0DS
µPD161401
5.2.5 Common scan circuit
The common scan circuit sets the sequence for the scan line of the common signal in which the display RAM is to be
read. The RAM line reading direction is set as shown in Table 5−
−5 by the COMR flag of control register 1 (R0).
For example, if the duty ratio is 1/64, the number of scroll steps is 0, and COMR = 0, the RAM line reading direction
is from 00H to 3FH. If COMR = 1, it is from 3FH to 00H.
Table 5−
−5. Relationship between Common Scan Circuit and Scan Direction
COMR
0
00H
→
4FH
(D0)
1
4FH
→
00H
In addition, scanning of the common outputs can be assigned by using the COM scanning address setting register
(R21) as shown in Table 5−
−6, so that the scanning can be started from any O1 to O80 output pin. Therefore, the
common wiring of the LCD panel can be optimized when any duty ratio is selected.
When COMR = 0, the scan start (COM1) pin and scan end (COMa) pin are the On and O(n+a−1) pins, respectively. The
value of a is 64, 72, and 80 for 1/64 duty, 1/72 duty, and 1/80 duty, respectively. When COMR = 1, the scan start
(COM1) pin and scan end (COMa) pin are the O(82−a−n) and O(80−−n+1) pins, respectively.
Examples of COM scan address settings for 1/64 duty, 1/72 duty, and 1/80 duty are shown in Tables 5−
−5, 5−
−7, and
5−
−8, respectively.
Table 5−
−6. COM Scanning Address Setting (1/64 duty)
COMR = 0
CSA4
CSA3
CSA2
CSA1
CSA0
n
the scan start
→
(COM1) pin
On
→
→
0
0
0
0
0
1
O1
0
0
0
0
1
2
O2
→
COMR = 1
the scan end
the scan start
(COMa)Note pin
(COM1) pin
O(n+a-1) Note
O(82-a-n) Note
→
O(80-n+1)
O64
O17
→
O16
→
O80
O65
O78
→
the scan end
(COMa)Note pin
O79
0
0
0
1
0
3
O3
→
O66
O15
→
0
0
0
1
1
4
O4
→
O67
O14
→
O77
0
0
1
0
0
5
O5
→
O68
O13
→
O76
0
0
1
0
1
6
O6
→
O69
O12
→
O75
O74
0
0
1
1
0
7
O7
→
O70
O11
→
0
0
1
1
1
8
O8
→
O71
O10
→
O73
0
1
0
0
0
9
O9
→
O72
O9
→
O72
0
1
0
0
1
10
O10
→
O73
O8
→
O71
O70
0
1
0
1
0
11
O11
→
O74
O7
→
0
1
0
1
1
12
O12
→
O75
O6
→
O69
0
1
1
0
0
13
O13
→
O76
O5
→
O68
0
1
1
0
1
14
O14
→
O77
O4
→
O67
O66
0
1
1
1
0
15
O15
→
O78
O3
→
0
1
1
1
1
16
O16
→
O79
O2
→
O65
1
0
0
0
0
17
O17
→
O80
O1
→
O64
Note When in 1/64 duty, a = 64.
Data Sheet S15726EJ2V0DS
25
µPD161401
Table 5−
−7. COM Scanning Address Setting (1/72 duty)
COMR = 0
CSA4
CSA3
CSA2
CSA1
CSA0
n
COMR = 1
the scan start → the scan end
(COMa)Note pin
(COM1) pin
→
O(n+a-1) Note
On
→
O1
O72
the scan start
→
(COM1) pin
O(82-a-n)
Note
O9
Remark
the scan end
(COMa)Note pin
→
O(80-n+1)
→
O80
0
0
0
0
0
1
0
0
0
0
1
2
O2
→
O73
O8
→
0
0
0
1
0
3
O3
→
O74
O7
→
O78
0
0
0
1
1
4
O4
→
O75
O6
→
O77
O76
O79
0
0
1
0
0
5
O5
→
O76
O5
→
0
0
1
0
1
6
O6
→
O77
O4
→
O75
0
0
1
1
0
7
O7
→
O78
O3
→
O74
0
0
1
1
1
8
O8
→
O79
O2
→
O73
O9
→
O1
→
O72
0
1
0
0
0
9
0
1
0
0
1
10
O80
Prohibit
since here
Note When in 1/72 duty, a = 72
Caution The COM scan address setting register (R21) should be set so that O1 ≤ scan start pin and scan end
pin ≤ O80. If any other settings are made the IC operation is not guaranteed.
Table 5−
−8. COM Scanning Address Setting (1/80 duty)
COMR = 0
CSA4
CSA3
CSA2
CSA1
CSA0
n
0
0
0
0
0
1
0
0
0
0
1
2
the scan start → the scan end
(COMa)Note pin
(COM1) pin
→
O(n+a-1) Note
On
→
O1
O80
COMR = 1
the scan start →
(COM1) pin
O(82-a-n) Note →
O1
→
Remark
the scan end
(COMa)Note pin
O(80-n+1)
O80
Prohibit
since here
Note When in 1/80 duty, a = 80
Caution When this µPD161401 is used in 1/80 duty, the COM scan address setting register (R21) should be set
to CSA4, CSA3, CSA2, CSA1, CSA0 = 0, 0, 0, 0, 0. If any other settings are made the IC operation is not
guaranteed.
26
Data Sheet S15726EJ2V0DS
µPD161401
Panel pin
COM output
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM60
COM61
COM62
COM63
COM64
address
Column
D1
ADC
0
1
LCD
Data Sheet S15726EJ2V0DS
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
O20
output D1
303
1
SEG
O60
O61
O62
O63
O64
302
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
2
Driver: On
SEG
5
SEG 299
Line
address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
301
4
SEG 300
Setting example 1/64 duty
COMR = 0
n = 1(CSA4 to CSA0 = 0)
3
3
SEG 301
D7 D6 D5
1
1
0
0
1
0
0
64H
D4 D3 D2 D1 D0
SEG
2
SEG 302
6
1
Data D7 D6 D5
0
0
0
0
0
0
0
0
0
0
0
0
0
1
00H
01H
D4 D3 D2 D1 D 0 D7 D6 D5 D4 D3 D2 D1 D 0
SEG 298
D6
D5
D4
D3
D2
D1
D0
SEG 303
X address
Figure 5−
−5. Configuration of X Address Register
27
µPD161401
5.2.6 Display data latch circuit
The display data latch circuit temporarily stores (latches) the display data that is output from the display data RAM to
the LCD driver circuit.
The display scan command for forwarding or reversing data and the display ON/OFF command control the latched
data and do not affect the data of the display data RAM.
5.2.7 Arbitrary address area access (window access mode (WAS))
With the µPD161401, any area of the display RAM selected by the MIN.⋅X/Y address registers (R7 and R9) and
MAX.⋅X/Y address registers (R8 and R10) can be accessed.
First, select the area to be accessed by using the MIN.⋅X/Y address registers and MAX.⋅X/Y address registers. When
WAS of control register 1 is set to 1, the window access mode is then selected. The address scanning setting by INC,
XDIR, and YDIR of control register 2 (R1) is also valid in this mode, in the same manner as when data is normally
written to the display RAM. In addition, data can be written from any address by specifying the X address register (R4)
and Y address register (R5).
Note that the display RAM must be accessed after setting the X address register (R6) and Y address register (R7) if
the window access area has been set or changed by the MIN.⋅ X/Y address register (R7, R9) or MAX.⋅ X/Y address
register (R8, R10).
Figure 5−
−6. Example of Incrementing Address When INC = 0, XDIR = 0, and YDIR = 0
MIN. . X address
Start point
MAX. . X address
64H
00H
00H
MIN. . Y address
.
.
.
MAX. . Y address
4FH
End point
Cautions 1. When using the window access mode, the relationship between the start point and end point
shown in the table below must be established.
Item
Address Relation Ship
X address
00H ≤ MIN.⋅X address ≤ X address (R4) ≤ MAX.⋅X address ≤ 64H
Y address
00H ≤ MIN.⋅Y address ≤ Y address (R5) ≤ MAX.⋅Y address ≤ 4FH
2. If invalid address data is set as the MIN./MAX.⋅⋅address, operation is not guaranteed.
3. Access the display RAM after setting the X address register (R6) and Y address register (R7) if the
window access area has been set or changed by the MIN.⋅⋅ X/Y address register (R7, R9) or
MAX.⋅⋅ X/Y address register (R8, R10).
28
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−
−7. Example of Sequence in Window Access Mode
Start
Control register 2
(WAS = 1)
Sets window access mode.
MIN. . X address register (R7)
Sets start point.
MIN. . Y address register (R9)
MAX. . X address register (R8)
Sets end point.
MAX. . Y address register (R10)
X address register (R4)
Y address register (R5)
Display memory access register (R12)
Data
Writing complete?
No
Yes
End
Data Sheet S15726EJ2V0DS
29
µPD161401
5.3 Screen Processing
5.3.1 Blink/reverse display circuit
The µPD161401 can blink or reverse a specific area of the full-dot display. Blinking is to turn ON/OFF display
repeatedly at about 1 Hz (complementary color or specified color can be selected) and reversing is to reverse the
grayscale data on the display.
The area to be blinked is specified by using the complementary color/specified color blink start/end line address
registers (R39, R40, R43, and R44), complementary color/specified color blink X address registers (R38, R42), and
complementary color/specified color blink data memory registers (R41, R45).
First, select a blink display start line address and end line address by using the start/end line address registers. Next,
select the column to be blinked by using the blink X address register and blink data memory register.
The specified color blink is blinked between the graphic data and the color data specified by the specified color setting
register (R46).
To select an area to be reversed, use the reverse start/end line address registers (R48, R49), reverse X address
register (R47), and reverse data memory access register (R50).
First, select line addresses at which reverse display is started and stopped, by using the reverse start/end line address
registers. Next, select a column to be reversed, by using the reverse X address register and reverse data memory
access register. The specified blink/reverse X address is incremented by one each time blink/reverse data has been
input.
The complementary color/specified color blink RAM and reverse RAM store the data to be blinked and reversed.
Each RAM is configured of 101 bits (12 × 8 + 5 bits).
To access a desired bit, specify an X address. Blink/reverse data D0 to D7 transmitted from the CPU corresponds to
−8.
SEGX on the LCD, as illustrated in Figure 5−
If the BLD bit and INV bit of the blink/reverse setting register (R37) are set to H after an area and data have been set,
blinking or reversing the data is started. Figure 5−
−9 shows the relationship between the start line address, end line
address, blinking/reversing data, and LCD.
If the same area is specified for complementary color blinking and specified color blinking, the specified color blinking
takes precedence.
Table 5−
−9. Reversing Operation and Display
Original Grayscale
After Reversing (supplement color)
R/G display data
0, 0, 0
1, 1, 1
0, 0, 1
1, 1, 0
0, 1, 0
1, 0, 1
0, 1, 1
1, 0, 0
1, 0, 0
0, 1, 1
1, 0, 1
0, 1, 0
1, 1, 0
0, 0, 1
1, 1, 1
0, 0, 0
B display data
30
0, 0
1, 1
0, 1
1, 0
1, 0
0, 1
1, 1
0, 0
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−
−8. Correspondence between Blink/Reverse Data and Segment
R38,R42,R47
X address
When an ADC = 0
D3
D2
D1
D0
Data
D7 D6 D5
0
0
0
0
0
0
0
1
00H
01H
D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
1
1
0
0
0CH
D4 D3 D2 D1 D0
pixel101 64
pixel100 63
pixel99 62
pixel98 61
pixel97 60
pixel16 0F
pixel15 0E
pixel14 0D
pixel13 0C
pixel12 0B
pixel11 0A
pixel10 09
pixel9 08
pixel8 07
pixel7 06
pixel6 05
pixel5 04
pixel4 03
pixel3 02
pixel2 01
pixel1 00
Note Note Note
Column output
LCD
Output
Note The value written in D2 to D0 of X address 0CH is invalid.
pixel101 64
pixel100 63
pixel99 62
pixel98 61
1
1
0
0
0CH
D4 D3 D2 D1 D0
pixel97 60
pixel16 0F
pixel15 0E
D 7 D6 D5
pixel14 0D
pixel13 0C
pixel12 0B
pixel11 0A
pixel10 09
pixel9 08
pixel8 07
pixel7 06
pixel6 05
pixel5 04
pixel4 03
D7 D6 D5
pixel1 00
Data
0
0
0
0
0
0
0
1
00H
01H
D4 D3 D2 D1 D0 D 7 D6 D5 D4 D3 D2 D 1 D 0
pixel3 02
D3
D2
D1
D0
pixel2 01
R38,R42,R47
X address
When an ADC = 1
Column output
n+6
n+7
LCD
Output
Note The value written in D7 to D5 of X address 00H is invalid.
Figure 5−
−9. Blink/Reverse Display Area Setting Image
n
n+1
n+2
n+3
n+4
n+5
Blink/reverse 0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0
data
;;;;
;
;;;;;;;;
;;;;;;
;
;;;;;
;
;
;;;;;;;;;;
Start line
End line
: Blink or reverse pixel
Data Sheet S15726EJ2V0DS
31
µPD161401
Figure 5−
−10. Example of Sequence of Setting Blink/Reverse Display
Start
Blink/reverse start line
address register
Blink/reverse end line
address register
Blink/reverse X address register
Blink/reverse data memory
Data
NO
Writing complete ?
YES
Blink/reverse setting register (R37)
(BLDn, INV = H)
End
The data configuration of the range specification registers (start/end line address registers R39, R40, R43, R44, R48,
and R49) of each line is in the format shown below. Each display area is set in this format. .
D7
D6
D5
D4
D3
D2
D1
D0
X_6
X_5
X_4
X_3
X_2
X_1
X_0
X_6 to X_0
Sets start/end line addresses.
Remark X_: CBS, CBE, SBS, SBE, IVS, IVE
32
Data Sheet S15726EJ2V0DS
µPD161401
5.3.2 Example of setting blink area
This section explains how to specify an area to be blinked, taking complementary color blinking as an example. The
same setting is also applied to specified color blinking and reverse display.
(1) Example of using 1 chip at duty ratio of 1/80
T.B.D.
Remark T.B.D. (To be determined.)
(2) Example of using 2 chip (Master and slave) at duty ratio of 1/80
T.B.D.
5.4 Oscillator
The µPD161401 has a CR oscillator (with external R) for main duty/sub-duty display. This oscillator generates the
display clock.
This oscillator is controlled by the DTY flag of control register 2 (R1), and the configuration of its display clock can be
set in accordance with the system used.
The function of each circuit of the oscillator is shown below. The main duty display/sub-duty display oscillator
becomes valid only when oscillation resistors (RM and RS) are connected to it. The clock for main duty display or subduty display can be selected depending on the status of the DTY flag of control register 2 (R1).
Figure 5−
−11. Oscillator Block
Selected by DTY
OSC IN1
OSC IN2
Oscillator for
main duty/sub-duty
OSC OUT
To graphic driver circuit
OSC SYNC
The relationship between the frame frequency (fFRAME) in the normal display mode, oscillation frequency (fOSCINn), and
set duty frame is as follows.
fFRAME = fOSCINn ÷ 16 ÷ N
N = Duty ratio
Data Sheet S15726EJ2V0DS
33
µPD161401
Table 5−
−10 shows the relationship between oscillation resistors RM and RS, and the display clock circuit.
Table 5−
−10. Relationship between Display Clock Circuit, Pins, and Resistor
RM Connection
RS Connection
Clock for Main Duty Display
Clock for Sub-duty Display
Example
Connected
Connected
Internal oscillation
Internal oscillation
A
Not connected
Not connected
External clock
External clock
B
Figure 5−
−12. Example of Using Clock
fM
OSC IN1
OSC IN1
fS
RM
OSC IN2
OSC IN2
RS
OSC OUT
Open
(A)
OSC OUT
(B)
OSCIN1 : For main duty
OSCIN2 : For sub-duty
Figure 5−
−13. Example of Master/Slave Connection
Master
Slave
(M,/S = H)
(M,/S = L)
OSC SYNC
OSC IN1
OSC IN2
Open
(A)
34
Data Sheet S15726EJ2V0DS
OSC OUT
µPD161401
5.5 Display Timing Generator
The display timing generator generates timing signals for the line address circuit and display data latch circuit, from
the display clock. The display data is latched to the display data latch circuit in synchronization with the display clock
and output to the segment driver output pins. The display data can be read completely independently of the access to
the display data RAM by the CPU. Therefore, even if the display data RAM is asynchronously accessed, no adverse
effect, such as flickering, occurs on the LCD.
The internal common timing, LCD AC signal (FR), and frame synchronization signal (FRSYNC) are generated by the
display clock. A driver waveform in the frame AC driving mode shown in Figure 5−
−14 is generated for the LCD driver
circuit.
When the µPD161401 is used in a multi-chip configuration, the display timing signals for the slave chip (FR and
FRSYNC) must be supplied from the master chip.
Table 5−
−11. Relationship between FR, FRSYNC, and Operation Mode
Operation Mode
FR
FRSYNC
Master (M,/S = H)
Output
Output
Slave (M,/S = L)
Input
Input
Data Sheet S15726EJ2V0DS
35
µPD161401
Figure 5−
−14. Driver Waveform in Frame AC Driver Mode
1 FRAME
1 2 3 4 5 6 7 8
78 79 80 1 2 3 4 5 6 7 8
OSCSYNC
FRSYNC
FR
RAM
DATA
VLCD
VLC1
VLC2
SEG1
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM1
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM2
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM80
VLC3
VLC4
VSS
36
Data Sheet S15726EJ2V0DS
78 79 80
µPD161401
5.6 Power Supply Circuit
5.6.1 Power supply circuit
The power supply circuit generates the voltage necessary for driving the LCD. The power circuit consists of a booster
circuit, voltage regulator circuit, and voltage follower circuit.
Power system control register 1 (R52) turns ON/OFF the transformer, reference voltage generator, voltage regulator
circuit (V regulator circuit), and voltage follower circuit (V/F circuit). Part of the internal power supply function and an
external power supply can be used in combination. Table 5−
−12 shows the functions controlled by the 4-bit data of
power system control register 1 (R52). Table 5−
−13 shows examples of combinations of the power circuit functions.
Table 5−
−12. Function of Each Bit of Power System Control Register
Status
Item
1
0
OP3
: Booster circuit control bit
ON
OFF
OP2
: Reference voltage generator control bit
ON
OFF
OP1
: Voltage regulator circuit (V regulator circuit) control bit
ON
OFF
OP0
: Voltage follower circuit (V/F circuit) control bit
ON
OFF
Table 5−
−13. Examples of Combinations (Reference Values)
Booster Reference V Regulator
V/F
External
Booster
Status
OP3
OP2
OP1
OP0
Circuit
voltage
Circuit
Circuit
<1> Only internal power supply is
1
1
1
1
Ο
Ο
Ο
Ο
VDD2
Used
0
1
1
1
×
Ο
Ο
Ο
VDD2, VOUT
Open
VDD2,
Used
Power Input
System Pins
used
<2> External VOUT power supply
<3> Only V/F circuit is used
<4> Only external power supply is
used
1
0
0
1
Ο
×
×
Ο
0
0
0
0
×
×
×
×
AMPOUT
VDD2, VOUT,
Open
VLCD,
VLC1 to VLC4
+
−
+
−
Remarks 1. The “booster system pins” are the C1 , C1 to C5 , C5 pins.
2. All the power circuits are turned OFF when the µPD161401 serves as a slave (M,/S pin = L).
5.6.2 Booster circuit
The power supply circuit has an internal booster circuit that increases the LCD driver voltage two- to seven-fold.
Because this booster circuit uses the internal oscillator signals, either the oscillator must be operating or an external
display clock must be input to operate this circuit.
The booster circuit usually uses the C1+, C1− to C5+, C5− pins and VDD2 pins. Keep the wiring impedance of these pins
as low as possible. The number of boosting steps for main duty display and sub-duty display is set as shown in Table
5−
−14 by the MBTn and SBTn flags of power system control register 4 (R55).
For the number of boosting steps and how to connect capacitors, refer to Figure 5−
−15.
Data Sheet S15726EJ2V0DS
37
µPD161401
VOUT
x5
VOUT
VOUT
VOUT
VOUT2
VOUT2
VOUT2
C5C5C5C5C5-
x2
x2
x4
VOUT
Open
x6
VOUT2
C5-
C5+
C4C4-
C3C4+
C5+
C5+
C4C4-
C5+
C5+
C4-
C4C5+
C2C3+
C1C2+
Open
x2
x2
x3
VOUT
x2
C3C4+
C2C3+
C1+
C1C2+
Open
x7
VOUT2
x2
C1+
C3C4+
Open
x2
VOUT2
x2
C1C2+
C1+
Open
C3C4+
C1+
x2
C3C4+
C2C3+
C2C3+
x2
C1C2+
x2
x2
C2C3+
C1+
C1C2+
x2
C3C4+
x2
C2C3+
C1+
C1C2+
Figure 5−
−15. Number of Boosting Steps and Capacitor Connection
x2
x2
To boost LCD drive voltage seven-fold
To boost LCD drive voltage six-fold
To boost LCD drive voltage five-fold
To boost LCD drive voltage four-fold
To boost LCD drive voltage three-fold
To boost LCD drive voltage two-fold
Remark “xN” (N = 2 to 7) of the capacitors in the above figure indicates the maximum voltage applied to the
capacitors.
xN : VDD2 x N (V)
Table 5−
−14. Number of Boosting Steps of Main Duty/Sub-duty Display Booster Circuit (during Normal Display)
38
MBT2
MBT1
MBT0
SBT2
SBT1
SBT0
0
0
0
Two
0
0
1
Three
0
1
0
Four
0
1
1
Five
1
0
0
Six
1
0
1
Seven
1
1
0
Prohibited
1
1
1
Prohibited
Number of Boosting steps (unit: fold)
Data Sheet S15726EJ2V0DS
µPD161401
5.6.3 Voltage regulator circuit
The boosted voltage from VOUT is supplied to the voltage regulator circuit and output to the LCD drive voltage pin VLCD.
Because the µPD161401 has a 128-step electronic volume function and an internal VLCD adjuster resistor, a highaccuracy voltage regulator circuit can be configured by adding only a few components.
VLCD regulator circuit
(a) When internal resistor for adjusting VLCD is used
By using the internal resistor for adjusting VLCD and the electronic control function, LCD drive voltage VLCD can be
controlled and the contrast of the LCD can be adjusted by using commands. In this case, no external resistor is
necessary. Where VLCD < VOUT, the value of VLCD can be calculated as follows:
Example Calculating value of VLCD (where VLCD < VOUT)
VLCD = (1 + Rb ) VEV
Ra
VLCD = (1 + Rb ) (1 − α ) VREG
Ra
256
Remark VEV = (1 − α ) VREG
256
Figure 5−
−16. Example of Circuit Using Internal Resistor for Adjustment VLCD
+
VLCD
VEV (constant power supply + electronic volume)
−
Rb
Ra
VREG is the internal fixed power source of the IC and has three types of temperature characteristic curves. These
temperature characteristic curves can be adjusted as shown in Table 5−
−15 depending on the setting of power system
control register 1 (R52) (TCS2 to TCS0).
Table 5−
−15 shows VREG at TA = 25°C.
Table 5−
−15. Adjusting Temperature Characteristic Curve
Status
Internal power supply
When external reference
TCS2
TCS1
TCS0
Temperature Gradient (unit: %/°C)
VREG (TYP.) (unit: V)
0
0
0
−0.12
1.77
0
0
1
−0.13
1.69
0
1
0
−0.15
1.63
0
1
1
−0.17
1.59
1
×
×
−
−
power supply is used
Data Sheet S15726EJ2V0DS
39
µPD161401
α is the value of the electronic volume register. It can take any of 128 values in accordance with the data set to the 7bit electronic control register. The value of α set by the main electronic volume register (R57) (main duty display) and
sub-electronic volume register (R58) (sub-duty display) is shown in Table 5−
−16.
Table 5−
−16. Changes in Value of α Depending on Setting of Electronic Volume Register
MEV6
MEV5
MEV4
MEV3
MEV2
MEV1
MEV0
SEV6
SEV5
SEV4
SEV3
SEV2
SEV1
SEV0
0
0
0
0
0
0
0
256
0
0
0
0
0
0
1
126
0
0
0
0
0
1
0
125
0
0
0
0
0
1
1
124
1
1
1
1
1
0
1
2
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
α
Rb/Ra is a ratio of the internal resistors for adjusting VLCD. This resistance ratio can be adjusted in 128 steps, by using
power control register 2 (R53) (VRRn: main duty display mode, and SVRn: sub-duty display mode). The value of the
reference voltage (1 + Rb/Ra) is determined as shown in Table 5−
−17, depending on the setting of 4 bits of the VLCD
internal resistance ratio register.
Table 5−
−17. Determining Reference Voltage Value by Setting of Internal Resistance Ratio Register
Register
40
VRR3
VRR2
VRR1
VRR0
SVR3
SVR2
SVR1
SVR0
0
0
0
0
3
0
0
0
1
4
0
0
1
0
5
0
0
1
1
6
0
1
0
0
7
0
1
0
1
8
0
1
1
0
9
0
1
1
1
10
1
0
0
0
11
1
0
0
1
12
1
0
1
0
13
1
0
1
1
14
1
1
0
0
15
1
1
0
1
16
1
1
1
0
17
1
1
1
1
18
Data Sheet S15726EJ2V0DS
1 + Rb/Ra
µPD161401
(b) When external resistor is used (when internal resistor for adjusting VLCD is not used)
LCD drive voltage VLCD can be controlled not only by a setting of the internal resistor for adjusting VLCD (IRS = L)
but also by connecting resistors Rae, Rbe, and Rce between VSS and VR, between VR and AMPOUTM, and between
VR and AMPOUTS, respectively. In this case also, LCD drive voltage VLCD and the contrast of the LCD can be
adjusted by using the electronic control function and commands.
In addition, the µPD161401 can select two values of VLCD for normal display and partial display. These values are
set by using an external divider resistor and automatically selected by the DTY flag of control register 2 (R1).
Where VLCD < VOUT, the value of VLCD can be calculated by the expression in Example 1 (DTY = 0) and the
expression in Example 2 (DTY = 1).
Example 1. To calculate value of VLCD (DTY = 0, in main duty display mode)
VLCD = (1 + Rbe ) VEV
Rae
VLCD = (1 + Rbe
Rae
) (1 −
Remark VEV = (1 −
α
) VREG
256
α ) VREG
256
Example 2. To calculate value of VLCD (DTY = 1, in sub-duty display mode)
VLCD = (1 +
Rce
) VEV
Rae
VLCD = (1 +
α
Rce
) (1 − 256
Rae
Remark VEV = (1 −
α
256
) VREG
) VREG
Figure 5−
−17. Example of Circuit Using External Resistor
+
VLCD
−
Main/sub-duty VLCD
adjustment selector
B
A
VR
VRS
AMPOUTS
AMPOUTM
Rbe
Rce
Rae
Main duty display mode
(DTY = 0)
A
B
Sub-duty display mode
(DTY = 1)
A
B
Data Sheet S15726EJ2V0DS
41
µPD161401
5.6.4 Level voltage control by operational amplifier
Although the µPD161401 has a power-saving power supply circuit, the display quality may be degraded if it is used to
drive a high-load LCD panel. The driving capability of the segment output can be controlled as shown in Table 5−
−18 by
LCS1 and LCS0 of power system control register 5 (R56), and the driving capability of the common outputs can be
controlled as shown in Table 5−
−19 by LCC1 and LCC0 of the same register. By controlling the driving capability, the
display quality and power consumption may be improved. Determine the driving capability in accordance with the actual
display status. If the display quality is not sufficiently improved in any driving mode, it will be necessary to supply the
LCD drive voltage from an external power supply.
In addition, the operational amplifier driving modes shown in Table 5−
−20 can be selected by the setting of HPM1 and
HPM0, so that the wait time to stabilize the supply voltage immediately after the power has been turned ON or OFF can
be shortened.
PSM1 specifies whether a boosting voltage of VDD2 × 2 is applied to the VLC3 or VLC4 level voltage follower of (refer to
Table 5−
−21). If a voltage boosted two-fold is applied to the voltage follower circuit, the current consumption may be
reduced.
Thoroughly confirm and evaluate the VLC3 and VLC4 levels of the LCD panel with the actual system to determine
whether the two-fold LCD drive voltage is to be supplied.
PSM0 can be used to set the current value of all the voltage follower circuits as shown in Table 5−
−22.
Table 5−
−18. Setting Driving Capability of Segment Outputs (LCS1, LCS0 = 0, 0)
LCS1
LCS0
Segment Output Driving Capability (unit: fold)
0
0
One
0
1
Two
1
0
Four
1
1
Eight
Table 5−
−19. Setting Driving Capability of Common Outputs (LCS1, LCS0 = 0, 0)
LCC1
LCC0
Common Output Driving Capability (unit: fold)
0
0
Two
0
1
Four
1
0
Eight
1
1
Sixteen
Table 5−
−20. Setting Operation Mode of Operational Amplifier
42
HPM1
HPM0
Mode Setting
0
0
Normal mode
0
1
Power supply ON mode 1
1
0
Power supply OFF mode
1
1
Power supply ON mode 2
Data Sheet S15726EJ2V0DS
µPD161401
Table 5−
−21. Setting of Two-Fold Drive Voltage
PSM1
Mode Setting
0
Not used
1
Used
Table 5−
−22. Voltage Follower Bias Current Setting
PSM0
Bias Current Setting (unit: fold)
0
One
1
Two
Data Sheet S15726EJ2V0DS
43
µPD161401
5.6.5 Application example of power supply circuit
Figure 5−
−18. IRS = H, [OP3, OP2, OP1, OP0] = [1, 1, 1, 1]
Six-fold drive voltage
VDD1
VDD2
VRS
VOUT
VR
Open
AMPOUTS
VOUT2
AMPOUTM
C1 +
VLCD
C 1C2+
VLC1
C2 -
VLC2
C3+
VLC3
C3 C4+
VLC4
C4 C5+
C5 VSS
Figure 5−
−19. IRS = L, [OP3, OP2, OP1, OP0] = [1, 1, 1, 1]
Six-fold drive voltage
VDD1
VDD2
VOUT
VRS
Open
AMPOUTS
Rc
VR
VOUT2
AMPOUTM
C1+
VLCD
C1 C2 +
VLC1
C 2C3+
C3 C4+
VLC2
VLC3
VLC4
C4 C5 +
C5 VSS
44
Data Sheet S15726EJ2V0DS
Rb' Ra'
µPD161401
Figure 5−
−20. IRS = H, [OP3, OP2, OP1, OP0] = [0, 0, 0, 1]
VDD1
VDD2
VRS
VR
VOUT
Open
VOUT2
Open
AMPOUTS
AMPOUTM
+
C1
-
C1
C2 +
C2C3+
Open
C3 C4 +
VLCD
VLC1
VLC2
VLC3
VLC4
C4 +
C5
C5 VSS
Figure 5−
−21. IRS = L, [OP3, OP2, OP1, OP0] = [0, 0, 0, 1]
VDD1
VDD2
VRS
Open
VR
VOUT
Open
VOUT2
AMPOUTS
C1+
AMPOUTM
C1 -
VLCD
C2+
C2C3+
Open
-
C3
C4+
C4C5 +
VLC1
VLC2
VLC3
VLC4
C5 VSS
Data Sheet S15726EJ2V0DS
45
µPD161401
Figure 5−
−22. IRS = L, [OP3, OP2, OP1, OP0] = [0, 0, 0, 0]
VDD1
VDD2
VRS
VOUT
AMPOUTS
VR
Open
AMPOUTM
VOUT2
Open
C1+
VLCD
C1 C2 +
VLC1
C2 C3 +
Open
VLC2
VLC3
C3 C4+
VLC4
C4 +
C5
C5 VSS
Figure 5−
−23. Master/Slave Connection Example 1
VRS
VDD1
VDD2
M,/S
VR
Open
+
C1
C1 +
C2
C2 +
C3
C3 +
C4
C4 +
C5
C5 -
VRS
VDD1
VDD2
VR
M,/S
AMPOUTS
AMPOUTS
AMPOUTM
VOUT
AMPOUTM
VOUT
Master
VOUT2
+
Open
VOUT2
C1 C2+
C2 C3+
Open
VLCD
VLCD
VLC1
VLC1
VLC2
VLC2
C4 C5+
VLC3
VLC3
C5 -
VLC4
VLC4
VSS
46
Slave
C1+
C3 C4+
VSS
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−
−24. Master/Slave Connection Example 2
VRS
VDD1
VDD2
M,/S
C
+
1
C1 C2+
VR
VR
Open
AMPOUTS
AMPOUTS
AMPOUTM
AMPOUTM
C1+
VOUT
C1 C2+
VOUT
C2 +
C3
Open
VDD1
VDD2
M,/S
VRS
VOUT2
Open
VOUT2
-
C3
C4 +
-
C4
+
C5
C5
-
Master
Slave
C2 C3+
C3 +
C4
VLCD
VLCD
VLC1
VLC1
VLC2
VLC2
C4 +
C5
VLC3
VLC3
C5 -
VLC4
VLC4
Open
VSS
VSS
Data Sheet S15726EJ2V0DS
47
µPD161401
5.7 Driving LCD
The µPD161401 has a full-dot driver. This full-dot driver can modulate grayscale, depending on the setting of the
pulse widths. In this driving mode, eight R/G output grayscales and four B output grayscales are selected from a 17stage grayscale palette, and the selected grayscales are registered to the output grayscale palette of the IC. For details,
refer to Table 5−
−23 Example of Pulse Width Modulation Output.
5.7.1 Full-dot pulse modulation
The pulse width modulation function of the µPD161401 divides the segment pulse width of the signal for normal LCD
display (16), and outputs the divided pulse width in accordance with the output timing of dots at the ratio of the
grayscale palette selected by a command.
Figure 5−
−25. Full-Dot Pulse Width Modulation
1 Frame
1 2 3 4 5 6 7 8
78 79 80 1 2 3 4 5 6 7 8
78 79 80
VLCD
VLC1
VLC2
SEG1
VLC3
VLC4
VSS
VLCD
VLC1
VLC2
COM1
VLC3
VLC4
VSS
;;
;;
Expanded view of part
1
2
3
16/16
8/16
;;
;
1/16
VLCD
VLC1
VLC2
Caution The width of the common output pulse is not modulated.
48
Data Sheet S15726EJ2V0DS
µPD161401
The pulse is output in the form of combined odd line/even line or even line/odd line output, as shown in Figure 5−
−26.
Table 5−
−23 shows the combination of the rising and falling edges of the pulse of each frame.
Figure 5−
−26. Example of Pulse Width Modulation Output of Odd/Even Line
1 Frame
1
2
3
4
5
6
7
8
9 10 11 12
78 79 80 1
2
3
4
5
6
7
8
VLCD
VLC1
VLC2
VLC3
VLC4
VSS
2
3
16/16
16/16
16/16
;
;;;
;
1
8/16
6/16 8/16
Data Sheet S15726EJ2V0DS
49
µPD161401
Table 5−
−23. Pulse Width Modulation Output
Grayscale Level
COM
0
1 or 2 Frames
3 or 4 Frames
SEG Odd Number
SEG Even Number
SEG Odd Number
SEG Even Number
2n+1
0
0
0
0
2n+2
0
0
0
0
2n+1
1↑
1↓
1↓
1↑
2n+2
1↓
1↑
1↑
1↓
2n+1
2↑
2↓
2↓
2↑
2n+2
2↓
2↑
2↑
2↓
2n+1
3↑
3↓
3↓
3↑
2n+2
3↓
3↑
3↑
3↓
4
2n+1
4↑
4↓
4↓
4↑
2n+2
4↓
4↑
4↑
4↓
5
2n+1
5↑
5↓
5↓
5↑
2n+2
5↓
5↑
5↑
5↓
6
2n+1
6↑
6↓
6↓
6↑
2n+2
6↓
6↑
6↑
6↓
7
2n+1
7↑
7↓
7↓
7↑
2n+2
7↓
7↑
7↑
7↓
8
2n+1
8↑
8↓
8↓
8↑
2n+2
8↓
8↑
8↑
8↓
9
2n+1
9↑
9↓
9↓
9↑
2n+2
9↓
9↑
9↑
9↓
2n+1
10 ↑
10 ↓
10 ↓
10 ↑
2n+2
10 ↓
10 ↑
10 ↑
10 ↓
2n+1
11 ↑
11 ↓
11 ↓
11 ↑
2n+2
11 ↓
11 ↑
11 ↑
11 ↓
2n+1
12 ↑
12 ↓
12 ↓
12 ↑
2n+2
12 ↓
12 ↑
12 ↑
12 ↓
2n+1
13 ↑
13 ↓
13 ↓
13 ↑
2n+2
13 ↓
13 ↑
13 ↑
13 ↓
2n+1
14 ↑
14 ↓
14 ↓
14 ↑
2n+2
14 ↓
14 ↑
14 ↑
14 ↓
2n+1
15 ↑
15 ↓
15 ↓
15 ↑
2n+2
15 ↓
15 ↑
15 ↑
15 ↓
2n+1
16 ↑
16 ↓
16 ↓
16 ↑
2n+2
16 ↓
16 ↑
16 ↑
16 ↓
1
2
3
10
11
12
13
14
15
16
Remarks 1. n: Integer of 0 to 39
2. ↑A: Pulse rises in the middle of A line output.
3. ↓A: Pulse rises at the beginning of A line output.
4. A: PWM pulse width (A/16)
50
Data Sheet S15726EJ2V0DS
µPD161401
5.7.2 Grayscale palette
The µPD161401 has 17 levels of grayscale outputs. Eight R/G output grayscales and four B output grayscales can be
selected for each of main duty display and sub-duty display, by using the grayscale data registers (R65 to R104), and
can be output as the grayscale outputs of the IC to R/G/B.
Table 5−
−24. Correspondence of Grayscale Levels of Grayscale Data Registers
Grayscale Level
Set Value of Grayscale Data Register
D4
D3
D2
D1
D0
Level 0
0
0
0
0
0
Level 1
0
0
0
0
1
Level 2
0
0
0
1
0
Level 3
0
0
0
1
1
Level 4
0
0
1
0
0
Level 5
0
0
1
0
1
Level 6
0
0
1
1
0
Level 7
0
0
1
1
1
Level 8
0
1
0
0
0
Level 9
0
1
0
0
1
Level 10
0
1
0
1
0
Level 11
0
1
0
1
1
Level 12
0
1
1
0
0
Level 13
0
1
1
0
1
Level 14
0
1
1
1
0
Level 15
0
1
1
1
1
Level 16
1
0
0
0
0
Remark
OFF data
50%
100%
Data Sheet S15726EJ2V0DS
51
µPD161401
5.7.3 Setting of display size
The µPD161401 can set the main duty cycles in a range of 1/80, 1/72 and 1/64 duty, the sub-duty cycles in a range of
1/48, 1/40, 1/32, 1/24 and 1/16 duty. This can be done by setting MDT6 to MDT0 and SDT6 to SDT0 of the main duty
setting register (R14) and sub-duty setting register (R17) as Table 5−
−25 and 5−
−26:
Table 5−
−25. Setting of Main Duty (R14)
MDT6
MDT5
MDT4
MDT3
MDT2
MDT1
MDT0
Duty
1
0
0
1
1
1
1
1/80
1
0
0
0
1
1
1
1/72
0
1
1
1
1
1
1
1/64
Table 5−
−26. Setting of Sub-duty (R17)
SDT6
SDT5
SDT4
SDT3
SDT2
SDT1
SDT0
Duty
0
1
0
1
1
1
1
1/48
0
1
0
0
1
1
1
1/40
0
0
1
1
1
1
1
1/32
0
0
1
0
1
1
1
1/24
0
0
0
1
1
1
1
1/16
5.7.4 Setting of LCD N-line inversion and M-line shift
During main duty display, the shift amount of the reverse position of AC driving and the reverse position of each
display frame can be set by the main duty N-line inversion register (R15) and main duty M-line shift register (R16). They
can also be set by the sub-duty N-line inversion register (R18) and sub-duty M-line shift register (R19) during sub-duty
display.
The N-line reverse cycle function can set a line to be reversed as shown in Table 5−
−27, depending on the setting of
MID5 to MID0 or SID5 to SID0 of the main or sub-duty N-line inversion register.
The M-line shift amount of the reverse position of each display frame can be set as shown in Table 5−
−28, by using
MSD5 to MSD0 or SSD5 to SSD0 of the main or sub-duty M-line shift register.
Table 5−
−27. Setting of N-line Inversion Register (R15)
52
MID5
MID4
MID3
MID2
MID1
MID0
Reversed
SID5
SID4
SID3
SID2
SID1
SID0
Cycle
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
1
0
0
1
0
1
38
1
0
0
1
1
0
39
1
0
0
1
1
1
40
Data Sheet S15726EJ2V0DS
µPD161401
Table 5−
−28. Setting of M-line Shift Register
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
0
0
0
0
1
1
3
1
0
0
1
1
0
38
1
0
0
1
1
1
39
1
0
1
0
0
0
40
Reversed Position Shift Amount
Make sure that the display size, reverse cycle, and shift amount of reverse position have the relationship indicated by
the following expression:
Display size (duty) ≥ reverse cycle ≥ reverse shift amount
Data Sheet S15726EJ2V0DS
53
µPD161401
5.7.5 Reverse driving between frames
In the µPD161401, the LCD drive waveform can be reversed and output between frames by setting the FXOR flag of
Driving mode select register (R64), as shown in Figure 5−
−27. This function is executed in combination with the reverse
cycle and reverse shift functions.
Figure 5−
−27. Image of Reversal between Pulse Width Modulation Frames
Reversal between frames not implemented (FXOR = 0)
Reverse cycle (R15, R18)
Frame n
Frame n+1
Frame n+2
Frame n+3
Reverse position shift amount (R16, R19)
Implementation of reversal between frames (FXOR = 1)
Reverse cycle (R15, R18)
Frame n
Frame n+1
Frame n+2
Frame n+3
Reverse position shift amount (R16, R19)
54
Data Sheet S15726EJ2V0DS
µPD161401
5.8 Display Mode
5.8.1 Selecting display mode
The µPD161401 has two display modes: main duty display and sub-duty display. In each of these modes, any duty
ratio can be selected and parts other than the display area can be scanned with a non-selected waveform.
The display mode can be selected by using the DTY flag of control register 2 (R1), and parameters such as the duty
ratio, bias value, and number of boosting steps are automatically selected as shown in the table below.
Display Setting
Main Duty Display (DTY = 0)
Sub-duty Display (DTY = 1)
Duty ratio
Main duty setting register (R14)
Sub-duty setting register (R17)
N-line inversion
Main duty N-line inversion register (R15)
Sub-duty N-line inversion register (R18)
M-line shift
Main duty M-line shift register (R16)
Sub-duty M-line shift register (R19)
VLCD adjustment
Bias value
Number of boosting steps
Power system control register 2 (R53)
Power system control register 2 (R53)
VRR3 to VRR0
SVR3 to SVR0
Power system control register 3 (R54)
Power system control register 3 (R54)
BIS2 to BIS0
SBIS2 to SBIS0
Power system control register 4 (R55)
Power system control register 4 (R55)
MBT2 to MBT0
SBT2 to SBT0
Electronic volume
Main electronic volume register (R57)
Sub-electronic volume register (R58)
Grayscale data setting
Main R grayscale data registers (R65 to R72)
Sub R grayscale data registers (R85 to R92)
Main G grayscale data registers (R73 to R80)
Sub G grayscale data registers (R93 to R100)
Main B grayscale data registers (R81 to R84)
Sub B grayscale data registers (R101 to R104)
When the mode is changed from the main duty display mode to the sub-duty display mode or vice versa, the display
screen may be temporarily disturbed, depending on the setting of each duty mode, if electric charge remains in the
smoothing capacitor connected between the LCD drive voltage pins (VLCD, VLC1 to VLC4) and VSS. It is recommended
that the following power sequence be observed to avoid any trouble that may occur when the display mode is changed.
Data Sheet S15726EJ2V0DS
55
µPD161401
★
(1) Main duty display mode to sub-duty display mode
Operation status
Main duty display mode
↓
Control register 1
DISP = 0, HALT = 0
R0
Display OFF. Internal operation starts.
R56
Change the operation mode of the operational
amplifier to “power OFF mode”.
R1
Sub-duty display mode setting Note1
↓
Power system control register 5
(HPM1 = 1, HPM0 = 0)
↓
Control register 2
DTY = 1
↓
Power system control register 5
(HPM1 = 0, HPM0 = 1)
R56
Wait time 2
Wait for at least 150 ms. Note2
↓
Power system control register 5
(HPM1 = 0, HPM0 = 0)
Wait time 1
Wait for at least 50 ms. Note2
Change the operation mode of the operational
amplifier to “power ON mode”.
R56
The operation mode of the operational amplifier:
“normal mode”.
R0
Display ON. Internal operation starts.
↓
Control register 1
(DISP = 1, HALT = 0)
↓
Setting completed
Notes 1. A scroll function cannot be used in sub-duty display mode. In the state where the scroll function is used by
main duty display mode when it changes to sub-duty, a scroll function is disregarded. Then, when it
changes to main duty display mode again, a scroll function returns to an effective state (state before
changing to sub-duty).
2. The wait times 1, 2 vary depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine these values after thorough evaluation
with the actual system.
56
Data Sheet S15726EJ2V0DS
µPD161401
★
(2) Sub-duty display mode to main duty display mode
Sub-duty display mode Note1
Operation status
↓
Control register 1
DISP = 0, HALT = 0
R0
Display OFF. Internal operation starts.
R56
Change the operation mode of the operational
amplifier to “power ON mode”.
R1
Main duty display mode setting
↓
Power system control register 5
(HPM1 = 0, HPM0 = 1)
↓
Control register 2
DTY = 0
↓
Power system control register 5
(HPM1 = 0, HPM0 = 0)
R56
Wait time
Wait for at least 160 ms. Note2
The operation mode of the operational amplifier:
“normal mode”.
↓
Control register 1
(DISP = 1, HALT = 0)
R0
Display ON. Internal operation starts.
↓
Setting completed
Notes 1. A scroll function cannot be used in sub-duty display mode. In the state where the scroll function is used by
main duty display mode when it changes to sub-duty, a scroll function is disregarded. Then, when it
changes to main duty display mode again, a scroll function returns to an effective state (state before
changing to sub-duty).
2. The wait time varies depending on the characteristics of the LCD panel and the capacitance of the boosting
or smoothing capacitor. It is recommended to determine this value after thorough evaluation with the actual
system.
Data Sheet S15726EJ2V0DS
57
µPD161401
5.8.2 Screen scrolling
The µPD161401 has a screen scroll function. This function is enabled during main duty display. The width of the area
to be fixed is specified by the scroll fixed area width register (R27) and the number of scroll steps is set by the scroll
step number register (R31). By these settings, other parts of screen can be scrolled with part of the screen fixed. To
specify the position of the area to be fixed, set the FIXAHL flag of the scroll fixed area position register (R23) as shown
in Table 5−
−29. Specify the fixed area position on the upper part of the LCD panel in master mode and on the bottom
part of the panel in slave mode.
Table 5−
−29. Scroll Fixed Area Width Register (R27)
FIXAW1
FIXAW0
Fixed area width
0
0
0
0
1
16
1
0
24
1
1
32
Table 5−
−30. Scroll Step Count Register (R31)
MST6
MST5
MST4
MST3
MST2
MST1
MST0
Number of Scroll Steps
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
1
0
0
1
1
1
0
78
1
0
0
1
1
1
1
79
1
0
1
0
0
0
0
Other settings prohibited
Note that the relationship between the number of scroll steps and the width of the scroll fixed area needs to be set so
that the following condition is set.
Number of scroll steps ≤ 79 − Width of scroll fixed area
Caution If values other than the above is set, the operation is not guaranteed.
Table 5−
−31. Scroll Fixed Area Position Register (R23)
58
FIXAHL
LCD Display Position
0
Bottom
1
Upper
Data Sheet S15726EJ2V0DS
µPD161401
5.8.3 Scroll setting examples
★
(1) Setting example 1
Duty: 1/64 duty
RAM read direction: normal (R0:COMR = 0)
Scroll fixed area width: 16 lines (R27: FIXAW1,0 = 0,1)
(a) Scroll fixed position: upper (R23: FIXAHL = 1)
Y address
0FH
Y address
COM1
00H
Fixed area
(b) Scroll fixed position: bottom (R23: FIXAHL = 0)
00H
COM16
Display RAM
Display RAM
3FH
COM49
30H
COM64
3FH
Fixed area
4FH
4FH
The relationships between the numbers of scroll steps and RAM Y address scan order in cases of (a) and (b) are as
follows.
(a)
Number of scroll steps: 0 (R31: MSTn = 00H)
RAM Y address: 00H → 0FH, 10H → 3FH
Number of scroll steps: 1 (R31: MSTn = 01H)
RAM Y address: 00H → 0FH, 11H → 40H
Number of scroll steps: 10 (R31: MSTn = 0AH)
RAM Y address: 00H → 0FH, 1AH → 49H
(b)
Number of scroll steps: 0 (R31: MSTn = 00H)
RAM Y address: 00H → 2FH, 30H → 3FH
Number of scroll steps: 1 (R31: MSTn = 01H)
RAM Y address: 00H → 2FH, 40H, 30H → 3FH
Number of scroll steps: 10 (R31: MSTn = 0AH)
RAM Y address: 0AH → 2FH, 40H → 49H, 30H → 3FH
Data Sheet S15726EJ2V0DS
59
µPD161401
★
(2) Setting example 2
Duty: 1/64 duty
RAM read direction: reverse (R0: COMR = 1)
Scroll fixed area width: 16 lines (R27: FIXAW1,0 = 0,1)
(a) Scroll fixed position: upper (R23: FIXAHL = 1)
Y address
0FH
Y address
COM64
00H
Fixed area
(b) Scroll fixed position: bottom (R23: FIXAHL = 0)
00H
COM49
Display RAM
Display RAM
3FH
COM16
30H
COM1
3FH
4FH
Fixed area
4Fh
The relationships between the numbers of scroll steps and RAM Y address scan order in cases of (a) and (b) are as
follows.
(a)
Number of scroll steps: 0 (R31: MSTn = 00H)
RAM Y address: 3FH → 10h, 0FH → 00H
Number of scroll steps: 1 (R31: MSTn = 01H)
RAM Y address: 40H → 11h, 0FH → 00H
Number of scroll steps: 10 (R31: MSTn = 0AH)
RAM Y address: 49H → 1Ah, 0FH → 00H
(b)
60
Number of scroll steps: 0 (R31: MSTn = 00H)
RAM Y address: 3Fh → 30H, 2FH → 00H
Number of scroll steps: 1 (R31: MSTn = 01H)
RAM Y address: 3Fh → 30H, 40h, 2FH → 01H
Number of scroll steps: 10 (R31: MSTn = 0AH)
RAM Y address: 3Fh → 30hH, 49H → 40H, 2FH → 0AH
Data Sheet S15726EJ2V0DS
µPD161401
5.9 Reset
When the reset command is input, the IC is initialized to the default status shown in the table below. Note that
initialization by using the /DISP pin should be used only to prevent malfunctioning due to noise.
Table 5−
−32. Default Values of Registers (1/2)
Register
Reset Command
/DISP
Control register 1
R0
Ο
Ο (DISP, TRON flag only)
Control register 2
R1
Ο
×
X address register
R4
Ο
×
Y address register
R5
Ο
×
MIN.⋅X address register
R7
Ο
×
MAX.⋅X address register
R8
Ο
×
MIN.⋅Y address register
R9
Ο
×
MIN.⋅Y address register
R10
Ο
×
Display memory access register
R12
×
×
Main duty setting register
R14
Ο
×
Main duty N-line inversion register
R15
Ο
×
Main duty M-line shift register
R16
Ο
×
Sub-duty setting register
R17
Ο
×
Sub-duty N-line inversion register
R18
Ο
×
Sub-duty M-line shift register
R19
Ο
×
COM scanning address setting register
R21
Ο
×
Sub-duty start address register
R22
Ο
×
Scroll fixed area position register
R23
Ο
×
Scroll fixed area width register
R27
Ο
×
Scroll steps number register
R31
Ο
×
Blinking/reverse setting register
R37
Ο
×
Complementary color blink X address register
R38
Ο
×
Complementary color blink start line address register
R39
Ο
×
Complementary color blink end line address register
R40
Ο
×
Complementary color blink data memory register
R41
×
×
Specified color blink X address register
R42
Ο
×
Specified color blink start line address register
R43
Ο
×
Specified color blink end line address register
R44
Ο
×
Specified color blink data memory register
R45
×
×
Specified color setting register
R46
Ο
×
Reverse X address register
R47
Ο
×
Reverse start line address register
R48
Ο
×
Remark O: Default value is input. X: Default value is not input.
Cautions 1. When initialization is made using the /DISP pin, the contents of memory are not guaranteed.
In this case, use the initialized RAM. When initialization is made via the reset command, the
contents of memory are retained.
2. If the device is initialized by the /DISP pin while the serial interface is being used, the serial clock
counter is initialized.
3. Always input the reset command as the first command after power application.
Data Sheet S15726EJ2V0DS
61
µPD161401
Table 5−
−32. Default Values of Registers (2/2)
Register
Reverse end line address register
R49
Reset Command
/DISP
Ο
×
Reversed data memory access register
R50
×
×
Power system control register 1
R52
Ο
×
Power system control register 2
R53
Ο
×
Power system control register 3
R54
Ο
×
Power system control register 4
R55
Ο
×
Power system control register 5
R56
Ο
×
Main electronic volume register
R57
Ο
×
Sub-electronic volume register
R58
Ο
×
RAM test mode setting register
R61
Ο
×
Driving mode select register
R64
Ο
×
Main R grayscale data registers 1 to 8
R65 to R72
Ο
×
Main G grayscale data registers 1 to 8
R73 to R80
Ο
×
Main B grayscale data registers 1 to 4
R81 to R84
Ο
×
Sub R grayscale data registers 1 to 8
R85 to R92
Ο
×
Sub G grayscale data registers 1 to 8
R93 to R100
Ο
×
Sub B grayscale data registers 1 to 8
R101 to R104
Ο
×
Remark O: Default value is input. X: Default value is not input.
Cautions 1. When initialization is made using the /DISP pin, the contents of memory are not guaranteed.
In this case, use the initialized RAM. When initialization is made via the reset command, the
contents of memory are retained.
2. If the device is initialized by the /DISP pin while the serial interface is being used, the serial clock
counter is initialized.
3. Always input the reset command as the first command after power application.
62
Data Sheet S15726EJ2V0DS
µPD161401
6. COMMANDS
The µPD161401 identifies data bus signals by a combination of the RS, /RD (E), and /WR (R,/W) signals. It interprets
and executes commands only in accordance with the internal timing, without being dependent upon the external clock.
Therefore, the processing speed is extremely high and, usually, no busy check is necessary.
An i80 system CPU interface inputs a low pulse to the /RD pin when it reads data from the µPD161401 to issue a
command. It inputs a low pulse to the /WR pin when it writes data to the µPD161401.
Data can be read from an M68 system CPU interface if a high-pulse signal is input to the R,/W pin, and written if a
low-pulse signal is input to the R,/W pin. A command is executed if a high-pulse signal is input to the E pin in this status.
Therefore, in the explanation of the commands and display commands in 6.1 Control Register 1 (R0) and the sections
that follow, the M68 system CPU interface uses H, instead of /RD (E), when reading status or display data. This is how
it differs from the i80 system CPU interface.
The commands of the µPD161401 are explained below, taking an i80 system CPU interface as an example. When the
serial interface is used, sequentially input data to the µPD161401, starting from D7.
The data bus length to input commands is as follows:
• Commands other than those that manipulate the display memory access register (R12) are input in byte units,
regardless of the value of BMOD (control register 2 (R1), bus length setting).
• The commands that manipulate the display memory access register (R12) are input in 1-byte units when BMOD = 1,
or in 2-byte units when BMOD = 0.
A. Commands other than those that manipulate display memory access register (R12)
BMOD = 1 (8-bit data bus)
Pin
D7
D6
D5
D4
D3
D2
D1
D0
DATA
D7
D6
D5
D4
D3
D2
D1
D0
BMOD = 0 (16-bit data bus)
Pin
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
Note
Note
Note
Note
Note
Note
Note
Note
D7
D6
D5
D4
D3
D2
D1
D0
Note 0 or 1
B. Display memory access register (R12)
BMOD = 1 (8-bit data bus)
Pin
D7
D6
D5
D4
D3
D2
D1
D0
DATA
D7
D6
D5
D4
D3
D2
D1
D0
BMOD = 0 (16-bit data bus)
Pin
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Sheet S15726EJ2V0DS
63
µPD161401
6.1 Control Register 1 (R0)
This command specifies the general operation mode of the µPD161401.
RS
E /RD
R,/W
D7
D6
D5
D4
D3
D2
D1
D0
TRON
WAS
COMF
DISP
STBY
HALT
ADC
COMR
/WR
1
1
TRON
0
0: Normal mode (all values written to the test register are ignored)
1: Test register valid mode (values written to the test register are valid)
WAS
0: Normal data write mode
COMF
0: Normal display operation
1: Window access mode (Refer to 5.2.7 Arbitrary address area access (window access mode (WAS)).)
1: All output from common pins is OFF (all the common pins output a non-selected waveform. At this time, the
segment pins output OFF data (level 0)).
DISP
0: Display OFF (All the LCD output pins output a VSS level, and the oscillator and DC/DC converter operate.)
1: Display ON
STBY
0: Normal operation
1: Internal operation and oscillation stop. Display OFF
HALT
0: Internal operation starts.
1: Internal operation stops (all the LCD output pins output a VSS level, the oscillator operates, and the DC/DC
converter stops, and the reference voltage generator operates).
ADC
Column addresses correspond to SEG outputs that are used to display the display data RAM (refer to Table 6−
−1).
COMR
Selects the direction in which the lines of the graphic RAM are read (refer to Table 6−
−2).
Table 6−
−1. Relationship between Column Address of Display RAM and Segment Output
SEG Output
SEG1
SEG303
•••
ADC
0
000H
→
Column address
→
12EH
(D1)
1
12EH
←
Column address
←
000H
Table 6−
−2. Relationship between Common Scan Circuit and Scan Direction
COMR
0
00H
→
4FH
(D0)
1
4FH
→
00H
Default (default value of reset command)
64
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Data Sheet S15726EJ2V0DS
µPD161401
6.2 Control Register 2 (R1)
This command specifies the general operation mode of the µPD161401.
RS
E
R,/W
/RD
/WR
1
0
1
FDM
D7
D6
FDM
D5
D4
BMOD
D3
D2
D1
D0
DTY
INC
XDIR
YDIR
Sets all screen display modes.
0: Normal operation
1: All screen display (Turns ON all screens [outputs grayscale level 16 to all screens].)
BMOD
Selects data length when parallel data is input.
0: 16-bit data bus
1: 8-bit data bus
DTY
0: Main duty display mode
1: Sub-duty display mode
INC Note
0: Increments/decrements X address each time it is accessed.
1: Increments/decrements Y address each time it is accessed.
XDIR Note
Specifies the direction in which the X address is to be accessed.
0: Increment (+1)
1: Decrement (-1)
YDIR
Note
Specifies the direction in which the Y address is to be accessed.
0: Increment (+1)
1: Decrement (-1)
Note If the access direction is changed by INC, XDIR, or YDIR, be sure to set the X address register (R4) and Y
address register (R5) before accessing the display RAM.
Table 6−
−3. Relationship between Functions of µPD161401 and Display Mode
Display Setting
Main Duty Display (DTY = 0)
Sub-duty Display (DTY = 1)
Duty
Main duty setting register (R14)
Sub-duty setting register (R17)
N-line inversion
Main duty N-line inversion register (R15)
Sub-duty N-line inversion register (R18)
M-line shift
Main duty M-line shift register (R16)
Sub-duty M-line shift register (R19)
VLCD adjustment
Bias value
Power system control register 2 (R53)
Power system control register 2 (R53)
VRR3 to VRR0
SVR3 to SVR0
Power system control register 3 (R54)
Power system control register 3 (R54)
BIS2 to BIS0
SBIS to SBIS0
Number of boosting
Power system control register 4 (R55)
Power system control register 4 (R55)
steps
MBT2 to MBT0
SBT2 to SBT0
Electronic volume
Main electronic volume register (R57)
Sub-electronic volume register (R58)
Grayscale data
Main R grayscale data register (R65 to R72)
Sub R grayscale data register (R85 to R92)
setting
Main G grayscale data register (R73 to R80)
Sub G grayscale data register (R93 to R100)
Main B grayscale data register (R81 to R84)
Sub B grayscale data register (R101 to R104)
Default (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
Note
0
Note
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
65
µPD161401
6.3 Reset Command Register (R3)
When this command is input, the registers of the µPD161401 (R0 to R104) are set to the default values.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
0
1
Caution At power application, be sure to input the reset command as the first command.
6.4 X Address Register (R4)
The X address register specifies the X address of the display RAM the CPU accesses. This address is automatically
incremented or decremented each time the display RAM has been accessed (INC = 0).
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
XA6
XA5
XA4
XA3
XA2
XA1
XA0
Caution If the access direction is changed by control register 2 (R1: INC, XDIR, YDIR) or window access area
is changed or set by MIN.⋅⋅X address register (R7, R9) and MAX.⋅⋅X address register (R8, R10), be sure
to set the X address register (R4) and Y address register (R5) before accessing the display RAM.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
6.5 Y Address Register (R5)
The Y address register specifies the Y address of the display RAM the CPU accesses. This address is automatically
incremented or decremented each time the display RAM is accessed (INC = 1).
RS
D7
1
YA6 to YA0
Caution
D6
D5
D4
D3
D2
D1
D0
YA6
YA5
YA4
YA3
YA2
YA1
YA0
Sets line address
If the access direction is changed by control register 2 (R1: INC, XDIR, YDIR), be sure to set the X
address register (R4) and Y address register (R5) before accessing the display RAM.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
66
Data Sheet S15726EJ2V0DS
µPD161401
6.6 MIN.·X Address Register (R7)
This register specifies the X address of the start point of the display RAM the CPU accesses when the window
access mode is used.
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
XMN6
XMN5
XMN4
XMN3
XMN2
XMN1
XMN0
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
6.7 MAX.·X Address Register (R8)
This register specifies the X address of the end point of the display RAM the CPU accesses when the window access
mode is used.
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
XMX6
XMX5
XMX4
XMX3
XMX2
XMX1
XMX0
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
6.8 MIN.·Y Address Register (R9)
This register specifies the Y address of the start point of the display RAM the CPU accesses when the window access
mode is used.
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
YMN6
YMN5
YMN4
YMN3
YMN2
YMN1
YMN0
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
67
µPD161401
6.9 MAX.·Y Address Register (R10)
This register specifies the Y address of the end point of the display RAM the CPU accesses when the window access
mode is used.
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
YMX6
YMX5
YMX4
YMX3
YMX2
YMX1
YMX0
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
6.10 Display Memory Access Register (R12)
The display memory access register is used to access the display RAM. When data is written to this register, it is
directly written to the display RAM. In the µPD161401, the data of the display access memory register (R12) cannot be
read.
BMOD = 1 (8-bit data bus)
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
D7
D6
D5
D4
D3
D2
D1
D0
BMOD = 0 (16-bit data bus)
RS
D15
D14
D13
D12
D11
D10
D9
D8
1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Default value (default value of reset command)
BMOD = 1 (8-bit data bus)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
BMOD = 0 (16-bit data bus)
D15
D14
D13
D12
D11
D10
D9
D8
Note
Note
Note
Note
Note
Note
Note
Note
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
68
Data Sheet S15726EJ2V0DS
µPD161401
6.11 Main Duty Setting Register (R14)
This register can set the display duty ratio in a range of 1/80, 1/72 and 1/64 duty as shown in Table 6−
−5 in the main
duty display mode.
Before changing the contents of this register, be sure to stop the internal operation by using the HALT command
(control register 1 (R0)).
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
MDT6
MDT5
MDT4
MDT3
MDT2
MDT1
MDT0
Table 6−
−5. Main Duty Setting Register (R14)
MDT6
MDT5
MDT4
MDT3
MDT2
MDT1
MDT0
Duty
1
0
0
1
1
1
1
1/80
1
0
0
0
1
1
1
1/72
0
1
1
1
1
1
1
1/64
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
1
0
0
1
1
1
1
Note 0 or 1
6.12 Main Duty N-line Inversion Register (R15)
This register can set the line position of AC driving in the main duty display mode as shown in Table 6−
−6.
RS
D7
D6
1
D5
D4
D3
D2
D1
D0
MID5
MID4
MID3
MID2
MID1
MID0
Table 6−
−6. Setting of Main Duty N-line Inversion Register (R15)
MID5
MID4
MID3
MID2
MID1
MID0
Line to be reversed
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
1
0
0
1
0
1
38
1
0
0
1
1
0
39
1
0
0
1
1
1
40
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
1
0
0
1
1
1
Note 0 or 1
Data Sheet S15726EJ2V0DS
69
µPD161401
6.13 Main Duty M-line Shift Register (R16)
This register shifts the reverse position of each frame in the main duty display mode by the shift amount shown in
Table 6−
−7.
RS
D7
D6
1
D5
D4
D3
D2
D1
D0
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Table 6−
−7. Main Duty M-line Shift Register (R16)
Shift amount of position
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
to be reversed
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
0
0
0
0
1
1
3
1
0
0
1
1
0
38
1
0
0
1
1
1
39
1
0
1
0
0
0
40
Make sure that the relationship between the display size, reverse cycle, and reverse position is established as follows.
Display size (Duty) ≥ reverse cycle ≥ reverse shift amount
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
0
0
0
0
0
0
Note 0 or1
70
Data Sheet S15726EJ2V0DS
µPD161401
6.14 Sub-duty Setting Register (R17)
This register can set the display duty ratio in a range of 1/48, 1/40, 1/32, 1/24 and 1/16 as shown in Table 6−
−8 in the
sub-duty display mode by setting SDT6 to SDT0.
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
SDT6
SDT5
SDT4
SDT3
SDT2
SDT1
SDT0
Table 6−
−8. Main Duty Setting Register (R17)
SDT6
SDT5
SDT4
SDT3
SDT2
SDT1
SDT0
Duty
0
1
0
1
1
1
1
1/48
0
1
0
0
1
1
1
1/40
0
0
1
1
1
1
1
1/32
0
0
1
0
1
1
1
1/24
0
0
0
1
1
1
1
1/16
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
1
0
1
1
1
1
Note 0 or 1
Data Sheet S15726EJ2V0DS
71
µPD161401
6.15 Sub-duty N-line Inversion Register (R18)
This register can set the line position of driving in the sub-duty display mode as shown in Table 6−
−9.
RS
D7
D6
1
D5
D4
D3
D2
D1
D0
SID5
SID4
SID3
SID2
SID1
SID0
Table 6−
−9. Sub-duty N-line Inversion Register (R18)
SID5
SID4
SID3
SID2
SID1
SID0
Line to be reversed
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
1
0
0
1
0
1
38
1
0
0
1
1
0
39
1
0
0
1
1
1
40
Caution Please protect the following relations.
Sub-duty display size (duty) ≥ sub-duty reversed line
If this relation is not protected, the operation is not guaranteed.
However, when the above-mentioned relation is not protected, inside µPD161401, processing which makes
reversed line equal to display size is carried out. In addition, the value of a register is not rewritten
automatically.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
1
0
0
1
1
1
Note 0 or 1
72
Data Sheet S15726EJ2V0DS
µPD161401
6.16 Sub-duty M-line Shift Register (R19)
This register shifts the reverse position of each frame in the sub-duty display mode by the shift amount shown in
Table 6−
−10.
RS
D7
D6
1
D5
D4
D3
D2
D1
D0
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
Table 6−
−10. Sub-duty M-line Shift Register (R19)
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
Shift amount of position to be reversed
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
2
0
0
0
0
1
1
3
1
0
0
1
1
0
38
1
0
0
1
1
1
39
1
0
1
0
0
0
40
Make sure that the relationship between the display size, reverse cycle, and reverse position is established as follows.
Display size (duty) ≥ reverse cycle ≥ reverse shift amount
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
0
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
73
µPD161401
6.17 COM Scanning Address Setting Register (R21)
This command specifies that scanning of the common outputs can be started from any of the On (n = 1 to 80) output
pins. Set the CSA4 to CSA0 bits as shown in Table 6−
−11 (1/2). The scan start pin can be specified by the value n
obtained from this table and the selected duty shown in Table 6−
−11 (2/2). The common wiring on the LCD panel can be
optimized according to the selected duty.
Tables 6−
−12, 6−
−13, and 6−
−14 indicate examples of the COM scan address settings for 1/64 duty, 1/72 duty, and 1/80
duty.
RS
D7
D6
D5
1
D4
D3
D2
D1
D0
CSA4
CSA3
CSA2
CSA1
CSA0
Table 6−
−11. COM Scanning Address Setting Register (1/2)
CSA4
CSA3
CSA2
CSA1
CSA0
n
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
1
0
3
0
1
1
1
0
15
0
1
1
1
1
16
1
0
0
0
0
17
1
0
0
0
1
Other settings prohibited
Table 6−
−11. COM Scanning Address Setting Register (2/2)
COMR = 0
Scanning start
(COM1) pin
On
→
→
COMR = 1
Scanning end
(COMa)
Note
O(n+a−1)
pin
Note
Scanning start
(COM1) pin
O(82−a−n)
→
→
Scanning end
(COMa) Note pin
O(80−n+1) Note
Note a = 64: 1/64 duty
a = 72: 1/72 duty
a = 80: 1/80 duty
Caution Set the COM scan address setting register so that the scan start pin and scan end pin satisfy the
equation below. If a value that exceeds this condition is set, the µPD161401 operation is not
guaranteed.
O1 ≤ Scan start pin and scan end pin ≤ O80
74
Data Sheet S15726EJ2V0DS
µPD161401
Table 6−
−12. Example of COM Scanning Address Setting (1/64 duty)
COMR = 0
Scanning start
CSA4
CSA3
CSA2
CSA1
CSA0
n
→
(COM1) pin
COMR = 1
Scanning end
(COMa)
Note
Scanning start
pin
(COM1) pin
→
Scanning end
(COMa)
Note
pin
On
→
O(n+a−1) Note
O(82−a−n)
→
O(80−n+1) Note
0
0
0
0
0
1
O1
→
O64
O17
→
O80
0
0
0
0
1
2
O2
→
O65
O16
→
O79
0
0
0
1
0
3
O3
→
O66
O15
→
O78
0
0
0
1
1
4
O4
→
O67
O14
→
O77
0
0
1
0
0
5
O5
→
O68
O13
→
O76
0
0
1
0
1
6
O6
→
O69
O12
→
O75
0
0
1
1
0
7
O7
→
O70
O11
→
O74
0
0
1
1
1
8
O8
→
O71
O10
→
O73
0
1
0
0
0
9
O9
→
O72
O9
→
O72
0
1
0
0
1
10
O10
→
O73
O8
→
O71
0
1
0
1
0
11
O11
→
O74
O7
→
O70
0
1
0
1
1
12
O12
→
O75
O6
→
O69
0
1
1
0
0
13
O13
→
O76
O5
→
O68
0
1
1
0
1
14
O14
→
O77
O4
→
O67
0
1
1
1
0
15
O15
→
O78
O3
→
O66
0
1
1
1
1
16
O16
→
O79
O2
→
O65
1
0
0
0
0
17
O17
→
O80
O1
→
O64
Note a = 64 at 1/64 duty
Data Sheet S15726EJ2V0DS
75
µPD161401
Table 6−
−13. Example of COM Scanning Address Setting (1/72 duty)
COMR = 0
COMR = 1
Scanning start → Scanning end
CSA4
CSA3
CSA2
CSA1
CSA0
n
(COM1) pin
Scanning start
(COMa) Note pin
(COM1) pin
→
Remark
Scanning end
(COMa)
Note
pin
On
→
O(n+a−1) Note
O(82−a−n)
→
O(80−n+1) Note
0
0
0
0
0
1
O1
→
O72
O9
→
O80
0
0
0
0
1
2
O2
→
O73
O8
→
O79
0
0
0
1
0
3
O3
→
O74
O7
→
O78
0
0
0
1
1
4
O4
→
O75
O6
→
O77
0
0
1
0
0
5
O5
→
O76
O5
→
O76
0
0
1
0
1
6
O6
→
O77
O4
→
O75
0
0
1
1
0
7
O7
→
O78
O3
→
O74
0
0
1
1
1
8
O8
→
O79
O2
→
O73
0
1
0
0
0
9
O9
→
O80
O1
→
O72
0
1
0
0
1
10
Other settings
prohibited
Note a = 72 at 1/72 duty
Caution Set the COM scan address setting register (R21) so that O1 ≤ scan start pin and scan end pin ≤ O80. If a
value that exceeds this condition is set, the µPD161401 operation is not guaranteed
Table 6−
−14. Example of COM Scanning Address Setting (1/80 duty)
COMR = 0
Scanning
CSA4
CSA3
CSA2
CSA1
CSA0
n
→
start
COMR = 1
Scanning end
Scanning start
(COMa) Note pin
(COM1) pin
→
Remark
Scanning end
(COMa) Note pin
(COM1) pin
0
0
0
0
0
1
0
0
0
0
1
2
On
→
O(n+a−1) Note
O(82−a−n)
→
O(80−n+1) Note
O1
→
O80
O1
→
O80
Other settings
prohibited
Note a = 80 at 1/80 duty
Caution When the µPD161401 is used in 1/80 duty, set the COM scan address setting register (R21) to CSA4,
CSA3, CSA2, CSA1, CSA0 = 0, 0, 0, 0, 0. If any other settings are made, the µPD161401 operation is not
guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
0
0
0
0
0
Note 0 or 1
76
Data Sheet S15726EJ2V0DS
µPD161401
6.18 Sub-duty Start Address Register (R22)
The sub-duty start address register specifies the start address of the display RAM the CPU accesses to use the subduty display mode. The sub-duty display area starts from this start line address and consists of the number of lines
specified by the sub-duty setting register (R17).
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
Table 6−
−15. Sub-duty Start Address Register
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
Common
0
0
0
0
0
0
0
COM1
0
0
0
0
0
0
1
COM2
0
0
0
0
0
1
0
COM3
0
0
0
0
0
1
1
COM4
1
0
0
1
1
0
1
COM78
1
0
0
1
1
1
0
COM79
1
0
0
1
1
1
1
COM80
Make sure that SSA (R22) and SDT (R17) have in the following relationship.
SSAn + SDTn ≤ MDT ≤ 4FH
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
77
µPD161401
6.19 Scroll Fixed Area Position Register (R23)
This command specifies the display position of the scroll fixed area to upper or bottom of side in LCD panel.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
FIXAHL
Table 6−
−16. Scroll Fixed Position Register (R23)
FIXAHL
Display Position
0
bottom
1
upper
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
1
Note 0 or 1
6.20 Scroll Fixed Area Width Register (R27)
This register selects the width of the area to be fixed from 0, 16, 24, and 32 lines.
RS
D7
D6
D5
D4
D3
D2
1
D1
D0
FIXAW1
FIXAW0
Table 4−
−16. Scroll Fixed Area Width Register (R27)
FIXAW1
FIXAW0
0
0
Fixed Area Width
0
0
1
16
1
0
24
1
1
32
Even if the screen display size is changed by the duty setting register (R14 and R17), FIXAW1 and FIXAW0 are not
overwritten.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
0
0
Note 0 or 1
78
Data Sheet S15726EJ2V0DS
µPD161401
6.21 Scroll Step Number Register (R31)
This register sets the number of scroll steps when the scroll function is used.
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
MST6
MST5
MST4
MST3
MST2
MST1
MST0
Table 6−
−18. Scroll Step Number Register (R31)
MST6
MST5
MST4
MST3
MST2
MST1
MST0
Number of Scroll Steps
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
1
0
0
1
1
0
1
77
1
0
0
1
1
1
0
78
1
0
0
1
1
1
1
79
1
0
1
0
0
0
0
Other settings prohibited
Caution The relationship between the number of scroll steps and scroll fixed area width should be as follows.
Number of scroll steps ≤ 79 − Scroll fixed area width
If values exceeding the above condition are set, the operation is not guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
79
µPD161401
6.22 Blink/Reverse Setting Register (R37)
This register controls blink display or reverse display. Blink display is controlled by the BLD1 and BLD0 flags of this
register, and reverse display is controlled by the INV flag, as shown in the table below.
The condition of each of the blink and reverse display areas is individually set by R38 to R50.
RS
D7
D6
D5
D4
1
D3
D2
INV
D1
D0
BLD1
BLD0
Table 6−
−19. Blink/Reverse Display Control
INV
Display
0
Reverse display OFF
1
Reverse display ON
BLD1
Display
0
Specified-color blink display OFF
1
Specified-color blink display ON
BLD0
Display
0
Complementary-color blink display OFF
1
Complementary-color blink display ON
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
0
Note
0
0
Note 0 or 1
6.23 Complementary Color Blink X Address Register (R38)
The complementary color blink X address register specifies the X address of the complementary color blink RAM the
CPU accesses. This address is automatically incremented each time the complementary color blink data RAM is
accessed.
RS
D7
D6
D5
D4
1
D3
D2
D1
D0
CBX3
CBX2
CBX1
CBX0
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
0
0
0
0
Note 0 or 1
80
Data Sheet S15726EJ2V0DS
µPD161401
6.24 Complementary Color Blink Start Line Address Register (R39)
The complementary color blink start line address register specifies the start line address the CPU accesses to use
complementary color blinking display. The range of the complementary color blink lines is determined by this register
and the complementary color blink end line address register.
RS
D7
1
CBS6 to CBS0
D6
D5
D4
D3
D2
D1
D0
CBS6
CBS5
CBS4
CBS3
CBS2
CBS1
CBS0
Setting
Sets a start line address
Caution Make sure that CBS [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
6.25 Complementary Color Blink End Line Address Register (R40)
The complementary color blink end line address register specifies the end line address the CPU accesses to use
complementary color blink display. The range of the complementary color blink lines is determined by this register and
the complementary color blink start line address register.
RS
D7
1
CBE6 to CBE0
D6
D5
D4
D3
D2
D1
D0
CBE6
CBE5
CBE4
CBE3
CBE2
CBE1
CBE0
Setting
Sets an end line address
Caution Make sure that CBE [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
81
µPD161401
6.26 Complementary Color Blink Data Memory Register (R41)
The complementary color blink data memory register is used to access the complementary color blink data RAM.
If this register is accessed for write, data is directly written to the complementary color blink data RAM.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
D7
D6
D5
D4
D3
D2
D1
D0
Data
Status
0
Normal
1
Complementary color blinking
Default value (default value of reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
6.27 Specified Color Blink X Address Register (R42)
The specified color blink X address register specifies the X address of the specified color blinking RAM the CPU
accesses. This address is automatically incremented each time the specified color blink data RAM is accessed.
RS
D7
D6
D5
D4
1
D3
D2
D1
D0
SBX3
SBX2
SBX1
SBX0
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
0
0
0
0
Note 0 or 1
82
Data Sheet S15726EJ2V0DS
µPD161401
6.28 Specified Color Blink Start Line Address Register (R43)
The specified color blink start line address register specifies the start line address the CPU accesses to use specified
color blinking display. The range of the specified color blink lines is determined by this register and the specified color
blinking end line address register.
RS
D7
1
SBS6 to SBS0
D6
D5
D4
D3
D2
D1
D0
SBS6
SBS5
SBS4
SBS3
SBS2
SBS1
SBS0
Setting
Sets a start line address.
Caution Make sure that SBS [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
6.29 Specified Color Blink End Line Address Register (R44)
The specified color blink end line address register specifies the end line address the CPU accesses to use specified
color blink display. The range of the specified color blink lines is determined by this register and the specified color blink
start line address register.
RS
D7
1
SBE6 to SBE0
D6
D5
D4
D3
D2
D1
D0
SBE6
SBE5
SBE4
SBE3
SBE2
SBE1
SBE0
Setting
Sets an end line address.
Caution Make sure that SBE [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Data Sheet S15726EJ2V0DS
83
µPD161401
6.30 Specified Color Blink Data Memory Register (R45)
The specified color blink data memory register is used to access the specified color blink data RAM. If this register is
accessed for write, data is directly written to the specified color blink data RAM.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
D7
D6
D5
D4
D3
D2
D1
D0
Data
Status
0
Normal
1
Specified color blinking
Default value (default value of reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
6.31 Specified Color Setting Register (R46)
This register sets specified color data when the specified color blink function is used. The data between this data and
the display RAM data blinks in a specified color.
RS
D7
D6
D5
D4
D3
D2
D1
1
D7
D6
D5
D4
D3
D2
D1
R
G
D0
Remark
D0
B
In 256-color mode
Default value (default value of reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
6.32 Reverse X Address Register (R47)
The reverse X address register specifies the X address of the reverse data RAM the CPU accesses. This address is
incremented each time the reverse RAM has been accessed.
RS
D7
D6
D5
D4
1
D3
D2
D1
D0
IVX3
IVX2
IVX1
IVX0
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
0
0
0
0
Note 0 or 1
84
Data Sheet S15726EJ2V0DS
µPD161401
6.33 Reverse Start Line Address Register (R48)
The reverse start line address register specifies start line address of the display RAM the CPU accesses for reverse
display. The range of the reverse lines is determined by this register and the reverse end line address register.
RS
D7
1
IVS6 to IVS0
D6
D5
D4
D3
D2
D1
D0
IVS6
IVS5
IVS4
IVS3
IVS2
IVS1
IVS0
Sets a start line address.
Caution Make sure that IVS [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
6.34 Reverse End Line Address Register (R49)
The reverse end line address register specifies the end line address of the display RAM the CPU accesses for reverse
display. The range of the reverse lines is determined by this register and the reverse start line address register.
RS
D7
1
IVE6 to IVE0
D6
D5
D4
D3
D2
D1
D0
IVE6
IVE5
IVE4
IVE3
IVE2
IVE1
IVE0
Setting
Sets an end line address.
Caution Make sure that IVE [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
85
µPD161401
6.35 Reverse Data Memory Access Register (R50)
The reverse data memory access register is used to access the reverse data RAM. When this register is accessed for
write, data is directly written to the reverse data RAM.
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
D7
D6
D5
D4
D3
D2
D1
D0
Data
Status
0
Normal
1
Reverse
Default value (default value of reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
86
Data Sheet S15726EJ2V0DS
Setting
µPD161401
6.36 Power System Control Register 1 (R52)
This command sets the power system mode of the µPD161401.
E
R,/W
RS
/RD
/WR
1
1
0
TCS2 to TCS0
OP3 to OP0
D7
D6
D5
D4
D3
D2
D1
D0
TCS2
TCS1
TCS0
OP3
OP2
OP1
OP0
These bits set the value that selects the temperature curve of the VREG voltage to a value shown in Table 6−
− 20.
These bits turn ON/OFF the booster circuit, reference voltage generator, control the voltage regulator circuit (V
regulator circuit) and voltage follower circuit (V/F circuit). The functions controlled by these four-power control
set command controlled by these 4 bits are listed in Table 6−
− 21.
Table 6−
−20. VREG Voltage Temperature Curve Value
TCS2
TCS1
TCS0
0
0
0
0
0
1
0
Temperature Gradient (unit: %/°C)
VREG (TYP.) (unit: V)
0
–0.12
1.77
1
–0.13
1.69
–0.15
1.63
–0.17
1.59
−
−
0
1
1
1
X
X
Status
Internal power supply
When external reference
power supply is used
Table 6−
−21. Details of Control by Each Bit of Power System Control Register
Status
Item
1
0
OFF
OP3
: Booster circuit control bit
ON
OP2
: Reference voltage generator control bit
ON
OFF
OP1
: Voltage regulator circuit (V regulator circuit) control bit
ON
OFF
OP0
: Voltage follower circuit (V/F circuit) control bit
ON
OFF
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
87
µPD161401
6.37 Power System Control Register 2 (R53)
This command sets the power system mode of the µPD161401.
E
R,/W
RS
/RD
/WR
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
VRR3
VRR2
VRR1
VRR0
SVR3
SVR2
SVR1
SVR0
VRR3 to VRR0
Setting
When the main duty display mode is used, the resistance ratio can be changed in 16 steps by the VLCD internal
resistance ratio adjustment command. Four bits of the VLCD internal resistance ratio adjustment register set the
reference value of (1 + Rb/Ra) to the value shown in Table 6−
−22.
SVR3 to SVR0
When the sub-duty display mode is used, the resistance ratio can be changed in 16 steps by the VLCD internal
resistance ratio adjustment command. Four bits of the VLCD internal resistance ratio adjustment register set the
reference value of (1 + Rb/Ra) to the value shown in Table 6−
−22.
Table 6-22. VLCD Internal Resistance Ratio Adjustment Register
Register
VRR2
VRR1
VRR0
SVR3
SVR2
SVR1
SVR0
0
0
0
0
3
0
0
0
1
4
0
0
1
0
5
0
0
1
1
6
0
1
0
0
7
0
1
0
1
8
0
1
1
0
9
0
1
1
1
10
1
0
0
0
11
1
0
0
1
12
1
0
1
0
13
1
0
1
1
14
1
1
0
0
15
1
1
0
1
16
1
1
1
0
17
1
1
1
1
18
Default value (default value of reset command)
88
1 + Rb/Ra
VRR3
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Data Sheet S15726EJ2V0DS
µPD161401
6.38 Power System Control Register 3 (R54)
This command sets the bias value for main duty display and sub-duty display by the µPD161401.
RS
D7
1
BIS2 to BIS0 Note
SBIS2 to SBIS0
Note
D6
D5
D4
BIS2
BIS1
BIS0
D3
D2
D1
D0
SBIS2
SBIS1
SBIS0
Setting
These flags select the bias ratio in the main duty display mode as follows:
BIS2
BIS1
BIS0
Bias Ratio
0
0
0
1/9 bias
0
0
1
1/8 bias
0
1
0
1/7 bias
0
1
1
1/6 bias
1
0
0
1/5 bias
1
0
1
Prohibited
1
1
0
Prohibited
1
1
1
Prohibited
These flags select the bias ratio in the sub-duty display mode as follows:
SBIS2
SBIS1
SBIS0
Bias Ratio
0
0
0
1/9 bias
0
0
1
1/8 bias
0
1
0
1/7 bias
0
1
1
1/6 bias
1
0
0
1/5 bias
1
0
1
Prohibited
1
1
0
Prohibited
1
1
1
Prohibited
Note Before changing these flags, execute the HALT command.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
Note
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
89
µPD161401
6.39 Power System Control Register 4 (R55)
This command sets the number of boosting steps for main duty display and sub-duty display of µPD161401 as shown
in Table 6−
−23.
RS
D7
1
D6
D5
D4
MBT2
MBT1
MBT0
D3
D2
D1
D0
SBT2
SBT1
SBT0
Setting
Table 6−
−23. Number of Boosting Steps for Main/Sub-duty Display of Booster Circuit
MBT2
MBT1
MBT0
SBT2
SBT1
SBT0
0
0
0
Two
0
0
1
Three
0
1
0
Four
0
1
1
Five
1
0
0
Six
1
0
1
Seven
1
1
0
Prohibited
1
1
1
Prohibited
Number of Boosting Steps (unit: fold)
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
Note
0
0
0
Note 0 or 1
90
Data Sheet S15726EJ2V0DS
µPD161401
6.40 Power System Control Register 5 (R56)
This command sets the status of the voltage follower circuit of the µPD161401 that drives the LCD, as follows:
RS
D7
D6
D5
D4
D3
D2
D1
D0
1
LCS1
LCS0
LCC1
LCC0
HPM1
HPM0
PSM1
PSM0
Setting
Table 6−
−24. Setting of Segment Output Driving Capability (LCS1, LCS0 = 0, 0)
LCS1
LCS0
Segment Output Driving Capability (unit: fold)
0
0
One
0
1
Two
1
0
Four
1
1
Eight
Table 6−
−25. Setting of Common Output Driving Capability (LCS1, LCS0 = 0, 0)
LCC1
LCC0
Common Output Driving Capability (unit: fold)
0
0
Two
0
1
Four
1
0
Eight
1
1
Sixteen
Table 6−
−26. Setting of Operational Amplifier Operation Mode
HPM1
HPM0
Mode Setting
0
0
Normal mode
0
1
Power ON mode1
1
0
Power OFF mode
1
1
Power ON mode2
Table 6−
−27. Setting of Two-fold Supply Voltage (VLC3, VLC4 Level Voltage Follower Power Supply)
PSM1
Mode Setting
0
Not used
1
used
Table 6−
−28. Setting of Voltage Follower Bias Current
PSM0
Bias Current Setting (unit: fold)
0
One
1
Two
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
0
1
0
Data Sheet S15726EJ2V0DS
91
µPD161401
6.41 Main Electronic Volume Register (R57)
The main electronic volume register specifies the electronic volume value for adjusting the contrast in the main duty
display mode, in 128 steps.
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
MEV6
MEV5
MEV4
MEV3
MEV2
MEV1
MEV0
Setting
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
6.42 Sub-electronic Volume Register (R58)
The sub-electronic volume register specifies an electronic volume value for adjusting the contrast in the sub-duty
display mode, in 128 steps.
RS
D7
1
D6
D5
D4
D3
D2
D1
D0
SEV6
SEV5
SEV4
SEV3
SEV2
SEV1
SEV0
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
0
0
0
0
0
0
0
Note 0 or 1
92
Data Sheet S15726EJ2V0DS
Setting
µPD161401
6.43 RAM Test Mode Setting Register (R61)
The RAM test mode setting register directly writes the data of each display status to the display RAM as shown in
Table 6−
−29.
RS
D7
D6
D5
D4
D3
1
D2
D1
D0
RTS2
RTS1
RTS0
Table 6−
−29. RAM Test Mode
RTS2
RTS1
RTS0
Write Data
0
0
0
Normal operation
0
0
1
all [00000000] / pixel display
0
1
0
all [11111111] / pixel display
0
1
1
Checker pattern display of [00000000] / [11111111]
1
0
0
Vertical grayscale bar display
1
0
1
Horizontal grayscale bar display
1
1
0
Each color grayscale display
1
1
1
256-color display
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
0
0
0
Note 0 or 1
6.44 Driving Mode Select Register (R64)
The FXOR flag of the drive mode select register controls the reversal of the LCD drive waveform between frames as
shown in Table 6−
−30. Note that the reverse function is executed between frames regardless of the FXOR flag during
sub-duty display.
RS
D7
D6
D5
D4
1
D3
D2
D1
D0
FXOR
Table 6−
−30. Driving Mode Select Register (R64)
FXOR
Reversing Between Frames
0
OFF
1
ON
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
0
Note
Note
Note
Note 0 or 1
Data Sheet S15726EJ2V0DS
93
µPD161401
6.45 Main R Grayscale Data Registers (R65 to R72)
The main R grayscale data registers specify the grayscale level of the R output in the main duty display mode. By
using these registers, grayscale display can be optimized.
Rx
Data
RS
R65
0, 0, 0
R66
0, 0, 1
R67
R68
D7
D6
D5
D4
D3
D2
D1
D0
1
MRG4
MRG3
MRG2
MRG1
MRG0
1
MRG4
MRG3
MRG2
MRG1
MRG0
0, 1, 0
1
MRG4
MRG3
MRG2
MRG1
MRG0
0, 1, 1
1
MRG4
MRG3
MRG2
MRG1
MRG0
R69
1, 0, 0
1
MRG4
MRG3
MRG2
MRG1
MRG0
R70
1, 0, 1
1
MRG4
MRG3
MRG2
MRG1
MRG0
R71
1, 1, 0
1
MRG4
MRG3
MRG2
MRG1
MRG0
R72
1, 1, 1
1
MRG4
MRG3
MRG2
MRG1
MRG0
D7
D6
D5
D4
D3
D2
D1
D0
Grayscale Level
×
×
×
0
0
0
0
0
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
0
1
1
1
1
Level 15
×
×
×
1
0
0
0
0
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
0
0
0
0
0
Note 0 or 1
94
Setting
Data Sheet S15726EJ2V0DS
µPD161401
6.46 Main G Grayscale Data Registers (R73 to R80)
The main G grayscale data registers specify the grayscale level of the G output in the main duty display mode. By
using these registers, grayscale display can be optimized.
Rx
Data
RS
R73
0, 0, 0
R74
0, 0, 1
R75
R76
D7
D6
D5
D4
D3
D2
D1
D0
1
MGG4
MGG3
MGG2
MGG1
MGG0
1
MGG4
MGG3
MGG2
MGG1
MGG0
0, 1, 0
1
MGG4
MGG3
MGG2
MGG1
MGG0
0, 1, 1
1
MGG4
MGG3
MGG2
MGG1
MGG0
R77
1, 0, 0
1
MGG4
MGG3
MGG2
MGG1
MGG0
R78
1, 0, 1
1
MGG4
MGG3
MGG2
MGG1
MGG0
R79
1, 1, 0
1
MGG4
MGG3
MGG2
MGG1
MGG0
R80
1, 1, 1
1
MGG4
MGG3
MGG2
MGG1
MGG0
Setting
D7
D6
D5
D4
D3
D2
D1
D0
Grayscale Level
×
×
×
0
0
0
0
0
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
0
1
1
1
1
Level 15
×
×
×
1
0
0
0
0
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
95
µPD161401
6.47 Main B Grayscale Data Registers (R81 to R84)
The main B grayscale data registers specify the grayscale level of the B output in the main duty display mode. By
using these registers, grayscale display can be optimized.
Rx
Data
RS
R81
0, 0
R82
0, 1
R83
R84
D7
D6
D5
D4
D3
D2
D1
D0
1
MBG4
MBG3
MBG2
MBG1
MBG0
1
MBG4
MBG3
MBG2
MBG1
MBG0
1, 0
1
MBG4
MBG3
MBG2
MBG1
MBG0
1, 1
1
MBG4
MBG3
MBG2
MBG1
MBG0
D7
D6
D5
D4
D3
D2
D1
D0
Grayscale Level
×
×
×
0
0
0
0
0
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
0
1
1
1
1
Level 15
×
×
×
1
0
0
0
0
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
0
0
0
0
0
Note 0 or 1
96
Setting
Data Sheet S15726EJ2V0DS
µPD161401
6.48 Sub R Grayscale Data Registers (R85 to R92)
The sub R grayscale data registers specify the grayscale level of the R output in the sub-duty display mode. By using
these registers, grayscale display can be optimized.
Rx
Data
RS
R85
0, 0, 0
R86
0, 0, 1
R87
R88
D7
D6
D5
D4
D3
D2
D1
D0
1
SRG4
SRG3
SRG2
SRG1
SRG0
1
SRG4
SRG3
SRG2
SRG1
SRG0
0, 1, 0
1
SRG4
SRG3
SRG2
SRG1
SRG0
0, 1, 1
1
SRG4
SRG3
SRG2
SRG1
SRG0
R89
1, 0, 0
1
SRG4
SRG3
SRG2
SRG1
SRG0
R90
1, 0, 1
1
SRG4
SRG3
SRG2
SRG1
SRG0
R91
1, 1, 0
1
SRG4
SRG3
SRG2
SRG1
SRG0
R92
1, 1, 1
1
SRG4
SRG3
SRG2
SRG1
SRG0
Setting
D7
D6
D5
D4
D3
D2
D1
D0
Grayscale Level
×
×
×
0
0
0
0
0
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
0
1
1
1
1
Level 15
×
×
×
1
0
0
0
0
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
97
µPD161401
6.49 Sub G Grayscale Data Registers (R93 to R100)
The sub G grayscale data registers specify the grayscale level of the G output in the sub-duty display mode. By using
these registers, grayscale display can be optimized.
Rx
Data
RS
R93
0, 0, 0
R94
0, 0, 1
R95
R96
D7
D6
D5
D4
D3
D2
D1
D0
1
SGG4
SGG3
SGG2
SGG1
SGG0
1
SGG4
SGG3
SGG2
SGG1
SGG0
0, 1, 0
1
SGG4
SGG3
SGG2
SGG1
SGG0
0, 1, 1
1
SGG4
SGG3
SGG2
SGG1
SGG0
R97
1, 0, 0
1
SGG4
SGG3
SGG2
SGG1
SGG0
R98
1, 0, 1
1
SGG4
SGG3
SGG2
SGG1
SGG0
R99
1, 1, 0
1
SGG4
SGG3
SGG2
SGG1
SGG0
R100
1, 1, 1
1
SGG4
SGG3
SGG2
SGG1
SGG0
D7
D6
D5
D4
D3
D2
D1
D0
Grayscale Level
×
×
×
0
0
0
0
0
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
0
1
1
1
1
Level 15
×
×
×
1
0
0
0
0
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
0
0
0
0
0
Note 0 or 1
98
Setting
Data Sheet S15726EJ2V0DS
µPD161401
6.50 Sub B Grayscale Data Registers (R101 to R104)
The sub B grayscale data registers specify the grayscale level of the B output in the sub-duty display mode. By using
these registers, grayscale display can be optimized.
Rx
Data
RS
R101
0, 0
R102
0, 1
R103
R104
D7
D6
D5
D4
D3
D2
D1
D0
1
SBG4
SBG3
SBG2
SBG1
SBG0
1
SBG4
SBG3
SBG2
SBG1
SBG0
1, 0
1
SBG4
SBG3
SBG2
SBG1
SBG0
1, 1
1
SBG4
SBG3
SBG2
SBG1
SBG0
Setting
D7
D6
D5
D4
D3
D2
D1
D0
Grayscale Level
×
×
×
0
0
0
0
0
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
0
1
1
1
1
Level 15
×
×
×
1
0
0
0
0
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
0
0
0
0
0
Note 0 or 1
Data Sheet S15726EJ2V0DS
99
µPD161401
7. µPD161401 REGISTER LIST
(1/2)
CS
RS
6
Index Register
5 4 3 2 1
0
0
Register Name
R/W
7
6
5
IR6
IR5
Data Bit
4
3
2
1
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
R3
Reset Command
0
1
0
0
0
0
1
0
0
R4
X Address Register
R/W
XA6
XA5
0
1
0
0
0
0
1
0
1
R5
Y Address Register
R/W
YA6
YA5
0
1
0
0
0
0
1
1
0
R6
0
1
0
0
0
0
1
1
1
R7
MIN.·X Address Register
R/W
0
1
0
0
0
1
0
0
0
R8
MAX. X Address Register
R/W
0
1
0
0
0
1
0
0
1
R9
MIN. Y Address Register
0
1
0
0
0
1
0
1
0
R10
MAX. Y Address Register
0
1
0
0
0
1
0
1
1
R11
0
1
0
0
0
1
1
0
0
R12
0
0
0
0
IR
Index Register
R0
Control Register 1
R/W
TRON
WAS COMF DISP
1
R1
Control Register 2
R/W
FDM
BMOD
0
R2
Display Memory Access Register
W
IR4
IR3
IR2
STBY HALT
IR1
IR0
ADC
COMR
YDIR
DTY
INC
XDIR
XA4
XA3
XA2
XA1
XA0
YA4
YA3
YA2
YA1
YA0
XMN6 XMN5 XMN4 XMN3 XMN2
XMN1
XMN0
XMX6 XMX5 XMX4 XMX3 XMX2
XMX1
XMX0
R/W
YMN6 YMN5 YMN4 YMN3 YMN2
YMN1
YMN0
R/W
YMX6 YMX5 YMX4 YMX3 YMX2
YMX1
YMX0
W
W
RES
D15
D14
D13
D15
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MDT1
MDT0
0
1
0
0
0
1
1
0
1
R13
0
1
0
0
0
1
1
1
0
R14
Main Duty Setting Register
R/W
0
1
0
0
0
1
1
1
1
R15
Main Duty N-line Inversion Register
R/W
MID5
MID2
MID1
MID0
0
1
0
0
1
0
0
0
0
R16
Main Duty M-line Shift Register
R/W
MSD5 MSD4 MSD3 MSD2
MSD1
MSD0
0
1
0
0
1
0
0
0
1
R17
Sub-duty Setting Register
R/W
SDT6 SDT5 SDT4 SDT3 SDT2
SDT1
SDT0
0
1
0
0
1
0
0
1
0
R18
Sub-duty N-line Inversion Register
R/W
SID5
SID2
SID1
SID0
0
1
0
0
1
0
0
1
1
R19
Sub-duty M-line Shift Register
R/W
SSD5 SSD4 SSD3 SSD2
SSD1
SSD0
0
1
0
0
1
0
1
0
0
R20
0
1
0
0
1
0
1
0
1
R21
COM Scanning Address Setting Register
R/W
CSA4 CSA3 CSA2
CSA1
CSA0
0
1
0
0
1
0
1
1
0
R22
Sub-duty Start Address Register
R/W
SSA4 SSA3
SSA1
0
1
0
0
1
0
1
1
1
R23
Scroll Fixed Area Position Register
R/W
FIXAHL
0
1
0
0
1
1
0
0
0
R24
0
1
0
0
1
1
0
0
1
R25
0
1
0
0
1
1
0
1
0
R26
0
1
0
0
1
1
0
1
1
R27
Scroll Fixed Area Width Register
R/W
FIXAW1 FIXAW0
0
1
0
0
1
1
1
0
0
R28
0
1
0
0
1
1
1
0
1
R29
0
1
0
0
1
1
1
1
0
R30
0
1
0
0
1
1
1
1
1
R31
Scroll Step Number Register
R/W
0
1
0
1
0
0
0
0
0
R32
0
1
0
1
0
0
0
0
1
R33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R34
R35
R36
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
Blink/Reverse Setting Register
Complementary Color Blink X Address Register
Specified Color Blink Data Memory Register
Specified Color Setting Register
Reverse X Address Register
Reverse Start Line Address Register
Reverse End Line Address Register
Reverse Data Memory Access Register
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
W
Power System Control Register 1
Power System Control Register 2
Power System Control Register 3
Power System Control Register 4
Power System Control Register 5
Main Electronic Volume Register
Sub-electronic Volume Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAM Test Mode Setting Register
R/W
100
Complementary Color Blink Start Line Address Register
Complementary Color Blink End Line Address Register
Complementary Color Blink Data Memory Register
Specified Color Blinking X Address Register
Specified Color Blink Start Line Address Register
Specified Color Blink End Line Address Register
Data Sheet S15726EJ2V0DS
MDT6 MDT5 MDT4 MDT3 MDT2
SSA6
SSA5
MID4
SID4
MID3
SID3
SSA2
MST6 MST5 MST4 MST3 MST2
SSA0
MST1
MST0
CBX2
CBS2
CBE2
D2
SBX2
SBS2
SBE2
D2
D2
IVX2
IVS2
IVE2
D2
BLD1
CBX1
CBS1
CBE1
D1
SBX1
SBS1
SBE1
D1
D1
IVX1
IVS1
IVE1
D1
BLD0
CBX0
CBS0
CBE0
D0
SBX0
SBS0
SBE0
D0
D0
IVX0
IVS0
IVE0
D0
D7
CBS6 CBS5 CBS4
CBE6 CBE5 CBE4
D6
D5
D4
D7
D7
SBS6
SBE6
D6
D6
SBS5
SBE5
D5
D5
SBS4
SBE4
D4
D4
D7
IVS6
IVE6
D6
IVS5
IVE5
D5
IVS4
IVE4
D4
INV
CBX3
CBS3
CBE3
D3
SBX3
SBS3
SBE3
D3
D3
IVX3
IVS3
IVE3
D3
TCS2
VRR2
BIS2
MBT2
LCS0
MEV6
SEV6
TCS1
VRR1
BIS1
MBT1
LCC1
MEV5
SEV5
TCS0
VRR0
BIS0
MBT0
LCC0
MEV4
SEV4
OP3
OP2
SVR3 SVR2
SBIS2
SBT2
HPM1 HPM0
MEV3 MEV2
SEV3 SEV2
OP1
SVR1
SBIS1
SBT1
PSM1
MEV1
SEV1
OP0
SVR0
SBIS0
SBT0
PSM0
MEV0
SEV0
RTS2
RST1
RST0
VRR3
LCS1
µPD161401
(2/2)
CS
RS
6
Index Register
5 4 3 2 1
0
Register Name
R/W
7
6
5
Data Bit
4
3
2
1
0
1
0
0
0
1
1
0
0
0
0
0
0
R64
IR
Driving Mode Select Register
0
1
1
0
0
0
0
0
1
R65
Main R Grayscale Data Register 1 (0, 0, 0)
MRG4 MRG3 MRG2 MRG1 MRG0
0
1
1
0
0
0
0
1
0
R66
Main R Grayscale Data Register 2 (0, 0, 1)
MRG4 MRG3 MRG2 MRG1 MRG0
0
1
1
0
0
0
0
1
1
R67
Main R Grayscale Data Register 3 (0, 1, 0)
MRG4 MRG3 MRG2 MRG1 MRG0
0
1
1
0
0
0
1
0
0
R68
Main R Grayscale Data Register 4 (0, 1, 1)
MRG4 MRG3 MRG2 MRG1 MRG0
0
1
1
0
0
0
1
0
1
R69
Main R Grayscale Data Register 5 (1, 0, 0)
MRG4 MRG3 MRG2 MRG1 MRG0
0
1
1
0
0
0
1
1
0
R70
Main R Grayscale Data Register 6 (1, 0, 1)
MRG4 MRG3 MRG2 MRG1 MRG0
0
1
1
0
0
0
1
1
1
R71
Main R Grayscale Data Register 7 (1, 1, 0)
MRG4 MRG3 MRG2 MRG1 MRG0
0
1
1
0
0
1
0
0
0
R72
Main R Grayscale Data Register 8 (1, 1, 1)
MRG4 MRG3 MRG2 MRG1 MRG0
0
1
1
0
0
1
0
0
1
R73
Main G Grayscale Data Register 1 (0 ,0, 0)
MGG4 MGG3 MGG2 MGG1 MGG0
0
1
1
0
0
1
0
1
0
R74
Main G Grayscale Data Register 2 (0, 0, 1)
MGG4 MGG3 MGG2 MGG1 MGG0
0
1
1
0
0
1
0
1
1
R75
Main G Grayscale Data Register 3 (0, 1, 0)
MGG4 MGG3 MGG2 MGG1 MGG0
0
1
1
0
0
1
1
0
0
R76
Main G Grayscale Data Register 4 (0, 1, 1)
MGG4 MGG3 MGG2 MGG1 MGG0
0
1
1
0
0
1
1
0
1
R77
Main G Grayscale Data Register 5 (1, 0, 0)
MGG4 MGG3 MGG2 MGG1 MGG0
0
1
1
0
0
1
1
1
0
R78
Main G Grayscale Data Register 6 (1, 0, 1)
MGG4 MGG3 MGG2 MGG1 MGG0
0
1
1
0
0
1
1
1
1
R79
Main G Grayscale Data Register 7 (1, 1, 0)
MGG4 MGG3 MGG2 MGG1 MGG0
0
1
1
0
1
0
0
0
0
R80
Main G Grayscale Data Register 8 (1, 1, 1)
MGG4 MGG3 MGG2 MGG1 MGG0
0
1
1
0
1
0
0
0
1
R81
Main B Grayscale Data Register 1 (0, 0)
MBG4 MBG3 MBG2 MBG1 MBG0
0
1
1
0
1
0
0
1
0
R82
Main B Grayscale Data Register 2 (0, 1)
MBG4 MBG3 MBG2 MBG1 MBG0
0
1
1
0
1
0
0
1
1
R83
Main B Grayscale Data Register 3 (1, 0)
MBG4 MBG3 MBG2 MBG1 MBG0
0
1
1
0
1
0
1
0
0
R84
Main B Grayscale Data Register 4 (1, 1)
MBG4 MBG3 MBG2 MBG1 MBG0
0
1
1
0
1
0
1
0
1
R85
Sub R Grayscale Data Register 1 (0, 0, 0)
SRG4 SRG3 SRG2 SRG1 SRG0
0
1
1
0
1
0
1
1
0
R86
Sub R Grayscale Data Register 2 (0, 0, 1)
SRG4 SRG3 SRG2 SRG1 SRG0
0
1
1
0
1
0
1
1
1
R87
Sub R Grayscale Data Register 3 (0, 1, 0)
SRG4 SRG3 SRG2 SRG1 SRG0
0
1
1
0
1
1
0
0
0
R88
Sub R Grayscale Data Register 4 (0, 1, 1)
SRG4 SRG3 SRG2 SRG1 SRG0
0
1
1
0
1
1
0
0
1
R89
Sub R Grayscale Data Register 5 (1, 0, 0)
SRG4 SRG3 SRG2 SRG1 SRG0
0
1
1
0
1
1
0
1
0
R90
Sub R Grayscale Data Register 6 (1, 0, 1)
SRG4 SRG3 SRG2 SRG1 SRG0
0
1
1
0
1
1
0
1
1
R91
Sub R Grayscale Data Register 7 (1, 1, 0)
SRG4 SRG3 SRG2 SRG1 SRG0
0
1
1
0
1
1
1
0
0
R92
Sub R Grayscale Data Register 8 (1, 1, 1)
SRG4 SRG3 SRG2 SRG1 SRG0
0
1
1
0
1
1
1
0
1
R93
Sub G Grayscale Data Register 1 (0, 0, 0)
SGG4 SGG3 SGG2 SGG1 SGG0
0
1
1
0
1
1
1
1
0
R94
Sub G Grayscale Data Register 2 (0, 0, 1)
SGG4 SGG3 SGG2 SGG1 SGG0
0
1
1
0
1
1
1
1
1
R95
Sub G Grayscale Data Register 3 (0, 1, 0)
SGG4 SGG3 SGG2 SGG1 SGG0
0
1
1
1
0
0
0
0
0
R96
Sub G Grayscale Data Register 4 (0, 1, 1)
SGG4 SGG3 SGG2 SGG1 SGG0
0
1
1
1
0
0
0
0
1
R97
Sub G Grayscale Data Register 5 (1, 0, 0)
SGG4 SGG3 SGG2 SGG1 SGG0
0
1
1
1
0
0
0
1
0
R98
Sub G Grayscale Data Register 6 (1, 0, 1)
SGG4 SGG3 SGG2 SGG1 SGG0
0
1
1
1
0
0
0
1
1
R99
Sub G Grayscale Data Register 7 (1, 1, 0)
SGG4 SGG3 SGG2 SGG1 SGG0
0
1
1
1
0
0
1
0
0
R100
Sub G Grayscale Data Register 8 (1, 1, 1)
SGG4 SGG3 SGG2 SGG1 SGG0
0
1
1
1
0
0
1
0
1
R101
Sub B Grayscale Data Register 1 (0, 0)
SBG4 SBG3 SBG2 SBG1 SBG0
0
1
1
1
0
0
1
1
0
R102
Sub B Grayscale Data Register 2 (0, 1)
SBG4 SBG3 SBG2 SBG1 SBG0
0
1
1
1
0
0
1
1
1
R103
Sub B Grayscale Data Register 3 (1, 0)
SBG4 SBG3 SBG2 SBG1 SBG0
0
1
1
1
0
1
0
0
0
R104
Sub B Grayscale Data Register 4 (1, 1)
SBG4 SBG3 SBG2 SBG1 SBG0
0
1
1
1
0
1
0
0
1
R105
0
1
1
1
0
1
0
1
0
R106
0
1
1
1
0
1
0
1
1
R107
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R108
R109
R110
R111
R112
R113
R114
R115
R116
R117
R118
R119
R120
R121
0
1
1
1
1
1
0
1
0
R122
0
1
1
1
1
1
0
1
1
R123
0
1
1
1
1
1
1
0
0
R124
0
1
1
1
1
1
1
0
1
R125
0
1
1
1
1
1
1
1
0
R126
0
1
1
1
1
1
1
1
1
R127
Data Sheet S15726EJ2V0DS
FXOR
101
µPD161401
8. POWER SEQUENCE
The µPD161401 has on-chip power circuits such as a booster circuit and a voltage follower circuit. Resetting by the
/DISP pin should only be used to prevent malfunctioning due to noise.
If charge remains in the smoothing capacitor connected between the LCD drive pins (VLCD, VLC1 to VLC4) and VSS, the
display screen may momentarily blackout when power is turned ON or OFF. It is therefore recommended to turn
ON/OFF power in the following sequence to avoid any trouble.
102
Data Sheet S15726EJ2V0DS
µPD161401
8.1 Power ON Sequence (with Internal Power Supply, Power ON → Display ON)
Power ON when /DISP pin = L
↓
Power supply is stabilized.
↓
/DISP pin = H
Wait for 50 µs or more.
↓
Reset command
R3
Initialization of registers
R0
Display OFF. Internal operation stops.
↓
Control register 1
DISP = 0, HALT = 1
↓
IC function setting by command input 1
Control register 1
(DISP = 0, HALT = 1)
Control register 2
↓
IC function setting by command input 2
Power system control register 1
(OP3, OP2, OP1, OP0 = 1, 1, 1, 1)
Power system control registers 2, 3, and 4
Power system control register 5
(HPM1, HPM0 = 0, 1)
Main electronic volume register
Sub-electronic volume register
Specify power ON mode 1 (master IC only).
↓
User setting by command input
Setting of functions such as grayscale data
↓
Initialization complete
↓
Control register 1
(DIPS = 0, HALT = 0)
R0
Display OFF. Internal operation starts.
↓
LCD display screen setting
Display start line set
Writing of screen data
+ Wait time
★
Wait time 1
Wait for 120 to 150 ms or more from when the internal
operation starts until the LCD turns ON Note.
↓
Power system control register 5
(HPM1, HPM0 = 0, 0)
(LCS1, LCS0 = 1,1)
(LCC1, LCC0 = 1,1)
★
(PSM = 1)
Change the operation mode of the operation amplifier to
“normal mode” (master IC only).
Segment output driving capability setting: x8
Common output driving capability setting: x16
Voltage follower bias current: x2
↓
<A> in the next page
Note
The wait times1, 2 vary depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine this value after thorough evaluation with
the actual system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
Data Sheet S15726EJ2V0DS
103
µPD161401
★
<A>
Wait time 2
Wait for at least 250 ms from when the output mode of the
operation amplifier is changed until the LCD turns ON Note.
↓
Power system control register 5
(HPM1, HPM0 = 0, 0)
(LCS1, LCS0 = x,x)
(LCC1, LCC0 = x,x)
R0
The operation mode of the operation amplifier: normal mode
Change the setting of the segment output driving capability,
common output driving capability, and voltage follower bias
current to the normal state.
R0
Display ON. Internal operation starts.
(PSM = x)
↓
Control register 1
(DIPS = 1, HALT = 0)
x: 0 or 1
Note
The wait times1, 2 vary depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine this value after thorough evaluation with
the actual system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
104
Data Sheet S15726EJ2V0DS
µPD161401
8.2 Power OFF Sequence (with Internal Power Supply)
Operation status
↓
Control register 1
DISP = 0, HALT = 0
R0
Display OFF. Internal operation starts.
R56
Change the operation mode of the operational
amplifier to “power OFF mode”.
R57
[MEV6, MEV5, MEV4, MEV3, MEV2, MEV1, MEV0]
= [0, 0, 0, 0, 0, 0, 0]
R58
[SEV6, SEV5, SEV4, SEV3, SEV2, SEV1, SEV0]
= [0, 0, 0, 0, 0, 0, 0]
↓
Power system control register 5
(HPM1, HPM0 = 1, 0)
↓
Main electronic volume register setting
↓
Sub-electronic volume register setting
★
Wait time 1
Wait for at least 120 ms Note.
↓
Control register 1
(DISP = 0, HALT = 1)
★
↓
R0
Display OFF. Internal operation stops.
Wait time 2
Wait for at least 380 ms before turning power OFF Note.
Power OFF
Note
The wait times 1, 2 vary depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine this value after thorough evaluation with
the actual system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
Data Sheet S15726EJ2V0DS
105
µPD161401
8.3 Power ON Sequence (with External Driving Power Supply, Power ON → Display ON)
This is an example of inputting a reference voltage to the VRS pin and a driving voltage to the VOUT pin from an
external power supply.
VDD1 and VDD2 ON, VOUT = Hi-Z
Logic power supply ON with /DISP pin = L
↓
Power supply stabilized.
↓
/DISP pin = H
↓
Reset command
R3
Wait for 50 µs or more.
Initialization of registers
↓
Control register 1
DISP = 0, HALT = 1
↓
R0
Display OFF. Internal operation stops.
IC function setting by command input 1
Control register 1
(DISP = 0, HALT = 1)
Control register 2
↓
IC function setting by command input 2
Power system control register 1
(OP3, OP2, OP1, OP0 = 1, 1, 1, 1)
Power system control registers 2, 3, and 4
Power system control register 5
(HPM1, HPM0 = 0, 1)
Main electronic volume register
Sub-electronic volume register
↓
Specify power ON mode1 (master IC only).
User setting by command input
Setting of functions such as grayscale data
↓
Initialization complete
↓
Control register 1
(DISP = 0, HALT = 0)
↓
R0
Supply voltage to VOUT pin.
Turn ON external driving power supply
↓
LCD screen setting
Display start line setting
Writing of screen data
+ Wait time
↓
★
Wait for at least 300 ms from when the internal operation
starts until the LCD turns ON Note.
Change the operation mode of the operation amplifier to
“normal mode” (master IC only).
Power system control register 5
(HPM1, HPM0 = 0, 0)
↓
Control register 1
(DIPS = 1, HALT = 0)
Display OFF. Internal operation starts.
R0
Display ON. Internal operation starts.
Note The time of 300 ms varies depending on the characteristics of the LCD panel and the capacitance of the
smoothing capacitor. It is recommended to determine this value after thorough evaluation with the actual
system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
106
Data Sheet S15726EJ2V0DS
µPD161401
8.4 Power OFF Sequence (with External Driving Power Supply)
This is an example of inputting a reference voltage to the VRS pin and a driving voltage to the VOUT pin from an
external power supply.
Operation status
↓
Control register 1
DISP = 0, HALT = 0
R0
Display OFF. Internal operation starts.
R56
Change the operation mode of the operational
amplifier to “power OFF mode”.
↓
Power system control register 5
(HPM1, HPM0 = 1, 0)
★
↓
Driving power supply OFF
Wait for at least 300 ms until power is OFF Note.
Turn OFF driving voltage VOUT after the levels of VLCD
and VLC1 to VLC4 have completely dropped.
↓
Power OFF
Note
Power to VDD1 and VDD2 OFF
The time of 300 ms varies depending on the characteristics of the LCD panel and the capacitance of the
smoothing capacitor. It is recommended to determine this value after thorough evaluation with the actual
system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
Data Sheet S15726EJ2V0DS
107
µPD161401
★
8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF
0 VDD
VOUT
/DISP pin = L
VDD ON
/DISP pin = H
RES = 1
DISP = 0, HALT = 1
TCS = 0,1,1(M) OP = 1,1,1,1 (M)
LCS = 1,1 LCC = 1,1 HPM = 0,1 (M)
HALT = 0
120 to 150 ms
LCS = 1,1 LCC = 1,1 HPM = 0,0 (M)
250 ms
LCS = X,X LCC = X,X HPM = 0,0 (M)
DISP = 1
Main Duty Display
DISP = 0
HPM = 1,0(M)
DTY = 1
50 ms
HPM = 0,1(M)
HPM = 0,0(M)
150 ms
DISP = 1
Sub Duty Display
DISP = 0
HPM = 0,1(M)
DTY = 0
160 ms
HPM = 0,0(M)
DISP = 1
Normal Duty Display
DISP = 0
HPM = 1,0(M)
EV = 0 PEV = 0(M)
120 ms
HALT = 1
380 ms
VDD OFF
Dotted line: VOUT
Solid line: VLCD
x: 1 or 0
Test conditions:
Supply voltage: VDD1 = VDD2 = 3.0 V
Number of boosting stages: x5 (in normal display mode), x3 (in partial display mode)
Capacitance: Between VLCn pin and Cn+/- pins = 1.0 µF
Caution Connect a capacitor of 0.1 µF or less to the AMPOUTM and AMPOUTS pins.
108
Data Sheet S15726EJ2V0DS
µPD161401
★
8.6 Flow of VOUT and VLCD Voltages in Display Output and HALT/Standby Modes
0 VDD
VOUT
Main Duty Display
DISP = 0
HPM = 1,0(M)
EV = 0
300 ms
HALT = 1(STBY = 1)
HALT(STBY)
HPM = 0,1(M)
EV = x,x(M)
HALT = 0(STBY = 0)
160 ms
HPM = 0,0(M)
DISP = 1
Dotted line: VOUT
Solid line: VLCD
x: 1 or 0
Test conditions:
Supply voltage: VDD1 = VDD2 = 3.0 V.
Number of boosting stages: x5 (in normal display mode), x3 (in partial display mode)
Capacitance: Between VLCn pin and Cn+/- pins = 1.0 µF
Caution Connect a capacitor of 0.1 µF or less to the AMPOUTM and AMPOUTS pins.
Data Sheet S15726EJ2V0DS
109
µPD161401
9. USING RAM TEST MODE
The µPD161401 has a test mode in which seven types of screen data are written to the display RAM. When using this
test mode, be sure to execute the following sequence. If the RAM test mode is executed in any other sequence,
erroneous data may be displayed.
Operating status
↓
Control register 1
DISP = 0, STBY = 1
R0
Display OFF. Standby setting
R61
Select data to be written to RAM.
R0
Display OFF. Standby cleared
↓
RAM test mode setting
↓
Control register 1
DISP = 0, STBY = 0
↓
Wait for 200 ms or more from when the internal operation
starts until the LCD turns OFF Note.
Wait time
↓
Control register 1
DISP = 1
R0
Display ON.
↓
Setting complete
Note The time of 200 ms varies depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine this value after thorough evaluation with
the actual system.
Remark The set display data is always written to the display RAM in the RAM test mode.
110
Data Sheet S15726EJ2V0DS
µPD161401
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C, VSS = 0 V)
Parameter
Symbol
Ratings
Unit
−0.3 to +4.0
V
Logic supply voltage
VDD1
Booster circuit supply voltage
VDD2
−0.3 to +4.0
V
Driver supply voltage
VOUT
−0.3 to +20.0
V
Driver reference power input voltage
VLCD,VLC1 to VLC4
−0.3 to VOUT + 0.3
V
Logic input voltage
VIN1
−0.3 to VDD1 + 0.3
V
Logic output voltage
VO1
−0.3 to VDD1 + 0.3
V
Logic I/O voltage
VI/O1
−0.3 to VDD1 + 0.3
V
Driver input voltage
VIN2
−0.3 to VOUT + 0.3
V
Driver output voltage
VO2
−0.3 to VOUT + 0.3
V
Operating ambient temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−55 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Logic supply voltage
VDD1
1.8
3.6
V
Booster circuit supply voltage
VDD2Note1
2.4
3.6
V
Note2
Driver supply voltage
VOUT
5.5
18.0
V
Logic supply voltage
VIN
0
VDD1
V
Driver supply voltage
VLCD,
0
VOUT
V
VOUT − 0.5
V
VLC1 to VLC4Note2
Maximum LCD voltage setting range VLCDNote3
Notes 1. It is essential that VDD1 ≤ VDD2.
2. These conditions are recommended when the LCD is driven by an external power supply.
3. This condition is recommended when the LCD is driven by the internal power supply circuit.
Cautions 1. Make sure that the relationship of VSS < VLC4 < VLC3 < VLC2 <VLC1 < VLCD ≤ VOUT is satisfied when the
LCD is driven by an external power supply.
2. Make sure that the condition described in 8. POWER SEQUENCE are satisfied when turning
power ON or OFF.
3. Keep the voltage at the VR and VRS pins to between 1.0 V and VDD1 when an external resistor is
used (when the internal resistor is not used to adjust VLCD).
Data Sheet S15726EJ2V0DS
111
µPD161401
Electrical Specifications (Unless otherwise specified, TA = −40 to +85°°C, VDD1 = 1.8 to 3.6 V, VDD2 = 2.4 to 3.6 V.)
Parameter
Symbol
Input voltage, high
VIH
Input voltage, low
VIL
Conditions
MIN.
TYP.Notes1
MAX.
0.8 VDD1
Unit
V
0.2 VDD1
V
Input current, high
IIH1
Other than D15 to D0
1
µA
Input current, low
IIL1
Other than D15 to D0
−1
µA
Output voltage, high
VOH
IOUT = −1 mA. Other than OCSOUT
Output voltage, low
VOL
IOUT = 1 mA. Other than OCSOUT
0.5
V
Leakage current, high
ILOH
D15 to D8, D7(SI), D6(SCL), D5 to D0,
10
µA
Leakage current, low
ILOL
−10
µA
4
kΩ
4
kΩ
VDD1 − 0.5
V
VIN/OUT = VDD1
D15 to D8, D7(SI), D6(SCL), D5 to D0,
VIN/OUT = VSS
Common output ON resistance
RCOM
VLCn → COMn, VOUT = 15 V, VLCD = 13 V,
1/9 bias, |IO| = 50 µA
Segment output ON resistance
RSEG
VLCn → SEGn, VOUT = 15 V, VLCD = 13 V,
Driver voltage (booster voltage)
VOUT
In 5-fold mode, VDD2 = 3.0 V,
1/9 bias, |IO| = 50 µA
13.8
V
16.6
V
diced display
In 6-fold mode, VDD2 = 3.0 V,
diced display
Regulated voltageNotes2
VREG
TA = 85°C.
1.430
1.485
1.540
V
50
mV
(TCS2, TCS1, TCS0) = (0,1,0)
Temperature curve –0.15 %/°C
Output voltage deflection
∆VLCn
VLCn: VLCD, VLC1 to VLC4,
−50
(OP3, OP2, OP1, OP0) = (0, 0, 0, 1)
VDD1 = 2.5 V, VOUT = 15 V,
AMPOUTM = 14 V, bias = 1/5 to 1/9,
IRS pin = L, display OFF, no load
Oscillation frequency Notes3
∆AMPOUT
IRS pin = H, 1+Rb/Ra = 10-fold
fOSC
VDD1 = 3.0 V, TA = 25°C, 1/80 duty,
−100
100
mV
72
85
97
kHz
33
40
46
kHz
175
280
µA
72
120
µA
10
µA
R = 360 kΩ (OSCIN1-OSCOUT)
VDD1 = 3.0 V, TA = 25°C, 1/38 duty,
R = 770 kΩ (OSCIN2-OSCOUT)
Current consumption
IDD11
Frame frequency = 70 Hz, all PWM
display output, 1/80 duty,
VDD1 = VDD2 = 3.0 V, VLCD = 13 V,
in 5-fold mode, driving mode (segment x
1, common x 4)
Frame frequency = 70 Hz, all PWM
display output, 1/32 duty,
VDD1 = VDD2 = 3.0 V, VLCD = 7.0 V,
in 3-fold mode, driving mode (segment x
1, common x 4)
Current consumption
IDD22
VDD1 = VDD2 = 3.0 V
(standby mode)
Notes1
The TYP. values are reference values at TA = 25°C (except for regulated voltage (VREG)).
2
The TYP. values of Regulated voltage (VREG) at TA = 25°C are MIN. 1.580 V, TYP. 1.635 V, MAX. 1.690 V
3
Oscillation frequency is changed under the influence of the wiring capacity to the external resistor for
oscillation.
112
Data Sheet S15726EJ2V0DS
µPD161401
Timing Requirements (Unless otherwise specified, TA = −30 to +85°°C.)
(1) i80 CPU interface
RS
tAS8
tf
tr
tAH8
/CS1
(CS2 = H)
tCYC8
tCCLR, tCCLW
/WR, /RD
tDS8
tCCHR, tCCHW
tDH8
D0 to D15(D7)
(Write)
tOH8
tACC8
D0 to D7
(Read)
(VDD1 = 1.8 to 2.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH8
RS
0
ns
Address setup time
tAS8
RS
0
ns
System cycle time
tCYC8
1000
ns
Control L pulse width (/WR)
tCCLW
/WR
160
ns
Control L pulse width (/RD)
tCCLR
/RD
430
ns
Control H pulse width (/WR)
tCCHW
/WR
160
ns
Control H pulse width (/RD)
tCCHR
/RD
160
ns
Data setup time
tDS8
D0 to D15 (D7)
160
ns
Data hold time
tDH8
D0 to D15 (D7)
0
ns
/RD access time
tACC8
D0 to D7, CL = 100 pF
0
470
ns
Output disable time
tOH8
D0 to D7, CL = 5 pF, RL = 3 kΩ
0
170
ns
Note The TYP. values are reference values at TA = 25°C.
(VDD1 = 2.0 to 2.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH8
RS
0
ns
Address setup time
tAS8
RS
0
ns
System cycle time
tCYC8
600
ns
Control L pulse width (/WR)
tCCLW
/WR
120
ns
Control L pulse width (/RD)
tCCLR
/RD
240
ns
Control H pulse width (/WR)
tCCHW
/WR
120
ns
Control H pulse width (/RD)
tCCHR
/RD
120
ns
Data setup time
tDS8
D0 to D15 (D7)
120
ns
Data hold time
tDH8
D0 to D15 (D7)
0
/RD access time
tACC8
D0 to D7, CL = 100 pF
0
280
ns
Output disable time
tOH8
D0 to D7 , CL = 5 pF, RL = 3 kΩ
0
170
ns
ns
Note The TYP. values are reference values at TA = 25°C.
Data Sheet S15726EJ2V0DS
113
µPD161401
(VDD1 = 2.5 to 3.6 V)
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH8
RS
0
ns
Address setup time
tAS8
RS
0
ns
System cycle time
tCYC8
100
ns
Control L pulse width (/WR)
tCCLW
/WR
40
ns
Control L pulse width (/RD)
tCCLR
/RD
40
ns
Control H pulse width (/WR)
tCCHW
/WR
40
ns
Control H pulse width (/RD)
tCCHR
/RD
40
ns
Data setup time
tDS8
D0 to D15 (D7)
40
ns
Data hold time
tDH8
D0 to D15 (D7)
0
ns
/RD access time
tACC8
D0 to D7, CL = 100 pF
0
50
ns
Output disable time
tOH8
D0 to D7, CL = 5 pF, RL = 3 kΩ
0
50
ns
Note The TYP. values are reference values at TA = 25°C.
Cautions 1. The rise and fall times (tr and tf) of an input signal are 10 ns or less.
2. All timing data is specified at 20% and 80% of VDD1.
114
Data Sheet S15726EJ2V0DS
µPD161401
(2) M68 CPU interface
RS
R,/W
tAS6
tf
tr
tAH6
/CS1
(CS2 = H)
tCYC6
tEWHR, tEWHW
E
tDS6
tEWLR, tEWLW
tDH6
D0 to D15 (D7)
(Write)
tACC6
tOH6
D0 to D7
(Read)
(VDD1 = 1.8 to 2.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH6
RS
0
Address setup time
tAS6
RS
0
ns
ns
System cycle time
tCYC6
1000
ns
Data setup time
tDS6
D0 to D15 (D7)
160
ns
Data hold time
tDH6
D0 to D15 (D7)
0
ns
Access time
tACC6
D0 to D7, CL = 100 pF
0
470
ns
Output disable time
tOH6
D0 to D7, CL = 5 pF, R = 3 kΩ
0
170
ns
Read
tEWHR
E
430
ns
Write
tEWHW
E
160
ns
Read
tEWLR
E
160
ns
Write
tEWLW
E
160
ns
Enable H pulse width
Enable L pulse width
Note The TYP. values are reference values at TA = 25°C.
(VDD1 = 2.0 to 2.5 V)
Parameter
Symbol
Conditions
Address hold time
tAH6
RS
Address setup time
tAS6
RS
System cycle time
tCYC6
MIN.
TYP.Note
MAX.
0
Unit
ns
0
ns
600
ns
ns
Data setup time
tDS6
D0 to D15 (D7)
120
Data hold time
tDH6
D0 to D15 (D7)
0
Access time
tACC6
D0 to D7, CL = 100 pF
0
280
ns
0
170
ns
Output disable time
ns
tOH6
D0 to D7, CL = 5 pF, R = 3 kΩ
tEWHR
E
240
ns
Write
tEWHW
E
120
ns
Read
tEWLR
E
120
ns
tEWLW
E
120
ns
Enable H pulse width
Read
Enable L pulse width
Write
Note The TYP. values are reference values at TA = 25°C.
Data Sheet S15726EJ2V0DS
115
µPD161401
(VDD1 = 2.5 to 3.6 V)
Parameter
Symbol
Conditions
MIN.
TYP.Note
MAX.
Unit
Address hold time
tAH6
RS
0
ns
Address setup time
tAS6
RS
0
ns
System cycle time
tCYC6
100
ns
Data setup time
tDS6
D0 to D15 (D7)
50
ns
Data hold time
tDH6
D0 to D15 (D7)
0
Access time
tACC6
D0 to D7, CL = 100 pF
0
50
ns
Output disable time
tOH6
D0 to D7, CL = 5 pF, R = 3 kΩ
0
50
ns
Read
tEWHR
E
40
ns
Write
tEWHW
E
40
ns
Read
tEWLR
E
40
ns
Write
tEWLW
E
40
ns
Enable H pulse width
Enable L pulse width
ns
Note The TYP. values are reference values at TA = 25°C.
Cautions 1. The rise and fall times (tr and tf) of an input signal are 10 ns or less. If the system cycle time is
short, (tr + tf) ≤ (tCYC6 – tEWLW – tEWHW) or (tr + tf) ≤ (tCYC6 – tEWLR – tEWHR).
2. All timing data is specified at 20% and 80% of VDD1.
116
Data Sheet S15726EJ2V0DS
µPD161401
(3) Serial interface
tCSS
tCSH
/CS1
(CS2 = H)
tSAS
tSAH
RS
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
(VDD1 = 1.8 to 2.5 V)
Parameter
Symbol
Condition
MIN.
TYP.Note
MAX.
Unit
Serial clock cycle
tSCYC
SCL
250
ns
SCL high-level pulse width
tSHW
SCL
100
ns
SCL low-level pulse width
tSLW
SCL
100
ns
Address hold time
tSAH
RS
150
ns
Address setup time
tSAS
RS
150
ns
Data setup time
tSDS
SI
100
ns
Data hold time
tSDH
SI
100
ns
CS - SCL time
tCSS
/CS1 (CS2 = H)
150
ns
tCSH
/CS1 (CS2 = H)
150
ns
Note TYP. values are reference values when TA = 25°C.
(VDD1 = 2.5 to 3.6 V)
Parameter
Symbol
Condition
MIN.
TYP.Note
MAX.
Unit
Serial clock cycle
tSCYC
SCL
150
ns
SCL high-level pulse width
tSHW
SCL
60
ns
SCL low-level pulse width
tSLW
SCL
60
ns
Address hold time
tSAH
RS
90
ns
Address setup time
tSAS
RS
90
ns
Data setup time
tSDS
SI
60
ns
Data hold time
tSDH
SI
60
ns
CS - SCL time
tCSS
/CS1 (CS2 = H)
90
ns
tCSH
/CS1 (CS2 = H)
90
ns
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% and 80% of VDD1.
Data Sheet S15726EJ2V0DS
117
µPD161401
(4) Common
Parameter
Symbol
Clock input 1
fM
Conditions
TYP.Note
MIN.
OSCIN1. External clock is used in main
MAX.
Unit
85
kHz
40
kHz
duty display mode,1/80 duty
Clock input 2
fS
OSCIN2. External clock is used in sub-duty
display mode, 1/40 duty
Note The TYP. values are reference value at a frame frequency = 70 Hz.
Cautions 1. The rise time and fall time (tr and tf) of an input signal is 15 ns or less.
2. All timing data is specified at 20% and 80% of VDD1.
(a) Timing of display control output
OSC SYNC
(OUT)
tDFR
FR
(VDD1 = 1.8 to 2.5 V)
Parameter
FR delay time
Symbol
tDFR
Conditions
MIN.
FR, CL = 50 pF
TYP.Note
MAX.
Unit
50
200
ns
TYP.Note
MAX.
Unit
20
80
ns
Note The TYP. values are reference values at TA = 25°C.
(VDD1 = 2.5 to 3.6 V)
Parameter
FR delay time
Symbol
tDFR
Conditions
FR, CL = 50 pF
Note The TYP. values are reference values at TA = 25°C.
Caution All timing data is specified at 20% and 80% of VDD1.
118
Data Sheet S15726EJ2V0DS
MIN.
µPD161401
(b) Reset timing
tRW
/DISP
tR
Reset
Internal status
End of reset
(VDD1 = 1.8 to 2.5 V)
Parameter
Symbol
Reset time
tR
Reset L pulse width
tRW
Conditions
/DISP
MIN.
TYP.Note
MAX.
Unit
50
µs
µs
50
Note The TYP. values are reference values at TA = 25°C.
(VDD1 = 2.5 to 3.6 V)
Parameter
Symbol
Reset time
tR
Reset L pulse width
tRW
Conditions
/DISP
MIN.
50
TYP.Note
MAX.
Unit
50
µs
µs
Note The TYP. values are reference values at TA = 25°C.
Caution All timing data is specified at 20% and 80% of VDD1.
Data Sheet S15726EJ2V0DS
119
µPD161401
11. CPU INTERFACE (Reference Example)
The µPD161401 can be connected to both an i80 system CPU and a M68 system CPU. In addition, the number of
signal lines can be reduced by using the serial interface.
The display area can be expanded by using two or more µPD161401 chips. In this case, each IC is selected and
accessed by a chip select signal.
(1) M68 series CPU
A0
RS
VDD1
IFM0
A1 to A15
VIMA
Decoder
CPU D0 to D15
IFM1
/CS1
D0 to D15
E
E
R,/W
R,/W
/RES
/DISP
GND
µ PD161401
VCC
VSS
/RES
(2) i80 series CPU
A0
RS
IFM0
A1 to A7
/IORQ
CPU
VDD1
Decoder
/CS1
IFM1
D0 to D15
D0 to D15
/RD
/RD
/WR
/WR
/RES
µ PD161401
VCC
/DISP
GND
VSS
/RES
(3) Serial interface in used
A0
A1 to A7
RS
Decoder
Open
CPU
IFM0
IFM1
/CS1
D0 to D5,
D8 to D15
Port1
SI(D7)
/Port2
SCL(D6)
/RES
/DISP
GND
VSS
/RES
120
VDD1
Data Sheet S15726EJ2V0DS
µPD161401
VCC
µPD161401
[MEMO]
Data Sheet S15726EJ2V0DS
121
µPD161401
[MEMO]
122
Data Sheet S15726EJ2V0DS
µPD161401
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S15726EJ2V0DS
123
µPD161401
• The information in this document is current as of June, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4