DATA SHEET MOS INTEGRATED CIRCUIT µPD31172 TM VRC4172 TM COMPANION CHIP FOR VR4121 DESCRIPTION The µPD31172 (commercial name: VRC4172) is a companion chip designed for NEC’s µPD30121 microprocessor (commercial name: VR4121). The VRC4172 has the following functions available on chip: a USB host controller, an IEEE1284 parallel controller, a 16550 serial controller, a PS/2 controller, general-purpose ports (GPIO), programmable chip select (PCS), and a PWM controller (a duty modulated light pulse generation function for LCD backlighting). The VRC4172 can be directly connected to the VR4121, allowing a reduction in the man-hours required for development of a Windows™ CE system. Detailed function descriptions are provided in the following user’s manual. Be sure to read it before designing. • VRC4172 User’s Manual (U14386E) FEATURES • Directly connectable to VR4121 • On-chip USB host controller • USB ports: 2 • Compliant with the USB OpenHCI specifications, release 1.0 • Communicates with USB device asynchronously with host CPU • Full-speed (12 Mbps) and low-speed (1.5 Mbps) modes supported • System clock: 48 MHz • On-chip PS/2 controller • On-chip IEEE1284 parallel controller • On-chip 16550 serial controller • General-purpose ports (GPIO): 24 • On-chip PWM controller • Duty modulated light pulse generation function for LCD backlighting • Internal maximum operating frequency: 48 MHz • Power supply voltage: VDD = 3.3 V ± 0.3 V • Package: 208-pin plastic FBGA APPLICATIONS • Battery-driven portable information devices • Peripheral devices for PCs, etc. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14388EJ2V0DS00 (2nd edition) Date Published May 2000 N CP(K) Printed in Japan The mark shows major revised points. µPD31172 ORDERING INFORMATION Part Number Package µPD31172F1-48-FN Internal Maximum Operating Frequency 208-pin plastic FBGA (15 × 15) 48 MHz PIN CONFIGURATION • 208-pin plastic FBGA (15 × 15) µPD31172F1-48-FN Bottom View Top View 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U T R P N M L K J H G F E D C B A A B C D E F G H J K L M N P R T U Index mark 2 Data Sheet U14388EJ2V0DS00 µPD31172 Symbol Name Symbol Name Symbol Name Symbol Name A1 GND C2 GND E3 CD3 J15 GND A2 AUTOFEED# C3 STROBE# E4 CD7 J16 UUCAS# A3 PE C4 ACK# E14 GND J17 ROMCS3# A4 INIT# C5 ERROR# E15 PPON1 K1 GPIO14 A5 IOCHRDY C6 AD6 E16 OCI2 K2 GPIO10 A6 AD19 C7 AD7 E17 USBRST# K3 GPIO7 A7 AD20 C8 AD8 F1 GPIO22 K4 GPIO3 A8 AD21 C9 VDD F2 GPIO18 K14 EXCS3# A9 AD22 C10 AD9 F3 CD2 K15 EXCS0# A10 AD23 C11 AD10 F4 CD6 K16 SCAS# A11 AD24 C12 AD11 F14 SCLK K17 SRAS# Note 1 C13 LCDBAK F15 PPON2 L1 GPIO13 Note 1 Reserved A12 A13 Reserved C14 SMI# F16 LCAS# L2 GPIO9 A14 DP1 C15 USBINT# F17 MRAS0# L3 GPIO6 A15 DN2 C16 GND G1 GPIO21 L4 GPIO2 A16 DP2 C17 RD# G2 GPIO17 L14 EXCS4# A17 LCDRDY D1 GND G3 CD1 L15 EXCS1# B1 PS2CLK D2 SELECTIN# G4 CD5 L16 Reserved (0) B2 VDD D3 DIR1284 G14 Reserved Note 1 L17 GND Note 1 B3 VDD D4 PS2INT G15 Reserved M1 GPIO12 B4 BUSY D5 SELECT G16 UCAS# M2 GPIO8 B5 GND D6 AD0 G17 MRAS1# M3 GPIO5 B6 AD12 D7 AD1 H1 GPIO20 M4 GPIO1 B7 AD13 D8 AD2 H2 GPIO16 M14 EXCS5# B8 AD14 D9 GND H3 CD0 M15 EXCS2# B9 AD15 D10 AD3 H4 CD4 M16 Reserved (0) B10 AD16 D11 AD4 H14 Reserved M17 CKE B11 AD17 D12 AD5 H15 ARBCLKSEL N1 RESET B12 AD18 D13 VDD H16 ULCAS# N2 BUSRQ0# B13 GND D14 IEN H17 ROMCS2# N3 GPIO4 B14 DN1 D15 WAKE J1 GPIO15 N4 GPIO0 B15 VDD D16 OCI1 J2 GPIO11 N14 GND B16 GND D17 LCDCS# J3 VDD N15 DSR# B17 WR# E1 GPIO23 J4 GND N16 RXD C1 PS2DATA E2 GPIO19 J14 VDD N17 RI# Note 1 Note 2 Note 2 Notes 1. Either leave pins A12, A13, G14, G15, and H14 open, or input 0 V. 2. Always input 0 V to pins L16 and M16. Remark # indicates active low. Data Sheet U14388EJ2V0DS00 3 µPD31172 Symbol Symbol Name Symbol Name Symbol Name P1 HOLDRQ# R1 HOLDAK# T1 BUSCLK U1 IOCS16# P2 BUSAK0# R2 GND T2 GND U2 IRQ P3 BUSRQ1# R3 BUSAK1# T3 VDD U3 IOR# P4 GND R4 DATA23 T4 VDD U4 IOW# P5 DATA31 R5 DATA22 T5 DATA15 U5 GND P6 DATA30 R6 VDD T6 DATA14 U6 DATA7 P7 DATA29 R7 DATA21 T7 GND U7 DATA6 P8 DATA28 R8 DATA20 T8 DATA13 U8 DATA5 P9 VDD R9 GND T9 DATA12 U9 DATA4 P10 DATA27 R10 DATA19 T10 DATA11 U10 DATA3 P11 DATA26 R11 DATA18 T11 DATA10 U11 DATA2 P12 DATA25 R12 VDD T12 GND U12 DATA1 P13 DATA24 R13 DATA17 T13 DATA9 U13 DATA0 P14 CLKOUT48M R14 DATA16 T14 DATA8 U14 GND P15 DCD# R15 CTS# T15 VDD U15 DTR# P16 TXD R16 GND T16 VDD U16 RTS# P17 INTRP R17 XOUT48M T17 XIN48M U17 GND Remark 4 Name # indicates active low. Data Sheet U14388EJ2V0DS00 µPD31172 PIN IDENTIFICATION ACK#: Acknowledge MRAS (0:1)#: DRAM Row Address Strobe AD (0:24): Address Bus OCI (1:2): Over Current Interrupt ARBCLKSEL: Arbitration Clock Select PE: Paper End AUTOFEED#: Autofeed PPON (1:2): Port Power ON BUSAK (0:1)#: Bus Acknowledge PS2CLK: PS2 Clock BUSCLK: System Bus Clock PS2DATA: PS2 Data BUSRQ (0:1)#: Bus Request PS2INT: PS2 Interrupt BUSY: Busy RD#: Read CD (0:7): Centronics Data RESET: Reset CKE: Clock Enable RI#: Ring Indicator CLKOUT48M: Clock Out of 48 MHz ROMCS (2:3)#: ROM Chip Select CTS#: Clear to Send RTS#: Request to Send DATA (0:31): Data Bus RXD: Receive Data DCD#: Data Carrier Detect SCAS#: Column Address Strobe for SCLK: SDRAM Clock DIR1284: Direction of 1284 DN (1:2): USB D− SDRAM DP (1:2): USB D+ SELECT: Select DSR#: Data Set Ready SELECTIN#: Select in DTR#: Data Terminal Ready SMI#: USB System Interrupt ERROR#: Error SRAS#: Row Address Strobe for EXCS (0:5)#: External CS GND: Ground GPIO (0:23): General Purpose I/O TXD: Transmit Data HOLDAK#: Hold Acknowledge UCAS#: Upper Column Address Strobe HOLDRQ#: Hold Request ULCAS#: Lower Byte of Upper Column IEN: USB Input Enable SDRAM STROBE#: Strobe Address Strobe INIT# Initialize USBINT#: USB Interrupt INTRP: Interrupt USBRST#: USB Reset IOCHRDY: I/O Channel Ready UUCAS#: IOCS16#: IO Chip Select 16 Upper Byte of Upper Column Address Strobe IOR#: I/O Read VDD: Power Supply Voltage IOW#: I/O Write WAKE: Wake Up Interrupt IRQ: I/O Request WR#: Write LCAS#: Lower Column Address Strobe XIN48M: Clock In of 48 MHz LCDBAK: LCD Back Light XOUT48M: Clock Out of 48 MHz LCDCS#: LCD Chip Select LCDRDY: LCD Ready Remark # indicates active low. Data Sheet U14388EJ2V0DS00 5 µPD31172 INTERNAL BLOCK DIAGRAM AND EXTERNAL BLOCK CONNECTION EXAMPLE 48 MHz DRAM controller PCI bus controller SDRAM Internal PCI bus VRC4172 USB host controller (OpenHCI 1.0) IEEE1284 parallel controller 16550 serial controller System bus VR4121 2 ports .. .. .. .. RS-232-C driver PS/2 controller PWM controller LCD backlight PCS (6 bits) GPIO (24 bits) PMU ICU 6 Data Sheet U14388EJ2V0DS00 µPD31172 CONTENTS 1. PIN FUNCTIONS................................................................................................................................... 8 1.1 Pin Function List ....................................................................................................................................... 8 1.2 Special Status Pins ................................................................................................................................. 11 1.3 External Processing of Pins and Drive Capacity.................................................................................. 13 1.4 Recommended Connection of Unused Pins......................................................................................... 15 2. ELECTRICAL SPECIFICATIONS...................................................................................................... 16 3. PACKAGE DRAWING ....................................................................................................................... 38 4. RECOMMENDED SOLDERING CONDITIONS................................................................................ 39 Data Sheet U14388EJ2V0DS00 7 µPD31172 1. PIN FUNCTIONS 1.1 Pin Function List (1) System bus interface signals Signal Name I/O Function SCLK I/O This is the SDRAM operating clock. AD (0:24) I/O These form a 25-bit address bus. I/O These form a 32-bit data bus. DATA (0:31) LCDCS# RD# Input I/O This is the LCD chip select signal. This signal becomes active when the VR4121 accesses the LCD using the AD or data bus. • Output: This signal becomes active when the VRC4172 accesses SDRAM. • Input: WR# I/O • Output: This signal becomes active when the VRC4172 writes data to SDRAM. • Input: LCDRDY This signal becomes active when the VR4121 writes data to the VRC4172’s PCI host bridge. This is the LCD ready signal. This signal becomes active when a state is entered whereby the VRC4172 can acknowledge an access to the LCD area from the VR4121. ROMCS (2:3)# I/O This is an SDRAM chip select signal. CKE I/O This is the SDRAM clock enable signal. UUCAS# I/O This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (24:31) pins. ULCAS# I/O This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (16:23) pins. MRAS (0:1)# I/O This is an SDRAM chip select signal. UCAS# I/O This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (8:15) pins. LCAS# I/O This is an SDRAM DQM signal. This signal controls the I/O buffers for the DATA (0:7) pins. IOR# Input This is the system bus I/O read signal. This signal becomes active when any resource except the USB inside the VRC4172 is accessed. IOW# Input This is the system bus I/O write signal. This signal becomes active when any resource except the USB inside the VRC4172 is accessed. Input This is the system bus reset signal. RESET 8 Output This signal becomes active when the VR4121 reads data from the VRC4172’s PCI host bridge. IOCS16# Output This is the dynamic bus-sizing request signal. IOCHRDY Output This is the system bus ready signal. HOLDRQ# Output This is the system bus access right request signal. HOLDAK# Input This is the system bus access enable signal. SRAS# I/O This is the SDRAM RAS signal. SCAS# I/O This is the SDRAM CAS signal. BUSRQ (0:1)# Input This is a signal input from the external bus master requesting access to the system bus. BUSAK (0:1)# Output This is a signal output to the external bus master permitting access to the system bus. INTRP Output This is an interrupt request signal from the 16550 serial controller or the IEEE1284 parallel controller. IRQ Output This is an interrupt request signal from the general-purpose ports (GPIO (0:23)) or the IEEE1284 parallel controller. USBINT# Output This is an interrupt request signal from the USB host controller. PS2INT Output This is an interrupt request signal from the PS/2 controller. BUSCLK Input This is the system bus clock. ARBCLKSEL Input This is a clock select signal for arbitrating the system bus (controls the HOLDRQ# signal) (1: Internal clock used, 0: BUSCLK used) Data Sheet U14388EJ2V0DS00 µPD31172 (2) USB Interface Signals Signal Name I/O Function DP (1:2) I/O This is the positive data signal. DN (1:2) I/O This is the negative data signal. PPON (1:2) Output This is the USB route-hub-port power supply control signal. OCI (1:2) Input This is the USB route-hub-port over-current status signal. Make this signal active when the current flowing through the Vbus line of the USB exceeds the reference value. IEN Input This is the USB buffer input enable signal. Make this signal active when the input signal to the USB port is validated. WAKE Output This is a wakeup interrupt request signal. SMI# Output This is a system interrupt request signal. Input This is the reset signal for the USB clock. USBRST# (3) IEEE1284 Interface Signals Signal Name I/O Function CD (0:7) I/O These are data signals STROBE# I/O This is the data strobe signal. ACK# I/O This is the acknowledge signal. BUSY I/O This is the busy signal. PE I/O This is the paper-end signal. SELECT I/O This is the select signal. AUTOFEED# I/O This is the autofeed signal. SLECTIN# I/O This is the select input signal. ERROR# I/O This is the fault signal. INIT# I/O This is the initialization signal. DIR1284 Output This signal outputs the transfer direction status. (4) RS-232-C Interface Signals Signal Name I/O Function RXD Input This is the receive data signal. CTS# Input This is the transmit enable signal. DSR# Input This is the data set ready signal. TXD Output This is the transmit data signal. RTS# Output This is the transmit request signal. DTR# Output This is the terminal equipment ready signal. DCD# Input This is the carrier detection signal. RI# Input This is the call display signal. Data Sheet U14388EJ2V0DS00 9 µPD31172 (5) PS/2 Interface Signals Signal Name I/O Function PS2CLK I/O This is the PS/2 clock signal. PS2DATA I/O This is the PS/2 data signal. (6) General-Purpose Port Signals Signal Name GPIO (0:23) I/O I/O Function These are general-purpose I/O signals. (7) General-Purpose Chip Select Signals Signal Name EXCS (0:5)# I/O Output Function These are general-purpose chip select signals. (8) LCD Interface Signals Signal Name LCDBAK I/O Output Function These are signals for controlling the LCD backlighting. (9) Clock Signals Signal Name XIN48M I/O Input Function This is the 48 MHz oscillator input pin. Connect to one side of a crystal resonator. XOUT48M Output This is the 48 MHz oscillator output pin. Connect to the other side of the crystal resonator. CLKOUT48M Output This is the 48 MHz clock output for the FIR of the VR4121. 10 Data Sheet U14388EJ2V0DS00 µPD31172 1.2 Special Status Pins (1/2) Signal Name After Reset When HOLDAK# = 1 SCLK Hi-Z Hi-Z AD (0:24) Hi-Z Hi-Z DATA (0:31) Hi-Z Hi-Z − − RD# Hi-Z Hi-Z WR# Hi-Z Hi-Z LCDRDY Hi-Z Hi-Z ROMCS (2:3)# Hi-Z Hi-Z CKE Hi-Z Hi-Z UUCAS# Hi-Z Hi-Z ULCAS# Hi-Z Hi-Z MRAS (0:1)# Hi-Z Hi-Z LCDCS# UCAS# Hi-Z Hi-Z LCAS# Hi-Z Hi-Z IOR# − − IOW# − − RESET − − IOCS16# Hi-Z Hi-Z IOCHRDY Hi-Z Hi-Z HOLDRQ# 1 1 − − SRAS# Hi-Z Hi-Z SCAS# Hi-Z Hi-Z BUSRQ (0:1)# − − BUSAK (0:1)# 1 Normal operation INTRP 0 Normal operation IRQ 0 Normal operation USBINT# 1 Normal operation PS2INT 0 Normal operation BUSCLK − − ARBCLKSEL − − DP (1:2) 1 Normal operation DN (1:2) 0 Normal operation PPON (1:2) 0 Normal operation OCI (1:2) − − IEN − − WAKE 0 Normal operation HOLDAK# Remark 0: Low level, 1: High level, Hi-Z: High impedance Data Sheet U14388EJ2V0DS00 11 µPD31172 (2/2) Signal Name After Reset When HOLDAK# = 1 SMI# 1 Normal operation USBRST# − − CD (0:7) Hi-Z Normal operation STROBE# Hi-Z Normal operation ACK# Hi-Z Normal operation BUSY Hi-Z Normal operation PE Hi-Z Normal operation SELECT Hi-Z Normal operation AUTOFEED# Hi-Z Normal operation SELECTIN# Hi-Z Normal operation ERROR# Hi-Z Normal operation INIT# Hi-Z Normal operation DIR1284 0 Normal operation RXD − − CTS# − − DSR# − − TXD 1 Normal operation RTS# 1 Normal operation DTR# 1 Normal operation DCD# − − RI# − − PS2CLK 0 Normal operation PS2DATA Hi-Z Normal operation GPIO (0:23) Hi-Z Normal operation EXCS (0:5)# 1 Normal operation LCDBAK 0 Normal operation CLKOUT48M 1 Normal operation Remark 0: Low level, 1: High level, Hi-Z: High impedance 12 Data Sheet U14388EJ2V0DS00 µPD31172 1.3 External Processing of Pins and Drive Capacity When using the VRC4172, process the pins externally, as shown in the table below. (1/2) Signal Name External Processing Drive Capacity Tolerance SCLK − 80 pF 3V AD (0:24) − 80 pF 3V DATA (0:31) − 80 pF 3V LCDCS# − 3V Note 1 80 pF 3V Note 1 80 pF 3V Pull up Pull up RD# Pull up WR# LCDRDY Pull up 40 pF 3V ROMCS (2:3)# Pull up 80 pF 3V CKE Pull down 80 pF 3V UUCAS# Pull up Note 1 80 pF 3V ULCAS# Pull up Note 1 80 pF 3V Note 1 80 pF 3V Note 1 80 pF 3V Note 1 80 pF 3V Note 1 − 3V Note 1 − 3V MRAS (0:1)# Pull up Pull up UCAS# Pull up LCAS# Pull up IOR# Pull up IOW# − − 3V IOCS16# Pull up 40 pF 3V IOCHRDY Pull up 40 pF 3V HOLDRQ# − 40 pF 3V HOLDAK# Pull up RESET − 3V Note 1 80 pF 3V Note 1 80 pF 3V Pull up SRAS# Pull up SCAS# BUSRQ (0:1)# − − 3V BUSAK (0:1)# − 40 pF 3V INTRP − 40 pF 3V IRQ − 40 pF 3V USBINT# − 40 pF 3V PS2INT − 40 pF 3V BUSCLK − − 3V ARBCLKSEL − − 3V DP (1:2) − Note 2 5V DN (1:2) − Note 2 5V Notes 1. The same specification has been made for these pins in the VR4121. If these pins have been processed in the VR4121, there is no need to perform this processing in the VRC4172. 2. In full-speed mode: 50 pF, In low-speed mode: 350 pF Remark There is no need to perform external processing if no particular external processing has been specified (−). Data Sheet U14388EJ2V0DS00 13 µPD31172 (2/2) Signal Name External Processing Drive Capacity Tolerance PPON (1:2) − 40 pF 3V OCI (1:2) − − 3V IEN − − 3V WAKE − 40 pF 3V SMI# − 40 pF 3V USBRST# − − 3V CD (0:7) − 40 pF 3V STROBE# Pull up 40 pF 3V ACK# Pull up 40 pF 3V BUSY Pull down 40 pF 3V PE Pull down 40 pF 3V SELECT Pull down 40 pF 3V AUTOFEED# Pull up 40 pF 3V SELECTIN# Pull up 40 pF 3V ERROR# Pull up 40 pF 3V INIT# Pull up 40 pF 3V DIR1284 − 40 pF 3V RXD − − 3V CTS# − − 3V DSR# − − 3V TXD − 40 pF 3V RTS# − 40 pF 3V DTR# − 40 pF 3V DCD# − − 3V RI# − − 3V PS2CLK Pull up 40 pF 5V PS2DATA Pull up 40 pF 5V GPIO (0:23) Pull up/pull down 40 pF 3V EXCS (0:5)# − 40 pF 3V LCDBAK − 40 pF 3V CLKOUT48M − 40 pF 3V Remark There is no need to perform external processing if no particular external processing has been specified (−). 14 Data Sheet U14388EJ2V0DS00 µPD31172 1.4 Recommended Connection of Unused Pins Connect unused pins as shown in the table below. Signal Name SCLK Recommended Connection Pull up Signal Name PPON (1:2) Recommended Connection Leave open AD (0:24) − OCI (1:2) Pull down DATA (0:31) − IEN Pull down LCDCS# Pull up WAKE Leave open RD# Pull up SMI# Leave open WR# Pull up USBRST# Pull down CD (0:7) Pull down LCDRDY ROMCS (2:3)# Leave open STROBE# Pull up Pull down ACK# Pull up UUCAS# Pull up BUSY Pull down ULCAS# Pull up PE Pull down MRAS (0:1)# Pull up SELECT Pull down UCAS# Pull up AUTOFEED# Pull up LCAS# Pull up SELECTIN# Pull up CKE Pull up IOR# − ERROR# Pull up IOW# − INIT# Pull up RESET − DIR1284 IOCS16# − RXD Pull down IOCHRDY − CTS# Pull up HOLDRQ# Leave open DSR# Pull up HOLDAK# Pull up TXD Leave open SRAS# Pull up RTS# Leave open SCAS# Pull up DTR# Leave open BUSRQ (0:1)# Pull up DCD# Pull up BUSAK (0:1)# Leave open RI# Pull up INTRP Leave open PS2CLK Pull up IRQ Leave open PS2DATA Pull up USBINT# Leave open GPIO (0:23) Pull down PS2INT Leave open EXCS (0:5)# Leave open BUSCLK Pull up LCDBAK Leave open ARBCLKSEL Pull down XIN48M Pull up DP (1:2) Pull down XOUT48M Leave open DN (1:2) Pull down CLKOUT48M Leave open Leave open Remark Pins with no particular specification (−) cannot be left unconnected. Data Sheet U14388EJ2V0DS00 15 µPD31172 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C) Parameter Power supply voltage Symbol Conditions Ratings Unit −0.5 to +4.6 V VI < VDD + 0.5 V −0.5 to +4.6 V VI < VDD + 3.0 V, DP (2:1), DN (2:1), PS2CLK, PS2DATA pins −0.5 to +6.6 V VO < VDD + 0.5 V −0.5 to +4.6 V VO < VDD + 3.0 V, DP (2:1), DN (2:1), PS2CLK, PS2DATA pins −0.5 to +6.6 V VDD Input voltage VI Output voltage VO Operating ambient temperature TA −40 to +85 °C Storage temperature Tstg −65 to +150 °C Cautions 1. Do not simultaneously short multiple outputs. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions displayed in DC Characteristics and AC Characteristics in this section indicate the ranges in which normal operation and product quality can be guaranteed. Capacitance (TA = 25°°C, VDD = 0 V) Parameter Input capacitance Symbol CI Output capacitance Note Output capacitance CO1 Conditions f = 1 MHz Unmeasured pins returned to 0 V. CO2 Note Applicable to DP (2:1), DN (2:1), PS2CLK, and PS2DATA pins. 16 Data Sheet U14388EJ2V0DS00 MIN. MAX. Unit 8 pF 8 pF 12 pF µPD31172 DC Characteristics (TA = −40 to +85°°C, VDD = 3.3 ± 0.3 V) (1) Pins except for DP (2:1), DN (2:1) Parameter Symbol Conditions Output voltage, high VOH1 IOH = −6 mA Output voltage, low VOL1 IOL = 6 mA VOH2 IOH = −9 mA VOL2 IOL = 9 mA VOH3 IOH = −3 mA Output voltage, low VOL3 IOL = 3 mA Input voltage, high VIH1 Input voltage, high Output voltage, high Note 1 Note 1 Output voltage, low Output voltage, high Note 2 Note 2 MIN. MAX. 2.4 Unit V 0.4 2.4 V V 0.4 2.4 V V 0.4 V 2.0 VDD V VIH2 2.0 5.5 V Input voltage, low VIL 0 0.8 V Power supply current IDD 300 mA Input leakage current ILI VI = VDD, GND ±10 µA Input leakage current, high ILIH VI = VDD, ARBCLKSEL pin 141 µA Output leakage current ILO VO = VDD, GND ±10 µA Note 2 Notes 1. Applicable to SCLK, AD (24:0), DATA (31:0), RD#, WR#, ROMCS (3:2)#, CKE#, UUCAS#, ULCAS#, MRAS (1:0)#, UCAS#, LCAS#, SRAS#, and SCAS# pins. 2. Applicable to PS2CLK and PS2DATA pins. (2) DP (2:1), DN (2:1) pins Parameter Symbol Conditions Output voltage, high VOH RL = 15 kΩ (connected to GND) Output voltage, low VOL RL = 1.5 kΩ (connected to VDD) Differential input sensitivity VDI Differential common mode range VCM Input voltage, high VIH_USB Input voltage, low VIL_USB MIN. MAX. Unit 2.8 3.6 V 0.3 V 0.2 VDI < 200 mV 0.8 V 2.5 2.0 V V 0.8 V Remark Refer to the USB specification, revision 1.0, for details. Data Sheet U14388EJ2V0DS00 17 µPD31172 AC Characteristics (TA = −40 to +85°°C, VDD = 3.3 ± 0.3 V) AC test input waveform VDD All output pins 1.4 V Test points 1.4 V 1.4 V Test points 1.4 V 0V AC test output test points VDD All output pins 0V 18 Data Sheet U14388EJ2V0DS00 µPD31172 Load Conditions (a) SCLK, AD (0:24), DATA (0:31), RD#, WR#, ROMCS (2:3)#, CLK#, UUCAS#, ULCAS#, ULCAS#, MRAS (0:1)#, UCAS#, LCAS#, SRAS#, SCAS# SCLK, AD (0:24), DATA (0:31), RD#, WR#, ROMCS (2:3)#, CLK#, UUCAS#, ULCAS#, MRAS (0:1)#, UCAS#, LCAS#, SRAS#, SCAS# DUT CL = 80 pF (b) DP (1:2), DN (1:2) DP (1:2), DN (1:2) DUT In full-speed mode: CL = 50 pF In low-speed mode: CL = 350 pF (c) Other output pins Output pins (except for (a) and (b) above) DUT CL = 40 pF Data Sheet U14388EJ2V0DS00 19 µPD31172 (1) Clock parameters Parameter Symbol XIN48M clock frequency Conditions MIN. fCLK TYP. MAX. Unit 48.0 50.0 MHz MIN. MAX. Unit (2) Reset parameters Parameter Symbol RESET signal high-level width USBRST# signal low-level width Conditions tRST 30 ns tUSBRST 30 ns (3) SDRAM interface parameters Parameter Symbol Conditions MIN. MAX. Unit SCLK cycle tSCLK 20.8 ns SCLK high-level width tSCLKH 8 ns SCLK low-level width tSCLKL 8 ns Data output hold time tSDM 2 ns Data output delay time tSDO Data input setup time tSDS 9.5 ns Data input hold time tSDH 2 ns 15 tSCLKH tSCLKL tSCLK SCLK (I/O) AD (24:0), WR#, ROMCS (3:2)#, UUCAS#, ULCAS#, UCAS#, LCAS#, MRAS (1:0)#, SRAS#, SCAS#, CKE (I/O) DATA (31:0) (output) DATA (31:0) (input) 20 tSDM tSDO tSDS Hi-Z tSDH Hi-Z Data Sheet U14388EJ2V0DS00 ns µPD31172 (4) System bus interface parameters (a) Access to I/O area Parameter Symbol Conditions MIN. MAX. Unit Command signal low-level width tCLCH 130 ns Address setup time (to command signal) tAVCL 10 ns Address hold time (from command signal) tCHAV 10 ns IOCS16# valid delay time tAVCV 12 ns IOCS16# floating delay time tAVCZ 10 ns 25 ns 30 ns Data output hold time tDM Data output delay time tDO Data input setup time tDS1 10 ns Data input setup time tDS2 10 ns Data input hold time tDH 10 ns Note 6 Note During 16550-compatible serial communication AD (24:0) (input) tAVCL tCHAV tCLCH IOR#/IOW# (input) tAVCV tAVCZ IOCS16# (output) tDS1 tDH DATA (31:0) (input) tDS2 tDH DATA (31:0) (input)Note tDO tDM DATA (31:0) (output) Note During 16550-compatible serial communication Remark The broken lines indicate high impedance Data Sheet U14388EJ2V0DS00 21 µPD31172 (b) Access to LCD area Parameter Symbol Conditions MIN. MAX. Unit Command signal low-level width tCLCH 90 ns Address setup time (to command signal) tAVCL 10 ns Address hold time (from command signal) tCHAV 10 ns LCDRDY valid delay time tAVRH 15 ns LCDRDY set delay time tCLRL 12 ns LCDRDY floating delay time tAVRZ 10 ns 25 ns 30 ns Data output hold time tDM 6 Data output delay time tDO Data output valid time tDV 10 ns Data input setup time tDS 10 ns Data input hold time tDH 10 ns (i) When accessing the internal PCI bus AD (24:0) (input) LCDCS# (input) tAVCL tCLCH tCHAV RD#/WR# (input) tAVRH LCDRDY (output) tCLRL tAVRZ tDS tDH DATA (31:0) (input) tDV DATA (31:0) (output) Remark The broken lines indicate high impedance 22 Data Sheet U14388EJ2V0DS00 tDM µPD31172 (ii) When accessing the configuration register of the PCI host controller AD (24:0) (input) LCDCS# (input) tAVCL tCHAV tCLCH RD#/WR# (input) LCDRDY (output) Hi-Z tDS tDH DATA (31:0) (input) DATA (31:0) Hi-Z (output) tDO Data Sheet U14388EJ2V0DS00 tDM Hi-Z 23 µPD31172 (5) GPIO parameters Parameter Symbol Conditions MIN. MAX. Unit GPIO (23:0) output delay time tGO 30 ns GPIO (23:0) interrupt request generation time tGI 30 ns GPIO (23:0) interrupt request clear time tGIC 35 ns (a) In output mode IOW# (input) tGO GPIO (23:0) (output) (b) In input mode GPIO (23:0) (input) tGI tGI IRQ (output) (level trigger interrupt) tGIC IRQ (output) (edge trigger interrupt) IOW# (input) (edge interrupt request clear) 24 Data Sheet U14388EJ2V0DS00 µPD31172 (6) PCS (Programmable Chip Select) parameters Parameter EXCS output delay time Symbol Conditions MIN. tEO MAX. Unit 30 ns MAX. Unit 8 tSCLK ns AD (24:0) (I/O) tEO tEO EXCS (5:0)# (output) (7) PWM (Pulse Width Modulation) parameters Parameter LCDBAK output delay time Symbol Conditions MIN. tLO IOW# (input) tLO LCDBAK (output)Note Note High level: enable, Low level: disable Data Sheet U14388EJ2V0DS00 25 µPD31172 (8) PS/2 parameters Parameter Symbol Conditions MIN. MAX. Unit PS2CLK clock high-level width tPSCH 3T ns PS2CLK clock low-level width tPSCL 3T ns PS2CLK output delay time tPSO T + 20 ns Transmission start time tPSGO 20 ns Transmit data output delay time tPSDO 3 T + 20 ns Receive data setup time tPSDS 0 ns Receive data hold time tPSDH 4T ns Receive disable setup time tPSN 3T Remark T = 125 ns (cycle of internal clock for controlling PS/2) (a) Transmission PS/2 interface disabled PS/2 interface enabled IOW# (input) tPSO Transmit data setting tPSO Input Output tPSCL tPSCH PS2CLK (I/O) Input tPSDO tPSGO PS2DATA (I/O) Start bit Input DATA0 DATA (1:7), parity bit Output Stop bit Input (b) Reception tPSCL tPSN PS2CLK (I/O) Input tPSDS PS2DATA (I/O) 26 Output tPSDH Start bit DATA0 DATA (1:7), parity bit Data Sheet U14388EJ2V0DS00 Stop bit ns µPD31172 (9) 16550-compatible serial interface parameters Parameter Symbol Transmit clock division ratio Transmit clock rising edge delay time (from CLK Conditions MIN. N Note 1 Transmit clock falling edge delay time (from CLK TYP. MAX. Unit 2 −1 16 1 ) tBHD 10 ns Note 1 tBLD 15 ns ) Transmit clock pulse low-level width tLW Transmit clock pulse high-level width tHW N=1 0.5CLKC ns N=2 1CLKC ns N=3 2CLKC ns N>3 2CLKC ns N=1 0.5CLKC ns N=2 1CLKC ns N=3 1CLKC ns N>3 (N − 2) CLKC ns Interrupt cancellation time (from IOR# ↑, when reading LSR register) tRINT1 40 ns Interrupt cancellation time (from IOR# ↓, when reading RBR register) tRINT2 30 ns Sample clock delay time (from RCLK) tSCD 10 ns Interrupt generation time (from valid data reception, reception error) tSINT 1 RCLKC Note 2 + 20 ns Interrupt cancellation time (from IOW# ↓, when writing to THR register) tHR 30 ns Interrupt cancellation time (from IOR# ↑, when reading IIR register) tIR 40 ns Transmission start time tIRS 8 BAUC 24 BAUC + 20 ns Interrupt generation time (from IOW# ↑, when writing to THR register) tSI 16 BAUC 24 BAUC + 20 ns Interrupt generation time (from stop bit) tSTI 8 BAUC + 20 ns RTS#, DTR delay time (from IOW# ↑, when writing to MCR register) tMDO 30 ns Interrupt cancellation time (from IOR# ↓, when reading MSR register) tRIM 30 ns Interrupt cancellation time (from RI# ↑, CTS#, DSR#, DCD#) tSIM 30 ns Notes 1. CLK is the internal system clock of the 16550 serial controller, and has a frequency of 1.8462 MHz. 2. When bit 0 of the FCR register is 1, tSINT = 3 RCLKC + 20 (ns). During a timeout interrupt, tSINT = 8 RCLKC + 20 (ns). Remark CLKC: CLK (internal system clock of 16550 serial controller) cycle RCLKC: RCLK (on-chip serial controller receive clock) cycle BAUC: BAUDOUTB (on-chip serial controller transmit clock) cycle RCLKC = BAUC in this case. Data Sheet U14388EJ2V0DS00 27 µPD31172 (a) Serial BAUDOUT timing CLK (internal, 1.8462 MHz) tBLD tHW tBHD BAUDOUTB (1 cycle) (internal) tBLD tLW tBHD tHW BAUDOUTB (2 cycles) (internal) tBLD tBHD tBLD tBHD tLW tHW BAUDOUTB (3 cycles) (internal) tLW tHW BAUDOUTB (N cycles, N > 3) (internal) tLW (b) Serial receive timing RCLK (BAUDOUTB) tSCD 8 RCLKC 16 RCLKC Internal sample clock RXD (input) Start bit DATA (5:8) Parity bit Stop bit Internal sample clock tSINT INTRP (output) (receive data existence interruptNote 1) INTRP (output) (receive status interruptNote 2) IOR# (input) (reading RBR register) tRINT2 tRINT1 IOR# (input) (reading LSR register) Notes 1. Dependant on the existence of receive data. At this time, bit 0 of the IER register is 1, and bits 3 to 1 of the IIR register are 0, 1, 0, respectively. 2. Dependant on the receive line status. At this time, bit 2 of the IER register is 1, and bits 3 to 1 of the IIR register are 0, 1, 1, respectively. 28 Data Sheet U14388EJ2V0DS00 µPD31172 (c) Serial transmission timing RXD (input) INTRPNote (output) Start bit DATA (5:8) Parity bit Stop bit Start bit tIRS tSTI tHR tSI IOW# (input) (writing to THR register) tHR tIR IOR# (input) (reading IIR register) Note Dependant on whether the transmit buffer is empty. At this time, bit 1 of the IER register is 1, and bits 3 to 1 of the IIR register are 0, 0, 1, respectively. (d) Serial modem control timing IOW# (input) (writing to MCR register) tMDO tMDO RTS#, DTR# (output) CTS#, DSR#, DCD# (input) tSIM tSIM INTRPNote (output) IOR# (input) (reading MSR register) tRIM tRIM tSIM RI# (input) Note Dependant on the modem status. At this time, bit 3 of the IER register is 1, and bits 3 to 1 of the IIR register are 0, 0, 0, respectively. Data Sheet U14388EJ2V0DS00 29 µPD31172 (10) IEEE1284-compliant parallel interface parameters (a) Parallel port control signal output Parameter Symbol MAX. Unit tCLK1284 24 MHz CD (7:0) output delay time (writing to DATA register) t1 30 ns INIT#, STROBE#, AUTOFEED#, SELECTIN# setup time t2 4T ns DIR1284 setup time t3 5T ns MAX. Unit Parallel interface internal clock frequency Conditions MIN. Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) IOW# (input) t1 CD (7:0) (I/O) t2 INIT#, STROBE#, AUTOFEED#, SELECTIN# (I/O) t3 DIR1284 (output) (b) Compatible mode using FIFO Parameter Symbol CD (7:0) setup time Conditions MIN. t4 24 T ns STROBE# pulse width t5 24 T ns BUSY response time t6 Note 1 12 T (from STROBE# ↑) t7 24 T ns Note 2 (from BUSY ↓) t8 0 ns t9 24 T ns CD (7:0) hold time CD (7:0) hold time Note 3 STROBE# setup time Notes 1. When there is no reaction from BUSY at a low level, STROBE# continues to output a low level. 2. Data is held while BUSY is high level. 3. When the FIFO buffer is empty, this signal is held at a high level. Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) CD (7:0) (output) Valid data t4 t5 t7 STROBE# (output) t8 t6 BUSY (input) 30 ns Note 2 Data Sheet U14388EJ2V0DS00 t9 µPD31172 (c) During ECP normal-direction transfer Parameter Symbol Conditions MIN. MAX. Unit 2T ns CD (7:0), AUTOFEED# setup time t10 1T BUSY response time (from STROBE# ↓) t11 0 STROBE# response time t12 2T BUSY response time (from STROBE# ↑) t13 0 CD (7:0) hold time t14 2T 4T ns t15 3T 6T ns MIN. MAX. Unit Note STROBE# setup time ns 4T ns ns Note When the FIFO buffer is empty, this signal is held at a high level. Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) CD (7:0) AUTOFEED# (output) Valid data t10 STROBE# (output) t11 t12 t13 t14 t15 BUSY (input) (d) During ECP reverse-direction transfer Parameter Symbol CD (7:0), BUSY setup time Conditions t16 0 ns t17 3T ns ACK# response time t18 0 ns AUTOFEED# response time (from ACK# ↑) t19 CD (7:0) hold time t20 0 ns ACK# setup time t21 0 ns AUTOFEED# response time Note (from ACK# ↓) 5T ns Note When the FIFO buffer is full, this signal is held at a low level. Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) CD (7:0) BUSY (input) Valid data t16 ACK# (input) t17 t18 t19 t20 t21 AUTOFEED# (output) Data Sheet U14388EJ2V0DS00 31 µPD31172 (e) Write timing in EPP1.9 mode Parameter Symbol Conditions MIN. MAX. Unit IOCHRDY setup time t22 3T ns CD (7:0) output delay time t23 30 ns STROBE# setup time, DIR1284 cancellation time (from IOW# ↓) t24 5T ns STROBE# setup time, DIR1284 cancellation time (from BUSY ↓) t25 4T ns SELECTIN#, AUTOFEED# setup time (from STROBE# ↓, valid data output) t26 Timeout generation time t27 10 µs SELECTIN#, AUTOFEED# cancellation time (from IOW# ↑) t28 3T ns IOCHRDY cancellation time t29 4T ns CD (7:0) hold time t30 1T ns STROBE# cancellation time, DIR1284 setup time t31 1T ns 0 ns Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) AD (24:0), DATA (31:0) (input) Valid data t27 IOW# (input) t22 t29 IOCHRDY (output) t24 t31 STROBE# (output) t26 SELECTIN# AUTOFEED# (output) t23 CD (7:0) (output) t30 Valid data t24 DIR1284 (output) t25 BUSY (input) 32 t28 Data Sheet U14388EJ2V0DS00 t31 µPD31172 (f) Read timing in EPP1.9 mode Parameter Symbol Conditions MIN. MAX. Unit IOCHRDY setup time t32 3T ns STROBE# setup time, DIR1284 cancellation time (from IOR# ↓) t33 5T ns STROBE# setup time, DIR1284 cancellation time (from BUSY ↓) t34 4T ns SELECTIN#, AUTOFEED# setup time (from IOR# ↓) t35 6T ns SELECTIN#, AUTOFEED# setup time (from DIR1284 ↑) t36 Timeout generation time t37 10 µs SELECTIN#, AUTOFEED# cancellation time (from IOR# ↑) t38 3T ns CD (7:0) hold time t39 IOCHRDY cancellation time t40 STROBE# cancellation time, DIR1284 setup time t41 30 ns 0 ns 3T 1T ns ns Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) AD (24:0) (input) t37 IOR# (input) DATA (31:0) (output) Hi-Z Hi-Z Valid data t32 t40 IOCHRDY (output) t33 t41 STROBE# (output) t34 t36 SELECTIN# AUTOFEED# (output) t38 t35 t39 CD (7:0) (input) Hi-Z t33 Valid data Hi-Z t41 DIR1284 (output) BUSY (input) t34 Data Sheet U14388EJ2V0DS00 33 µPD31172 (g) Write timing in EPP1.7 mode Parameter Symbol Conditions MIN. MAX. Unit CD (7:0) output delay time t42 30 ns STROBE# setup time t43 3T ns SELECTIN#, AUTOFEED# setup time t44 4T ns IOCHRDY setup time t45 3T ns Timeout generation time t46 10 µs IOCHRDY cancellation time t47 3T ns SELECTIN#, AUTOFEED# cancellation time t48 3T ns STROBE# cancellation time t49 1T ns CD (7:0) hold time t50 30 ns Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) AD (24:0), DATA (31:0) (input) Valid data IOW# (input) t50 t42 CD (7:0) (output) Valid data t43 t49 STROBE# (output) t48 t44 SELECTIN# AUTOFEED# (output) DIR1284 (output) t46 BUSY (input) t45 IOCHRDY (output) 34 Data Sheet U14388EJ2V0DS00 t47 µPD31172 (h) Read timing in EPP1.7 mode Parameter Symbol Conditions MIN. MAX. Unit 3T ns DIR1284 setup time t51 SELECTIN#, AUTOFEED# setup time t52 IOCHRDY setup time t53 3T ns Timeout generation time t54 10 µs IOCHRDY cancellation time t55 3T ns SELECTIN#, AUTOFEED# cancellation time t56 3T ns CD (7:0) hold time t57 0 ns DIR1284 cancellation time t58 1T ns 30 ns Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) AD (24:0) (input) IOR# (input) DATA (31:0) (output) Hi-Z Hi-Z Valid data STROBE# (output) t52 t56 SELECTIN# AUTOFEED# (output) CD (7:0) (input) t57 Hi-Z Hi-Z Valid data t51 t58 DIR1284 (output) t54 BUSY (input) t53 t55 IOCHRDY (output) Data Sheet U14388EJ2V0DS00 35 µPD31172 (i) Interrupt request timing Parameter Symbol Conditions MIN. MAX. Interrupt request setup time t59 Interrupt request generation time (from ACK#↑, ERROR# ↓) t60 3T ns Interrupt request cancellation time (from IOW# ↑) t61 5T ns t62 3T ns t63 5T ns Note Interrupt request cancellation time (from IOR# ↑) Interrupt request generation time (from IOW# ↑) 4T Unit ns Note When bit 7 of the CNFGA register = 0 Remark T: Parallel interface internal clock cycle (41.6 ns (MIN.)) IOW# (input) IOR# (input) ACK# (input) t60 t61 t60 INTRP, IRQ (output) t59 ERROR# (input) t60 36 t60 Data Sheet U14388EJ2V0DS00 t62 t63 µPD31172 (11) USB interface Applicable to the DP (2:1) and DN (2:1) pins. Refer to the USB specification, revision 1.0, for details. Full-speed mode Low-speed mode Parameter Symbol Rise time tR Fall time tF tR, tF matching tRFM Differential output signal crossover point VCRS Rise time Conditions tR MIN. MAX. Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tR/tF 90 110 % 1.3 2.0 V CL = 50 pF 75 CL = 350 pF Fall time tF ns 300 CL = 50 pF 75 CL = 350 pF ns 300 ns 80 120 % tR, tF matching tRFM Differential output signal crossover point VCRS 1.3 2.0 V Imp. 28 43 Ω Impedance tR/tF ns 90% 90% VCRS DP (2:1), DN (2:1) 10% 10% tR Data Sheet U14388EJ2V0DS00 tF 37 µPD31172 3. PACKAGE DRAWING 208-PIN PLASTIC FBGA (15x15) OUTLINE DRAWINGS w D S B D1 ZD B 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ZE A E1 E UTRPN MLK JH GF EDCB A w INDEX MARK 4 – R0.3 S A 4 – C1.0 A 25° y1 A2 S S y e S 208 – φ b A1 φx M S A B ITEM D MILLIMETERS 15.00±0.10 D1 14.4 E E1 15.00±0.10 14.4 w 0.20 e A 0.80 1.51±0.15 A1 A2 0.35±0.10 1.16 b 0.50 +0.05 −0.10 x 0.08 y y1 0.10 0.20 ZD ZE 1.1 1.1 P208S1-80-2C 38 Data Sheet U14388EJ2V0DS00 µPD31172 4. RECOMMENDED SOLDERING CONDITIONS The µPD31172 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Note Count: Three times or less, Exposure limit: 7 days (after that, prebake at 125°C for Recommended Condition Symbol IR35-107-3 10 to 72 hours) VPS Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher), Note Count: Three times or less, Exposure limit: 7 days (after that, prebake at 125°C for VP15-107-3 10 to 72 hours) Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) – Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U14388EJ2V0DS00 39 µPD31172 [MEMO] 40 Data Sheet U14388EJ2V0DS00 µPD31172 [MEMO] Data Sheet U14388EJ2V0DS00 41 µPD31172 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 42 Data Sheet U14388EJ2V0DS00 µPD31172 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Hong Kong Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U14388EJ2V0DS00 43 µPD31172 Related Documents: Reference Materials: VRC4172 User’s Manual (U14386E) VR4121 User’s Manual (U13569E) VR4121 Data Sheet (U14691E) Electrical Characteristics for Microcomputer (IEI-601) The related documents indicated in this publication may include preliminary versions. versions are not marked as such. However, preliminary VR4121 and VRC4172 are trademarks of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. 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NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8