NEC UPD46128512-E9X

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
μPD46128512-X
128M-BIT CMOS MOBILE SPECIFIED RAM
8M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
Description
The μPD46128512-X is a high speed, low power, 134,217,728 bits (8,388,608 words by 16 bits) CMOS Mobile
Specified RAM featuring asynchronous page read and random write, synchronous burst read/write function.
The μPD46128512-X is fabricated with advanced CMOS technology using one-transistor memory cell.
Features
• 8,388,608 words by 16 bits organization
• Asynchronous page read mode
• Synchronous read and write mode
• Burst length: 8 words / 16 words / continuous
• Clock latency: 5, 6, 7, 8, 9, 10
• Burst sequence: Linear burst
• Max clock frequency: 108/83 MHz
• Byte data control: /LB (DQ0 to DQ7), /UB (DQ8 to DQ15)
• Low voltage operation: 1.7 to 2.0 V
• Operating ambient temperature: TA = −30 to +85 °C
• Chip Enable input: /CE1 pin
• Standby Mode input: CE2 pin
• Standby Mode 1: Normal standby (Memory cell data hold valid)
• Standby Mode 2: Density of memory cell data hold is variable
μPD46128512
Clock
Asynchronous Operating
Supply current
Operating
frequency
initial access
supply
ambient
At operating
MHz
time
voltage
temperature
mA
(MAX.)
(TYP.)
(MAX.)
ns
V
°C
(MAX.)
Density of data hold
Density of data hold
(MAX.)
At standby μA
128M 32M
bits
-E9X
Note
-E10X
-E11X
108
Note
83
-E12X
70
1.7 to 2.0
−30 to +85
60
85
50
70
60
85
50
bits
16M
8M
0M
bits
bits
bits
bits
65
80
250 T.B.D. T.B.D. T.B.D.
128M 32M
bits
16M
8M
0M
bits
bits
bits
T.B.D. T.B.D. T.B.D.
Note Under consideration
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M17507EJ2V0DS00 (2nd edition)
Date Published September 2005 CP (K)
Printed in Japan
The mark
shows major revised points.
2005
15
μ PD46128512-X
Ordering Information
μPD46128512-X is mainly shipping by wafer.
Please consult with our sales offices for package samples and ordering information.
2
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Pin Configuration
The following is pin configuration of package sample.
/xxx indicates active low signal.
93-PIN TAPE FBGA (12x9)
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
A BCDE FGH J K LM N P
P NM L K J HGF EDCBA
Top View
A
10
NC
9
B
C
NC
NC
NC
NC
NC
8
7
D
J
K
A16
NC
Vss
A14
NC
DQ15
DQ7
DQ14
A9
A10
DQ6
DQ13
DQ12
DQ5
E
F
G
H
NC
NC
A15
A21
A22
A11
A12
A13
A8
A19
M
N
P
NC
NC
NC
NC
NC
L
NC
6
NC
/WE
CE2
A20
NC
NC
DQ4
VCC
NC
NC
5
NC
CLK
/ADV
/WAIT
NC
NC
DQ3
VCC
DQ11
NC
/LB
/UB
A18
A17
DQ1
DQ9
DQ10
DQ2
NC
A7
A6
A5
A4
GND
/OE
DQ0
DQ8
NC
NC
NC
A3
A2
A1
A0
NC
/CE1
NC
NC
NC
NC
4
3
2
1
NC
A0 to A22
: Address inputs
DQ0 to DQ15 : Data inputs / outputs
NC
NC
NC
NC
NC
CLK
: Clock input
/ADV
: Address Valid Input
/CE1
: Chip select input
/WAIT
: Wait output
CE2
: Standby mode input
VCC
: Power supply
/WE
: Write enable input
GND
: Ground
/OE
: Output enable input
NC Note
: No Connection
/LB, /UB
: Byte data select input
NC
Note Some signals can be applied because this pin is not internally connected.
Remark Refer to Package Drawing for the index mark.
Preliminary Data Sheet M17507EJ2V0DS
3
μ PD46128512-X
Block Diagram
Standby mode control
VCC
VCCQ
Refresh
control
GND
Refresh
counter
A0
to
A22
CLK
/ADV
Address buffer
Memory cell array
134,217,728 bits
Row
decoder
Address latch
DQ0 to DQ7
Input data
controller
DQ8 to DQ15
/WAIT
Internal state
control
/CE1
CE2
/LB
/UB
/WE
/OE
4
Preliminary Data Sheet M17507EJ2V0DS
Sense amplifier /
Switching circuit
Column decoder
Output data
controller
μ PD46128512-X
Truth Table
Asynchronous Operation
Mode
/CE1
CE2
/ADV
/OE
/WE
/LB
/UB
DQ
/WAIT
DQ0 to DQ7 DQ8 to DQ15
H
H
×
×
×
×
×
High-Z
High-Z
High-Z
×
L
×
×
×
×
×
High-Z
High-Z
High-Z
L
H
Note3
L
H
L
L
DOUT
DOUT
High-Z
Lower byte read
L
H
DOUT
High-Z
High-Z
Upper byte read
H
L
High-Z
DOUT
High-Z
Output disable
H
H
High-Z
High-Z
High-Z
×
×
High-Z
High-Z
High-Z
L
L
DIN
DIN
High-Z
Lower byte write
L
H
DIN
High-Z
High-Z
Upper byte write
H
L
High-Z
DIN
High-Z
H
H
High-Z
High-Z
High-Z
Not selected (Standby Mode 1)
Not selected (Standby Mode 2)
Word read
Note1
Output disable
H
Word write
Abort write
Notes 1.
L
Note2
CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition).
2. If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not available.
3.
Fixed LOW or toggle HIGH → LOW → HIGH
Remark H, HIGH : VIH, L, LOW : VIL, ×: VIH or VIL
Clock pin must be fixed either LOW or HIGH.
Preliminary Data Sheet M17507EJ2V0DS
5
μ PD46128512-X
Burst Operation
Mode
/CE1
Not selected (Standby Mode 1)
Not selected (Standby Mode 2)
Note1
Start address latch
CE2
CLK
/ADV
/OE
/WE
/LB
/UB
DQ
/WAIT
DQ0 to DQ7
DQ8 to DQ15
Note8
H
H
×
×
×
×
×
×
High-Z
High-Z
High-Z
×
L
×
×
×
×
×
×
High-Z
High-Z
High-Z
L
H
Note4
L
× Note7
× Note7
× Note9
× Note9
High-Z Note5
High-Z Note5
×
H
L
H
DOUT
DOUT
Output
Advanced burst read to next address
Note4
Valid
Burst read suspend
Burst read resume
Note2
Note2
Burst read termination Note3
Advanced burst write to next address
×
L
H
High-Z
High-Z
HIGH
L
DOUT
DOUT
HIGH
×
High-Z
High-Z
High-Z
DIN
DIN
Output
H
L
Note4
Valid
Burst write suspend
Burst write resume
Note2
Note2
Burst write termination Note3
Abort write
Note6
Notes 1.
2.
×
×
L
×
H
High-Z
High-Z
HIGH
L
DIN
DIN
HIGH
×
High-Z
High-Z
High-Z
High-Z
High-Z
HIGH
Note10
HIGH
HIGH
CE2 pin must be fixed HIGH except Standby Mode 2 (refer to 2.3 Standby Mode Status Transition).
Be sure to suspend or resume a burst read after outputting the first read access data.
Be sure to suspend or resume a burst write after latching the first write data.
Burst write suspend or resume is available when setting WC = 1 (/WE level control) through Mode Register
Set.
3.
/CE1 must be fixed HIGH during tTRB specification until next read or write operation.
4.
Valid clock edge shall be set either positive or negative edge through Mode Register Set.
5.
If /OE = LOW and /LB = /UB = LOW, output is valid. If /OE = LOW and /LB = /UB = HIGH, output is high
impedance.
If /WE = LOW, output is high impedance. If /OE = /WE = HIGH, output is high impedance.
6.
If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not
available.
7.
Both of two pins (/OE and /WE) or either of two should be connected to HIGH. It is prohibited to bring the
both /OE and /WE to LOW.
8.
9.
Refer to the 4.10 /WAIT.
For the Burst Read, the /UB, /LB setup time to CLK (tBC) must be satisfied. For the Burst Write, the /UB,
/LB setup time to CLK (tBC) must be satisfied. Once /LB and /UB inputs are determined, they must not be
changed until the end of burst operation.
10. In case of WC = 0, /WE is HIGH.
In case of WC = 1, /WE is LOW.
The explanation of WC refers to Table 5-2. Mode Register Definition (5th Bus Cycle) and 5.9 /WE
control.
Remark H, HIGH : VIH, L, LOW : VIL, ×: VIH or VIL,
6
: valid edge
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
CONTENTS
1. Initialization .................................................................................................................................................. 9
2. Partial Refresh ........................................................................................................................................... 11
2.1 Standby Mode.......................................................................................................................................................... 11
2.2 Density Switching .................................................................................................................................................... 11
2.3 Standby Mode Status Transition.............................................................................................................................. 11
2.4 Addresses for Which Partial Refresh Is Supported.................................................................................................. 13
3. Page Read Operation ................................................................................................................................ 14
3.1 Features of Page Read Operation ........................................................................................................................... 14
3.2 Page Length ............................................................................................................................................................ 14
3.3 Page-Corresponding Addresses.............................................................................................................................. 14
3.4 Page Start Address.................................................................................................................................................. 14
3.5 Page Direction ......................................................................................................................................................... 14
3.6 Interrupt during Page Read Operation..................................................................................................................... 14
3.7 When Page Read is not Used.................................................................................................................................. 14
4. Burst Operation ......................................................................................................................................... 15
4.1 Features of Burst Operation .................................................................................................................................... 15
4.2 Burst Length ............................................................................................................................................................ 15
4.3 Latency .................................................................................................................................................................... 15
4.4 Single Write ............................................................................................................................................................. 17
4.5 /WE Control ............................................................................................................................................................. 17
4.6 Burst Read Suspend/Resume ................................................................................................................................. 18
4.7 Burst Write Suspend/Resume ................................................................................................................................. 19
4.8 Burst Read Termination........................................................................................................................................... 20
4.9 Burst Write Termination ........................................................................................................................................... 21
4.10 /WAIT..................................................................................................................................................................... 22
4.10.1 Feature of /WAIT Output ............................................................................................................................. 22
4.10.2 Dummy Wait Cycles at Continuous Burst Operation ................................................................................... 25
4.11 Reset Function from Synchronous Burst Mode to Asynchronous Page Mode....................................................... 27
5. Mode Register Settings............................................................................................................................. 28
5.1 Mode Register Setting Method ................................................................................................................................ 28
5.2 Cautions for Setting Mode Register ......................................................................................................................... 28
5.3 Partial Refresh Density ............................................................................................................................................ 30
5.4 Burst Length ............................................................................................................................................................ 30
5.5 Function Mode ......................................................................................................................................................... 30
5.6 Valid Clock Edge ..................................................................................................................................................... 30
5.7 Read Latency (Write Latency) ................................................................................................................................. 30
5.8 Single Write ............................................................................................................................................................. 30
5.9 /WE Control ............................................................................................................................................................. 31
5.10 Reset to Page Mode .............................................................................................................................................. 31
5.11 Reserved Bits ........................................................................................................................................................ 31
5.12 Cautions for Timing Chart of Setting Mode Register.............................................................................................. 32
6. Electrical Specifications ........................................................................................................................... 33
Preliminary Data Sheet M17507EJ2V0DS
7
μ PD46128512-X
7. Asynchronous AC Specification, Timing Chart ..................................................................................... 36
8. Synchronous AC Specification, Timing Chart........................................................................................ 57
9. Mode Register Setting Timing.................................................................................................................. 74
10. Standby Mode Timing Chart................................................................................................................... 77
11. Package Drawing..................................................................................................................................... 78
12. Recommended Soldering Conditions ................................................................................................... 79
8
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
1. Initialization
Initialize the μPD46128512-X at power application using the following sequence to stabilize internal circuits.
There are 2 method of initialization.
Initialization Timing 1
(1) Following power application, make CE2 HIGH after fixing CE2 to LOW for the period of tVHMH.
Make /CE1 HIGH before making CE2 HIGH.
(2) /CE1 and CE2 are fixed HIGH for the period of tMHCL.
Normal operation is possible after the completion of initialization.
Figure 1-1. Initialization Timing Chart 1
Nomal Operation
Intialization
/CE1 (Input)
tCHMH
tMHCL
tVHMH
CE2 (Input)
VCC, VCCQ
Cautions 1.
2.
VCC (MIN.), VCCQ (MIN.)
Make CE2 LOW when starting the power supply.
tVHMH is specified from when the power supply voltage reaches the prescribed minimum value
(VCC (MIN.), VCCQ (MIN.)).
Initialization Timing 1
Parameter
Symbol
MIN.
MAX.
Unit
Power application to CE2 LOW hold
tVHMH
50
μs
/CE1 HIGH to CE2 HIGH
tCHMH
0
ns
Following power application CE2 HIGH hold to /CE1 LOW
tMHCL
300
μs
Preliminary Data Sheet M17507EJ2V0DS
9
μ PD46128512-X
Initialization Timing 2
(1) Following power application, make CE2 and /CE1 HIGH for the period of tMHCL.
Normal operation is possible after the completion of initialization.
Figure 1-2. Initialization Timing Chart 2
Nomal Operation
Intialization
/CE1 (Input)
tMHCL
CE2 (Input)
VCC, VCCQ
Cautions 1.
VCC (MIN.), VCCQ (MIN.)
tMHCL is specified from when the power supply voltage reaches the prescribed minimum value
(VCC (MIN.), VCCQ (MIN.)).
2.
If the period from power supplying to value VCC (MIN.), VCCQ (MIN.) is beyond 10 ms or power
supply is not stable rise, should be used Initialization Timing Chart 1.
Initialization Timing 2
Parameter
Symbol
Following power application /CE1, CE2 HIGH hold to /CE1 LOW
10
tMHCL
Preliminary Data Sheet M17507EJ2V0DS
MIN.
300
MAX.
Unit
μs
μ PD46128512-X
2. Partial Refresh
2.1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 128M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
2.2 Density Switching
In Standby Mode 2, the densities that can be selected for performing refresh are 32M bits, 16M bits, 8M bits, and 0M
bit.
The density for performing refresh can be set with the mode register. Once the refresh density has been set in the
mode register, these settings are retained until they are set again, while applying the power supply. However, the mode
register setting will become undefined if the power is turned off, so set the mode register again after power application.
(For how to perform mode register settings, refer to section 5. Mode Register Settings.)
2.3 Standby Mode Status Transition
In Standby Mode 1, /CE1 and CE2 are HIGH. In Standby Mode 2, CE2 is LOW. In Standby Mode 2, if 0M bit is set as
the density, it is necessary to perform initialization the same way as after applying power, in order to return to normal
operation from Standby Mode 2. When the density has been set to 32M bits, 16M bits, or 8M bits in Standby Mode 2, it is
not necessary to perform initialization to return to normal operation from Standby Mode 2.
For the timing charts, refer to Figure 10-1. Standby Mode 2 Entry / Exit Timing Chart (Asynchronous Mode),
Figure 10-2. Standby Mode 2 (data not held) Entry / Exit Timing Chart (Asynchronous Mode).
Preliminary Data Sheet M17507EJ2V0DS
11
12
Figure 2-1. Standby Mode State Machine
Power On
Mode Register
Setting
Initialize
Initialize Note
/CE1 = VIH,
CE2 = VIH
Burst Mode
Page Mode
Burst Mode
Page Mode
/CE1 = V IH,
CE2 = V IH
Standby
Mode1
Preliminary Data Sheet M17507EJ2V0DS
/CE1 = V IH,
CE2 = V IL
/CE1 = V IH,
CE2 = V IL (RP=0)
/CE1 = V IH,
CE2 = V IL
/CE1 = V IL,
CE2 = V IH
/CE1 = V IH,
CE2 = V IH
/CE1 = V IH,
CE2 = V IH
CE2 = V IL (RP=0)
CE2 = V IL
/CE1 = V IH,
CE2 = V IL (RP=1)
/CE1 = V IL,
CE2 = V IH
/CE1 = V IH,
CE2 = V IL (RP=0)
/CE1 = V IH,
CE2 = V IH
Active
Standby
Mode1
/CE1 = V IH,
CE2 = V IH
CE2 = V IL (RP=1)
Standby Mode2
(32Mbit/16Mbit/8Mbit)
/CE1 = V IH,
CE2 = V IL (RP=1)
Standby Mode2
(32Mbit/16Mbit/8Mbit)
Active
CE2 = V IL (RP=0)
CE2 = V IL (RP=1)
CE2 = V IL
Standby Mode2
(Data not held)
μ PD46128512-X
Note Case “Initialization Timing 2” : Following initialization, set mode register.
Standby Mode2
(Data not held)
μ PD46128512-X
2.4 Addresses for Which Partial Refresh Is Supported
Data hold density
Correspondence address
32M bits
000000H to 1FFFFFH
16M bits
000000H to 0FFFFFH
8M bits
000000H to 07FFFFH
Preliminary Data Sheet M17507EJ2V0DS
13
μ PD46128512-X
3. Page Read Operation
For the timing charts, refer to Figure 7-10. Asynchronous Page Read Cycle Timing Chart.
3.1 Features of Page Read Operation
Features
Item
Page length
16 words
Page read-corresponding addresses
A3, A2, A1, A0
Page read start address
Don’t care
Page direction
Don’t care
Interrupt during page read operation
Enabled
Note
Note /CE1 = HIGH, or any change in address A4 or higher will initiate a new read access specified as tAA or tACE.
3.2 Page Length
16 words is supported as the page lengths. Page length is not necessary to set through Mode Register.
3.3 Page-Corresponding Addresses
The 16 words page read-enabled addresses are A3, A2, A1, and A0. Fix addresses other than A3, A2, A1, and A0
during page read operation.
3.4 Page Start Address
Since random page read is supported, any address (A3, A2, A1 and A0 with the 16 words page) can be used as the
page read start address.
3.5 Page Direction
Since random page read is possible, there is not restriction on the page direction.
3.6 Interrupt during Page Read Operation
When generating an interrupt during page read, make /CE1 HIGH or change A4 and higher addresses.
3.7 When Page Read is not Used
Since random page read is supported, even when not using page read, random access is possible as usual.
14
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
4. Burst Operation
Burst operation is valid when burst mode is set through mode register.
4.1 Features of Burst Operation
Function
Features
Burst Length
8, 16, Continuous
Read Latency
5, 6, 7, 8, 9, 10
Write Latency
4, 5, 6, 7, 8, 9
Burst Sequence
Linear
Single Write
Single Write, Burst Write
Valid Clock Edge
Rising Edge, Falling Edge
4.2 Burst Length
Burst length is the number of word to be read or written during synchronous burst read/write operation as the result of a
single address latch cycle. It can be set on 8, 16words boundary or continuous for entire address through Mode Register
Set sequence. Starting from initial address being latched, device internal address counter assign +1 to the previous
address until reaching the end of boundary address. After completing read data out or write data latch for the set burst
length, operation automatically end except for continuous burst. When continuous burst length is set, read /write is
endless unless it is terminated by the rising edge of /CE1.
4.3 Latency
Read Latency (RL) is the number of clock cycles between the address being latched and first read data becoming
available during synchronous burst read operation. It is set through Mode Register Set sequence after power application.
Once RL is set through Mode Register Set sequence, write latency, that is the number of clock cycles between address
being latched and first write data being latched, is automatically set to RL−1.
Latency Count
Grade
-E9X
Asynchronous
Frequency
access time
<108 MHz
70 ns
8, 9, 10
7, 8, 9
85 ns
10
9
70 ns
7, 8, 9, 10
6, 7, 8, 9
85 ns
8, 9, 10
7, 8, 9
70 ns
6, 7, 8, 9, 10
5, 6, 7, 8, 9
85 ns
7, 8, 9, 10
6, 7, 8, 9
70 ns
5, 6, 7, 8, 9, 10
4, 5, 6, 7, 8, 9
85 ns
5, 6, 7, 8, 9, 10
4, 5, 6, 7, 8, 9
-E10X
-E9X, -E11X
<83 MHz
-E10X, -E12X
-E9X, -E11X
<66 MHz
-E10X, -E12X
-E9X, -E11X
<52 MHz
-E10X, -E12X
Read Latency
Write Latency
Note
Clock
Note Write Latency = Read Latency−1
Preliminary Data Sheet M17507EJ2V0DS
15
μ PD46128512-X
Figure 4-1. Latency Definition
CLK (Input)
Address (Input)
Valid
/ADV (Input)
/CE1 (Input)
RL = 5
DQ (Output)
Read Latency = 5
High-Z
Q0
Q1
Q2
Q3
Q4
Q5
D1
D2
D3
D4
D5
D6
Q0
Q1
Q2
Q3
Q4
D1
D2
D3
D4
D5
Q0
Q1
Q2
Q3
D1
D2
D3
D4
Q0
Q1
Q2
D1
D2
D3
Q0
Q1
D1
D2
Write Latency = 4
DQ (Input)
High-Z
Read Latency = 6
RL = 6
DQ (Output)
D0
High-Z
Write Latency = 5
DQ (Input)
High-Z
Read Latency = 7
RL = 7
DQ (Output)
D0
High-Z
Write Latency = 6
DQ (Input)
High-Z
Read Latency = 8
RL = 8
DQ (Output)
D0
High-Z
Write Latency = 7
DQ (Input)
High-Z
Read Latency = 9
RL = 9
DQ (Output)
D0
High-Z
Write Latency = 8
DQ (Input)
High-Z
Read Latency = 10
RL = 10
DQ (Output)
D0
High-Z
Q0
Write Latency = 9
DQ (Input)
16
High-Z
D0
Preliminary Data Sheet M17507EJ2V0DS
D1
μ PD46128512-X
4.4 Single Write
Single write operation is a single-word length synchronous write operation. The μPD46128512-X is supporting two
type of synchronous write operation, “Burst Read & Single Write” and “Burst Read & Burst Write”, configurable with SW
bit in the mode register. When the device set to the “Burst Read & Single Write” operation mode, the burst length at the
synchronous write operation is always fixed to single word length regardless of the burst length (BL) setting in the mode
register, however, BL setting is still effective in synchronous read operation (Refer to 5. Mode Register Settings).
Refer to Figure 8-8.
Synchronous Burst Write Cycle Timing Chart (/WE level Control), Figure 8-9.
Synchronous Burst Write Cycle Timing Chart (/WE single clock control), Figure 8-10. Synchronous Single Write
Timing Chart.
4.5 /WE Control
The μPD46128512-X is supporting two type of timing control with /WE input signal, “/WE level control” and “/WE single
clock control” configurable with WC bit in the mode register at synchronous write operation. In case of /WE level
controlling, /WE must be asserted LOW before the 2nd clock input timing (T1).
Refer to Figure 8-8.
Synchronous Burst Write Cycle Timing Chart (/WE level Control), Figure 8-9.
Synchronous Burst Write Cycle Timing Chart (/WE single clock control).
Figure 4-2. /WE Control
T0
T1
T2
T3
T4
T5
T6
T7
CLK (Input)
Address (Input)
Add
/ADV (Input)
Read Latency = 5
/CE1 (Input)
/WE Level Control
tWES
/WE (Input)
DQ0 to DQ15 (Input)
/WAIT (Output)
High-Z
D0
D1
D2
D3
D0
D1
D2
D3
High-Z
/WE Single Clock Control
tWES tWEH
/WE (Input)
DQ0 to DQ15 (Input)
/WAIT (Output)
High-Z
High-Z
Preliminary Data Sheet M17507EJ2V0DS
17
μ PD46128512-X
4.6 Burst Read Suspend/Resume
A burst read operation can be suspended by bringing /OE signal from LOW to HIGH during the burst read operation.
The /OE signal must be required to meet the specified setup / hold time to the clock which the data being suspended.
Once the /OE is brought to HIGH, output data turns to be high impedance state after specific time duration.
The burst read suspend will be effective after outputting first read data, or after outputting dummy wait cycles in case of
dummy wait cycling insertion at continuous burst read mode.
The burst suspend mode will be resumed by re-asserting /OE to LOW, and the first output data is from the same
address location as of being suspended.
Figure 4-3. Burst Read Suspend/Resume
CLK (Input)
A0 to A22 (Input)
/ADV (Input)
H
/CE1 (Input)
L
tSOEH tSOES
/OE (Input)
tSOEH tSOES
tSOP
tOHZ
tBACC
DQ0 to DQ15 (Output)
18
Q0
tBDH
Q1
tBACC
High-Z
Preliminary Data Sheet M17507EJ2V0DS
tBDH
Q2
Q3
μ PD46128512-X
4.7 Burst Write Suspend/Resume
A burst write operation can be suspended by bringing /WE signal from LOW to HIGH during the burst write operation.
The /WE signal must be required to meet the specified setup / hold time to the clock which the data being suspended.
The burst write suspend will be effective after inputting first write data.
The burst suspend mode will be resumed by re-asserting /WE to LOW, and the first write data is written to the same
address location as of being suspended. Burst write suspend or resume is available only when WC = 1(/WE level
control) is set to the mode register (refer to Table 5-2. Mode Register Definition (5th Bus Cycle).
Figure 4-4. Burst Write Suspend/Resume
T4
T5
T6
T7
T8
T9
T10
CLK (Input)
A0 to A22 (Input)
/ADV (Input)
H
/CE1 (Input)
L
tWEH tWES
/WE (Input)
tWEH tWES
tSWHP
tWDS tWDH
DQ0 to DQ15 (Output)
D0
D1
tWDS tWDH
High-Z
Preliminary Data Sheet M17507EJ2V0DS
D2
D3
19
μ PD46128512-X
4.8 Burst Read Termination
Burst read termination can be performed by transferring /CE1 LOW to HIGH during the burst read. When continuous
burst length is set, burst read is endless unless it is terminated. Be sure to terminate a burst read after outputting the first
read access data.
In order to guarantee the last data output, the specified minimum value of /CE1 = LOW hold time (tCEH) against clock
edge must be satisfied. In order to perform next operation after burst read termination, the specified minimum value of
Burst Read Termination recovery time (tTRB) must be satisfied.
Figure 4-5. Burst Read Termination
CLK (Input)
tACS
A0 to A22 (Input)
tACH
Valid
tAH
tCHV tCSV tCHV
/ADV (Input)
tCEH tCES
/CE1 (Input)
tCEH tCES
tTRB
tCHZ
/OE (Input)
tBACC
DQ0 to DQ15 (Output)
20
Q1
Q2
tBDH
Q3
Preliminary Data Sheet M17507EJ2V0DS
High-Z
μ PD46128512-X
4.9 Burst Write Termination
Burst write termination can be performed by transferring /CE1 LOW to HIGH during the burst write. When continuous
burst length is set, burst write is endless unless it is terminated. Be sure to terminate a burst write after latching the first
write data.
In order to guarantee the last write data is latched, the specified minimum value of /CE1 = LOW hold time against clock
edge must be satisfied. In order to perform next operation after burst write termination, the specified minimum value of
Burst Write Termination recovery time (tTRB) must be satisfied.
Figure 4-6. Burst Write Termination
CLK (Input)
tACS
A0 to A22 (Input)
tACH
Valid
tAH
tCHV tCSV tCHV
/ADV (Input)
tWRB
tCEH tCES
/CE1 (Input)
tCEH tCES
tTRB
/WE (Input)
tWDS tWDH
DQ0 to DQ15 (Output)
D1
D2
D3
Preliminary Data Sheet M17507EJ2V0DS
High-Z
21
μ PD46128512-X
4.10 /WAIT
4.10.1 Feature of /WAIT Output
The /WAIT output signal indicates the internal status, busy (LOW) or ready (HIGH), during the burst read and burst
write operation.
The /WAIT output state changes depend on the /CE1 and /ADV condition. When /CE1 held entire LOW, the /WAIT
output corresponds with /ADV state and turns to LOW by /ADV assertion. The /WAIT output stays high impedance at
standby mode (/CE1 = HIGH) and turns to LOW at active mode brought by /CE1 assertion.
The /WAIT output will be asserted to LOW after specific time duration triggered by falling edge of /CE1, or falling edge
of /ADV when /CE1 held entire LOW. When the /WAIT output LOW, it indicates the output data is not valid at the next
clock cycle.
The /WAIT output asserts HIGH one clock cycle before the valid data output.
The /WAIT output retains the same state as of the clock cycle right before being suspended with /OE brought to HIGH.
Figure 4-7. Burst Read /WAIT Output (/CE1 = HIGH → LOW)
T0
T1
T2
T3
T4
T5
CLK (Input)
A0 to A22 (Input)
Add
/ADV (Input)
/CE1 (Input)
/WE (Input)
H
RL = 5
DQ0 to DQ15 (Output)
High-Z
Q0
tCEWA
/WAIT (Output)
22
High-Z
Preliminary Data Sheet M17507EJ2V0DS
tCLWA
μ PD46128512-X
Figure 4-8. Burst Read /WAIT Output (/CE1 = LOW, /ADV = HIGH → LOW)
T0
T1
T2
T3
T4
T5
CLK (Input)
A0 to A22 (Input)
Add
/ADV (Input)
tADWA
/CE1 (Input)
L
/WE (Input)
H
RL = 5
DQ0 to DQ15 (Output)
High-Z
Q0
tCLWA
/WAIT (Output)
The /WAIT output will be asserted to LOW after specific time duration from the falling edge of the /CE1, or falling edge
of the /ADV when /CE1 held LOW at burst write operation. When the /WAIT output LOW, it indicates the input data can
not be accepted at the next clock cycle. The /WAIT output asserts HIGH one clock cycle before the valid data input. The
/WAIT output retains the same state as of the clock cycle right before being suspended with /WE brought to HIGH.
The /WAIT output always stay high impedance state under asynchronous mode setting.
Preliminary Data Sheet M17507EJ2V0DS
23
μ PD46128512-X
Figure 4-9. Burst Write /WAIT Output (/CE1 = HIGH → LOW)
T0
T1
T2
T3
T4
T5
D0
D1
CLK (Input)
A0 to A22 (Input)
Add
/ADV (Input)
/CE1 (Input)
tWES
/WE (Input)
(WC = 1)
tWES tWEH
/WE (Input)
(WC = 0)
RL = 5
DQ0 to DQ15 (Output)
High-Z
tCEWA
/WAIT (Output)
tCLWA
High-Z
Figure 4-10. Burst Write /WAIT Output (/CE1 = LOW, /ADV = HIGH → LOW)
T0
T1
T2
T3
T4
T5
CLK (Input)
A0 to A22 (Input)
Add
/ADV (Input)
tADWA
/CE1 (Input)
tWES
/WE (Input)
(WC = 1)
tWES tWEH
/WE (Input)
(WC = 0)
RL = 5
DQ0 to DQ15 (Output)
High-Z
D0
tCLWA
/WAIT (Output)
24
Preliminary Data Sheet M17507EJ2V0DS
D1
μ PD46128512-X
4.10.2 Dummy Wait Cycles at Continuous Burst Operation
In continuous burst operation, dummy wait cycles may be needed when a burst sequence crosses the first 16-word
boundary. Whether dummy wait cycles is needed or not depends on start address and the number of dummy wait cycles
depends on Read Latency (See Table 4-1. Burst Sequence and 4-2. Dummy Wait Cycles and Read Latency).
During the dummy cycle period, /WAIT output LOW.
Table 4-1. Burst Sequence
Start
Burst length = 8
Burst length = 16
Continuous
Address
Linear
Linear
Linear
xx00 H
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-…
xx01 H
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-…
xx02 H
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-…
xx03 H
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-…
xx04 H
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-…
xx05 H
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-…
xx06 H
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-…
xx07 H
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22-…
xx08 H
8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7
8-9-10-11-12-13-14-15-16-17-18-19-20-21-22-23-…
xx09 H
9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8
9-10-11-12-13-14-15-16-17-18-19-20-21-22-23-24-…
xx0A H
10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9
10-11-12-13-14-15-16-17-18-19-20-21-22-23-24-25-…
xx0B H
11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10
11-12-13-14-15-W-16-17-18-19-20-21-22-23-24-25-…
xx0C H
12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11
12-13-14-15-W-W-16-17-18-19-20-21-22-23-24-25-…
xx0D H
13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12
13-14-15-W-W-W-16-17-18-19-20-21-22-23-24-25-…
xx0E H
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-W-W-W-W-16-17-18-19-20-21-22-23-24-25-…
xx0F H
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-W-W-W-W-W-16-17-18-19-20-21-22-23-24-25-…
xx10 H
…
xx11 H
…
16-17-18-19-20-21-22-23-24-25-26-…
17-18-19-20-21-22-23-24-25-26-27-…
…
…
…
xxnB H
-xxnB -xxnC-xxnD-xxnE-xxnF-W-xx(n+1)0-xx(n+1)1-…
xxnC H
-xxnC-xxnD-xxnE-xxnF-W-W-xx(n+1)0-xx(n+1)1-…
xxnD H
-xxnD-xxnE-xxnF-W-W-W-xx(n+1)0-xx(n+1)1-…
xxnE H
-xxnE-xxnF-W-W-W-W-xx(n+1)0-xx(n+1)1-xx(n+1)2-…
xxnF H
-xxnF-W-W-W- W-W-xx(n+1)0-xx(n+1)1-xx(n+1)2-…
…
…
…
…
Remarks 1. The above table assumes Read Latency is set 5. W shows Dummy Wait Cycles.
2. Address is in HEX.
Preliminary Data Sheet M17507EJ2V0DS
25
μ PD46128512-X
Table 4-2. Dummy Wait Cycles and Read Latency
Start
Read Latency
Read Latency
Read Latency
Read Latency
Read Latency
Address
=5
=6
=9
= 10
=n
(Write Latency
= 4)
(Write Latency
(Write Latency
(Write Latency
(Write Latency
= 5)
= 6)
= 7)
= n−1)
xxx0 H
No wait
No wait
…
No wait
No wait
No wait
xxx1 H
No wait
No wait
…
No wait
No wait
No wait
xxx2 H
No wait
No wait
…
No wait
No wait
No wait
xxx3 H
No wait
No wait
…
No wait
No wait
No wait
xxx4 H
No wait
No wait
…
No wait
No wait
No wait
xxx5 H
No wait
No wait
…
No wait
No wait
No wait
xxx6 H
No wait
No wait
…
No wait
1 cycle
xxx7 H
xxx8 H
xxx9 H
No wait
No wait
No wait
No wait
No wait
No wait
…
…
…
…
1 cycle
2 cycle
3 cycle
2 cycle
3 cycle
4 cycle
xxxA H
No wait
1 cycle
…
4 cycle
5 cycle
xxxB H
1 cycle
2 cycle
…
5 cycle
6 cycle
xxxC H
xxxD H
2 cycle
3 cycle
3 cycle
4 cycle
…
…
6 cycle
7 cycle
7 cycle
8 cycle
xxxE H
4 cycle
5 cycle
…
8 cycle
9 cycle
xxxF H
5 cycle
6 cycle
…
9 cycle
10 cycle
Remark Address is in HEX.
26
Preliminary Data Sheet M17507EJ2V0DS
(n−9) Wait cycles are needed after
boundary data output (n = 10).
(n−8) Wait cycles are needed after
boundary data output. (n =/> 9)
(n−7) Wait cycles are needed after
boundary data output. (n =/> 8)
(n−6) Wait cycles are needed after
boundary data output. (n =/> 7)
(n−5) Wait cycles are needed after
boundary data output. (n =/> 6)
(n−4) Wait cycles are needed after
boundary data output. (n =/> 5)
(n−3) Wait cycles are needed after
boundary data output. (n =/> 5)
(n−2) Wait cycles are needed after
boundary data output. (n =/> 5)
(n−1) Wait cycles are needed after
boundary data output. (n =/> 5)
n Wait cycles are needed after
boundary data output. (n =/> 5)
μ PD46128512-X
4.11 Reset Function from Synchronous Burst Mode to Asynchronous Page Mode
Even during the burst operation mode, the μ PD46128512-X has the reset feature of changing synchronous burst
mode to asynchronous page mode.
This reset is achieved by toggling CE2 signal HIGH → LOW → HIGH.
This reset to asynchronous page mode can be enable / disable with mode register setting.
Since the CE2 signal originally controls partial refresh function, the partial refresh operation can also be performed
during the reset operation according to the density specified in the mode register. Please refer to the timing diagram and
requirement below. Note that the timing requirement differs with the partial refresh density.
In case when the reset to asynchronous page mode is disabled in the mode register, only the partial refresh operation
can be performed with CE2 signal toggling. Refer to Figure 2-1. Standby Mode State Machine.
Figure 4-11. Reset Entry Timing Chart to Asynchronous Page Mode
CLK (Input)
tCE2S
tRST
CE2 (Input)
tCES
tCHML
tMHCL
/CE1 (Input)
Synchronous Burst Operation
Reset to Page Standby Mode2
Parameter
Symbol
Reset to asynchronous page and standby mode2 entry
Asynchronous Page Operation
MIN.
MAX.
Unit
Note
tCHML
0
ns
tMHCL
30
ns
1
300
μs
2
/CE1 HIGH to CE2 LOW
Reset to asynchronous page and standby mode2 to normal operation
CE2 HIGH to /CE1 LOW
/CE1 = HIGH setup time to CLK
tCES
5
ns
CE2 = LOW hold time to CLK
tCE2S
1
ns
Reset time to asynchronous page mode
tRST
70
ns
Notes 1.
2.
In case the density for partial refresh are 32M bits / 16M bits / 8M bits in standby mode2
In case the density for partial refresh is 0M bits in standby mode2
Preliminary Data Sheet M17507EJ2V0DS
27
μ PD46128512-X
5. Mode Register Settings
The μPD46128512-X has several modes, Page Read mode, Burst Read mode, Burst write mode, Single Write mode,
Asynchronous Write mode, Deep Power Down mode, Partial Refresh mode.
Mode Resister setting defines Partial Refresh Density, Burst Length, Latency, Burst Sequence, Write mode (Burst or
Single), Valid Clock Edge, Support burst write suspend/resume or not .
The several modes can be set using mode register. Since the initial value of the mode register at power application is
undefined, be sure to set the mode register after initialization at power application.
5.1 Mode Register Setting Method
To set each mode, write any data twice, write specific data twice, read any address in succession after the highest
address (7FFFFFH) is read (6 cycles in total).
Cycle
Operation
Address
Data
1st cycle
Read
7FFFFFH
Read Data (RDa)
2nd cycle
Write
7FFFFFH
RDa
Note
or Don’t care
Note
or Don’t care
3rd cycle
Write
7FFFFFH
RDa
4th cycle
Write
7FFFFFH
Code 1
5th cycle
Write
7FFFFFH
Code 2
6th cycle
Read
Don’t care
Read Data (RDb)
Note In order to hold the highest address (7FFFFFH) cell data during mode register setting, be sure to set the same
data with 1st cycle read data in the 2nd and 3rd cycle (write cycle).
Commands are written to the command register. The command register is used to latch the addresses and data
required for executing commands, and it does not have an exclusive memory area.
For the timing chart and flow chart, refer to Figure 9-1. Mode Register Setting Timing Chart (Asynchronous
Timing + CLK fixed LOW/HIGH), Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + toggle
CLK), Figure 9-3. Mode Register Setting Timing Char t (Synchronous Timing), Figure 9-4. Mode Register Setting
Flow Chart. Table 5-1, Table 5-2 shows the commands and command sequences.
5.2 Cautions for Setting Mode Register
Since, for the mode register setting, the internal counter status is judged by toggling /CE1 and /OE, toggle /CE1 at
every cycle during entry (one read cycle, four write cycles and one read cycle), and toggle /OE like /CE1 at the first and
the 6th read cycles.
If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the
mode register is not performed correctly.
Cancellation of the mode register setting must be performed before the write in the 3rd bus cycle is determined.
Cancellation in the 4th bus cycle or later should not be performed. If performed, data and previous register setting are
not guaranteed, so the mode register must be re-setup after the 6th bus cycle is complete.
When the highest address (7FFFFFH) is read consecutively two or more times, the mode register setting entries are
not performed correctly. Mode setting is available after power application and read or write operation other than the
highest address (7FFFFFH) are performed.
Once the several modes have been set in the mode register, these settings are retained until they are set again, while
applying the power supply. However, the mode register setting will become undefined except page mode (M = 1) if the
power is turned off, so set the mode register again after power application.
28
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
For the timing chart and flow chart, refer Figure 9-1. Mode Register Setting Timing Chart (Asynchronous Timing
+ CLK fixed LOW/HIGH), Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + toggle CLK),
Figure 9-3. Mode Register Setting Timing Char t (Synchronous Timing), Figure 9-4. Mode Register Setting Flow
Chart.
Table 5-1. Mode Register Definition (4th Bus Cycle)
Data Code
DQ1, DQ0
DQ4 to DQ2
Symbol
PS
Function
Partial Refresh Density
BL
Burst Length
Value
00
32M bit
01
16M bit
10
8M bit
11
0M bit
010
8 word
011
16 word
111
Continuous
Others
DQ5
M
DQ6
Function Mode
VE
Valid Clock Edge
−
DQ15 to DQ7
−
Description
Reserved
0
Burst
1
Page
0
Falling Edge
1
Rising Edge
111111111
Reserved (All “1” are necessary)
Table 5-2. Mode Register Definition (5th Bus Cycle)
Data Code
DQ2 to DQ0
Symbol
RL
Function
Value
Read Latency
010
5 (Write Latency = 4)
(Write Latency)
011
6 (5)
100
7 (6)
101
8 (7)
110
9 (8)
111
10 (9)
Others
DQ3
DQ4
SW
DQ15 to DQ8
RP
−
Reserved
0
Burst Read & Burst Write
1
Burst Read & Single Write
0
Single clock control without suspend
1
Level control with suspend
−
11
Reserved (All “1” are necessary)
Reset to Page mode
0
Reset available to Page mode
1
Reset not available to Page mode
/WE Control
−
DQ6, DQ5
DQ7
Single Write
WC
Description
−
11111111
Preliminary Data Sheet M17507EJ2V0DS
Reserved (All “1” are necessary)
29
μ PD46128512-X
5.3 Partial Refresh Density
The density for performing refresh in power down mode can be set with mode register. Setting DQ1 and DQ0 to 00 at
the 4th bus cycle sets a partial refresh density of 32 M-bit hold; setting DQ1 and DQ0 to 01 at the 4th bus cycle sets a
partial refresh density of 16 M-bit hold; setting DQ1 and DQ0 to 10 at the 4th bus cycle sets a partial refresh density of 8
M-bit hold; and setting DQ1 and DQ0 to 11 at the 4th bus cycle sets a partial refresh density of 0 (no hold).
Since the Partial Refresh mode is not entered unless CE2 = LOW, when partial refresh is not used, it is not necessary
to set the mode register.
5.4 Burst Length
Sets the burst length in the burst mode. Setting DQ4 to DQ2 to 010 at the 4th bus sets 8word of burst length; setting
DQ4 to DQ2 to 011 at the 4th bus cycle sets 16word of burst length; setting DQ4 to DQ2 to 111 at the 4th bus cycle sets
continuous of burst length
5.5 Function Mode
Select function mode. Setting DQ5 to 0 at the 4th bus sets a function mode of burst and setting DQ5 to 1 at the 4th
bus sets a function mode of page. After power application, page mode is set as an initial state.
5.6 Valid Clock Edge
Select valid clock edge (Rising edge or Falling edge) in the burst mode. Setting DQ6 to 0 at the 4th bus cycle sets
clock falling edge; setting DQ6 to 1 at the 4th bus cycle sets clock rising edge.
5.7 Read Latency (Write Latency)
Sets the number of clock cycles (latency) between the address input and the output of the first data in the burst read
mode, the address input and the write data input in the burst write mode. Setting DQ2 to DQ0 to 010 at the 5th bus cycle
sets read latency of 5; setting DQ2 to DQ0 to 011 at the 5th bus sets read latency of 6; setting DQ2 to DQ0 to 100 at the
5th bus sets read latency of 7; setting DQ2 to DQ0 to 101 at the 5th bus sets read latency of 8; setting DQ2 to DQ0 to
110 at the 5th bus sets read latency of 9; setting DQ2 to DQ0 to 111 at the 5th bus sets read latency of 10. Once specific
RL is set through Mode Register Setting sequence, write latency, that is the number of clock cycles between address
input and first write data input, is automatically set to RL−1.
For the latency count, refer to Figure 4-1. Latency Definition
5.8 Single Write
Sets the write mode. Setting DQ3 to 0 at the 5th bus cycle sets burst write mode; setting DQ3 to 1 at the 5th bus cycle
sets single write mode.
30
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
5.9 /WE Control
Sets the /WE timing in burst write operation and burst write suspend / resume available or not. Setting DQ4 to 0 at the
5th bus cycle sets /WE single clock control, and burst write suspend / resume are not supported. In single clock control,
/WE is available at the 1st clock edge of /ADV = LOW; setting DQ4 to 1 at the 5th bus cycle sets /WE level control, and
burst write suspend / resume are supported. In level control, /WE is sure to transfer LOW to HIGH after latching last
write data in burst write operation.
Refer to Figure 8-8.
Synchronous Burst Write Cycle Timing Chart (/WE level Control), Figure 8-9.
Synchronous Burst Write Cycle Timing Chart (/WE single clock control), Figure 8-11. Synchronous Burst Write
Suspend Timing Chart.
5.10 Reset to Page Mode
Sets the Reset function from synchronous burst mode to asynchronous page mode. Setting DQ7 to 0 at the 5th bus
cycle sets reset available from synchronous burst mode to asynchronous page mode. Setting DQ7 to 1 at the 5th bus
cycle sets reset unavailable.
5.11 Reserved Bits
Reserved bits must be 1 because reserved bits are used for internal test mode entry. Be sure to set DQ15 to DQ7 to 1
at the 4th and DQ15 to DQ8 and DQ6 and DQ5 at the 5th bus cycles.
Preliminary Data Sheet M17507EJ2V0DS
31
μ PD46128512-X
5.12 Cautions for Timing Chart of Setting Mode Register
Timing charts for setting mode register are following 3 methods.
<Setting 1> Setting method by CLK fixed HIGH or LOW at asynchronous timing (asynchronous timing)
<Setting 2> Setting method by toggling CLK at asynchronous timing (asynchronous timing+ toggle CLK)
<Setting 3> Setting method at synchronous timing (synchronous timing)
For timing chart, refer to Figure 9-1. Mode Register Setting Timing Chart (asynchronous timing+ CLK fixed
LOW/HIGH), Figure 9-2. Mode Register Setting Timing Chart (asynchronous timing+ toggle CLK), Figure 9-3.
Mode Register Setting Timing Chart (synchronous timing).
It is recommended to set Mode Register contents through <Setting 1>, since <Setting 1> is used regardless of device
status, asynchronous or synchronous.
<Setting 2> procedure can be performed when the device is in the asynchronous (page) mode. In case the mode
register setting is possible only with <Setting 2> procedure, “reset to page” function using the CE2 signal toggling will be
required in changing the operation from synchronous (burst) mode to asynchronous (page) mode. (Refer to 4.11 Reset
Function from Synchronous Burst Mode to Asynchronous Page Mode)
<Setting 3> procedure can be performed when the device is in the synchronous (burst) mode.
Figure 5-1. Mode Register Setting State Machine
Power On
Asynchronous Mode
(Default)
<Setting 1>
<Setting 2>
<Setting 1>
<Setting 2>
<Setting 1>
<Setting 2>
Asynchronous
Mode
Synchronous
Mode
<Setting 1>
<Setting 3>
<Setting 1>
<Setting 2>
32
<Setting 1>
<Setting 3>
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
6. Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Condition
Rating
VCC
Supply voltage for Output
VCCQ
Unit
–0.5
Note
to +2.5
V
–0.5
Note
to +2.5
V
–0.5
Note
Input / Output voltage
VT
to 2.5
V
Operating ambient temperature
TA
–30 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Note –1.0 V (MIN.) (Pulse width: 30 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
VCCQ
Input HIGH voltage
VIH
VIL
Operating ambient temperature
TA
Notes 1.
2.
MIN.
MAX.
Unit
1.7
2.0
V
1.7
2.0
V
0.8VCC
VCC+0.3
V
0.2VCC
V
+85
°C
Note1
Supply voltage for Output
Input LOW voltage
Condition
Note1
–0.3
Note2
–30
Use same voltage condition (VCC = VCCQ)
–0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
CIN
VIN = 0 V
8
pF
Input / Output capacitance
CDQ
VDQ = 0 V
10
pF
Remarks 1.
2.
VIN: Input voltage, VDQ: Input / Output voltage
These parameters are not 100% tested.
Preliminary Data Sheet M17507EJ2V0DS
33
μ PD46128512-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
Density of
MIN.
TYP.
Note1
MAX.
Unit
data hold
Input leakage current
ILI
VIN = 0 V to VCC
–1.0
+1.0
μA
DQ leakage current
ILO
VDQ = 0 V to VCCQ, /CE1 = VIH or
–1.0
+1.0
μA
mA
/WE = VIL or /OE = VIH
Operating supply
ICCA1
current
ICCA2
/CE1 = VIL, IDQ = 0 mA,
Cycle time = 70 ns
60
Asynchronous mode
Cycle time = 85 ns
50
/CE1 = VIL, Frequency = 83 MHz, RL = 7,
50
mA
30
mA
μA
IDQ = 0 mA, burst length = 1,
Synchronous mode
Operating supply Burst
ICCA3
current
/CE1 = VIL, Frequency = 83MHz, RL = 7,
IDQ = 0 mA, burst length = Continuous
Standby supply current
ISB1
ISB2
/CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V
/CE1 ≥ VCC − 0.2 V, CE2 ≤ 0.2 V
128M bits
Note2
80
250
32M bits
Note2
T.B.D.
T.B.D.
16M bits
Note2
T.B.D.
T.B.D.
T.B.D.
T.B.D.
15
65
8M bits
Note2
0M bit
Output HIGH voltage
VOH
IOH = –0.5 mA
Output LOW voltage
VOL
IOL = 1 mA
Notes 1.
2.
0.8VCCQ
0.2VCCQ
V
TYP. means reference value measured at TA = 25°C. This value is not a guarantee value.
The current measured more than 30 ms after standby mode entry (/CE1 changes from LOW to HIGH).
It is specified as 2 mA (MAX.) in case of less than 30 ms after /CE1 transition.
Remark VIN: Input voltage, VDQ: Input / Output voltage
34
V
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[For DQ pins]
Input Waveform (Rise and Fall Time ≤ 3 ns)
Vcc
0.8Vcc
Vcc / 2
0.2Vcc
GND
Test Points
Vcc / 2
tT
Parameter
Symbol
Transition time
tT
Test Condition
The transition time from 0.8VCC to 0.2VCC
MAX.
Unit
3
ns
MAX.
Unit
3
ns
and from 0.2VCC to 0.8VCC
Output Waveform
VccQ / 2
Test Points
VccQ / 2
Output Load
30 pF
[For all other input pins]
Input Waveform (Rise and Fall Time ≤ 3 ns)
Vcc
0.8Vcc
Vcc / 2
0.2Vcc
GND
Test Points
Vcc / 2
tT
Parameter
Transition time
Symbol
tT
Test Condition
The transition time from 0.8VCC to 0.2VCC
and from 0.2VCC to 0.8VCC
Preliminary Data Sheet M17507EJ2V0DS
35
μ PD46128512-X
7. Asynchronous AC Specification, Timing Chart
Asynchronous Read Cycle
Parameter
Symbol
-E9X, -E11X
MIN.
Read cycle time
tRC
-E10X, -E12X
MAX.
70
MIN.
Unit
Note
ns
1
MAX.
85
Address access time
tAA
70
85
/CE1 access time
tACE
70
85
ns
/OE to output valid
tOE
45
60
ns
/LB, /UB to output valid
tBA
Output hold from address change
tOH
3
Page read cycle time
tPRC
20
Page access time
tPAA
/CE1 to output in low impedance
tCLZ
10
10
ns
/OE to output in low impedance
tOLZ
5
5
ns
/LB, /UB to output in low impedance
tBLZ
5
5
/CE1 to output in high impedance
tCHZ
9
9
ns
/OE to output in high impedance
tOHZ
9
9
ns
/LB, /UB to output in high impedance
tBHZ
9
9
ns
15
ns
45
60
3
–15
ns
ns
25
20
ns
ns
25
ns
ns
Address set to /CE1 LOW
tASC
Address invalid time
tAX
–15
Address set to /OE LOW
tASO
0
0
ns
/OE HIGH to address hold
tOHAH
−5
−5
ns
/CE1 HIGH to address hold
tCHAH
0
0
ns
15
tCLOL
−5
/OE LOW to /CE1 HIGH
tOLCH
45
60
ns
Address set to /ADV HIGH
tASV
7
7
ns
/ADV HIGH to address hold
tAH
3
3
ns
/ADV LOW pulse width
tVPL
7
7
ns
/CE1 HIGH pulse width
tCP
10
10
ns
/LB, /UB HIGH pulse width
tBP
10
10
/OE HIGH pulse width
tOP
10
/OE HIGH to /WE set
tOES
10
10,000
10
10,000
ns
/WE HIGH to /OE set
tOEH
10
10,000
10
10,000
ns
10,000
−5
ns
/CE1 LOW to /OE LOW
Notes 1.
+10,000
10
Output load: 30 pF
2.
Output load: 5 pF
3.
tAX (MAX.) is applied while /CE1, /OE and /ADV are being hold at LOW.
4.
When tASO ≥ | tCHAH |, tCHAH (MIN.) is −15 ns.
t CHAH
Address (Input)
/CE1 (Input)
/OE (Input)
t ASO
5.
36
tOP, tOES and tOEH (MAX.) are applied while /CE1 is being hold at LOW.
Preliminary Data Sheet M17507EJ2V0DS
2
+10,000
3
4
ns
ns
10,000
ns
5
μ PD46128512-X
Asynchronous Write Cycle
Parameter
Symbol
-E9X, -E11X
MIN.
MAX.
-E10X, -E12X
MIN.
Unit
MAX.
Write cycle time
tWC
70
85
ns
/CE1 to end of write
tCW
50
60
ns
Address valid to end of write
tAW
55
60
ns
/LB, /UB to end of write
tBW
50
60
ns
Write pulse width
tWP
50
55
ns
Write recovery time
tWR
0
0
ns
Write recovery time (/WE = HIGH → /CE1 = HIGH)
tWHCH
0
/CE1 pulse width
tCP
10
10
ns
/LB, /UB HIGH pulse width
tBP
10
10
ns
/WE HIGH pulse width
tWHP
10
10
ns
/WE HIGH pulse width (/CE1 = LOW)
tWHP1
10
Address setup time
tAS
0
0
ns
/CE1 HIGH to address hold
tCHAH
0
0
ns
/LB, /UB HIGH to address hold
tBHAH
0
0
ns
/LB, /UB byte mask setup time
tBS
0
0
ns
/LB, /UB byte mask hold time
tBH
0
0
ns
/LB, /UB byte mask over wrap time
tBWO
30
30
ns
Data valid to end of write
tDW
25
25
ns
Data hold time
tDH
0
0
ns
Address set to /ADV HIGH
tASV
7
7
ns
/ADV HIGH to address hold
tAH
3
3
ns
/ADV LOW pulse width
tVPL
7
7
ns
/OE HIGH to /WE set
tOES
10
10,000
10
10,000
ns
/WE HIGH to /OE set
tOEH
10
10,000
10
10,000
ns
Notes 1.
10,000
10,000
0
10
Note
10,000
10,000
ns
ns
1
2
When tAS ≥ | tCHAH | and tCP ≥ 18 ns, tCHAH (MIN.) is –15 ns.
tCHAH
Address (Input)
/CE1 (Input)
/OE (Input)
tASO
2.
tOES and tOEH (MAX.) are applied while /CE1 is being hold at LOW.
Preliminary Data Sheet M17507EJ2V0DS
37
μ PD46128512-X
Figure 7-1. Asynchronous Read Cycle Timing Chart 1 (Basic Timing1)
tRC
A1
Address (Input)
/ADV (Input)
L
tACE
tASC
tCHAH
/CE1 (Input)
tCP
tCLZ
tCLOL
tCHZ
tOE
/OE (Input)
tOHZ
tOLZ
tBA
/LB, /UB (Input)
tBHZ
tBLZ
High-Z
DQ (Output)
Cautions 1.
2.
High-Z
Data Out Q1
In read cycle, CE2 and /WE should be fixed HIGH.
CLK should be fixed HIGH or LOW.
Figure 7-2. Asynchronous Read Cycle Timing Chart 2-1 (Basic Timing2-1)
tRC
Address (Input)
A1
A2
tASV
tAH
tVPL
/ADV (Input)
tASC
tVPL
tASC
tACE
/CE1 (Input)
tCP
tCLOL
tCHZ
tOE
/OE (Input)
tOHZ
tOLZ
tBA
/LB, /UB (Input)
tBHZ
tBLZ
DQ (Output)
Cautions 1.
2.
38
High-Z
Data Out Q1
In read cycle, CE2 and /WE should be fixed HIGH.
CLK should be fixed HIGH or LOW.
Preliminary Data Sheet M17507EJ2V0DS
High-Z
μ PD46128512-X
Figure 7-3. Asynchronous Read Cycle Timing Chart 2-2 (Basic Timing2-2)
tRC
Address (Input)
A1
A2
tASV
tAH
tVPL
/ADV (Input)
tASC
tVPL
tASC
tACE
/CE1 (Input)
tCP
tCHZ
/OE (Input)
L
tBA
/LB, /UB (Input)
tBHZ
tBLZ
High-Z
DQ (Output)
Cautions 1.
2.
High-Z
Data Out Q1
In read cycle, CE2 and /WE should be fixed HIGH.
CLK should be fixed HIGH or LOW.
Figure 7-4. Asynchronous Read Cycle Timing Chart 2-3 (Basic Timing2-3)
Address (Input)
A1
A2
tASV
tAH
tVPL
/ADV (Input)
tRC
tAA
/CE1 (Input)
tASO
L
tASO
tOE
/OE (Input)
tOHZ
tOLZ
tBA
/LB, /UB (Input)
tBHZ
tBLZ
DQ (Output)
Cautions 1.
2.
High-Z
Data Out Q1
High-Z
In read cycle, CE2 and /WE should be fixed HIGH.
CLK should be fixed HIGH or LOW.
Preliminary Data Sheet M17507EJ2V0DS
39
μ PD46128512-X
Figure 7-5. Asynchronous Read Cycle Timing Chart 3 (/CE1 Controlled)
tRC
tRC
tCHAH
tACE
tASC
A3
A2
A1
Address (Input)
tASC
tCHAH
tACE
/CE1 (Input)
tCP
tCP
tCLZ
/OE (Input)
L
/LB, /UB (Input)
L
tCLZ
tCHZ
High-Z
DQ (Output)
tCHZ
High-Z
Cautions 1.
High-Z
Data Out Q2
Data Out Q1
In read cycle, CE2 and /WE should be fixed HIGH.
2. /ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Figure 7-6. Asynchronous Read Cycle Timing Chart 4 (/OE Controlled)
tRC
Address (Input)
tRC
tAA
tAA
/CE1 (Input)
A3
A2
A1
L
tASO
tOE
tASO
tOHAH
tOE
tASO
tOHAH
/OE (Input)
tOP
tOP
/LB, /UB (Input)
tOLZ
High-Z
DQ (Output)
tOLZ
High-Z
Data Out Q1
Cautions 1.
2.
40
tOHZ
tOHZ
Data Out Q2
High-Z
In read cycle, CE2 and /WE should be fixed HIGH.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 7-7. Asynchronous Read Cycle Timing Chart 5 (/CE1, /OE Controlled)
tRC
Address (Input)
tRC
A2
A1
tCHAH
tAA
tOHAH
tACE
A3
tOLCH
/CE1 (Input)
tCHZ
tCLZ
tCLOL
/OE (Input)
tOE
tOE
tASO
tOHZ
tOHAH
tASO
tOHZ
tOLZ
tOLZ
/LB, /UB (Input)
High-Z
DQ (Output)
Cautions 1.
2.
High-Z
Data Out Q1
High-Z
Data Out Q2
In read cycle, CE2 and /WE should be fixed HIGH.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Figure 7-8. Asynchronous Read Cycle Timing Chart 6 (Address Controlled)
tRC
tRC
A2
A1
Address (Input)
tAX
/CE1 (Input)
L
/OE (Input)
L
/LB, /UB (Input)
L
tAA
tAX
tOH
DQ (Output)
tAA
2.
tOH
tOH
Data Out Q1
Cautions 1.
A3
Data Out Q2
In read cycle, CE2 and /WE should be fixed HIGH.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Preliminary Data Sheet M17507EJ2V0DS
41
μ PD46128512-X
Figure 7-9. Asynchronous Read Cycle Timing Chart 7 (/LB, /UB Controlled)
tRC
tRC
Address (Input)
A2
A1
tAX
/CE1 (Input)
L
/OE (Input)
L
tAX
tAA
/LB, /UB (Input)
A3
tAA
tBP
tBP
tBA
tBA
tBHZ
tBLZ
High-Z
DQ (Output)
Cautions 1.
2.
tBHZ
tBLZ
High-Z
Data Out Q1
High-Z
Data Out Q2
In read cycle, CE2 and /WE should be fixed HIGH.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Figure 7-10. Asynchronous Page Read Cycle Timing Chart
tRC
tPRC
tPRC
tPRC
tPRC
tPRC
tPRC
tPRC
AN+2
AN+3
AN+4
AN+5
AN+6
AN+7
Address
(A4-A22) (Input)
Page Address
(A0-A3) (Input)
AN
AN+1
tOH
/CE1 (Input)
tCHZ
tASO
tOE
/OE (Input)
tAA
tPAA
tPAA
tPAA
tPAA
tPAA
tPAA
tOH
tOH
tOH
tOH
tOH
tOH
tOH
High-Z
DQ (Output)
QN
Cautions 1.
2.
42
tOHZ
tPAA
QN+1
QN+2
QN+3
QN+4
QN+5
In read cycle, CE2 and /WE should be fixed HIGH.
/LB and /UB should be fixed LOW.
3.
/ADV should be fixed LOW. CLK should be fixed HIGH or LOW.
4.
Fix /CE1 and /OE to LOW throughout a page operation.
5.
Arbitrary order and combination of A0-A3 is possible in the page operation.
Preliminary Data Sheet M17507EJ2V0DS
QN+6
QN+7
μ PD46128512-X
Figure 7-11. Asynchronous Write Cycle Timing Chart 1 (Basic Timing1)
tWC
A1
Address (Input)
/ADV (Input)
L
tAS
tCW
tWR
/CE1 (Input)
tAS
tWP
tWR
tAS
tBW
tWR
/WE (Input)
/LB, /UB (Input)
tOES
/OE (Input)
tDW
High-Z
DQ (Input)
Cautions 1.
tDH
High-Z
Data In D1
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
Preliminary Data Sheet M17507EJ2V0DS
43
μ PD46128512-X
Figure 7-12. Asynchronous Write Cycle Timing Chart 2 (Basic Timing2)
tWC
tWC
A1
Address (Input)
A2
tASV
tAH
tVPL
/ADV (Input)
tVPL
tASC
tCW
tWR
tAS
/CE1 (Input)
tAS
tWP
tWR
tAS
tAS
tBW
tWR
tAS
/WE (Input)
/LB, /UB (Input)
tOES
/OE (Input)
tDW
High-Z
DQ (Input)
Cautions 1.
tDH
Data In D1
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
44
High-Z
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 7-13. Asynchronous Write Cycle Timing Chart 3 (/CE1 Controlled)
Address (Input)
tAS
tWC
tWC
A1
A2
tAS
tWR
tCW
A3
tCW
tWR
/CE1 (Input)
tCP
/WE (Input)
L
/LB, /UB (Input)
L
tCP
tASO
tOHAH
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ (Input)
Cautions 1.
tDH
Data In D1
tDW
High-Z
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
Preliminary Data Sheet M17507EJ2V0DS
45
μ PD46128512-X
Figure 7-14. Asynchronous Write Cycle Timing Chart 4 (/WE Controlled)
tWC
Address (Input)
tWC
A3
A2
A1
tCHAH
tCW
tCHAH
tCW
/CE1 (Input)
tAS
tWP
tWHCH
/WE (Input)
tCP
tAS
tWP
tWHCH
tCP
tWHP
/LB, /UB (Input)
tOHAH
tASO
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ (Input)
Cautions 1.
tDH
Data In D1
tDW
High-Z
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
46
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 7-15. Asynchronous Write Cycle Timing Chart 5 (/WE Controlled)
Address (Input)
tWC
tWC
A1
A2
tAW
/CE1 (Input)
A3
tAW
L
tAS
tWP
tWR
tAS
tWP
tWR
/WE (Input)
tWHP1
/LB, /UB (Input)
tOHAH
tASO
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ (Input)
Cautions 1.
tDH
Data In D1
tDW
High-Z
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
Preliminary Data Sheet M17507EJ2V0DS
47
μ PD46128512-X
Figure 7-16. Asynchronous Write Cycle Timing Chart 6 (/LB, /UB Controlled)
Address (Input)
/CE1 (Input)
tWC
tWC
A1
A2
A3
L
/WE (Input)
tAS
tBW
/LB, /UB (Input)
tBW
tAS
tWR
tWR
tBP
tBP
tOHAH
tASO
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ (Input)
Cautions 1.
tDH
Data In D1
tDW
High-Z
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
48
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 7-17. Asynchronous Write Cycle Timing Chart 7 (/LB, /UB Independent Controlled 1)
Address (Input)
/CE1 (Input)
tWC
tWC
A1
A2
A3
L
/WE (Input)
tAS
tWR
tBW
/LB (Input)
tAS
/UB (Input)
tBW
tWR
tBP
tOHAH
tASO
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ0 to DQ7 (Input)
tDH
Data In D1
High-Z
tDW
High-Z
DQ8 to DQ15 (Input)
Cautions 1.
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
Preliminary Data Sheet M17507EJ2V0DS
49
μ PD46128512-X
Figure 7-18. Asynchronous Write Cycle Timing Chart 8 (/LB, /UB Independent Controlled 2)
Address (Input)
/CE1 (Input)
tWC
tWC
A1
A2
A3
L
tBW
tAS
tWR
/WE (Input)
tWP
tBH
tWR
/LB (Input)
tBS
tAS
/UB (Input)
tBP
tASO
tOHAH
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ0 to DQ7 (Input)
tDH
Data In D1
High-Z
tDW
High-Z
DQ8 to DQ15 (Input)
Cautions 1.
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
50
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 7-19. Asynchronous Write Cycle Timing Chart 9 (/LB, /UB Independent Controlled 3)
Address (Input)
/CE1 (Input)
tWC
tWC
A1
A2
A3
L
tAS
tWP
tAS
tWR
tWP
tWR
/WE (Input)
tWHP1
tBH
tBS
/LB (Input)
tBH
tBS
/UB (Input)
tOHAH
tASO
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ0 to DQ7 (Input)
tDH
High-Z
Data In D1
tDW
High-Z
DQ8 to DQ15 (Input)
Cautions 1.
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
Preliminary Data Sheet M17507EJ2V0DS
51
μ PD46128512-X
Figure 7-20. Asynchronous Write Cycle Timing Chart 10 (/LB, /UB Independent Controlled 4)
Address (Input)
/CE1 (Input)
tWC
tWC
A1
A2
A3
L
tAS
tWR
tBW
tAS
tBW
tWR
/WE (Input)
tWHP1
tBH
tBS
/LB (Input)
tBS
tBH
/UB (Input)
tOHAH
tASO
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ0 to DQ7 (Input)
tDH
High-Z
Data In D1
tDW
High-Z
DQ8 to DQ15 (Input)
Cautions 1.
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
52
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 7-21. Asynchronous Write Cycle Timing Chart 11 (/LB, /UB Independent Controlled 5)
Address (Input)
/CE1 (Input)
tWC
tWC
A1
A2
A3
L
tAS
tBW
tAS
tWR
tBW
tWR
/WE (Input)
tWHP1
tBS
tBH
/LB (Input)
tBS
tBH
/UB (Input)
tOHAH
tASO
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ0 to DQ7 (Input)
tDH
High-Z
Data In D1
tDW
High-Z
DQ8 to DQ15 (Input)
Cautions 1.
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
Preliminary Data Sheet M17507EJ2V0DS
53
μ PD46128512-X
Figure 7-22. Asynchronous Write Cycle Timing Chart 12 (/LB, /UB Independent Controlled 6)
tWC
Address (Input)
tWC
A1
/CE1 (Input)
A3
A2
L
/WE (Input)
tBW
tAS
tAS
tWR
tWR
tBW
/LB (Input)
tAS
tBW
tWR
tAS
tBWO
tBW
tWR
tBWO
/UB (Input)
tOHAH
tASO
tOES
tOEH
/OE (Input)
tDW
High-Z
DQ0 to DQ7 (Input)
Data In D1
tDW
High-Z
DQ8 to DQ15 (Input)
Cautions 1.
tDW
tDH
tDH
Data In D1
tDH
Data In D2
tDW
High-Z
tDH
Data In D2
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
54
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 7-23. Asynchronous Write-Read Cycle Timing Chart
tWC
Address (Input)
tRC
A1
tAS
tCW
tRC
tAA
/CE1 (Input)
tCHZ
tAS
tWP
/WE (Input)
tOEH
tOE
tOHZ
/OE (Input)
tOLZ
tAS
tBW
tBHZ
/LB, /UB (Input)
tDW
High-Z
DQ (Input/Output)
Cautions 1.
tDH
Data In D1
High-Z
Data Out Q1
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
Preliminary Data Sheet M17507EJ2V0DS
55
μ PD46128512-X
Figure 7-24. Asynchronous Read-Write Cycle Timing Chart
tRC
tRC
tWC
Address (Input)
A1
tAA
tWR
tACE
tCW
/CE1 (Input)
tCLZ
tWP
tWR
/WE (Input)
tASO
tOE
tOES
/OE (Input)
tOLZ
tOHZ
tWR
tBA
tBW
/LB, /UB (Input)
tBLZ
tDW
High-Z
DQ (Input/Output)
Cautions 1.
High-Z
Data Out Q1
tDH
Data In D1
High-Z
During address transition, at least one of pins /CE1 and /WE, or both of /LB and /UB pins should
be inactivated.
2.
Do not input data to the DQ pins while they are in the output state.
3.
In write cycle, CE2 and /OE should be fixed HIGH.
4.
/ADV should be fixed LOW or toggled HIGH → LOW → HIGH. CLK should be fixed HIGH or LOW.
Remark Write operation is done during the overlap time of LOW of following signals.
• /CE1
• /WE
• /LB and/or /UB
56
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
8. Synchronous AC Specification, Timing Chart
Synchronous Read / Write Common Specification
Parameter
Symbol
-E9X, -E10X
-E11X, -E12X
MIN.
MAX.
MIN.
MAX.
0.1
108
0.1
83
Unit
Note
MHz
1
Clock Specifications
Cycle frequency
tCYCLE
CLK HIGH width
tCH
3
3
ns
CLK LOW width
tCL
3
3
ns
CLK rise / fall time
tCHCL
3
3
ns
Address Latching Specifications
Address setup time to CLK
tACS
5
5
ns
Address hold time to CLK
tACH
4
4
ns
/ADV setup time to CLK
tCSV
5
/ADV hold time from CLK
tCHV
1
1
ns
/ADV = LOW pulse width
tVPL
7
7
ns
Address hold time from /ADV = HIGH
tAH
3
3
ns
/CE1 setup time to CLK
tCES
5
5
ns
/CE1 to output in low impedance
tCLZ
10
10
ns
/OE to output in low impedance
tOLZ
5
5
ns
/LB, /UB to output in low impedance
tBLZ
5
5
ns
/CE1 to output in high impedance
tCHZ
9
9
ns
/OE to output in high impedance
tOHZ
9
9
ns
/LB, /UB to output in high impedance
tBHZ
9
9
ns
/WAIT output time from /CE1 = LOW
tCEWA
10
13
ns
/WAIT output time from /ADV = LOW
tADWA
10
13
ns
/WAIT = HIGH output time from CLK
tCLWA
7
8
ns
/WAIT in high impedance from /CE1 = HIGH
tCWHZ
10
10
ns
10,000
5
10,000
ns
Asynchronous Specification
2
/WAIT Specification
3
2
Others
/CE1 hold time
tCEH
1
1
ns
/LB, /UB hold time
tLUH
1
1
ns
/CE1 HIGH pulse width
tCP
10
10
ns
Notes 1.
Case BL (Burst Length) = Continuous : 2 MHz (MIN.)
2.
Output load: 5 pF
3.
Output load: 30 pF
Preliminary Data Sheet M17507EJ2V0DS
57
μ PD46128512-X
Synchronous Burst Read Cycle
Parameter
Symbol
-E9X, -E10X
MIN.
MAX.
-E11X, -E12X
MIN.
Unit
Note
ns
1
MAX.
Synchronous Read Specifications
Burst access time
tBACC
Output data hold time
tBDH
2
2
ns
/OE setup time to CLK for data output
tOC
30
30
ns
/LB, /UB setup time to CLK for data output
tBC
30
30
ns
/OE setup time for burst read suspend
tSOES
5
5
ns
/OE hold time for burst read suspend
tSOEH
1
1
ns
Burst read suspend time (/OE = HIGH)
tSOP
9
Burst read termination recovery time
tTRB
18
Note1.
7
10,000
8
12
10,000
24
ns
ns
Output load: 30 pF
Synchronous Burst Write Cycle
Parameter
Symbol
-E9X, -E10X
MIN.
MAX.
-E11X, -E12X
MIN.
Unit
MAX.
Synchronous Write Specifications
/LB, /UB setup time to CLK
tBC
30
30
ns
tWES
5
5
ns
tWEH
1
1
ns
Write data setup time
tWDS
5
5
ns
Write data hold time
tWDH
1
1
ns
/WE HIGH pulse width
tSWHP
9
tWRB
2
2
CLK
tTRB
18
24
ns
for latching data
/WE setup time for CLK
(In /WE single clock control operation)
(In burst write suspend operation)
/WE hold time in the write operation
(In /WE single clock control operation)
(In burst write suspend operation)
/ADV LOW from CLK for latching the latest
data
Burst write termination recovery time
58
10,000
Preliminary Data Sheet M17507EJ2V0DS
12
10,000
ns
Note
μ PD46128512-X
Figure 8-1. Synchronous CLK Input Timing Chart
tCL
tCYCLE
tCH
tCHCL
VIH
CLK (Input)
VIL
Figure 8-2. Synchronous Burst Read Cycle Timing Chart (/CE1 Control)
T0
T1
T2
T3
T4
T5
T6
Tm
Tn
T0
T1
T2
T3
T4
tCYCLE
CLK (Input)
tCH
tACH
tACS
tCL
tCHCL
tCHCL
tACS
tACH
Valid
Valid
Address (Input)
tAH
tAH
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tVPL
tCES
tCES
tCLZ
tCEH
tCLZ
tCEWA
/CE1 (Input)
tCP
tCEWA
tCWHZ
/OE (Input)
L
/WE (Input)
H
/LB, /UB (Input)
L
tCLWA
High-Z
High-Z
/WAIT (Output)
tCHZ
RL = 5
tBACC
High-Z
DQ (Output)
Remarks 1.
tBDH
tBDH
Q0
Q1
QBL
High-Z
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
QBL means the latest data out of burst length.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
Preliminary Data Sheet M17507EJ2V0DS
59
μ PD46128512-X
Figure 8-3. Synchronous Burst Read Cycle Timing Chart (/ADV Control)
T0
T1
T2
T3
T4
T5
T6
Tm
Tn
T0
T1
T2
T3
tCYCLE
CLK (Input)
tACH
tACS
tCH
tCL
tCHCL
tCHCL
tACS
tACH
Valid
Valid
Address (Input)
tAH
tAH
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tVPL
tADWA
/CE1 (Input)
L
/OE (Input)
L
/WE (Input)
H
/LB, /UB (Input)
L
tADWA
tCLWA
tCLWA
/WAIT (Output)
RL = 5
tBACC
DQ (Output)
tBDH
Q0
Remarks 1.
tBDH
Q1
QBL
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
QBL means the latest data out of burst length.
60
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
Preliminary Data Sheet M17507EJ2V0DS
T4
μ PD46128512-X
Figure 8-4. Synchronous Burst Read Cycle Timing Chart (/OE Control)
T0
T1
T2
T3
T4
T5
T6
Tm
Tn
T0
T1
T2
T3
T4
tCYCLE
CLK (Input)
tACS
tCH
tACH
tCL
tCHCL
tCHCL
tACS
Valid
Address (Input)
tACH
Valid
tAH
tAH
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tVPL
tADWA
/CE1 (Input)
tADWA
L
tSOEH
tOC
/OE (Input)
tOLZ
/WE (Input)
tOHZ
tOLZ
tBHZ
tBLZ
H
tBC
/LB, /UB (Input)
tBLZ
tCLWA
tCLWA
/WAIT (Output)
RL = 5
tBACC
High-Z
DQ (Output)
Remarks 1.
tBDH
Q0
tBDH
Q1
QBL
High-Z
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
QBL means the latest data out of burst length.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tOC and tBC are defined from CLK rising edge of RL−1 to /OE = LOW, /LB and /UB = LOW.
Preliminary Data Sheet M17507EJ2V0DS
61
μ PD46128512-X
Figure 8-5. Synchronous Burst /WAIT Timing Chart (Continuous)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCYCLE
CLK (Input)
tACS
tCH
tACH
tCL
tCHCL
tCHCL
ADDmf
Address (Input)
tAH
tCHV tCSV tCHV
/ADV (Input)
tVPL
tCES
/CE1 (Input)
tCEWA
tCLZ
tOC
/OE (Input)
tOLZ
/WE (Input)
H
tBC
/LB, /UB (Input)
tBLZ
tCLWA
tCLWA
tCLWA
High-Z
/WAIT (Output)
RL = 5
tBACC
High-Z
DQ (Output)
Remarks 1.
tBDH
Qmf
Qn1
The above timing chart assumes Burst length is continuous.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tOC and tBC are defined from CLK rising edge of RL−1 to /OE = LOW, /LB and /UB = LOW.
5.
The above timing chart assumes Read Latency is 5 and start address is from xxxfH and the number of
dummy wait cycles are 5 cycles.
62
Qn0
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 8-6. Synchronous Burst Read Suspend Timing Chart
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCYCLE
CLK (Input)
tACS
tCH
tACH
tCL
tCHCL
tCHCL
Valid
Address (Input)
tAH
tCHV tCSV tCHV
/ADV (Input)
tVPL
tCES
tCLZ
tCEWA
/CE1 (Input)
tOC
tSOEH tSOES
tSOEH tSOES
tOLZ
/OE (Input)
tSOP
/WE (Input)
H
tBC
tBLZ
/LB, /UB (Input)
tCLWA
High-Z
/WAIT (Output)
RL = 5
tBACC
High-Z
DQ (Output)
Remarks 1.
tBDH
Q0
tBACC
High-Z
tBDH
Q1
Q2
Q3
Q4
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tOC and tBC are defined from CLK rising edge of RL−1 to /OE = LOW, /LB and /UB = LOW.
5.
Burst read suspend is valid after outputting the first read access data (Q0).
Preliminary Data Sheet M17507EJ2V0DS
63
μ PD46128512-X
Figure 8-7. Synchronous Burst Read Termination Cycle Timing Chart
T0
T1
T2
T3
T4
T0
T1
T2
T3
tCYCLE
CLK (Input)
tACS
tCH
tACH
tCL
tCHCL
tCHCL
Valid
Address (Input)
tACS
tACH
Valid
tAH
tAH
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tVPL
tCES
tCES
tCLZ
tCLZ
tCEH tCES
tCEWA
tCEWA
/CE1 (Input)
tTRB
tOC
tOLZ
/OE (Input)
/WE (Input)
H
tBC
tBLZ
/LB, /UB (Input)
tCWHZ
tCLWA
High-Z
High-Z
/WAIT (Output)
tCHZ
RL = 5
tBACC
High-Z
Remarks 1.
64
tBDH
Q0
DQ (Output)
High-Z
The above timing chart assumes Read Latency is 5.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tOC and tBC are defined from CLK rising edge of RL−1 to /OE = LOW, /LB and /UB = LOW.
5.
tTRB is specified from /CE1 de-assert to /CE1 assert for next operation.
6.
Burst read termination is valid after outputting the first read access data (Q0).
7.
In case continuous burst read is set, /CE1 de-assert is needed for burst read termination.
Preliminary Data Sheet M17507EJ2V0DS
T4
μ PD46128512-X
Figure 8-8. Synchronous Burst Write Cycle Timing Chart (/WE Level Control)
T0
T1
T2
T3
T4
T5
Tl
Tm
Tn
T0
T1
tCYCLE
CLK (Input)
tACS
tACH
tCH
tCL
tACS
Valid
Address (Input)
tACH
Valid
tAH
tAH
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tVPL
tWRB
tCES
tCEH tCES
tCEWA
tCEH tCWHZ
tCEWA
/CE1 (Input)
/OE (Input)
H
tWEH
tWES
/WE (Input)
tLUH
tBC
/LB, /UB (Input)
tCLWA
/WAIT (Output)
High-Z
High-Z
RL = 5
tWDS tWDH
DQ (Input)
Remarks 1.
High-Z
D0
D1
DBL
High-Z
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
DBL means the latest data input of burst length.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tBC is defined from CLK rising edge of RL−1 to /LB and /UB = LOW.
Preliminary Data Sheet M17507EJ2V0DS
65
μ PD46128512-X
Figure 8-9. Synchronous Burst Write Cycle Timing Chart (/WE Single Clock Control)
T0
T1
T2
T3
T4
T5
Tl
Tm
Tn
T0
T1
tCYCLE
CLK (Input)
tACS
tACH
tCH
tCL
tACS
Valid
Address (Input)
tACH
Valid
tAH
tAH
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tVPL
tWRB
tCES
tCEH tCES
tCEWA
tCEH tCWHZ
tCEWA
/CE1 (Input)
/OE (Input)
H
tWES tWEH
tWES tWEH
/WE (Input)
tLUH
tBC
/LB, /UB (Input)
tCLWA
/WAIT (Output)
High-Z
High-Z
RL = 5
tWDS tWDH
DQ (Input)
Remarks 1.
High-Z
D0
D1
DBL
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
DBL means the latest data input of burst length.
66
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tBC is defined from CLK rising edge of RL−1 to /LB and /UB = LOW.
Preliminary Data Sheet M17507EJ2V0DS
High-Z
μ PD46128512-X
Figure 8-10. Synchronous Single Write Cycle Timing Chart (/WE level Control)
T0
T1
T2
T3
T4
T0
T1
T2
T3
tCYCLE
CLK (Input)
tCH
tACH
tACS
tCL
tACS
Valid
Valid
Address (Input)
tACH
tAH
tAH
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tVPL
tWRB
tADWA
tCEH
tCES
tCES
/CE1 (Input)
tCEWA
/OE (Input)
tCEWA
H
tWEH
tWES
/WE (Input)
tBC
tLUH
/LB, /UB (Input)
tCLWA
High-Z
/WAIT (Output)
RL = 5
tWDS tWDH
High-Z
D0
DQ (Input)
Remarks 1.
High-Z
The above timing chart assumes Read Latency is 5.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tBC is defined from CLK rising edge of RL−1 to /LB and /UB = LOW.
Preliminary Data Sheet M17507EJ2V0DS
67
μ PD46128512-X
Figure 8-11. Synchronous Burst Write Suspend Timing Chart
T0
T1
T2
T3
T4
T5
T6
T7
T8
tCYCLE
CLK (Input)
tACS
tACH
tCH
tCL
tCHCL
tCHCL
Valid
Address (Input)
tAH
tCHV tCSV tCHV
/ADV (Input)
tVPL
tCES
tCEWA
/CE1 (Input)
/OE (Input)
H
tWEH tWES
tWES
tWEH tWES
/WE (Input)
tSWHP
tBC
/LB, /UB (Input)
tCLWA
High-Z
/WAIT (Output)
RL = 5
tWDS tWDH
High-Z
DQ (Input)
Remarks 1.
68
D0
tWDS tWDH
High-Z
The above timing chart assumes Read Latency is 5.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tBC is defined from CLK rising edge of RL−1 to /LB and /UB = LOW.
5.
Burst write suspend is valid after latching the first write data
Preliminary Data Sheet M17507EJ2V0DS
D1
D2
D3
D4
T9
μ PD46128512-X
Figure 8-12. Synchronous Burst Write Termination Timing Chart
T0
T1
T2
T3
T4
T0
T1
T2
T3
T4
tCYCLE
CLK (Input)
tCH
tCL
tCHCL
tCHCL
tACH
tACS
tACS
tACH
Valid
Valid
Address (Input)
tAH
tAH
tCHV tCSV tCHV
tCHV tCSV tCHV
/ADV (Input)
tVPL
tWRB
tVPL
tCES
tCES
tCEH tCES
tCEWA
tCEWA
/CE1 (Input)
tTRB
/OE (Input)
H
tWES
/WE (Input)
tBC
/LB, /UB (Input)
tCWHZ
tCLWA
tCLWA
High-Z
High-Z
/WAIT (Output)
RL = 5
tWDS tWDH
High-Z
D0
DQ (Input/Output)
Remarks 1.
tWDS tWDH
High-Z
D0
High-Z
The above timing chart assumes Read Latency is 5.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tBC is defined from CLK rising edge of RL−1 to /LB and /UB = LOW.
5.
Burst write suspend is valid after latching the first write data
6.
In case continuous burst write is set, /CE1 de-assert is needed for burst write termination.
Preliminary Data Sheet M17507EJ2V0DS
69
μ PD46128512-X
Figure 8-13. Synchronous Burst Read – Burst Write Cycle Timing Chart (/CE1 Control)
tCYCLE
CLK (Input)
tCH
tCL
tACH
tACS
Valid
Address (Input)
tAH
tCHV tCSV tCHV
/ADV (Input)
tVPL
tCES
tCEWA
tCEH
tCEH
/CE1 (Input)
tCP
tCHZ
tCWHZ
tCWHZ
tSOEH
/OE (Input)
tOHZ
tWES
tWEH
/WE (Input)
tLUH
tLUH
tBC
/LB, /UB (Input)
tCLWA
tBHZ
High-Z
/WAIT (Output)
High-Z
RL = 5
tBACC
DQ (Input/Output)
Remarks 1.
tBDH
tWDS tWDH
High-Z
QBL
D0
DBL
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
QBL means the latest data out of burst length. DBL means the latest data input of burst length.
70
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tBC is defined from CLK rising edge of RL−1 to /LB and /UB = LOW.
Preliminary Data Sheet M17507EJ2V0DS
High-Z
μ PD46128512-X
Figure 8-14. Synchronous Burst Read – Burst Write Cycle Timing Chart (/ADV Control)
tCYCLE
CLK (Input)
tCH
tCL
tACH
tACS
Valid
Address (Input)
tAH
tCHV tCSV tCHV
/ADV (Input)
tVPL
/CE1 (Input)
L
tSOEH
/OE (Input)
tOHZ
tWES
tWEH
/WE (Input)
tLUH
tLUH
tBC
/LB, /UB (Input)
tBHZ
tCLWA
tADWA
High-Z
/WAIT (Output)
RL = 5
tBACC
DQ (Input/Output)
Remarks 1.
tBDH
tWDS tWDH
High-Z
QBL
D0
DBL
High-Z
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
QBL means the latest data out of burst length. DBL means the latest data input of burst length.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tBC is defined from CLK rising edge of RL−1 to /LB and /UB = LOW.
Preliminary Data Sheet M17507EJ2V0DS
71
μ PD46128512-X
Figure 8-15. Synchronous Burst Write – Burst Read Cycle Timing Chart (/CE1 Control)
tCYCLE
CLK (Input)
tCH
tCL
tACS
tACH
Valid
Address (Input)
tAH
tCHV tCSV tCHV
/ADV (Input)
tWRB
tVPL
tCES
tCEH
tCLZ
/CE1 (Input)
tCP
tCEWA
tCWHZ
tOC
/OE (Input)
tOLZ
tWEH
/WE (Input)
tLUH
tBC
/LB, /UB (Input)
tBLZ
tCLWA
High-Z
/WAIT (Output)
RL = 5
tWDS tWDH
DQ (Input/Output)
Remarks 1.
tBACC
High-Z
DBL
tBDH
Q0
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
DBL means the latest data input of burst length.
72
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tOC and tBC are defined from CLK rising edge of RL−1 to /OE = LOW, /LB and /UB = LOW.
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 8-16. Synchronous Burst Write – Burst Read Cycle Timing Chart (/ADV Control)
tCYCLE
CLK (Input)
tCH
tCL
tACS
tACH
Valid
Address (Input)
tAH
tCHV tCSV tCHV
/ADV (Input)
tWRB
/CE1 (Input)
tVPL
L
tOC
/OE (Input)
tOLZ
tWEH
/WE (Input)
tLUH
tBC
/LB, /UB (Input)
tBLZ
tADWA
tCLWA
/WAIT (Output)
RL = 5
tWDS tWDH
DQ (Input/Output)
Remarks 1.
tBACC
High-Z
DBL
tBDH
Q0
The above timing chart assumes Read Latency is 5 and Burst Length is 8 or 16.
DBL means the latest data input of burst length.
2.
CE2 should be fixed HIGH.
3.
Valid clock edge is the rising edge.
4.
tOC and tBC are defined from CLK rising edge of RL−1 to /OE = LOW, /LB and /UB = LOW.
Preliminary Data Sheet M17507EJ2V0DS
73
μ PD46128512-X
9. Mode Register Setting Timing
Figure 9-1. Mode Register Setting Timing Chart (Asynchronous Timing + CLK fixed LOW/HIGH)
H
CLK (Input)
L
Address (Input)
tRC
tWC
tWC
tWC
tWC
tRC
7FFFFFH
7FFFFFH
7FFFFFH
7FFFFFH
7FFFFFH
Don't care
/CE1 (Input)
tCE
tCHZ
tOE
tOHZ
tCE
tCHZ
tOE
tOHZ
/OE (Input)
tWP
tWR
tWP
tWR
tWP
tWR
tWP
tWR
/WE (Input)
tDW
DQ (Input/Output)
High-Z
RDa
tDW
tDH
High-Z
tDH
High-Z
Don't care
tDW
tDH
High-Z
tDW
tDH
High-Z
High-Z
Code1
Don't care
High-Z
Code2
RDb
/LB, /UB (Input)
Remarks 1.
For the data of Code1 and Code2, refer to Table 5-1. Mode Register Definition (4th Bus Cycle) and
Table 5-2. Mode Register Definition (5th Bus Cycle).
2.
RDa and RDb are the output data.
3.
/ADV fixed LOW or toggle HIGH → LOW → HIGH.
Figure 9-2. Mode Register Setting Timing Chart (Asynchronous Timing + Toggle CLK)
CLK (Input)
Address (Input)
tRC
tWC
tWC
tWC
tWC
tRC
7FFFFFH
7FFFFFH
7FFFFFH
7FFFFFH
7FFFFFH
Don't care
/CE1 (Input)
tCE
tCHZ
tOE
tOHZ
tCE
tCHZ
tOE
tOHZ
/OE (Input)
tWP
tWR
tWP
tWR
tWP
tWR
tWP
tWR
/WE (Input)
tDW
DQ (Input/Output)
High-Z
RDa
tDW
tDH
High-Z
tDH
High-Z
Don't care
tDW
tDH
High-Z
Don't care
tDW
tDH
High-Z
High-Z
Code1
Code2
High-Z
RDb
/LB, /UB (Input)
Remarks 1.
For the data of Code1 and Code2, refer to Table 5-1. Mode Register Definition (4th Bus Cycle) and
Table 5-2. Mode Register Definition (5th Bus Cycle).
74
2.
RDa and RDb are the output data.
3.
/ADV fixed LOW or toggle HIGH → LOW → HIGH.
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
Figure 9-3. Mode Register Setting Timing Chart (Synchronous Timing)
CLK (Input)
Address (Input)
*A
High-Z
*A
High-Z
*A
High-Z
*A
High-Z
*A
High-Z
Don't
care
High-Z
/ADV (Input)
/CE1 (Input)
/OE (Input)
/WE (Output)
/LB, /UB (Input)
DQ (Input/Output)
High-Z
RDa
High-Z
Don't
care
High-Z
Don't
care
High-Z
Code1
High-Z
Code2
High-Z
RDb
High-Z
Caution Refer to 8. Synchronous Read/Write specification.
Remarks 1.
2.
*A means the highest address (7FFFFFH).
For the data of Code1 and Code2, refer to Table 5-1. Mode Register Definition (4th Bus Cycle) and
Table 5-2. Mode Register Definition (5th Bus Cycle).
3.
RDa and RDb are the output data.
Preliminary Data Sheet M17507EJ2V0DS
75
μ PD46128512-X
Figure 9-4. Mode Register Setting Flow Chart
Start
No
Read Operation
Address = 7FFFFFH
toggled the
/CE1 and /OE
Yes
No
Write Operation
Address = 7FFFFFH
toggled the /CE1
Yes
No
Write Operation
Address = 7FFFFFH
toggled the /CE1
Yes
Write Operation
Address = 7FFFFFH
toggled the /CE1
Mode Register Setting Exit
No
Yes
Write Data = Code 1 Note1
No
Yes
Write Operation
Address = 7FFFFFH
toggled the /CE1
No
Yes
Write Data = Code 2 Note2
No
Yes
Read Operation
Address = Don't Care
toggled the /CE1 and /OE
End
Notes 1.
Refer to Table 5-1.
2.
Refer to Table 5-2.
76
Preliminary Data Sheet M17507EJ2V0DS
Re-setup the mode register
μ PD46128512-X
10. Standby Mode Timing Chart
Figure 10-1. Standby Mode 2 Entry / Exit Timing Chart (Asynchronous Mode)
CE2 (Input)
tMHCL
tCHML
/CE1 (Input)
Standby
Mode 1
Standby Mode 2
Figure 10-2. Standby Mode 2 Entry / Exit Timing Chart (Synchronous Mode)
CLK (Input)
tCE2S
CE2 (Input)
tCES
tCES
tMHCL
/CE1 (Input)
Standby
Mode 1
Standby Mode 2
Standby Mode 2 Entry / Exit
Parameter
Symbol
MIN.
MAX.
Unit
Note
Standby mode 2 entry /CE1 HIGH to CE2 LOW
tCHML
0
ns
Standby mode 2 exit to normal operation CE2 HIGH to /CE1 LOW
tMHCL
30
ns
1
300
μs
2
/CE1 = HIGH setup time to CLK
tCES
5
ns
CE2 = LOW hold time to CLK
tCE2S
1
ns
Notes 1.
This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 32M bits / 16M bits /
8M bits).
2.
This is the time it takes to return to normal operation from Standby Mode 2 (data not held).
Preliminary Data Sheet M17507EJ2V0DS
77
μ PD46128512-X
11. Package Drawing
The following is a package drawing of package sample.
93-PIN TAPE FBGA (12x9)
w S B
E
ZD
ZE
B
10
9
8
7
6
5
4
3
2
1
D
A
PNM L K J H G F E D C B A
INDEX MARK
w S A
ITEM
D
A
y1
A2
S
S
y
e
S
φb
78
φx
M
A1
S AB
Preliminary Data Sheet M17507EJ2V0DS
MILLIMETERS
9.0±0.1
E
12.0±0.1
w
0.2
e
0.8
A
1.3±0.1
A1
0.16±0.05
A2
1.14
b
0.40±0.05
x
0.08
y
0.1
y1
0.2
ZD
0.9
ZE
0.8
P93F9-80-CR2
μ PD46128512-X
12. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD46128512-X package sample.
Type of Surface Mount Device
μPD46128512F9-CR2 : 93-pin TAPE FBGA (12x9)
Preliminary Data Sheet M17507EJ2V0DS
79
μ PD46128512-X
Revision History
Edition/
Date
2nd edition/
Page
Type of
Location
(Previous edition → This edition)
This
Previous
edition
edition
p.6
p.6
Modification Burst Operation
p.14
p.14
Modification 3. Page Read Operation
Sep. 2005
Description
revision
Addition
Notes 3 and 8 have been modified.
Note 10 has been added.
3.1 Features of Page Read
Text has been modified.
Note has been modified.
Operation
p.17
p.18
p.17
p.18
Modification 4.4 Single Write
Text has been modified.
4.5 /WE Control
Text has been modified.
Modification 4.6 Burst Read Suspend/
Text has been modified.
Resume
p.19
p.19
Modification 4.7 Burst Write Suspend/
Text has been modified.
Resume
p.22
p.22
p.23
p.23
Modification 4.10.1 Feature of /WAIT output
Addition
Text has been modified.
Figure 4-8. Read /WAIT Output Text has been added.
(/CE1 = LOW, /ADV = HIGH →
LOW)
p.25
p.25
Addition
Table 4-1. Burst Sequence
Remark 2 has been added.
p.26
p.26
Addition
Table 4-2. Dummy Wait Cycles
“(Write Latency = n-1)” has been added in
and Read Latency
parameter of table.
Modification
p.27
p.27
Addition
Remark has been modified.
4.11 Reset Function from
“Refer to Figure 2-1. Standby Mode State
Synchronous Burst Mode to
Machine.” has been added.
Asynchronous Page Mode
p.28
p.28
Modification 5.1 Mode Register Setting
Addition
“read a specific address”
Method
→ “read any address”
5.2 Cautions for Setting Mode
“except page mode (M = 1)” has been added.
Register
p.32
p.32
Modification 5. 12 Caution for Timing Chart
Text has been modified.
of Setting Mode
p.42
p.42
Addition
Figure 7-10. Asynchronous
Cautions 4 and 5 have been added.
Page Read Cycle Timing Chart
pp.43-56 pp.43-56 Modification Each Figures
p.57
p.57
Modification 8. Synchronous AC
Remark has been modified.
Title has been modified.
Specification, Timing Chart
p.77
p.77
Modification Figure 10-2. Standby Mode 2
Title has been modified.
Entry / Exit Timing Chart
(Synchronous Mode)
80
Preliminary Data Sheet M17507EJ2V0DS
μ PD46128512-X
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Preliminary Data Sheet M17507EJ2V0DS
81
μ PD46128512-X
• The information in this document is current as of September, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
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defined above).
M8E 02. 11-1