NEC UPD6126AG

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD6125A, 6126A
4-BIT SINGLE CHIP MICROCONTROLLER
FOR REMOTE CONTROL TRANSMISSION
DESCRIPTION
The µPD6125A and 6126A are 4-bit single-chip microcontrollers for infrared remote controllers for TVs, VCRs,
stereos, cassette decks, air conditioners, etc.
These microcontrollers consist of ROM, RAM, a 4-bit parallel-processing ALU, a programmable timer, key input/
output ports, and transmit output ports. Functioning is controlled in software.
FEATURES
•
Transmitter for programmable infrared remote
•
1 pin
controller
•
•
Transmission-in-progress indication pin (S-OUT):
•
19 types of instructions
Instruction execution time:
17.6 µs (with 455-kHz
Transmit carrier frequency (REM)
fOSC/12, fOSC/8
ceramic oscillator)
•
Standby operation (HALT/STOP mode)
•
Program memory (ROM) capacity: 1002 × 10 bits
•
Low power consumption
•
Data memory (RAM) capacity: 32 × 5 bits
•
Current consumption in STOP mode (TA = 25°C)
•
9-bit programmable timer: 1 channel
•
I/O pins (KI/O): 8 pins
•
I/O pins (I/O)
1 µA MAX.
•
Low-voltage operation: VDD = 2.0 to 6.0 V
• µPD6125A: 4 pins
• µPD6126A: 8 pins
•
Input pins (KI): 4 pins
•
Serial input pins (S-IN): 1 pin
Caution To use the NEC transmission format, ask NEC to supply the custom code.
The mask option (PLA data) setting of µPD6125A, µPD6126A is different from that of the µPD6125,
6126.
When a register is used as the operand of a branch instruction, do not use R0.
The information in this document is subject to change without notice.
Document No. U12392EJ4V0DS00 (4th edition)
(Previous No. IC-2014B)
Date Published May 1997 N
Printed in Japan
The mark
shows major revised points.
©
1989
µPD6125A, 6126A
ORDERING INFORMATION
Part Number
Package
µPD6125ACA-XXX
24-pin plastic shrink DIP (300 mil)
µPD6125AG-XXX
24-pin plastic SOP (300 mil)
µPD6126AG-XXX
28-pin plastic SOP (375 mil)
Remark XXX indicates a ROM code suffix.
PIN CONFIGURATION (Top View)
• µ PD6125A
2
• µ PD6126A
I/O03 1
24 KI/O0
I/O11 1
28 I/O12
I/O02 2
23 KI/O1
I/O10 2
27 I/O13
I/O01 3
22 KI/O2
I/O03 3
26 KI/O0
I/O00 4
21 KI/O3
I/O02 4
25 KI/O1
S-IN 5
20 KI/O4
I/O01 5
24 KI/O2
S-OUT 6
19 KI/O5
I/O00 6
23 KI/O3
REM 7
18 KI/O6
S-IN 7
22 KI/O4
VDD 8
17 KI/O7
S-OUT 8
21 KI/O5
OSC-OUT 9
16 KI0
REM 9
20 KI/O6
OSC-IN 10
15 KI1
VDD 10
19 KI/O7
VSS 11
14 KI2
OSC-OUT 11
18 KI0
AC 12
13 KI3
OSC-IN 12
17 KI1
VSS 13
16 KI2
AC 14
15 KI3
µPD6125A, 6126A
BLOCK DIAGRAM
ROM
D.P.
CNTL CNTL
(L)
(H)
1002 × 10 bit
L
H
MPX
32 × 5 bit
ROM
(L)
SP
MPX
ROM
D.P.
PC(L)
ROM
(H)
PC(H)
ALU
TIMER TIMER
(L)
(H)
ADD
DEC
ACC
RAM
RAM
KEY
KEY
OUT(L) OUT(H)
KEY
IN
KI/O0-KI/07
K I0 -KI3
I/O
10 bit
OSC
MOD
OSC-IN S-OUT REM
OSC-OUT
Note
Watchdog
timer
function
S-IN
I/O
Note
AC
µPD6125A: I/O00-I/O03
µPD6126A: I/O00-I/O03, I/O10-I/O13
DIFFERENCES AMONG PRODUCTS
Part Number
Item
µPD6125A
µPD6126A
ROM capacity
1002 × 10 bits (Mask ROM)
RAM capacity
32 × 5 bits
I/O pins
12 (KI/O0-7, I/O00-03)
S-IN pins
16 (KI/O0-7, I/O00-03, I/O10-13)
Provided
Current consumption
(fOSC = STOP) (MAX.)
1 µA
S-IN high level input
current (MAX.)
15 µA
Transmit carrier frequency
fOSC/12, fOSC/8
Low-voltage detection
(reset) circuit
Not provided
Supply voltage
Package
VDD = 2.0 to 6.0 V
• 24-pin plastic SOP
(300 mil)
• 24-pin plastic shrink DIP
(300 mil)
• 28-pin plastic SOP
(375 mil)
3
µPD6125A, 6126A
1.
PROGRAM COUNTER (PC) ……… 10 BITS
The program counter (PC) is a binary counter, which holds the address information for the program memory.
Figure 1-1. Program Counter Organization
PC 9
PC 8
PC 7
PC 6
PC 5
PC 4
PC 3
PC 2
PC 1
PC 0
PC
Normally, the program counter contents are automatically incremented each time an instruction is executed,
according to the number of instruction bytes.
When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination.
Immediate data or the data memory contents are loaded to all or some bits of the PC.
When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack
memory. Then, a value needed for each jump instruction will be loaded.
When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded
into the PC.
When “all clear” is input or on reset, the PC contents are cleared to “000H”.
2. STACK POINTER (SP) ……… 2 BITS
This 2-bit register holds the start address information for the stack area. The stack area is shared with the data
memory.
The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when
the return instruction (RET) is executed.
The stack pointer is cleared to “00B” after reset or “all clear” is input, and indicates the highest address FH for the
data memory as the stack area.
The figure below shows the relationship for the stack pointer and the data memory area.
Data memory
RC
RD
RE
RF
(SP)
11B
10B
01B
00B
If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset signal
will be generated.
4
µPD6125A, 6126A
3. PROGRAM MEMORY (ROM) ……… 1002 STEPS × 10 BITS
The program memory (ROM) is configured in 10 bits steps. It is addressed by the program counter.
Program and table data are stored in the program memory.
Figure 3-1. Program Memory Map
000H
0FFH
100H
1FFH
200H
2FFH
300H
3E9H
3EAH
3FFH
Test program
area
4. DATA MEMORY (RAM) ……… 32 WORDS × 5 BITS
The data memory is a RAM of 32 words × 5 bits. The data memory stores processing data. In some cases, the
data memory is processed in 8-bit units. R0 may be used as the data pointer for the ROM.
After power application, the RAM will be undefined. The RAM retains the previous data on reset.
Figure 4-1. Data Memory Organization
1
0
R0
to
RB
RC
to
RF
Caution
SP-3
SP-2
SP-1
SP-0
Avoid using the RAM areas RD, RE, and RF in a CALL routine as much as possible because these
areas are also used as stack memory areas (to prevent program hang-up in case the value of
the SP is destroyed due to some reason such as noise).
When using these RAM areas as general-purpose RAM areas, be sure to include stack pointer
checking in the main routine.
5
µPD6125A, 6126A
5. DATA POINTER (R0)
R0 (R10, R00) for the data memory can serve as the data pointer for the ROM.
R0 specifies the low-order 8 bits in the ROM address. The high-order 2 bits in the ROM address are specified by
the control register.
Table referencing for ROM data can be easily executed by calling the ROM contents by setting the ROM address
to the data pointer.
When “all clear” is input or on reset, it becomes undefined.
Figure 5-1. Data Pointer Organization
Control registers
(P1 )
AD 9
AD 8
R10
AD 7
AD 6
R00
AD 5
AD 4
AD 3
AD 2
AD 1
AD 0
R0
6. ACCUMULATOR (A) ……… 4 BITS
The accumulator (A) is a 4-bit register. The accumulator plays a major role in each operation.
When “all clear” is input or on reset, it becomes undefined.
Figure 6-1. Accumulator Organization
A3
A2
A1
A0
A
7. ARITHMETIC LOGIC UNIT (ALU) ……… 4 BITS
The arithmetic logic unit (ALU) is a 4-bit operation circuit, and executes simple operations, such as arithmetic
operations.
8. FLAGS
(1) Status flag
When the status for each pin is checked by the STTS instruction, if the condition coincides with the condition
specified by the STTS instruction, the status flag (F) is set (to 1).
When “all clear” is input or on reset, it becomes undefined.
(2) Carry flag
When the INC (increment) instruction or the RL (rotate left) instruction is executed, if a carry is generated from
the MSB for the accumulator, the carry flag (C) is set (to 1).
The carry flag (C) is also set (to 1), if the contents for the accumulator are “FH”, when the SCAF instruction is
executed.
When “all clear” is input or on reset, it becomes undefined.
6
µPD6125A, 6126A
9. SYSTEM CLOCK GENERATION CIRCUIT
The system clock generation circuit consists of an oscillation circuit, which uses a ceramic resonator (400kHz to
500kHz).
Figure 9-1. System Clock Generation Circuit
OSC-IN
OSC-OUT
STOP mode
ø
System clock
In the STOP mode (oscillation stop HALT instruction), the oscillation circuit in the system clock generation circuit
stops its operation, and the system clock ø is stopped.
7
µPD6125A, 6126A
10. TIMER
The timer block determines the transmission output pattern. The timer consists of 10 bits, of which 9 bits serve
as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output validity.
The 9-bit down counter is decremented (-1) every 8/fOSC(s) in synchronization with the machine cycle, after starting
down count operation. Down counting stops after all of the 9 bits become 0. When down counting is stopped, the
signal indicating that the timer operation has stopped, is output. If the CPU is at standby (HALT TIMER) for the timer
operation completion, the standby (HALT) condition is released and the next instruction will be executed. If the next
instruction again sets the value of the down counter, down counting continues without any error (the carrier output
of the REM pin is not affected).
Set the down count time according to the following calculation; (set value (HEX) + 1) x 8/fOSC. Setting the value
to the timer is done by the timer manipulation instruction.
When the down counter is operating, the remote control transmission carrier can be output to the REM pin. Whether
or not to output the carrier can be selected by the MSB for the timer register block. Set “1”, when outputting the carrier,
or “0”, when not outputting the carrier.
If all the down counter bits become “0”, when outputting the carrier, the carrier output will be stopped. When not
outputting the carrier, the REM pin output will become low level.
A signal in synchronization with the REM output is output to the S-OUT pin. However, the waveform for the SOUT pin is low, when the carrier is being output to the REM pin, or it is high, when the carrier is not being output to
the REM pin.
If the HALT instruction, which initiates the oscillation stop mode, is executed when the down counter is operating,
the oscillation stop mode is initiated after down counting is stopped (after 0).
Timer operation STOP/RUN is controlled by the control register (P1). (Refer to 13. CONTROL REGISTER (P1).)
When “all clear” is input or on reset, the REM pin goes low and S-OUT pin goes high. All 10 bits of the timer are
cleared to 000H.
Caution
Because the timer clock is not synchronized with the carrier output, the pulse width may be
shortened at the beginning and end of the carrier output.
Figure 10-1. Timer Block Organization
Set by timer mainpulation instruction
MSB
1/0
fosc / 8
9-bit down counter
Clear
Zero detection circuit
S–OUT
REM
Carrier
(fosc/12, fosc/8)
Selected by control register
8
D2 of control register P1
(Timer RUN/STOP)
µPD6125A, 6126A
11. PIN FUNCTIONS
11.1 KI/O Pin (P0)
This is the 8-bit I/O pin for key-scan output. When the control register (P1) is set for the input port, the port can
be used as an 8-bit input pin. When the port is set for the input mode, all of these pins are pulled down to the VSS
level inside the LSI.
When “all clear” is input or on reset, input/output mode goes into effect, and the value of output latch becomes
undefined.
Figure 11-1. KI/O Pin Organization
P10
P0
KI/O7
KI/O6
(P1 )
Countrol
register
P00
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
11.2 KI/O Pull-Down Resistor Organization
V DD
P-ch
Input/output selection
Pin
N-ch
Output signal
V SS
Input signal
CMOS
R
Pull-down resistor
N-ch
When KI/O is set to the input mode, pull-down resistor R is turned on.
9
µPD6125A, 6126A
11.3 I/O Pin (P3, P4
Note
)
P3/P4 are input/output pins for adding a key matrix. The LSB of control registers P13 and P14 switches between
input and output modes.
When in input mode, all pins are pulled down by the LSI to the VSS level.
When “all clear” is input or on reset, input mode goes into effect, and the output latch value becomes undefined.
Figure 11-2. I/O Pin Organization
Note
P13, P14
P3/P4
P03, P04
IN/OUT
I/O3
I/O2
Note
I/O1
I/O0
IN/OUT
0 ······· Input mode
1 ······· Output mode
P3 ··· I/O00 to I/O03,
P4 ··· I/O10 to I/O13
Note µPD6125A is not equipped with P13, P14, P03, and P04.
11.4 I/O Pull-Down Resistor Organization
VDD
Input/output selection
P-ch
Pin
N-ch
Output signal
VSS
Input signal
I/O pull-down resistor switch
(Mask option)
CMOS
R
Pull-down resistor
Nch
The use of pull-down resistors for I/O can be selected by using the mask option.
When the pull-down resistor switch is turned on (1 is set) by the mask option, the pull-down resistor R is turned
on only in input mode.
Caution
10
When using the pins as key switches, turn on the pull-down resistor switch by the mask option.
µPD6125A, 6126A
11.5 KI Pin (P12)
This is the 4-bit pin for key input. All of these pins can be pulled down to the VSS level by mask option.
Figure 11-3. KI Pin Organization
P12
P2
KI3
KI2
KI1
KI0
Mask option
11.6 KI Pull-Down Resistor Organization
V DD
P-ch
Pin
Input signal
KI pull-down
resistor switch
(Mask option)
N-ch
Pull-down
resistor
V SS
V SS
When the pull-down resistor switch is turned on (set 1) by the mask option, pull-down resistor R is turned on.
Caution
When using the pin as the key switch, turn on the pull-down resistor switch by the mask option.
11
µPD6125A, 6126A
11.7 S-OUT Pin
By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that
communication is in progress.
The S-OUT pin is a CMOS output pin.
The S-OUT pin goes high on reset.
11.8 S-IN Pin (D0 Bit of P1)
To input serial data, use the S-IN pin. When control register (P1) is set to serial input mode, the S-IN pin is connected
as an input to the LSB of the accumulator. The S-IN pin can be pulled down to the VSS level by a mask option from
within the LSI. In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is
copied to the LSB of the accumulator.
If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no
through current flows internally.
When the RL A instruction is executed, the MSB is copied to the LSB.
When “all clear” is input or on reset, the S-IN pin goes into a high-impedance state.
Figure 11-4. The S-IN Pin Organization
A3
A2
A1
S-IN
A0
Mask option
CY
Control
register
12
µPD6125A, 6126A
12. PORT REGISTER (P×)
KI/O, I/O, KI, and the control register are handled as port registers.
The table below shows the relations between the port registers and pins.
Table 12-1. Relations between Port Registers and Pins
Input Mode
Output Mode
Pin
Name
Read
Write
Read
Write
KI/O
Pin status
Output latch
Pin status
Output latch
KI
Pin status
–
–
–
Pin status
Output latch
Pin status
Output latch
I/O0
I/O1
S-IN
On Reset
Undefined [I/O mode, output latch]
Input mode
Input mode
Output latch is undefined.
Pin status is read by RL A instruction when D0 of P1 register = 1.
P 1 × (H)
P 0 × (L)
K I/O7-4
P 10
K I/O3-0
P0
Control register (L)
P1
P 00
Control register (H)
P 11
P 01
K I3-0
P2
P 12
P 02
IN/OUT
P 13
Caution
I/O 0
P3
I/O 1
P4
P 03
IN/OUT
P 14
High impedance (D0 of P1 register = 0)
P 04
The µPD6125A is not equipped with I/O10-I/O13 pins.
13
µPD6125A, 6126A
13. CONTROL REGISTER (P1)
The control register contains of 10 bits. The controllable items are shown in Table 13-1.
Table 13-1. Control Register (P1)
Bit
D9
Name
D8
Test mode
D7
D6
D5
D4
D3
D2
D1
D0
–
HALT
D.P.
AD 9
D.P.
AD 8
MOD
Timer
K I/O
RL A CC
A0 ←
NOP
AD 9 =0
AD 8 =0
f OSC/8
STOP
IN
A3
OSC
STOP
AD 9 =1
AD 8 =1
f OSC/12
RUN
OUT
S-IN
0
Set
Value
Be sure to reset to 0.
1
D0 .......................... Specifies data to be input to A0 when the accumulator is shifted to the left.
0: A3, 1: S-IN
D1 .......................... Specifies the status of KI/O, as follows:
0: input mode, 1: output mode
D2 .......................... Specifies the status of the timer, as follows:
0: Count stop, 1: Count execution
D3 .......................... Specifies the carrier frequency output from the REM pin.
0: fOSC/8, 1: fOSC/12
D4, D5 ................. Specify the high-order 2 bits of the ROM data pointer.
D6 .......................... Determines what happen to the oscillation circuit when the HALT instruction is executed.
0: Oscillation does not stop
1: Oscillation stops (STOP mode)
D7 .......................... Be sure to reset this bit to 0.
D8, D9 ................. These bits specify test modes. Be sure to reset them to 0.
Remark D0 = D8 = D9 = 0 on reset, and the other bits are undefined.
14
µPD6125A, 6126A
14. STANDBY FUNCTION (HALT INSTRUCTION)
The µPD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption,
when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode).
In the standby mode, the program execution stops. However, the contents of the internal registers and the data
memory are all retained.
14.1 STOP Mode (Oscillation Stop HALT Instruction)
In the STOP mode, the operation of the system clock generation circuit (ceramic resonator oscillation circuit) stops.
Therefore, operations requiring the system clock will stop.
If the HALT instruction is executed during timer operation, the program counter stops. The oscillation stop mode
will be initiated, after the timer count down operation is completed.
14.2 HALT Mode (Oscillation Continue HALT Instruction)
The CPU stops its operation, until the HALT release condition is satisfied.
The system clock operation continues in this mode.
14.3 Standby Release Conditions
(1) S-IN input
(2) KI/O input
(3) KI input
(4) Timer count down operation completion
(5) I/O input
(6) KI, I/O input
Remark Either high level or low level can be specified for setting a release condition by input.
Table 14-1. Standby Mode Releasing Condition
D3
0/1
0
D2
D1
D0
Releasing
Condition
0
0
0
S-IN
When RL ←A 3 is selected, the standby mode is
always released.
0
0
1
K I/O
Valid only in the IN mode.
0
1
0
KI
0
1
1
Timer
Released when 0.
1
0
0
I/O 0
Valid only in the IN mode.
1
0
1
I/O 1
1
1
0
KI, I/O0, I/O1
Remarks
0/1
1
Releasing condition:
Caution
Judged as an error and initialized even if one of the
I/O is in OUT mode.
"0"···Low level detection
"1"···High level detection
µPD6125A is not equipped with I/O10 - I/O13 pins.
15
µPD6125A, 6126A
15. AC PIN (ALL CLEAR PIN)
Internal part of the CPU including the program counter can be reset by setting the AC pin to the low level.
Watchdog Timer Function
A power-on reset function and a CR watchdog timer function, that can be controlled by program, can be realized
by connecting a 0.1 µF capacitor across the AC pin and the VSS.
VDD
Charge mode
Charge start instruction
0.1 µF
Execute HALT instruction
immediately before NOP.
(Charge for 0.4 ms or more)
Discharge mode
Discharge start instruction
0.1 µF
Charge-discharge
pattern
Discharge starts after the NOP
instruction execution.
(Discharge time is about 5 ms from VDD to V th )
V
V DD
The pattern must be
controlled by the program,
in such a manner that
the C charge level will not
go below V thL .
V thL
t
Caution
When the watchdog timer function is not used, switch to charging mode by executing a NOP
instruction immediately before a HALT instruction at the beginning of the program. (Be sure
to connect the capacitor.)
16
µPD6125A, 6126A
16. MASK OPTIONS (PLA DATA)
The following items can be selected by mask option selection:
• Provide/not provide KI, I/O, S-IN pin pull-down resistor
• Carrier duty selection (1/2, 1/3) at fOSC/12
• Hang-up detection specification
Mask option data should be registered at the object code end.
BIT Assignment by Switch Selection
LSB
Address
MSB
Corresponding
Portion
0
KI
pull-down resistor
KI0
KI1
KI2
KI3
1
Duty
S-IN
0
0
0
Duty
selection
0
0
S-IN
pull-down
resistor
0
2
Hang up detection
KI/O
ALL
HALT
S-IN
HALT
KI/O
HALT
KI
HALT
I/O0
HALT
I/O1
I/O0
ALL
I/O1
ALL
3
I/O0
pull-down resistor
I/O00
I/O01
I/O02
I/O03
0
4
I/O1
pull-down resistor
I/O10
I/O11
I/O12
I/O13
0
Caution
7
6
5
4
3
2
1
0
0
µPD6125A is not equipped with I/O10 - I/O13 pins.
Switch for Data
(1) Pull-down resistor
When 0 ··· Not provided (OFF)
When 1 ··· Provided (ON)
(2) Modulation duty (at fOSC/12)
When 0 ··· 1/2 duty
When 1 ··· 1/3 duty
(3) Hang-up detection
<1> KI/O ALL, I/O0 ALL, I/O1 ALL
If the switch for hang-up detection KI/O ALL (I/O0 ALL, I/O1 ALL) is set to ON (1) by mask option, the system
is reset, if in oscillation HALT (STOP) mode, the KI/O (I/O0, I/O1) pin is in input mode, or if at least one of
the KI/O (I/O0, I/O1) pins is low (AC pin discharge mode).
When 0 ··· No reset function (OFF)
When 1 ··· Reset function (ON)
Caution To use a pin as a key source of a key matrix, be sure to set the switch to ON by mask option.
17
µPD6125A, 6126A
Figure 16-1. Hang-up Detection KI/O ALL Organization
K I/O0 output signal
K I/O1 output signal
VDD
K I/O2 output signal
K I/O3 output signal
K I/O4 output signal
To RESET circuit
K I/O5 output signal
K I/O6 output signal
K I/O7 output signal
Hang-up detection
KI/O ALL switch
(Mask option)
KI/O input/output selection
Remark
The above is also applicable to I/O0 ALL, I/O1 ALL.
<2> HALT releasing condition specification (S-IN, KI/O, KI, I/O0, I/O1)
If the condition specified by mask option to be unused is satisfied in the HALT mode, the system is reset.
When 0 ··· Used
When 1 ··· Unused
Caution Be sure to specify the HALT mode of the unused releasing condition to be unused (set).
18
µPD6125A, 6126A
17. PROGRAM DEVELOPMENT TOOLS
To develop programs for the µPD6125A, 6126A, an assembler and an emulator for the µPD612X series are
available from I.C. Corp. For details, contact IC Corp.
18. ORDERING ROM CODE
<1> To generate the data required for ordering a mask ROM, after assembling the program, convert the HEX
file to a ROM file by using the PROM utility program "UPDPROM".
Caution
When using "UPDPROM" select "27256" for PROM TYPE.
<2> Confirm that the instruction ROM code data is stored in addresses 0 through 7D3H of the PROM.
Also confirm that the mask option ROM code data are stored in the following addresses.
µPD6125A: Addresses 7FF0H through 7FF3H
µPD6126A: Addresses 7FF0H through 7FF4H
19
µPD6125A, 6126A
19. INSTRUCTION SET
Accumulator Manipulation Instructions
Rr
R10
R11
R12
R1F
R 00
R 01
R 0F
D00
D01
D02
D0F
D20
D21
D2F
E00
E01
E02
E0F
E20
E21
E2F
A00
A01
A02
A0F
A20
A21
A2F
P10
P11
P12
P13
P14
P00
P01
P02
P03
P04
F18
218
D18
E18
A18
F19
219
D19
E19
A19
F1A
21A
D1A
E1A
A1Z
F1B
21B
D1B
E1B
A1B
F1C
21C
D1C
E1C
A1C
F38
238
D38
E38
A38
F39
239
D39
E39
A39
F3A
23A
D3A
E3A
A3A
F3B
23B
D3B
E3B
A3B
F3C
23C
D3C
E3C
A3C
P0
P1
P2
P3
P4
318
319
31A
31B
31C
R10
R11
R12
R1F
R 00
R 01
R 0F
F00
F01
F02
F0F
F20
F21
F2F
200
201
202
20F
220
221
22F
R0
R1
R2
RF
300
320
301
321
302
322
30F
32F
–
ANL
ANL
ANL
ANL
A, R r
A, @R 0 H
A, @R 0 L
A, #data
D10
D30
D31
ORL
ORL
ORL
ORL
A, R r
A, @R 0 H
A, @R 0 L
A, #data
E10
E30
E31
XRL
XRL
XRL
XRL
A, R r
A, @R 0 H
A, @R 0 L
A, #data
A10
A30
A31
INC
RL
A
A
A13
F13
Input/Output Instructions
PP
IN
OUT
ANL
ORL
XRL
A,
PP ,
A,
A,
A,
PP
A
PP
PP
PP
PP
OUT
PP #data
P1P and P0P operate in pair format
Data Transfer Instructions
Rr
MOV
MOV
MOV
MOV
A, R r
A, @R 0 H
A, @R 0 H
A, #data
MOV
Rr , A
Rr
MOV
MOV
Rr , #data
Rr , @R 0
F10
F30
F31
R1r and R0r operate in pair format
20
µPD6125A, 6126A
Branch Instructions
Rr
–
JMP0
addr
411
JMP0
Rr Note
–
JC
addr
611
JC
Rr Note
–
JNC
addr
631
JNC
Rr Note
–
JF
addr
711
JF
Rr Note
–
JNF
addr
731
Rr
JNF
Note
Note
–
R0
R1
R2
RF
–
401
402
40F
–
601
602
60F
–
621
622
62F
–
701
702
70F
–
721
722
72F
← Pair register
r=1–F
r = 0 cannot be used.
Subroutine Instructions
PP
CALL0 addr
RET
P0
P1
312
412
411
Timer/Counter Manipulation Instructions
Tt
MOV
MOV
MOV
MOV
A,
Tt ,
T,
T,
Tt
A
#data
@R 0
T0-1
T1
T0
–
F1F
21F
F3F
23F
R 00
R 01
R 02
R 0F
120
121
122
12F
31F
33F
Other Instructions
HALT #data
111
STTS R 0r
STTS #data
131
SCAF
D13
NOP
000
21
µPD6125A, 6126A
20. TYPICAL APPLICATION CIRCUIT EXAMPLE
(1) µPD6125A application circuit example
1
2
3
4
SE303A-C
SE307-C
SE313
SE1003-C
5
VDD
(no carrier)
I/O03
KI/O0
I/O02
KI/O1
I/O01
KI/O2
I/O00
KI/O3
S-IN
KI/O4
KI/O5
KI/O6
6
2SC2001, 3616
2SD1513, 1614
2SD1616
2.0 Ω
7
S-OUT
8
9
21
20
19
18
17
Mode
selection
Key matrix
(8 × 8 = 64 keys) switch
VDD
OSC-OUT
KI0
KI1
10
C1
11
12
Caution
22
REM µ PD6125A
3.0 V
47 µ F
23
(with carrier)
C2
+
KI/O7
24
OSC-IN
KI2
VSS
KI3
16
15
14
13
AC
0.1 µ F
The ceramic resonator start-up capacitor value must be determined, by taking the voltage level
and the oscillation start-up characteristics for the ceramic resonator into consideration.
22
µPD6125A, 6126A
(2) µPD6126A application circuit example
1
2
3
4
5
6
I/O11
I/O12
I/O10
I/O13
7
27
I/O03
I/O02
KI/O0
I/O01
KI/O1
I/O00
KI/O2
KI/O3
SE303A-C
SE307-C
SE313
SE1003-C
28
S-IN
VDD
KI/O4
KI/O5
26
25
24
23
22
21
µ PD6126A KI/O6 20
(no carrier)
KI/O7
2.0 Ω
8
2SC2001, 3616
2SD1513, 1614
2SD1616
9
19
S-OUT
Key matrix
(8 × 12 = 96 keys)
REM
Mode
selection
switch
(with carrier)
10
100 pF
11
VDD
OSC-OUT
KI1
3.0 V
12
100 pF
13
14
47 µ F
+
Caution
KI0
OSC-IN
KI2
VSS
KI3
18
17
16
15
AC
0.1 µ F
The ceramic resonator start-up capacitor value must be determined, by taking the voltage level
and the oscillation start-up characteristics for the ceramic resonator into consideration.
23
µPD6125A, 6126A
21. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
Ratings
Unit
Supply voltage
VDD
–0.3 to +7.0
V
Input voltage
VIN
–0.3 to VDD+0.3
V
Operating ambient temperature
TA
–20 to +75
°C
Storage temperature
Tstg
–40 to +125
°C
Caution
If the rated value of even one of the above parameters is exceeded even momentarily, the quality
of the product may be degraded. Absolute maximum ratings therefore specify the values
exceeding which the product may be physically damaged. Never exceed these values when
using the product.
Recommended Operating Range (TA = –20 to +75 °C)
Symbol
MIN.
MAX.
Unit
Supply voltage
Parameter
VDD
2.0
6.0
V
Oscillation frequency
fOSC
400
500
kHz
24
TYP.
µPD6125A, 6126A
DC Characteristics (VDD = 3.0V, fOSC = 455kHz, TA = 25 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
Unit
Supply voltage
VDD
Current dissipation 1
IDD1
fOSC = 455 kHz
Current dissipation 2
IDD2
fOSC= STOP
REM high level output current
IOH1
VO = 1.0 V
REM low level output current
IOL1
VO = 0.3 V
0.5
1.5
2.5
mA
S-OUT high level output current
IOH2
VO = 2.7 V
–0.3
–1.0
–2.0
mA
S-OUT low level output current
IOL2
VO = 0.3 V
1
1.5
KI high level input current
IIH1
VI = 3.0 V
10
KI high level input current
IIH1'
VI = 3.0 V, without pull-down resistor
KI low level input current
IIL1
VI = 0 V
KI/O, I/O high level input current
IIH2
VI = 3.0 V
KI/O, I/O high level input current
IIH2'
KI/O, I/O low level input current
IIL2
KI/O, I/O high level output current
IOH3
VO = 2.5 V
–1.5
KI/O, I/O low level output current
IOL3
VO = 2.1 V
25
KI, I/O high level input voltage
VIH1
2.1
3.0
V
KI, I/O low level input voltage
VIL1
0
0.9
V
KI/O high level input voltage
VIH2
1.3
3.0
V
KI/O low level input voltage
VIL2
0
0.4
V
AC pull-up resistor
R1
VI = 0 V
0.3
3.0
kΩ
R2
VI = 2.7 V
150
AC pull-down resistor
2.0
MAX.
0.3
6.0
V
1.0
mA
1.0
–5
–8
µA
mA
mA
30
µA
0.2
µA
–0.2
µA
30
µA
VI = 3.0 V, without pull-down resistor
0.2
µA
VI = 0 V
–0.2
µA
–2.0
–4.0
mA
50
100
µA
10
1500
kΩ
AC high level input voltage
VIH3
1.8
400
3.0
V
AC low level input voltage
VIL3
0
1.2
V
Recommended Ceramic Resonator
External Capacitance (pF)
Manufacturer
Murata Mfg. Co., Ltd.
Toko Ceramic Co., Ltd.
Product
Oscillation Voltage Range (V)
C1
C2
MIN.
MAX.
CSB375P
220
220
2.0
3.3
CSB400P
220
220
2.0
5.0
CSB455E
100
100
2.0
5.0
CSB480E
100
100
2.0
5.0
CSB500E
100
100
2.0
3.3
CRK400
100
100
2.0
6.0
CRK455
100
100
2.0
6.0
CRK500
100
100
2.0
6.0
Remarks
25
µPD6125A, 6126A
22. CHARACTERISTICS CURVE (Target Value)
3.0
2.0
1.0
0.2
0.4
0.6
0.8
V DD = 3 V
–5.0
0
1.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-level output voltage VOL [V]
High-level output voltage V OH [V]
I OL vs VOL characteristic examples (S-OUT)
(TA = 25 ± 3 °C)
I OH vs VOH characteristic examples (S-OUT)
(TA = 25 ± 3 °C)
V DD = 3 V
4.0
3.0
2.0
1.0
0
–10.0
High-level output current IOH [mA]
Low-level output current I OL [mA]
5.0
Low-level output current I OL [ µ A]
V DD = 3 V
4.0
0
0.2
0.4
0.6
0.8
–3.0
V DD = 3 V
–2.0
–1.0
0
1.0
2.0
2.2
2.4
2.6
2.8
3.0
low-level output voltage VOL [V]
High-level output voltage V OH [V]
I OL vs VOL characteristic examples (K I/O0 -K I/O3 , I/O)
(TA = 25 ± 3 °C)
I OL vs VOL characteristic examples (K I/O0 -K I/O7 )
(TA = 25 ± 3 °C)
V DD = 3 V
50
0
1.0
2.0
Low-level output voltage VOL [V]
26
High-level output current IOH [mA]
5.0
I OH vs VOH characteristic examples (REM)
(TA = 25 ± 3 °C)
Low-level output current I OL [ µ A]
Low-level output current I OL [mA]
I OL vs VOL characteristic examples (REM)
(TA = 25 ± 3 °C)
3.0
V DD = 3 V
50
0
1.0
2.0
Low-level output voltage VOL [V]
3.0
µPD6125A, 6126A
High-level output current IOH [mA]
I OH vs V OH characteristic examples (K I/O, I/O)
(TA = 25 ± 3 °C)
VDD = 3 V
–4.0
–3.0
–2.0
–1.0
0
2.2
2.4
2.6
2.8
3.0
High-level output voltage VOH [V]
27
µPD6125A, 6126A
23. PACKAGE DRAWINGS
(1) µPD6125A package drawings (1/2)
16-Pin Plastic SOP (300 mil) (units in mm)
24 PIN PLASTIC SHRINK DIP (300 mil)
fig. blank a
24
13
1
12
A
K
G
H
J
I
L
F
D
N
M
C
NOTE
B
M
R
ITEM
MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
23.12 MAX.
0.911 MAX.
B
1.78 MAX.
0.070 MAX.
2) Item "K" to center of leads when formed parallel.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020 +0.004
–0.005
F
0.85 MIN.
0.033 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
7.62 (T.P.)
0.300 (T.P.)
L
6.5
0.256
M
0.25 +0.10
–0.05
0.010 +0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
S24C-70-300B-1
28
µPD6125A, 6126A
24 PIN PLASTIC SOP (300 mil)
24
13
P
detail of lead end
1
12
A
H
J
E
K
F
G
I
C
N
D
M
L
B
M
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
15.54 MAX.
0.612 MAX.
B
0.78 MAX.
0.031 MAX.
C
1.27 (T.P.)
0.050 (T.P.)
D
0.40 +0.10
–0.05
0.016 +0.004
–0.003
E
0.1±0.1
0.004±0.004
F
1.8 MAX.
0.071 MAX.
G
1.55
0.061
H
7.7±0.3
0.303±0.012
I
5.6
0.220
J
1.1
0.043
K
0.20 +0.10
–0.05
0.008 +0.004
–0.002
L
0.6±0.2
0.024 +0.008
–0.009
M
0.12
0.005
N
0.10
0.004
P
3° +7°
–3°
3° +7°
–3°
P24GM-50-300B-4
29
µPD6125A, 6126A
(1) µPD6125A package drawings (2/2)
24-PIN SHRINK DIP FOR ES (REFERENCE) (Unit in mm)
fig. blank c
30
µPD6125A, 6126A
24-PIN CERAMIC MINI FLAT PACKAGE FOR ES (REFERENCE) (Unit in mm)
31
µPD6125A, 6126A
(2) µPD6126A package drawings (1/2)
20-Pin Plastic SOP (300 mil) (units in mm)
28 PIN PLASTIC SOP (375 mil)
28
fig. blank e
15
P
detail of lead end
1
14
A
H
J
E
K
F
G
I
B
C
D
M
L
N
M
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
18.07 MAX.
0.712 MAX.
B
0.78 MAX.
0.031 MAX.
C
1.27 (T.P.)
0.050 (T.P.)
D
0.40 +0.10
–0.05
0.016 +0.004
–0.003
E
0.1±0.1
0.004±0.004
F
2.9 MAX.
0.115 MAX.
G
2.50
0.098
H
10.3±0.3
0.406 +0.012
–0.013
I
7.2
0.283
J
1.6
0.063
K
0.15 +0.10
–0.05
0.006 +0.004
–0.002
L
0.8±0.2
0.031 +0.009
–0.008
M
0.12
0.005
N
0.15
0.006
P
3° +7°
–3°
3° +7°
–3°
P28GM-50-375B-3
32
µPD6125A, 6126A
(2) µPD6126A package drawings (2/2)
28-PIN CERAMIC SOP FOR ES (REFERENCE) (Unit in mm)
fig. blank f
33
µPD6125A, 6126A
24. RECOMMENDED SOLDERING CONDITIONS
It is recommended that µPD6125A and 6126A be soldered under the following conditions.
For details on the recommended soldering conditions, refer to Information Document Semiconductor Device
Mounting Technology Manual (C10535E).
For other soldering methods and conditions, consult NEC.
Table 24-1. Surface-Mount Type Soldering Conditions
(1) µPD6125AG-XXX: 24-pin plastic SOP (300 mil)
Soldering Method
Soldering Conditions
Symbol for
Recommended
Condition
Infrared reflow
Package peak temperature: 230 °C, time: 30 seconds max. (210 °C min.),
number of times: 1
IR30-00-1
VPS
Package peak temperature: 215 °C, time: 40 seconds max. (200 °C min.),
number of times: 1
VP15-00-1
Partial heating
Pin temperature: 300 °C max., time: 3 seconds max. (per device side)
–
(2) µPD6126AG-XXX: 28-pin plastic SOP (375 mil)
Soldering Method
Soldering Conditions
Symbol for
Recommended
Condition
Infrared reflow
Package peak temperature: 230 °C, time: 30 seconds max. (210 °C min.),
number of times: 1
IR30-00-1
VPS
Package peak temperature: 215 °C, time: 40 seconds max. (200 °C min.),
VP15-00-1
number of times: 1
Wave soldering
Solder bath temperature: 260 °C max., time: 10 seconds max., number of times: 1
Pre-heating temperature: 120 °C max. (package surface temperature)
Partial heating
Pin temperature: 300 °C max., time: 3 seconds max. (per device side)
Caution
WS60-00-1
–
Use more than one soldering method should be avoided (except in the case of partial heating).
Table 24-2. Insertion Type Soldering Conditions
µPD6125ACA-XXX: 24-pin plastic shrink DIP (300 mil)
Soldering Method
Soldering Conditions
Wave soldering (Only for pin)
Solder bath temperature: 260 °C max., time: 10 seconds max.
Partial heating
Pin temperature: 300 °C max., time: 3 seconds max. (per pin)
Caution
34
Wave soldering is only for pins in order that jet solder can not contact with the chip directly.
µPD6125A, 6126A
APPENDIX µPD612X SERIES PRODUCTS
Part Number
Item
µPD6124A
µPD6600A
512 × 10 bits
(Mask ROM)
µPD61P24
1002 × 10 bits
(One-time PROM)
µPD6125A
ROM capacity
1002 × 10 bits
(Mask ROM)
RAM capacity
32 × 5 bits
I/O pins
8 pins (KI/O0-7)
S-IN pins
Provided
Current consumption
(fOSC = STOP) (MAX.)
2 µA
1 µA
S-IN high level input
current (MAX.)
30 µA
15 µA
Transmit carrier frequency
fOSC/12, fOSC/8
Low-voltage detector
Provided
Not provided
Mask option
Provided
Not provided
(Fixed)
Provided
Supply voltage
VDD = 2.0 to 5.5 V
VDD = 2.2 to 5.5 V
VDD = 2.0 to 6.0 V
Package
• 20-pin plastic SOP (300 mil)
• 20-pin plastic shrink DIP (300 mil)
µPD6126A
1002 × 10 bits
(Mask ROM)
12 pins
(KI/O0-7,
I/O00-03)
16 pins
(KI/O0-7,
I/O00-03, I/O10-13)
(reset) circuit
VDD = 2.2 to 3.6 V
• 24-pin plastic
SOP (300 mil)
• 24-pin plastic
shrink DIP
(300 mil)
• 28-pin plastic
SOP (375 mil)
35
µPD6125A, 6126A
[MEMO]
36
µPD6125A, 6126A
[MEMO]
37
µPD6125A, 6126A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to
be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
38
µPD6125A, 6126A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
39
µPD6125A, 6126A
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5