NEC UPD703031A

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703031A, 703031AY, 703033A,
703033AY, 70F3033A, 70F3033AY
TM
V850/SB1
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY (V850/SB1) are 32-/16-bit
single-chip microcontrollers of the V850 FamilyTM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial
interfaces, A/D converter, DMA controller, and so on are integrated on a single chip.
The µPD70F3033A and 70F3033AY have flash memory in place of the internal mask ROM of the µPD703033A
and 703033AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
TM
V850/SB1, V850/SB2 User’s Manual Hardware: U13850E
V850 Family User’s Manual Architecture:
U10243E
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time: 50 ns (@ internal 20 MHz operation)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
load/store instructions
{ Memory space: 16 MB linear address space
{ Internal memory ROM: 128 KB (µPD703031A, 703031AY: mask ROM)
256 KB (µPD703033A, 703033AY: mask ROM)
256 KB (µPD70F3033A, 70F3033AY: flash memory)
RAM: 12 KB (µPD703031A, 703031AY)
16 KB (µPD703033A, 703033AY, 70F3033A, 70F3033AY)
{ Interrupt/exception: µPD703031A, 703033A, 70F3033A (external: 8, internal: 30 sources, exception: 1 source)
µPD703031AY, 703033AY, 70F3033AY (external: 8, internal: 31 sources, exception: 1 source)
{ I/O lines Total: 83
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)
8-bit timer (6 channels: TM2 to TM7)
{ Watch timer: 1 channel
{ Watchdog timer: 1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14734EJ1V0DS00 (1st edition)
Date Published April 2000 N CP(K)
Printed in Japan
©
2000
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
{ Serial interface
• Asynchronous serial interface (UART0, UART1)
• Clocked serial interface (CSI0 to CSI3)
• 3-wire variable length serial interface (CSI4)
2
2
2
• I C bus interface (I C0, I C1) (µPD703031AY, 703033AY, 70F3033AY only)
{ 10-bit resolution A/D converter: 12 channels
{ DMA controller: 6 channels
{ Real-time output port: 8 bits × 1 channel or 4 bits × 2 channels
{ ROM correction: 4 places can be corrected
{ Power-saving function: HALT/IDLE/STOP modes
{ Packages: 100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic QFP (14 × 20)
{ µPD70F3033A, 70F3033AY
• Can be replaced with µPD703033A and 703033AY (internal mask ROM) in mass production
APPLICATIONS
{ AV equipment (audio, car audio, VCR, TV, etc.)
ORDERING INFORMATION
Part Number
Package
Internal ROM
×××-8EU
µPD703031AGC-×××
×××
×××-8EU
µPD703031AYGC-×××
×××
100-pin plastic LQFP (fine pitch) (14 × 14)
Mask ROM (128 KB)
100-pin plastic LQFP (fine pitch) (14 × 14)
Mask ROM (128 KB)
×××-3BA
µPD703031AGF-×××
×××
×××-3BA
µPD703031AYGF-×××
×××
100-pin plastic QFP (14 × 20)
Mask ROM (128 KB)
100-pin plastic QFP (14 × 20)
Mask ROM (128 KB)
×××-8EU
µPD703033AGC-×××
×××
×××-8EU
µPD703033AYGC-×××
×××
100-pin plastic LQFP (fine pitch) (14 × 14)
Mask ROM (256 KB)
100-pin plastic LQFP (fine pitch) (14 × 14)
Mask ROM (256 KB)
×××-3BA
µPD703033AGF-×××
×××
×××-3BA
µPD703033AYGF-×××
×××
100-pin plastic QFP (14 × 20)
Mask ROM (256 KB)
100-pin plastic QFP (14 × 20)
Mask ROM (256 KB)
Note
µPD70F3033AGC-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
Flash memory (256 KB)
µPD70F3033AYGC-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
Flash memory (256 KB)
Note
µPD70F3033AGF-3BA
100-pin plastic QFP (14 × 20)
Flash memory (256 KB)
µPD70F3033AYGF-3BA
100-pin plastic QFP (14 × 20)
Flash memory (256 KB)
Note
Note
Note Under development
Remarks 1. ××× indicates ROM code suffix.
2. ROMless versions are not provided.
2
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
PIN CONFIGURATION (Top View)
100-pin plastic LQFP (fine pitch) (14 × 14)
• µPD703031AGC-×××-8EU
• µPD70F3033AGC-8EU
• µPD703031AYGC-×××-8EU
• µPD70F3033AYGC-8EU
• µPD703033AGC-×××-8EU
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P71/ANI1
P70/ANI0
AVREF
AVSS
AVDD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BVSS
BVDD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P107/RTP7/KR7/A12
P110/WAIT/A1
P111/A2
P112/A3
P113/A4
RESET
XT1
XT2
REGC
X2
X1
VSS
VDD
CLKOUT
P90/LBEN/WRL
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P96/HLDRQ
P40/AD0
P41/AD1
P42/AD2
P43/AD3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P21/SO2
P22/SCK2/SCL1Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EVDD
EVSS
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
IC/VPPNote 1
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9
P105/RTP5/KR5/A10
P106/RTP6/KR6/A11
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P20/SI2/SDA1Note 2
P15/SCK1/ASCK0
P14/SO1/TXD0
P13/SI1/RXD0
P12/SCK0/SCL0Note 2
P11/SO0
P10/SI0/SDA0Note 2
P07/INTP6
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
• µPD703033AYGC-×××-8EU
Notes 1.
IC: Connect directly to VSS (µPD703031A, 703031AY, 703033A, 703033AY).
VPP: Connect to VSS in normal operation mode (µPD70F3033A, 70F3033AY).
2.
SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703031AY, 703033AY,
and 70F3033AY.
Data Sheet U14734EJ1V0DS00
3
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
100-pin plastic QFP (14 × 20)
• µPD703031AGF-×××-3BA
• µPD70F3033AGF-3BA
• µPD703031AYGF-×××-3BA
• µPD70F3033AYGF-3BA
• µPD703033AGF-×××-3BA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P13/SI1/RXD0
P12/SCK0/SCL0Note 2
P11/SO0
P10/SI0/SDA0Note 2
P07/INTP6
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
• µPD703033AYGF-×××-3BA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
AVREF
AVSS
AVDD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BVSS
BVDD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P111/A2
P112/A3
P113/A4
RESET
XT1
XT2
REGC
X2
X1
VSS
VDD
CLKOUT
P90/LBEN/WRL
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P96/HLDRQ
P40/AD0
P14/SO1/TXD0
P15/SCK1/ASCK0
P20/SI2/SDA1Note 2
P21/SO2
P22/SCK2/SCL1Note 2
P23/RXD1/SI3
P24/TXD1/SO3
P25/ASCK1/SCK3
EVDD
EVSS
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10/SI4
P33/TI11/SO4
P34/TO0/A13/SCK4
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
IC/VPPNote 1
P100/RTP0/KR0/A5
P101/RTP1/KR1/A6
P102/RTP2/KR2/A7
P103/RTP3/KR3/A8
P104/RTP4/KR4/A9
P105/RTP5/KR5/A10
P106/RTP6/KR6/A11
P107/RTP7/KR7/A12
P110/WAIT/A1
Notes 1.
IC: Connect directly to VSS (µPD703031A, 703031AY, 703033A, 703033AY).
VPP: Connect to VSS in normal operation mode (µPD70F3033A, 70F3033AY).
2.
SCL0, SCL1, SDA0, and SDA1 are available only in the µPD703031AY, 703033AY,
and 70F3033AY.
4
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
PIN IDENTIFICATION
A1 to A21:
Address Bus
P80 to P83:
Port 8
AD0 to AD15:
Address/Data Bus
P90 to P96:
Port 9
ADTRG:
AD Trigger Input
P100 to P107:
Port 10
ANI0 to ANI11:
Analog Input
P110 to P113:
Port 11
ASCK0, ASCK1:
Asynchronous Serial Clock
RD:
Read
ASTB:
Address Strobe
REGC:
Regulator Clock
AVDD:
Analog Power Supply
RESET:
Reset
AVREF:
Analog Reference Voltage
RTP0 to RTP7:
Real-time Output Port
AVSS:
Analog Ground
RTPTRG:
RTP Trigger Input
BVDD:
Power Supply for Bus Interface
R/W:
Read/Write Status
BVSS:
Ground for Bus Interface
RXD0, RXD1:
Receive Data
CLKOUT:
Clock Output
SCK0 to SCK4:
Serial Clock
DSTB:
Data Strobe
SCL0, SCL1:
Serial Clock
EVDD:
Power Supply for Port
SDA0, SDA1:
Serial Data
EVSS:
Ground for Port
SI0 to SI4:
Serial Input
HLDAK:
Hold Acknowledge
SO0 to SO4:
Serial Output
HLDRQ:
Hold Request
TI00, TI01, TI10, :
Timer Input
IC:
Internally Connected
TI11, TI2 to TI5
INTP0 to INTP6:
Interrupt Request from Peripherals
TO0 to TO5:
Timer Output
KR0 to KR7:
Key Return
TXD0, TXD1:
Transmit Data
LBEN:
Lower Byte Enable
UBEN:
Upper Byte Enable
NMI:
Non-Maskable Interrupt Request
V DD:
Power Supply
P00 to P07:
Port 0
VPP:
Programming Power Supply
P10 to P15:
Port 1
VSS:
Ground
P20 to P27:
Port 2
WAIT:
Wait
P30 to P37:
Port 3
WRH:
Write Strobe High Level Data
P40 to P47:
Port 4
WRL:
Write Strobe Low Level Data
P50 to P57:
Port 5
X1, X2:
Crystal for Main Clock
P60 to P65:
Port 6
XT1, XT2:
Crystal for Sub-clock
P70 to P77:
Port 7
Data Sheet U14734EJ1V0DS00
5
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
ROM
Note 1
TI00, TI01,
TI10, TI11
TO0, TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
Timer/counters
16-bit timer
: TM0, TM1
8-bit timer
: TM2 to TM7
SIO
SO0
SI0/SDA0Note 3
SCK0/SCL0Note 3
SO2
SI2/SDA1Note 3
SCK2/SCL1Note 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SI4
SCK4
CPU
INTC
RAM
Note 2
PC
ROM
correction
32-bit barrel
shifter
Multiplier
16 × 16 → 32
System
registers
HLDRQ (P96)
HLDAK (P95)
Instruction
queue
ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT (P110)
BCU
ALU
A1 to A12
(P100 to P107, P110 to P113)
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
General registers
32 bits × 32
CSI0/I2C0Note 3
CSI2/I2C1Note 3
CSI1/UART0
Ports
RTP
CSI3/UART1
A/D
converter
Key return
function
KR0 to KR7
DMAC: 6ch
RTP0 to RTP7
RTPTRG
AVDD
AVREF
AVSS
ANI0 to ANI11
ADTRG
Variable length
CSI4
P110 to P113
P100 to P107
P90 to P96
P80 to P83
P70 to P77
P60 to P65
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P15
P00 to P07
CG
3.3 V
Regulator
CLKOUT
X1
X2
XT1
XT2
RESET
VDD
REGC
Watch timer
Watchdog timer
Notes 1.
µPD703031A, 703031AY:
128 KB (mask ROM)
µPD703033A, 703033AY:
256 KB (mask ROM)
VSS
BVDD
BVSS
EVDD
EVSS
VPPNote 4
ICNote 5
µPD70F3033A, 70F3033AY: 256 KB (flash memory)
2.
3.
µPD703031A, 703031AY:
12 KB
µPD703033A, 703033AY, 70F3033A, 70F3033AY:
16 KB
I C bus interface and SDAn and SCLn pins are available only in the µPD703031AY, 703033AY,
2
and 70F3033AY.
6
4.
µPD70F3033A, 70F3033AY
5.
µPD703031A, 703031AY, 703033A, 703033AY
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
CONTENTS
1.
DIFFERENCES AMONG PRODUCTS ............................................................................................... 8
1.1
2.
3.
4.
Differences of µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY................. 8
PIN FUNCTIONS.................................................................................................................................. 9
2.1
Port Pins..................................................................................................................................................... 9
2.2
Non-Port Pins........................................................................................................................................... 11
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 15
PROGRAMMING FLASH MEMORY (µPD70F3033A, 70F3033AY ONLY) ................................... 19
3.1
Selecting Communication Mode ............................................................................................................ 19
3.2
Function of Flash Memory Programming.............................................................................................. 20
3.3
Connecting Dedicated Flash Programmer ............................................................................................ 20
ELECTRICAL SPECIFICATIONS...................................................................................................... 22
4.1
Flash Memory Programming Mode (µPD70F3033A, 70F3033AY only) ............................................... 47
5.
PACKAGE DRAWINGS..................................................................................................................... 48
6.
RECOMMENDED SOLDERING CONDITIONS ............................................................................... 50
Data Sheet U14734EJ1V0DS00
7
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
1. DIFFERENCES AMONG PRODUCTS
1.1 Differences of µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY
Part Number
µPD703031A
µPD703031AY
µPD703033A
µPD703033AY
µPD70F3033A µPD70F3033AY
Item
Internal ROM
128 KB (mask ROM)
Flash memory
programming pin
None
Provided (VPP)
Flash memory
programming mode
None
Provided (VPP = 7.8 V)
2
256 KB (mask ROM)
I C bus interface
pins (SCL0, SCL1,
SDA0, SDA1)
None
Electrical
specifications
Current consumption, etc. differs.
Others
Noise immunity and noise radiation differ because circuit scale and mask layout differ.
Cautions 1.
Provided
None
Provided
256 KB (flash memory)
None
Provided
There are differences in noise immunity and noise radiation between the flash memory and
mask ROM versions. When pre-producing an application set with the flash memory version
and then mass-producing it with the mask ROM version, be sure to conduct sufficient
evaluations for the commercial samples (not engineering samples) of the mask ROM
version.
2. When replacing the flash memory versions with mask ROM versions, write the same code
in the empty area of the internal ROM.
8
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
P00
I/O
PULL
I/O
Yes
P01
Function
Port 0
8-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
NMI
INTP0
P02
INTP1
P03
INTP2
P04
INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG
P07
INTP6
P10
I/O
Yes
P11
Port 1
6-bit I/O port
Input/output can be specified in 1-bit units.
SI0/SDA0
SO0
P12
SCK0/SCL0
P13
SI1/RXD0
P14
SO1/TXD0
P15
SCK1/ASCK0
P20
I/O
Yes
P21
Port 2
8-bit I/O port
Input/output can be specified in 1-bit units.
SI2/SDA1
SO2
P22
SCK2/SCL1
P23
SI3/RXD1
P24
SO3/TXD1
P25
SCK3/ASCK1
P26
TI2/TO2
P27
TI3/TO3
P30
I/O
Yes
P31
Port 3
8-bit I/O port
Input/output can be specified in 1-bit units.
TI00
TI01
P32
TI10/SI4
P33
TI11/SO4
P34
TO0/A13/SCK4
P35
TO1/A14
P36
TI4/TO4/A15
P37
TI5/TO5
P40 to P47
I/O
No
Port 4
8-bit I/O port
Input/output can be specified in 1-bit units.
AD0 to AD7
P50 to P57
I/O
No
Port 5
8-bit I/O port
Input/output can be specified in 1-bit units.
AD8 to AD15
Remark
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
9
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2/2)
Pin Name
I/O
PULL
P60 to P65
I/O
No
Port 6
6-bit I/O port
Input/output can be specified in 1-bit units.
A16 to A21
P70 to P77
Input
No
Port 7
8-bit input port
ANI0 to ANI7
P80 to P83
Input
No
Port 8
4-bit input port
ANI8 to ANI11
I/O
No
Port 9
7-bit I/O port
Input/output can be specified in 1-bit units.
LBEN/WRL
P90
P91
Function
Alternate Function
UBEN
P92
R/W/WRH
P93
DSTB/RD
P94
ASTB
P95
HLDAK
P96
HLDRQ
P100
I/O
Yes
P101
Port 10
8-bit I/O port
Input/output can be specified in 1-bit units.
RTP0/A5/KR0
RTP1/A6/KR1
P102
RTP2/A7/KR2
P103
RTP3/A8/KR3
P104
RTP4/A9/KR4
P105
RTP5/A10/KR5
P106
RTP6/A11/KR6
P107
RTP7/A12/KR7
P110
P111
I/O
Yes
Port 11
4-bit I/O port
Input/output can be specified in 1-bit units.
A1/WAIT
A2
P112
A3
P113
A4
Remark
10
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2.2 Non-Port Pins
(1/4)
Pin Name
A1
I/O
PULL
Output
Yes
Function
Low-order address bus used for external memory expansion
Alternate Function
P110/WAIT
A2
P111
A3
P112
A4
P113
A5
P100/RTP0/KR0
A6
P101/RTP1/KR1
A7
P102/RTP2/KR2
A8
P103/RTP3/KR3
A9
P104/RTP4/KR4
A10
P105/RTP5/KR5
A11
P106/RTP6/KR6
A12
P107/RTP7/KR7
A13
P34/TO0/SCK4
A14
P35/TO1
A15
P36/TO4/TI4
A16 to A21
Output
No
High-order address bus used for external memory expansion
P60 to P65
AD0 to AD7
I/O
No
16-bit multiplexed address/data bus used for external memory
expansion
P40 to P47
AD8 to AD15
P50 to P57
ADTRG
Input
Yes
A/D converter external trigger input
P05/INTP4
ANI0 to ANI7
Input
No
Analog input to A/D converter
P70 to P77
ANI8 to ANI11
ASCK0
P80 to P83
Input
Yes
ASCK1
Baud rate clock input for UART0
P15/SCK1
Baud rate clock input for UART1
P25/SCK3
External address strobe output
P94
ASTB
Output
No
AVDD
−
−
Positive power supply for A/D converter and alternate port
−
AVREF
Input
−
Reference voltage input for A/D converter
−
AVSS
−
−
Ground potential for A/D converter and alternate port
−
BVDD
−
−
Positive power supply for bus interface and alternate port
−
BVSS
−
−
Ground potential for bus interface and alternate port
−
CLKOUT
Output
−
Internal system clock output
−
DSTB
Output
No
External data strobe output
EVDD
−
−
Positive power supply for I/O ports and alternate-function pins
(except bus interface alternate port)
−
EVSS
−
−
Ground potential for I/O ports and alternate-function pins
(except bus interface alternate port)
−
HLDAK
Output
No
Bus hold acknowledge output
P95
HLDRQ
Input
No
Bus hold request input
P96
−
−
IC
Remark
Internally connected
(µPD703031A, 703031AY, 703033A, 703033AY only)
P93/RD
−
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
11
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2/4)
Pin Name
INTP0
I/O
PULL
Input
Yes
Function
External interrupt request input (analog noise elimination)
Alternate Function
P01
INTP1
P02
INTP2
P03
INTP3
P04
INTP4
Input
Yes
External interrupt request input (digital noise elimination)
INTP5
P05/ADTRG
P06/RTPTRG
INTP6
Input
Yes
External interrupt request input (digital noise elimination
supporting remote controller)
P07
KR0
Input
Yes
Key return input
P100/RTP0/A5
KR1
P101/RTP1/A6
KR2
P102/RTP2/A7
KR3
P103/RTP3/A8
KR4
P104/RTP4/A9
KR5
P105/RTP5/A10
KR6
P106/RTP6/A11
KR7
P107/RTP7/A12
LBEN
Output
No
External data bus’s low-order byte enable output
P90/WRL
NMI
Input
Yes
Non-maskable interrupt request input
P00
RD
Output
No
Read strobe output
P93/DSTB
REGC
−
−
Regulator output stabilization capacitance connection
−
RESET
Input
−
System reset input
−
Output
Yes
RTP0
Real-time output port
P100/KR0/A5
RTP1
P101/KR1/A6
RTP2
P102/KR2/A7
RTP3
P103/KR3/A8
RTP4
P104/KR4/A9
RTP5
P105/KR5/A10
RTP6
P106/KR6/A11
RTP7
P107/KR7/A12
RTPTRG
R/W
RXD0
Input
Yes
Real-time output port external trigger input
P06/INTP5
Output
No
External read/write status output
P92/WRH
Input
Yes
Serial receive data input for UART0 and UART1
P13/SI1
RXD1
SCK0
P23/SI3
I/O
Yes
Serial clock I/O (3-wire type) for CSI0 to CSI3
P12/SCL0
SCK1
P15/ASCK0
SCK2
P22/SCL1
SCK3
P25/ASCK1
SCK4
Remark
12
I/O
Yes
Serial clock I/O (3-wire type) for variable length CSI4
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
P34/TO0/A13
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(3/4)
Pin Name
SCL0
I/O
PULL
I/O
Yes
SCL1
SDA0
I/O
Yes
SDA1
SI0
Input
Yes
Function
2
Alternate Function
2
Serial clock I/O for I C0 and I C1
(µPD703031AY, 703033AY, 70F3033AY only)
2
2
P12/SCK0
P22/SCK2
Serial transmit/receive data I/O for I C0 and I C1
(µPD703031AY, 703033AY, 70F3033AY only)
P10/SI0
Serial receive data input (3-wire type) for CSI0 to CSI3
P10/SDA0
P20/SI2
SI1
P13/RXD0
SI2
P20/SDA1
SI3
P23/RXD1
SI4
Input
Yes
Serial receive data input (3-wire type) for variable length CSI4
P32/TI10
SO0
Output
Yes
Serial transmit data output (3-wire type) for CSI0 to CSI3
P11
SO1
P14/TXD0
SO2
P21
SO3
P24/TXD1
SO4
Output
Yes
Serial transmit data output (3-wire type) for variable length CSI4
P33/TI11
TI00
Input
Yes
External count clock input for TM0/external capture trigger
input for TM0
P30
TI01
External capture trigger input for TM0
P31
TI10
External count clock input for TM1/external capture trigger
input for TM1
P32/SI4
TI11
External capture trigger input for TM1
P33/SO4
External count clock input for TM2 to TM5
P26/TO2
TI2
Input
Yes
TI3
P27/TO3
TI4
P36/TO4/A15
TI5
P37/TO5
TO0
Output
Yes
Pulse signal output for TM0 and TM1
TO1
TO2
P34/A13/SCK4
P35/A14
Output
Yes
Pulse signal output for TM2 to TM5
P26/TI2
TO3
P27/TI3
TO4
P36/TI4/A15
TO5
P37/TI5
TXD0
Output
Yes
Serial transmit data output for UART0 and UART1
TXD1
UBEN
P14/SO1
P24/SO3
Output
No
VDD
−
−
Positive power supply pin
−
VPP
−
−
High voltage apply pin for program write/verify
(µPD70F3033A, 70F3033AY only)
−
VSS
−
−
Ground potential
−
WAIT
Input
Yes
Control signal input for inserting wait in bus cycle
P110/A1
WRH
Output
No
High-order byte write strobe signal output for external data
bus
P92/R/W
Remark
High-order byte enable output for external data bus
P91
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
13
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(4/4)
Pin Name
I/O
PULL
Function
Output
No
Low-order byte write strobe signal output for external data bus
X1
Input
No
Resonator connection for main clock
X2
−
WRL
XT1
Input
XT2
−
Remark
14
Alternate Function
P90/LBEN
−
−
No
Resonator connection for subsystem clock
−
−
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are show in Table 2-1. For
the input/output schematic circuit diagram of each type, refer to Figure 2-1.
Table 2-1. Types of Pin I/O Circuits (1/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Power Supply
8-A
EVDD
Input state:
10-A
EVDD
Input state:
EVDD
Input state:
EVDD
Input state:
Input state:
P00
NMI
P01
INTP0
P02
INTP1
P03
INTP2
P04
INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG
P07
INTP6
P10
SI0/SDA0
P11
SO0
P12
SCK0/SCL0
10-A
P13
SI1/RXD0
8-A
P14
SO0/TXD0
26
26
P15
SCK1/ASCK0
10-A
P20
SI2/SDA1
10-A
P21
SO2
P22
SCK2/SCL1
P23
SI3/RXD1
P24
SO3/TXD1
P25
SCK3/ASCK1
10-A
P26
TI2/TO2
8-A
P27
TI3/TO3
P30
TI00
P31
TI01
P32
TI10/SI4
P33
TI11/SO4
P34
TO0/A13/SCK4
P35
TO1/A14
5-A
P36
TI4/TO4/A15
8-A
P37
TI5/TO5
P40 to
P47
AD0 to AD7
5
BVDD
P50 to
P57
AD8 to AD15
5
BVDD
P60 to
P65
A16 to A21
5
BVDD
26
Recommended Connection of Unused Pins
Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
10-A
26
8-A
Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
Independently connect to BVDD or
BVSS via a resistor.
Output state: Leave open.
Data Sheet U14734EJ1V0DS00
15
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Table 2-1. Types of Pin I/O Circuits (2/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Power Supply
Recommended Connection of Unused Pins
Independently connect to AVDD or AVSS via a
resistor.
P70 to
P77
ANI0 to ANI7
9
AVDD
P80 to
P83
ANI8 to ANI11
9
AVDD
P90
LBEN/WRL
5
BVDD
Input state:
P91
UBEN
P92
R/W/WRH
P93
DSTB/RD
P94
ASTB
P95
HLDAK
P96
HLDRQ
P100
RTP0/A5/KR0
10-A
EVDD
Input state:
P101
RTP1/A6/KR1
P102
RTP2/A7/KR2
P103
RTP3/A8/KR3
P104
RTP4/A9/KR4
P105
RTP5/A10/KR5
P106
RTP6/A11/KR6
P107
RTP7/A12/KR7
P110
A1/WAIT
5-A
EVDD
Input state:
P111
A2
P112
A3
P113
A4
Leave open.
Independently connect to BVDD or
BVSS via a resistor.
Output state: Leave open.
26
Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
Independently connect to EVDD or
EVSS via a resistor.
Output state: Leave open.
CLKOUT
–
4
BVDD
RESET
–
2
EVDD
XT1
–
16
–
Connect to VSS via a resistor.
XT2
–
16
–
Leave open.
AVREF
–
–
–
Connect to AVSS via a resistor.
Note 1
–
–
–
Connect directly to VSS.
–
–
–
Connect to VSS.
IC
Note 2
VPP
Notes 1.
2.
–
µPD703031A, 703031AY, 703033A, 703033AY
µPD70F3033A, 70F3033AY
Caution Three power supply systems are available to supply power to the I/O buffers of the V850/SB1’s
pins: EVDD, BVDD, and AVDD. The voltage ranges that can be used for these I/O buffer power
supplies are shown below.
EVDD, BVDD: 3.0 V to 5.5 V
AVDD: 4.5 V to 5.5 V
The electrical specifications differ depending on whether the power supply voltage range is 3.0
V to under 4.0 V, or 4.0 V to 5.5 V.
16
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 2-1. Pin Input/Output Circuits (1/2)
Type 2
Type 5-A
VDD
Pullup
enable
P-ch
VDD
Data
IN
P-ch
IN/OUT
Output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
Input
enable
Type 8-A
Type 4
VDD
VDD
Data
Pullup
enable
P-ch
OUT
Output
disable
P-ch
VDD
Data
P-ch
N-ch
IN/OUT
Output
disable
N-ch
Push-pull output that can be set for high-impedance output
(both P-ch and N-ch off)
Type 5
Type 9
VDD
Data
P-ch
P-ch
IN/OUT
Output
disable
IN
+
N-ch
Comparator
–
N-ch
VREF (threshold voltage)
Input enable
Input
enable
Caution VDD in the circuit diagrams can be read as EVDD, BVDD, or AVDD, as appropriate.
Data Sheet U14734EJ1V0DS00
17
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 2-1. Pin Input/Output Circuits (2/2)
Type 10-A
Type 26
VDD
Pullup
enable
Pullup
enable
P-ch
VDD
Data
VDD
P-ch
VDD
Data
P-ch
P-ch
IN/OUT
Open drain
Output disable
N-ch
IN/OUT
Open drain
Output
disable
N-ch
Type 16
Feedback cut-off
P-ch
XT1
XT2
Caution VDD in the circuit diagrams can be read as EVDD, BVDD, or AVDD, as appropriate.
18
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
3. PROGRAMMING FLASH MEMORY (µPD70F3033A, 70F3033AY ONLY)
There are the following two methods for writing a program to the flash memory.
(1) On-board programming
Write a program to the flash memory using a dedicated flash programmer after the µPD70F3033A and
70F3033AY have been mounted on the target board. Also mount a connector, etc. on the target board to
communicate with the dedicated flash programmer.
(2) Off-board programming
Write a program using a dedicated adapter before the µPD70F3033A and 70F3033AY have been mounted on
the target board.
3.1 Selecting Communication Mode
To write the flash memory, use a dedicated flash programmer and serial communication.
Select a serial
communication mode from those listed in Table 3-1 in the format shown in Figure 3-1. Each communication mode is
selected by the number of VPP pulses shown in Table 3-1.
Table 3-1. Communication Modes
Communication Mode
Pins Used
Number of VPP Pulses
CSI0
SO0 (serial data output)
SI0 (serial data input)
SCK0 (serial clock input)
0
CSI0 + HS
SO0 (serial data output)
SI0 (serial data input)
SCK0 (serial clock input)
P15 (3-wire + handshake signal output of handshake communication)
3
UART0
TXD0 (serial data output)
RXD0 (serial data input)
8
Figure 3-1. Communication Mode Selecting Format
7.8 V
VPP
VDD
VSS
VDD
RESET
VSS
Data Sheet U14734EJ1V0DS00
19
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
3.2 Function of Flash Memory Programming
Operations such as writing to flash memory are performed by various command/data transmission and reception
operations according to the selected communication mode. The major functions are shown below.
Table 3-2. Major Functions of Flash Memory Programming
Description
Function
Category
Command
Verify
Batch verify
Compares the contents of the entire memory and the input data.
Erase
Batch erase
Erases the contents of the entire memory.
Write back
Writes back the contents which is overerased.
Blank check
Batch blank check
Checks the erase state of the entire memory.
Data write
High-speed write
Writes data by the specification of the write start address and the
number of bytes to be written, and executes verify check.
Continuous write
Writes data from the address following the high-speed write command
executed immediately before, and executes verify check.
Status read out
Reads out the status of operations.
Oscillation frequency
setting
Sets the oscillation frequency.
Erase time setting
Sets the erase time of batch erase.
Write time setting
Sets the write time of data write.
Write back time setting
Sets the write back time.
Baud rate setting
Sets the baud rate when using UART0.
Silicon signature
Reads out the silicon signature information.
Reset
Restarts the system of flash programmer.
System
setting/control
3.3 Connecting Dedicated Flash Programmer
The connection of the dedicated flash programmer and the µPD70F3033A and 70F3033AY differs according to
the communication mode. The connections for each communication mode are shown below.
Figure 3-2. Connection of Dedicated Flash Programmer in CSI0 Mode
Dedicated flash programmer
VPP
VPP
VDD
VDD
GND
VSS
RESET
RESET
SI
SO0
SO
SI0
SCK
20
µPD70F3033A, 70F3033AY
SCK0
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 3-3. Connection of Dedicated Flash Programmer in CSI0 + HS Mode
Dedicated flash programmer
µPD70F3033A, 70F3033AY
VPP
VPP
VDD
VDD
GND
VSS
RESET
RESET
SI
SO0
SO
SI0
SCK
SCK0
HS
P15
Figure 3-4. Connection of Dedicated Flash Programmer in UART0 Mode
Dedicated flash programmer
µPD70F3033A, 70F3033AY
VPP
VPP
VDD
VDD
GND
VSS
RESET
RESET
RxD
TXD0
TxD
RXD0
Data Sheet U14734EJ1V0DS00
21
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Supply voltage
Input voltage
Analog input voltage
Analog reference input voltage
Output current, low
Output current, high
Output voltage
Operating ambient temperature
Symbol
Ratings
Unit
VDD pin
–0.5 to +7.0
V
AVDD
AVDD pin
–0.5 to +7.0
V
BVDD
BVDD pin
–0.5 to +7.0
V
EVDD
EVDD pin
–0.5 to +7.0
V
AVSS
AVSS pin
–0.5 to +0.5
V
BVSS
BVSS pin
–0.5 to +0.5
V
EVSS
EVSS pin
–0.5 to +0.5
VDD
VI1
Conditions
Note 1 (BVDD pin)
VI2
Note 2 (EVDD pin)
VI3
VPP pin (µPD70F3033A, 70F3033AY only)
VIAN
Note 3 (AVDD pin)
AVREF
IOL
IOH
VO1
AVREF pin
V
–0.5 to EVDD + 0.5
–0.5 to +8.5
V
Note 4
V
Note 4
V
–0.5 to AVDD + 0.5
–0.5 to AVDD + 0.5
4.0
mA
Total for P00 to P07, P10 to P15, P20 to
P25
25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
25
mA
Total for P40 to P47, P90 to P96, CLKOUT
25
mA
Total for P50 to P57, P60 to P65
25
mA
Per pin
–4.0
mA
Total for P00 to P07, P10 to P15, P20 to
P25
–25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
–25
mA
Total for P40 to P47, P90 to P96, CLKOUT
–25
mA
Total for P50 to P57, P60 to P65
–25
Note 1 (BVDD pin)
VO2
Note 2 (EVDD pin)
TA
Normal operation mode
Tstg
V
Note 4
–0.5 to BVDD + 0.5
Per pin
Flash memory programming mode
(µPD70F3033A, 70F3033AY only)
Storage temperature
V
Note 4
µPD703031A, 703031AY
mA
Note 4
V
Note 4
V
–0.5 to BVDD + 0.5
–0.5 to EVDD + 0.5
–40 to +85
°C
10 to 85
°C
–65 to +150
°C
–40 to +125
°C
µPD703033A, 703033AY
µPD70F3033A, 70F3033AY
Notes 1. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins
2. Ports 0, 1, 2, 3, 10, 11, RESET, and their alternate-function pins
3. Ports 7, 8, and their alternate-function pins
4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
22
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Cautions
1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC,
and GND. Open-drain pins or open-collector pins, however, can be directly connected to
each other. Direct connection of the output pins between an IC product and an external
circuit is possible, if the output pins can be set to the high-impedance state and the output
timing of the external circuit is designed to avoid output conflict.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (TA = 25°C)
Parameter
Symbol
Input capacitance
CI
I/O capacitance
CIO
Output capacitance
CO
Conditions
MIN.
TYP.
MAX.
Unit
15
pF
15
pF
15
pF
fC = 1 MHz
Unmeasured pins returned to 0 V
Operating Conditions
(1) Operating frequency
Operating Frequency (fXX)
VDD
AVDD
BVDD
EVDD
Remark
2 to 20 MHz
4.0 to 5.5 V
4.5 to 5.5 V
4.0 to 5.5 V
4.0 to 5.5 V
Note 1
2 to 17 MHz
4.0 to 5.5 V
4.5 to 5.5 V
3.0 to 5.5 V
3.0 to 5.5 V
Note 1
Other than IDLE mode
4.0 to 5.5 V
4.5 to 5.5 V
3.0 to 5.5 V
3.0 to 5.5 V
–
IDLE mode
3.5 to 5.5 V
4.5 to 5.5 V
3.0 to 5.5 V
3.0 to 5.5 V
Note 2
32.768 kHz
Notes 1. During STOP mode (subsystem oscillator operating), VDD = 3.5 to 5.5 V. Shifting to STOP mode or
restoring from STOP mode must be performed at VDD = 4.0 V min.
2. Shifting to IDLE mode or restoring from IDLE mode must be performed at VDD = 4.0 V min.
(2) CPU operating frequency
Parameter
CPU operating frequency
Symbol
fCPU
Conditions
Main system clock operation
Subsystem clock operation
Data Sheet U14734EJ1V0DS00
MIN.
TYP.
0.25
32.768
MAX.
Unit
20
MHz
kHz
23
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Recommended Oscillator
(1) Main system clock oscillator (TA = –40 to +85°C)
(a) Connection of ceramic resonator or crystal resonator
X1
Parameter
Oscillation frequency
Oscillation stabilization time
Symbol
X2
Conditions
fXX
MIN.
TYP.
2
MAX.
Unit
20
MHz
19
–
Upon reset release
2 /fXX
s
–
Upon STOP mode release
Note
s
Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS).
Cautions 1. Main system clock oscillator operates on the output voltage of the on-chip regulator.
External clock input is prohibited.
2. When using the main system clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
3. Ensure that the duty of oscillation waveform is between 5.5 and 4.5.
4. Sufficiently evaluate the matching between the µPD703031A, 703031AY, 703033A, 703033AY,
70F3033A, 70F3033AY and the resonator.
24
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2) Subsystem clock oscillator (TA = –40 to +85°C)
(a) Connection of crystal resonator
XT1
Parameter
Symbol
Oscillation frequency
fXT
Oscillation stabilization time
–
XT2
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
10
s
Cautions 1. Subsystem clock oscillator operates on the output voltage of the on-chip regulator.
External clock input is prohibited.
2. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figure to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
3. Sufficiently evaluate the matching between the µPD703031A, 703031AY, 703033A, 703033AY,
70F3033A, 70F3033AY and the resonator.
Data Sheet U14734EJ1V0DS00
25
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
DC Characteristics
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
Input voltage, high
Symbol
VIH1
VIH2
VIH3
Input voltage, low
Output voltage, high
Conditions
Note 1
Note 2
Note 3
TYP.
MAX.
Unit
4.0 V ≤ BVDD ≤ 5.5 V
0.7BVDD
BVDD
V
3.0 V ≤ BVDD < 4.0 V
0.8BVDD
BVDD
V
4.0 V ≤ EVDD ≤ 5.5 V
0.7EVDD
EVDD
V
3.0 V ≤ EVDD < 4.0 V
0.8EVDD
EVDD
V
4.0 V ≤ EVDD ≤ 5.5 V
0.7EVDD
EVDD
V
3.0 V ≤ EVDD < 4.0 V
0.8EVDD
EVDD
V
4.5 V ≤ AVDD ≤ 5.5 V
0.7AVDD
AVDD
V
VIH4
Note 4
VIL1
Note 1
BVSS
0.3BVDD
V
VIL2
Note 2
EVSS
0.3EVDD
V
VIL3
Note 3
EVSS
0.3EVDD
V
VIL4
Note 4
AVSS
0.3AVDD
V
VOH1
Note 1
VOH2
Notes 2, 3
(except RESET)
Output voltage, low
MIN.
VOL
3.0 V ≤ BVDD ≤ 5.5 V,
IOH = –100 µA
BVDD–0.5
V
4.0 V ≤ BVDD ≤ 5.5 V,
IOH = –3 mA
BVDD–1.0
V
3.0 V ≤ EVDD ≤ 5.5 V,
IOH = –100 µA
EVDD–0.5
V
4.0 V ≤ EVDD ≤ 5.5 V,
IOH = –3 mA
EVDD–1.0
V
IOL = 3 mA,
3.0 V ≤ BVDD, EVDD ≤ 5.5 V
0.5
V
IOL = 3 mA,
4.0 V ≤ BVDD, EVDD ≤ 5.5 V
0.4
V
Input leakage current, high
ILIH
VI = VDD = BVDD = EVDD = AVDD
5
µA
Input leakage current, low
ILIL
VI = 0 V
–5
µA
Output leakage current, high
ILOH
5
µA
Output leakage current, low
ILOL
–5
µA
Notes 1. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins
2. P11, P14, P21, P24, P34, P35, P110 to P113, and their alternate-function pins
3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P100 to P107,
RESET, and their alternate-function pins
4. Ports 7, 8, and their alternate-function pins
26
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
DC Characteristics
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
µPD703031A,
Supply current
Symbol
IDD1
Conditions
MIN.
Note 1
In normal operation mode
TYP.
MAX.
Unit
25
40
mA
µPD703031AY,
IDD2
In HALT mode
10
20
mA
µPD703033A,
IDD3
In IDLE
Note 2
mode
Watch timer operating
1
4
mA
IDD4
In STOP
mode
Watch timer, subsystem
oscillator operating
13
70
µA
Subsystem oscillator
stopped, XT1 = VSS
8
70
µA
µPD703033AY
Note 1
IDD5
In normal mode (subsystem
Note 3
operation)
50
150
µA
IDD6
In IDLE mode (subsystem
Note 3
operation)
13
70
µA
µPD70F3033A,
IDD1
In normal operation mode
33
60
mA
µPD70F3033AY
IDD2
In HALT mode
10
20
mA
IDD3
In IDLE
Note 2
mode
Watch timer operating
1
4
mA
IDD4
In STOP
mode
Watch timer, subsystem
oscillator operating
13
100
µA
Subsystem oscillator
stopped, XT1 = VSS
8
100
µA
Pull-up resistance
Note 1
Note 1
IDD5
In normal mode (subsystem
Note 3
operation)
200
600
µA
IDD6
In IDLE mode (subsystem
Note 3
operation)
90
180
µA
RL
VIN = 0 V
30
100
kΩ
10
Notes 1. fCPU = fXX = 20 MHz, all peripheral functions operating, output buffer: OFF
2. fXX = 20 MHz
3. fCPU = fXT = 32.768 kHz, main system clock oscillator stopped
Remark
TYP. values are reference values for when TA = 25°C, VDD = BVDD = EVDD = AVDD = 5.0 V. The current
consumed by the output buffer is not included.
Data Sheet U14734EJ1V0DS00
27
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
Data retention voltage
VDDDR
STOP mode
Data retention current
IDDDR
VDD = VDDDR,
XT1 = VSS
(subsystem
stopped)
MIN.
TYP.
Note
3.0
MAX.
Unit
5.5
V
µPD703031A,
µPD703031AY,
µPD703033A,
µPD703033AY
8
70
µA
µPD70F3033A,
µPD70F3033AY
8
100
µA
Supply voltage rise time
tRVD
200
µs
Supply voltage fall time
tFVD
200
µs
Supply voltage hold time
(from STOP mode setting)
tHVD
0
ms
STOP release signal input time
tDREL
0
ms
Data retention high-level input voltage
VIHDR
All input ports
0.9VDDDR
VDDDR
V
Data retention low-level input voltage
VILDR
All input ports
0
0.1VDDDR
V
Note
During STOP mode (subsystem oscillator operating), VDD = 3.5 to 5.5 V.
Shifting to STOP mode or
restoring from STOP mode must be performed at VDD = 4.0 V min.
Remark
TYP. values are reference values for when TA = 25°C.
Setting STOP mode
V DDDR
VDD
tFVD
tRVD
tHVD
RESET (input)
NMI, INTPn (input)
(Released by falling edge)
NMI, INTPn (input)
(Released by rising edge)
28
tDREL
V IHDR
V IHDR
V ILDR
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
AC Characteristics (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS =
AVSS = BVSS = EVSS = 0 V)
AC Test Input Waveform (VDD: EVDD, BVDD, AVDD)
VDD
VIH
VIH
Test points
Input signal
0V
VIL
VIL
AC Test Output Test Points (EVDD, BVDD)
VOH
VOH
Output signal
Test points
VOL
VOL
Load Conditions
DUT
(Device under test)
CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance
of the device to 50 pF or less by inserting a buffer or by some other means.
Data Sheet U14734EJ1V0DS00
29
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(1) Clock timing
(a) TA = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V
MIN.
MAX.
CLKOUT output cycle
Parameter
<1>
Symbol
tCYK
Conditions
50 ns
31.2 µs
Unit
CLKOUT high-level width
<2>
tWKH
0.4tCYK – 12
CLKOUT low-level width
<3>
tWKL
0.4tCYK – 12
CLKOUT rise time
<4>
tKR
12
ns
CLKOUT fall time
<5>
tKF
12
ns
MIN.
MAX.
Unit
31.2 µs
ns
ns
(b) TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V
Parameter
Symbol
Conditions
CLKOUT output cycle
<1>
tCYK
58.8 ns
CLKOUT high-level width
<2>
tWKH
0.4tCYK – 15
CLKOUT low-level width
<3>
tWKL
0.4tCYK – 15
CLKOUT rise time
<4>
tKR
15
ns
CLKOUT fall time
<5>
tKF
15
ns
<1>
<2>
<3>
CLKOUT (output)
<4>
30
Data Sheet U14734EJ1V0DS00
<5>
ns
ns
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2) Output waveform (other than port 4, port 5, port 6, port 9, X1, and CLKOUT)
(TA = –40 to +85°°C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = BVSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Output rise time
<6>
tOR
20
ns
Output fall time
<7>
tOF
20
ns
<7>
<6>
Output signal
(3) Reset timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
RESET pin high-level width
<8>
tWRSH
500
ns
RESET pin low-level width
<9>
tWRSL
500
ns
<8>
<9>
RESET (input)
Data Sheet U14734EJ1V0DS00
31
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(4) Bus timing
(a) Clock asynchronous (TA = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB↓)
<10>
tSAST
0.5T – 16
ns
Address hold time (from ASTB↓)
<11>
tHSTA
0.5T – 15
ns
Address float from DSTB↓
<12>
tFDA
0
ns
Data input setup time from address
<13>
tSAID
(2 + n)T – 40
ns
Data input setup time from DSTB↓
<14>
tSDID
(1 + n)T – 40
ns
Delay time from ASTB↓ to DSTB↓
<15>
tDSTD
0.5T – 15
ns
Data input hold time (from DSTB↑)
<16>
tHDID
0
ns
Address output time from DSTB↑
<17>
tDDA
(1 + i)T – 15
ns
Delay time from DSTB↑ to ASTB↑
<18>
tDDST1
0.5T – 15
ns
Delay time from DSTB↑ to ASTB↓
<19>
tDDST2
(1.5 + i)T – 15
ns
DSTB low-level width
<20>
tWDL
(1 + n)T – 22
ns
ASTB high-level width
<21>
tWSTH
T – 15
ns
Data output time from DSTB↓
<22>
tDDOD
Data output setup time (to DSTB↑)
<23>
tSODD
(1 + n)T – 25
ns
Data output hold time (from DSTB↑)
<24>
tHDOD
T – 20
ns
WAIT setup time (to address)
<25>
tSAWT1
n≥1
1.5T – 40
ns
<26>
tSAWT2
n≥1
(1.5 + n)T – 40
ns
<27>
tHAWT1
n≥1
(0.5 + n)T
ns
<28>
tHAWT2
n≥1
(1.5 + n)T
ns
<29>
tSSTWT1
n≥1
T – 32
ns
<30>
tSSTWT2
n≥1
(1 + n)T – 32
ns
<31>
tHSTWT1
n≥1
nT
ns
<32>
tHSTWT2
n≥1
(1 + n)T
ns
HLDRQ high-level width
<33>
tWHQH
T + 10
ns
HLDAK low-level width
<34>
tWHAL
T – 15
ns
Bus output delay time from HLDAK↑
<35>
tDHAC
–6
ns
Delay time from HLDRQ↓ to HLDAK↓
<36>
tDHQHA1
Delay time from HLDRQ↑ to HLDAK↑
<37>
tDHQHA2
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
10
0.5T
ns
(2n + 7.5)T + 25
ns
1.5T + 25
ns
Remarks 1. T = 1/fCPU (fCPU: CPU clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
32
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(b) Clock asynchronous (TA = –40 to +85°°C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB↓)
<10>
tSAST
0.5T – 20
ns
Address hold time (from ASTB↓)
<11>
tHSTA
0.5T – 20
ns
Address float from DSTB↓
<12>
tFDA
0
ns
Data input setup time from address
<13>
tSAID
(2 + n)T – 50
ns
Data input setup time from DSTB↓
<14>
tSDID
(1 + n)T – 50
ns
Delay time from ASTB↓ to DSTB↓
<15>
tDSTD
0.5T – 15
ns
Data input hold time (from DSTB↑)
<16>
tHDID
0
ns
Address output time from DSTB↑
<17>
tDDA
(1 + i)T – 15
ns
Delay time from DSTB↑ to ASTB↑
<18>
tDDST1
0.5T – 15
ns
Delay time from DSTB↑ to ASTB↓
<19>
tDDST2
(1.5 + i)T – 15
ns
DSTB low-level width
<20>
tWDL
(1 + n)T – 35
ns
ASTB high-level width
<21>
tWSTH
T – 15
ns
Data output time from DSTB↓
<22>
tDDOD
Data output setup time (to DSTB↑)
<23>
tSODD
(1 + n)T – 35
ns
Data output hold time (from DSTB↑)
<24>
tHDOD
T – 25
ns
WAIT setup time (to address)
<25>
tSAWT1
n≥1
1.5T – 55
ns
<26>
tSAWT2
n≥1
(1.5 + n)T – 55
ns
<27>
tHAWT1
n≥1
(0.5 + n)T
ns
<28>
tHAWT2
n≥1
(1.5 + n)T
ns
<29>
tSSTWT1
n≥1
T – 45
ns
<30>
tSSTWT2
n≥1
(1 + n)T – 45
ns
<31>
tHSTWT1
n≥1
nT
ns
<32>
tHSTWT2
n≥1
(1 + n)T
ns
HLDRQ high-level width
<33>
tWHQH
T + 10
ns
HLDAK low-level width
<34>
tWHAL
T – 25
ns
Bus output delay time from HLDAK↑
<35>
tDHAC
–6
ns
Delay time from HLDRQ↓ to HLDAK↓
<36>
tDHQHA1
Delay time from HLDRQ↑ to HLDAK↑
<37>
tDHQHA2
WAIT hold time (from address)
WAIT setup time (to ASTB↓)
WAIT hold time (from ASTB↓)
10
0.5T
ns
(2n + 7.5)T + 25
ns
1.5T + 25
ns
Remarks 1. T = 1/fCPU (fCPU: CPU clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from
X1.
Data Sheet U14734EJ1V0DS00
33
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(c) Clock synchronous (TA = –40 to +85°C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT↑ to address
<38>
tDKA
0
19
ns
Delay time from CLKOUT↑ to address
float
<39>
tFKA
–12
10
ns
Delay time from CLKOUT↓ to ASTB
<40>
tDKST
0
19
ns
Delay time from CLKOUT↑ to DSTB
<41>
tDKD
0
19
ns
Data input setup time (to CLKOUT↑)
<42>
tSIDK
20
ns
Data input hold time (from CLKOUT↑)
<43>
tHKID
5
ns
Data output delay time from CLKOUT↑
<44>
tDKOD
WAIT setup time (to CLKOUT↓)
<45>
tSWTK
20
ns
WAIT hold time (from CLKOUT↓)
<46>
tHKWT
5
ns
HLDRQ setup time (to CLKOUT↓)
<47>
tSHQK
20
ns
HLDRQ hold time (from CLKOUT↓)
<48>
tHKHQ
5
ns
Delay time from CLKOUT↑ to address
float (during bus hold)
<49>
tDKF
19
ns
Delay time from CLKOUT↑ to HLDAK
<50>
tDKHA
19
ns
19
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
(d) Clock synchronous (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT↑ to address
<38>
tDKA
0
22
ns
Delay time from CLKOUT↑ to address
float
<39>
tFKA
–16
10
ns
Delay time from CLKOUT↓ to ASTB
<40>
tDKST
0
19
ns
Delay time from CLKOUT↑ to DSTB
<41>
tDKD
0
22
ns
Data input setup time (to CLKOUT↑)
<42>
tSIDK
20
ns
Data input hold time (from CLKOUT↑)
<43>
tHKID
5
ns
Data output delay time from CLKOUT↑
<44>
tDKOD
WAIT setup time (to CLKOUT↓)
<45>
tSWTK
24
ns
WAIT hold time (from CLKOUT↓)
<46>
tHKWT
5
ns
HLDRQ setup time (to CLKOUT↓)
<47>
tSHQK
24
ns
HLDRQ hold time (from CLKOUT↓)
<48>
tHKHQ
5
ns
Delay time from CLKOUT↑ to address
float (during bus hold)
<49>
tDKF
19
ns
Delay time from CLKOUT↑ to HLDAK
<50>
tDKHA
19
ns
22
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
34
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(e) Read cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
T2
TW
T3
CLKOUT (output)
<38>
A1 to A15 (output)
A16 to A21 (output)
Note (output)
<42>
<13>
<43>
<39>
AD0 to AD15 (I/O)
Address
Data
<40>
<10>
<11>
<16>
<40>
ASTB (output)
<21>
<41>
<41>
<18>
<17>
<19>
<12>
<15>
<14>
DSTB, RD (output)
<29><45> <46>
<20>
<45>
<46>
<31>
<30>
<32>
WAIT (input)
<25>
<27>
<26>
<28>
Note R/W, UBEN, LBEN
Remark
The broken lines indicate high impedance.
Data Sheet U14734EJ1V0DS00
35
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(f) Write cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
T2
TW
T3
CLKOUT (output)
<38>
A1 to A15 (output)
A16 to A21 (output)
Note (output)
<44>
AD0 to AD15 (I/O)
Address
Data
<40>
<10>
<11>
<40>
ASTB (output)
<21>
<41>
<41>
<18>
<22>
<15>
<24>
<23>
DSTB, WRL, WRH (output)
<29><45> <46>
<31>
<30>
<32>
WAIT (input)
<25>
<27>
<26>
<28>
Note R/W, UBEN, LBEN
Remark
36
The broken lines indicate high impedance.
Data Sheet U14734EJ1V0DS00
<20>
<45>
<46>
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(g) Bus hold timing
TH
TH
TH
TH
TI
CLKOUT (output)
<47>
<47> <48>
<33>
HLDRQ (input)
<50>
<50>
<37>
<36>
HLDAK (output)
<34>
<49>
<35>
A16 to A19 (output)
Note (output)
A1 to A15 (output)
AD0 to AD15 (I/O)
Data
ASTB (output)
DSTB, RD (output)
WRL, WRH (output)
Note R/W, UBEN, LBEN
Remark
The broken lines indicate high impedance.
Data Sheet U14734EJ1V0DS00
37
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(5) Interrupt timing
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
NMI high-level width
<51>
tWNIH
500
ns
NMI low-level width
<52>
tWNIL
500
ns
INTPn high-level width
<53>
tWITH
500
ns
3T + 20
ns
3Tsmp + 20
ns
500
ns
3T + 20
ns
3Tsmp + 20
ns
n = 0 to 3, analog noise
elimination
n = 4, 5, digital noise
elimination
n = 6, digital noise
elimination
INTPn low-level width
<54>
tWITL
n = 0 to 3, analog noise
elimination
n = 4, 5, digital noise
elimination
n = 6, digital noise
elimination
Remarks 1. T = 1/fXX
2. Tsmp = Noise elimination sampling clock cycle
<51>
<52>
<53>
<54>
NMI (input)
INTPn (input)
Remark n = 0 to 6
38
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(6) RPU timing (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter
TIn0, TIn1 high-level width
Symbol
<55>
tTIHn
Conditions
n = 0, 1
MIN.
MAX.
Unit
Note
ns
Note
2Tsam + 20
ns
2Tsam + 20
TIn0, TIn1 low-level width
<56>
tTILn
n = 0, 1
TIn high-level width
<57>
tTIHn
n = 2 to 5
3T + 20
ns
TIn low-level width
<58>
tTILn
n = 2 to 5
3T + 20
ns
Note Tsam can select the following count clocks by setting the PRMn2 to PRMn0 bits of prescaler mode registers
n0, n1 (PRMn0, PRMn1).
When n = 0 (TM0), Tsam = 2T, 4T, 16T, 64T, 256T, or 1/INTWTNI cycle
When n = 1 (TM1), Tsam = 2T, 4T, 16T, 32T, 128T, or 256T
However, when the TIn0 valid edge is selected as the count clock, Tsam = 4T.
Remark T = 1/fXX
<55>
<56>
<57>
<58>
TIn0, TIn1 (input)
TIn (input)
Remark
n = 0 to 5
Data Sheet U14734EJ1V0DS00
39
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(7) Asynchronous serial interface (UART0, UART1) timing
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASCKn cycle time
<59>
tKCY13
200
ns
ASCKn high-level width
<60>
tKH13
80
ns
ASCKn low-level width
<61>
tKSO13
80
ns
Remark n = 0, 1
<59>
<60>
<61>
ASCKn (input)
Remark n = 0, 1
40
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(8) 3-wire serial interface (CSI0 to CSI3) timing
(a) Master mode (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle
<62>
tKCY1
400
ns
SCKn high-level width
<63>
tKH1
140
ns
SCKn low-level width
<64>
tKL1
140
ns
SIn setup time (to SCKn↑)
<65>
tSIK1
50
ns
SIn hold time (from SCKn↑)
<66>
tKSI1
50
ns
Delay time from SCKn↓ to SOn output
<67>
tKSO1
60
ns
MAX.
Unit
Remark n = 0 to 3
(b) Slave mode (TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
SCKn cycle
<62>
tKCY2
400
ns
SCKn high-level width
<63>
tKH2
140
ns
SCKn low-level width
<64>
tKL2
140
ns
SIn setup time (to SCKn↑)
<65>
tSIK2
50
ns
SIn hold time (from SCKn↑)
<66>
tKSI2
50
ns
Delay time from SCKn↓ to SOn output
<67>
tKSO2
4.0 V ≤ EVDD ≤ 5.5 V
60
ns
3.0 V ≤ EVDD < 4.0 V
100
ns
Remark n = 0 to 3
<62>
<63>
<64>
SCKn (I/O)
<65>
SIn (input)
<66>
Input data
<67>
SOn (output)
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0 to 3
Data Sheet U14734EJ1V0DS00
41
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(9) 3-wire variable length serial interface (CSI4) timing
(a) Master mode (TA = –40 to +85°°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
SCK4 cycle
Symbol
<68>
SCK4 high-level width
SCK4 low-level width
SI4 setup time (to SCK4↑)
<69>
<70>
<71>
tKCY1
tKH1
tKL1
tSIK1
SI4 hold time (from SCK4↑)
<72>
tKSI1
Delay time from SCK4↓ to SO4
output
<73>
tKSO1
Conditions
MIN.
MAX.
4.0 V ≤ EVDD ≤ 5.5 V
200
ns
3.0 V ≤ EVDD < 4.0 V
400
ns
4.0 V ≤ EVDD ≤ 5.5 V
60
ns
3.0 V ≤ EVDD < 4.0 V
140
ns
4.0 V ≤ EVDD ≤ 5.5 V
60
ns
3.0 V ≤ EVDD < 4.0 V
140
ns
4.0 V ≤ EVDD ≤ 5.5 V
25
ns
3.0 V ≤ EVDD < 4.0 V
50
ns
20
ns
55
Unit
ns
(b) Slave mode (TA = –40 to +85°°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
SCK4 cycle
SCK4 high-level width
SCK4 low-level width
SI4 setup time (to SCK4↑)
42
Symbol
<68>
<69>
<70>
<71>
tKCY2
tKH2
tKL2
tSIK2
SI4 hold time (from SCK4↑)
<72>
tKSI2
Delay time from SCK4↓ to SO4
output
<73>
tKSO2
Conditions
MIN.
MAX.
Unit
4.0 V ≤ EVDD ≤ 5.5 V
200
ns
3.0 V ≤ EVDD < 4.0 V
400
ns
4.0 V ≤ EVDD ≤ 5.5 V
60
ns
3.0 V ≤ EVDD < 4.0 V
140
ns
4.0 V ≤ EVDD ≤ 5.5 V
60
ns
3.0 V ≤ EVDD < 4.0 V
140
ns
4.0 V ≤ EVDD ≤ 5.5 V
25
ns
3.0 V ≤ EVDD < 4.0 V
50
ns
20
ns
4.0 V ≤ EVDD ≤ 5.5 V
55
ns
3.0 V ≤ EVDD < 4.0 V
100
ns
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
<68>
<69>
<70>
SCK4 (I/O)
<71>
SI4 (input)
<72>
Input data
<73>
SO4 (output)
Remark
Output data
The broken lines indicate high impedance.
Data Sheet U14734EJ1V0DS00
43
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(10) I C bus mode (µPD703031AY, 703033AY, 70F3033AY only)
2
(TA = –40 to +85°C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
SCLn clock frequency
Normal Mode
High-Speed Mode
MIN.
MAX.
MIN.
MAX.
Unit
–
fCLK
0
100
0
400
kHz
<74>
tBUF
4.7
–
1.3
–
µs
Hold time
<75>
tHD:STA
4.0
–
0.6
–
µs
SCLn clock low-level width
<76>
tLOW
4.7
–
1.3
–
µs
SCLn clock high-level width
<77>
tHIGH
4.0
–
0.6
–
µs
Setup time for start/restart
conditions
<78>
tSU:STA
4.7
–
0.6
–
µs
Data hold
time
<79>
tHD:DAT
5.0
–
–
–
µs
Bus-free time (between
stop/start conditions)
Note 1
CBUS
compatible
master
Note 2
2
0
I C mode
Data setup time
<80>
tSU:DAT
250
Note 2
Note 3
0.9
0
–
Note 4
100
–
µs
–
ns
Note 5
300
ns
Note 5
300
ns
SDAn and SCLn signal rise
time
<81>
tR
–
1000
20 + 0.1Cb
SDAn and SCLn signal fall
time
<82>
tF
–
300
20 + 0.1Cb
Stop condition setup time
<83>
tSU:STO
4.0
–
0.6
–
µs
Pulse width of spike
suppressed by input filter
<84>
tSP
–
–
0
50
ns
Capacitance load of each
bus line
–
Cb
–
400
–
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin.. of SCLn
signal) in order to occupy the undefined area at the falling edge of SCLn.
3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time
(tHD:DAT) needs to be satisfied.
2
2
4. The high-speed mode I C bus can be used in the normal-mode I C bus system. In this case, set the
high-speed mode I2C bus so that it meets the following conditions.
• If the system does not extend the SCLn signal’s low state hold time:
tHD:DAT ≥ 250 ns
• If the system extends the SCLn signal’s low state hold time:
Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000
+ 250 = 1250 ns: Normal mode I2C bus specification).
5.
Cb: Total capacitance of one bus line (unit: pF)
Remark n = 0, 1
44
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
<77>
<76>
SCLn (I/O)
<82>
<81>
<79>
<80>
<78>
<75>
<84>
<83>
<75>
SDAn (I/O)
<74>
Stop
condition
Start
condition
Restart
condition
Stop
condition
n = 0, 1
Remark
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF, VSS = AVSS = 0 V, Output pin load
capacitance: CL = 50 pF)
Parameter
Symbol
Resolution
Conditions
MIN.
TYP.
MAX.
Unit
10
10
10
bit
ADM2 = 00H
±0.6
%FSR
ADM2 = 01H
±1.0
%FSR
10
µs
±0.4
%FSR
ADM2 = 00H
±0.4
%FSR
ADM2 = 01H
±0.6
%FSR
ADM2 = 00H
±4.0
LSB
ADM2 = 01H
±6.0
LSB
ADM2 = 00H
±4.0
LSB
ADM2 = 01H
±6.0
LSB
4.5
5.5
V
–
Note 1
Overall error
–
Conversion time
Zero-scale error
Full-scale error
tCONV
Note 1
AINL
Note 1
Integral linearity error
5
AINL
Note 2
Differential linearity error
Note 2
INL
DNL
Analog reference voltage
AVREF
AVREF = AVDD
Analog power supply voltage
AVDD
4.5
5.5
V
Analog input voltage
VIAN
AVSS
AVREF
V
AVREF input current
AIREF
1
2
mA
AVDD current
AIDD
ADM2 = 00H
3
6
mA
ADM2 = 01H
4
8
mA
Notes 1. Excluding quantization error (±0.05 %FSR)
2. Excluding quantization error (±0.5 LSB)
Remarks 1. LSB: Least Significant Bit
FSR: Full Scale Range
2. ADM2: A/D converter mode register 2
Data Sheet U14734EJ1V0DS00
45
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Regulator (TA = –40 to +85°°C, VDD = 4.0 to 5.5 V, VSS = 0 V)
Parameter
Symbol
Output stabilization time
<85>
tREG
Conditions
MIN.
Stabilization capacitance C = 1 µF
(Connected to REGC pin)
1
TYP.
MAX.
Unit
ms
VDD
<85>
BVDD, EVDD
RESET (input)
Cautions 1. Be sure to start inputting supply voltage (VDD) when RESET = VSS = EVSS = BVSS = 0 V
(the above state), and make RESET high level after the tREG period has elapsed.
2. If supply voltage (BVDD or EVDD) is input before the tREG period has elapsed following the
input of supply voltage (VDD), data may be driven from the pins until the tREG period has
elapsed because the I/O buffers’ power supply was turned on while the circuit was in an
undefined state. To avoid this situation, it is recommended to input supply voltage
(BVDD or EVDD) after the tREG period has elapsed following the input of supply voltage
(VDD).
46
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
4.1 Flash Memory Programming Mode (µPD70F3033A, 70F3033AY only)
Basic characteristics (TA = 10 to 85°°C)
Parameter
Symbol
Operating frequency
fX
Power supply voltage
VDD
Write current
IDDW
Conditions
When VPP = VPP1
IPPW
Erase current
IDDE
IPPE
VPP power supply voltage
When VPP = VPP1
MAX.
Unit
2
20
MHz
4.5
5.5
V
VDD pin
63
mA
VPP pin
50
mA
VDD pin
63
mA
VPP pin
100
mA
0.6
V
VPP0
During normal operation
VPP1
During flash memory programming
MIN.
TYP.
0
7.5
7.8
8.1
V
CWRT
20
20
20
Times
Unit erase time
tER
0.2
0.2
0.2
s
Total erase time
tERT
5.8
s
Write count
Note
Note Erase/write are regarded as 1 cycle.
Data Sheet U14734EJ1V0DS00
47
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
5. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C D
R
Q
26
25
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
16.00±0.20
B
14.00±0.20
C
14.00±0.20
D
16.00±0.20
F
1.00
G
1.00
H
0.22 +0.05
−0.04
I
J
0.08
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.17 +0.03
−0.07
N
0.08
P
1.40±0.05
Q
0.10±0.05
R
+7°
3° −3°
S
1.60 MAX.
S100GC-50-8EU-1
48
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
100-PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
Q
R
31
30
100
1
F
G
J
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
23.6±0.4
B
20.0±0.2
C
14.0±0.2
D
17.6±0.4
F
0.8
G
H
0.6
0.30±0.10
I
0.15
J
K
L
0.65 (T.P.)
1.8±0.2
0.8±0.2
M
0.15+0.10
−0.05
N
0.10
P
2.7±0.1
Q
R
S
0.1±0.1
5°±5°
3.0 MAX.
P100GF-65-3BA1-4
Data Sheet U14734EJ1V0DS00
49
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
6. RECOMMENDED SOLDERING CONDITIONS
The µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY should be soldered and mounted
under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 6-1. Surface Mounting Type Soldering Conditions (1/2)
100-pin plastic LQFP (fine pitch) (14 × 14)
(1) µPD703031AGC-×××
×××-8EU:
×××
100-pin plastic LQFP (fine pitch) (14 × 14)
×××-8EU:
×××
µPD703031AYGC-×××
×××-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14)
×××
µPD703033AGC-×××
100-pin plastic LQFP (fine pitch) (14 × 14)
×××-8EU:
×××
µPD703033AYGC-×××
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
Note
Exposure limit: 7 days (after that, prebake at 125°C for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
Note
Exposure limit: 7 days (after that, prebake at 125°C for 10 hours)
VP15-107-2
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
(2) µPD70F3033AGC-8EU:
µPD70F3033AYGC-8EU:
Soldering Method
100-pin plastic LQFP (fine pitch) (14 × 14)
100-pin plastic LQFP (fine pitch) (14 × 14)
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
Note
Exposure limit: 3 days (after that, prebake at 125°C for 10 hours)
IR35-103-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
Note
Exposure limit: 3 days (after that, prebake at 125°C for 10 hours)
VP15-103-2
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
50
Do not use different soldering methods together (except for partial heating).
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Table 6-1. Surface Mounting Type Soldering Conditions (2/2)
(3) µPD703031AGF-×××
×××-3BA:
×××
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
×××-3BA:
×××
µPD703031AYGF-×××
×××-3BA: 100-pin plastic QFP (14 × 20)
×××
µPD703033AGF-×××
100-pin plastic QFP (14 × 20)
×××-3BA:
×××
µPD703033AYGF-×××
100-pin plastic QFP (14 × 20)
µPD70F3033AGF-3BA:
µPD70F3033AYGF-3BA:
Soldering Method
100-pin plastic QFP (14 × 20)
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
Note
Exposure limit: 7 days (after that, prebake at 125°C for 20 hours)
IR35-207-2
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
Note
Exposure limit: 7 days (after that, prebake at 125°C for 20 hours)
VP15-207-2
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: once
Preheating temperature: 120°C max. (package surface temperature)
Note
Exposure limit: 7 days (after that, prebake at 125°C for 20 hours)
WS60-207-1
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
Data Sheet U14734EJ1V0DS00
51
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
[MEMO]
52
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
[MEMO]
Data Sheet U14734EJ1V0DS00
53
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Caution
2
2
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use
2
2
these components in an I C system, provided that the system conforms to the I C Standard
Specification as defined by Philips.
Reference document
Note
Electrical Characteristics for Microcomputer (IEI-601)
Note
This document number is that of the Japanese version.
V850/SB1, V850/SB2, and V850 Family are trademarks of NEC Corporation.
54
Data Sheet U14734EJ1V0DS00
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U14734EJ1V0DS00
55
µPD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8