NEC UPD77213GJ-XXX-8EN

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD77210, 77213
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
The µPD77210 and 77213 are 16-bit fixed-point digital signal processors (DSP).
Compared with the existing members of the µPD77111 Family, the µPD77210 Family consumes less power and is
ideal for battery-driven mobile terminal applications such as PDAs and cellular telephones. The µP77210 Family is
DSP is also compatible with the µPD77111 Family at the binary level.
The µPD77210 Family consists of the µPD77210 and 77213. Unless otherwise specified, the µPD77210 Family
refers to the entire family. If there are some differences in function or operation among family products, they are
described under their respective names.
The functions of the µPD77210 Family are described in detail in the following user’s manuals. Refer to these
manuals when designing your system.
µPD77210 Family User’s Manual - Architecture:
In preparation
µPD77016 Family User’s Manual - Instructions:
U13116E
FEATURES
• Instruction cycle (operating clock):
µPD77210
6.25 ns MIN. (160 MHz MAX.)
µPD77213
8.33 ns MIN. (120 MHz MAX.)
• Memory
-Internal instruction memory:
µPD77210 :RAM 31.5 Kwords x 32 bits
µPD77213 :RAM 15.5 Kwords x 32 bits
ROM 64 Kwords x 32 bits
-Data memory:
µPD77210 :RAM 30 Kwords x 16 bits x 2 planes (X and Y data memories)
External memory space 1 Mwords x 16 bits (common to X and Y data memories)
µPD77213 :RAM 18 Kwords x 16 bits x 2 planes (X and Y data memories)
ROM 32 Kwords x 16 bits x 2 planes (X and Y data memories)
External memory space 1 Mwords x 16 bits (common to X and Y data memories)
• Peripheral
-Audio serial interface: 1 channel
-16-bit timer: 2 channels
-Time-division serial interface: 1 channel
-Peripheral-memory DMA transfer function
-16-bit host interface: 1 channel
-SD (Secure Digital) card interface
:µPD77213 only
-16-bit general-purpose port
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15203EJ3V0DS00 (3rd edition)
Date Published November 2001 NS CP(K)
Printed in Japan
The mark
shows major revised points.
©
2001
µPD77210, 77213
• Supply voltage
-DSP core supply voltage:
1.425 to 1.65 V (MAX. operating speed 120 MHz),
-I/O pin supply voltage:
2.7 to 3.6 V
1.55 to 1.65 V (MAX. operating speed 160 MHz) µPD77210 only
ORDERING INFORMATION
Parts Number
µPD77210F1-DA2
Package
161-pin plastic fine pitch BGA (10 x 10)
µPD77210GJ-8EN
144-pin plastic LQFP (fine pitch) (20 x 20)
µPD77213F1-xxx-DA2
161-pin plastic fine pitch BGA (10 x 10)
µPD77213GJ-xxx-8EN
144-pin plastic LQFP (fine pitch) (20 x 20)
Remark xxx indicates ROM code suffix.
2
Data Sheet U15203EJ3V0DS
BLOCK DIAGRAM
Peripheral unit
X bus
External memory
External
memory I/O
Y bus
Note
Serial I/O
(AUDIO)
Host I/O
Peripheral bus
Data Sheet U15203EJ3V0DS
Serial I/O
(TDM)
Peripheral-memory transfer bus
SD Card I/O
X memory
Y memory
R0 to R7
Y memory
data
addressing
unit
X memory
data
addressing
unit
Data memory
unit
DMA
controller
Interrupt
controller
Main bus
MAC
16 × 16 + 40 → 40
ALU (40)
BSFT
Operation unit
Program control
unit
Port
Loop control
stack
PC stack
Instruction
memory
Timer
CPU control
Clock control
IE
I/O
Note µ PD77213 only
RESET CSTOP HALTS STOPS
CLKOUT CLKIN
PLL
3
µPD77210, 77213
Interrupt
control
µPD77210, 77213
FUNCTIONAL PIN BLOCK
TSO
TSORQ
TSOEN
TSCK
TSI
TSIEN
TSIAK
Serial interface
(time division serial)
IVDD
EVDD
RESET
INTmn
CLKIN
CLKOUT
PLL0 to PLL3
MA0 to MA19
MD0 to MD15
MRD
MWR
MHOLDRQ
MHOLDAK
MBSTB
MWAIT
2
Host interface
16
P0 to P15
HCS
HA0, HA1
HRD
HRE
HWR
HWE
HD0 to HD15
Clock
4
STOPS
CSTOP
HALTS
SDCLK
SDMON
16
Reset and interrupt
16
SDDAT0
SDCR
Note
Port
+3.3 V
ASOEN/LRCLK
ASIEN/MCLK
ASCK/BCLK
ASI
ASO
Serial interface
(audio serial)
SD card interface
+1.5 V
System control
20
16
External data memory
interface
TIMOUT
TDO, TICE
TCK, TDI, TMS, TRST
Timer
2
4
For debugging
GND
Note µPD77213 only
Caution Some port pins, host interface pins, serial interface pins, interrupt pins, and SD card interface
pins are alternate function pins.
Remark m, n = 0 to 3
4
Data Sheet U15203EJ3V0DS
DSP FUNCTION LIST
Memory
space
(words ×
bits)
Item
µPD77110
Int. instruction RAM
35.5 K × 32
1 K × 32
3.5 K × 32
Int. instruction ROM
None
31.75 K × 32
48 K × 32
24 K × 16 each
3 K × 16 each
16 K × 16 each
None
16 K × 16 each
32 K × 16 each
Data RAM
µPD77111
µPD77112
µPD77113A
µPD77114
µPD77115
µPD77210
µPD77213
11.5 K × 32
31.5 K × 32
15.5 K × 32
64K × 32
None
16 K × 16 each
30 K × 16 each
18 K × 16 each
(X/Y memory)
Data ROM
32 K × 16 each
None
(X/Y memory)
Ext. instruction memory
Ext. data memory (X/Y
None
32 K × 16 each
None
16 K × 16 each
None
8 K × 16 each
None
1 M × 16
1 M × 16 (8 K ×
memory)
Data Sheet U15203EJ3V0DS
Instruction cycle (at maximum
operating speed)
16, using SD I/F)
15.3 ns
13.3 ns
6.25 ns
8.33 ns
(65 MHz)
(75 MHz)
(160 MHz)
(120 MHz)
Integer multiple
Multiple
Integer multiple
Integer multiple of ×1 to 16
of ×1 to 8
of ×1 to 16
(mask option)
(external pin)
Peripheral
Integer multiple of ×10 to 64
(external pin)
(external pin)
Serial interface
2 channels
1 channel
(speech CODEC)
(audio CODEC)
16-bit bus
8-bit bus
Host interface
General-purpose
2 channels (time-division, audio)
8 bits
4 bits
16 bits (some are alternative with host)
port (I/O
programmable)
Others
None
−
−
Supply voltage
Package
100-pin TQFP
80-pin TQFP
80-pin FBGA
−
−
−
1 channel
2 channels
(16-bit resolution)
(16-bit resolution)
SD card I/F
−
SD card I/F
DSP core: 2.5 V
DSP core: 1.5 V
I/O pins: 3 V
I/O pins: 3.3 V
100-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin TQFP
161-pin FBGA
80-pin FBGA
144-pin LQFP
5
µPD77210, 77213
Timer
µPD77210, 77213
PIN CONFIGURATIONS
161-pin plastic fine pitch BGA (10 x 10)
•µPD77210F1-DA2
•µPD77213F1-xxx-DA2
(Bottom View)
(Top View)
14
13
12
11
10
9
8
7
6
5
4
3
2
1
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A
B
C
Index mark
6
Data Sheet U15203EJ3V0DS
D
E
F
G
H
J
K
L
M
N
P
µPD77210, 77213
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A1
NC
C14
EVDD
H2
HD7
M5
TSORQ
A2
NC
D1
P10/HD10/INT22
H3
HD6
M6
MA0
A3
P5/INT11
D2
P11/HD11/INT32
H4
GND
M7
MA4
A4
P2/INT20
D3
P12/HD12/INT03
H11
MD5
M8
MA5
A5
GND
D4
GND
H12
MD4
M9
MA10
A6
EVDD
D5
GND
H13
MD1
M10
MA12
A7
IVDD
D6
P1/INT10
H14
MD3
M11
MA15/ReservedNote
A8
IVDD
D7
GND
J1
EVDD
M12
MA19/SDCLKNote
A9
PLL0
D8
GND
J2
HCS
M13
MA18/SDCRNote
A10
STOPS
D9
GND
J3
HA1
M14
EVDD
A11
EVDD
D10
GND
J4
HWR
N1
A12
TRST
D11
TMS
J11
GND
N2
NC
A13
NC
D12
TICE
J12
MD0
N3
ASIEN/MCLK
A14
NC
D13
MD12
J13
MBSTB
N4
TSCK
B1
NC
D14
MD15
J14
IVDD
N5
TSIAK
B2
NC
E1
P14/HD14/INT23
K1
HA0
N6
MA1
B3
P7/INT31
E2
P15/HD15/INT33
K2
HRD
N7
MA2
B4
P6/INT21
E3
P13/HD13/INT13
K3
TIMOUT
N8
MA7
B5
P3/INT30
E4
GND
K4
ASO
N9
MA9
B6
CLKOUT
E5
NC
K11
GND
N10
MA11
B7
IVDD
E11
GND
K12
MWR
N11
MA16/ReservedNote
B8
PLL3
E12
MD14
K13
MWAIT
N12
MA17/ReservedNote
B9
PLL1
E13
MD9
K14
EVDD
N13
NC
B10
CSTOP
E14
MD11
L1
HWE
N14
NC
B11
I.C.
F1
EVDD
L2
HRE
P1
NC
B12
TCK
F2
HD1
L3
GND
P2
NC
B13
NC
F3
HD2
L4
GND
P3
ASI
B14
NC
F4
HD0
L5
TSIEN
P4
TSO
C1
EVDD
F11
MD10
L6
GND
P5
TSI
C2
P8/HD8/INT02
F12
MD13
L7
GND
P6
EVDD
C3
P9/HD9/INT12
F13
MD7
L8
MA8
P7
IVDD
C4
P4/INT01
F14
EVDD
L9
GND
P8
MA3
C5
P0/INT00
G1
HD3
L10
MA14/SDDAT0Note
P9
MA6
C6
CLKIN
G2
HD5
L11
GND
P10
EVDD
C7
PLL2
G3
HD4
L12
MHOLDRQ
P11
MA13/SDMONNote
NC
C8
HALTS
G4
GND
L13
MRD
P12
EVDD
C9
RESET
G11
GND
L14
MHOLDAK
P13
NC
C10
I.C.
G12
MD8
M1
EVDD
P14
NC
C11
TDI
G13
MD2
M2
ASCK/BCLK
C12
TDO
G14
MD6
M3
ASOEN/LRCLK
C13
GND
H1
IVDD
M4
TSOEN
Note MA13 to MA19 pins of the µPD77213 are alternate function pins.
Data Sheet U15203EJ3V0DS
7
µPD77210, 77213
144-pin plastic LQFP (fine pitch) (20 x 20) (Top View)
•µPD77210GJ-8EN
GND
TCK
TDI
TMS
TRST
I.C.
I.C.
EVDD
GND
RESET
STOPS
CSTOP
HALTS
PLL0
PLL1
PLL2
PLL3
IVDD
GND
CLKIN
IVDD
GND
IVDD
GND
CLKOUT
EVDD
GND
P0/INT00
P1/INT10
P2/INT20
P3/INT30
P4/INT01
P5/INT11
P6/INT21
P7/INT31
GND
EVDD
GND
MHOLDRQ
MA19/SDCLKNote
MA18/SDCRNote
MWR
MRD
MHOLDAK
MD1
MD0
MBSTB
MWAIT
GND
EVDD
MD3
MD2
GND
IVDD
MD5
MD4
MD15
MD14
MD13
MD12
MD11
MD10
GND
EVDD
MD9
MD8
MD7
MD6
GND
TICE
TDO
EVDD
•µPD77213GJ-xxx-8EN
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
1
108
2
107
3
106
4
105
5
104
6
103
7
102
8
101
9
100
10
99
11
98
12
97
13
96
14
95
15
94
16
93
17
92
18
91
19
90
20
89
21
88
22
87
23
86
24
85
25
84
26
83
27
82
28
81
29
80
30
79
31
78
32
77
33
76
34
75
35
74
36
73
Note MA13 to MA19 pins of the µPD77213 are alternate function pins.
8
Data Sheet U15203EJ3V0DS
HRE
HWR
HWE
TIMOUT
ASOEN/LRCLK
ASO
EVDD
GND
HA0
HA1
HRD
EVDD
GND
HCS
IVDD
GND
GND
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
P15/HD15/INT33
EVDD
P13/HD13/INT13
P14/HD14/INT23
P11/HD11/INT32
P12/HD12/INT03
P9/HD9/INT12
P10/HD10/INT22
GND
P8/HD8/INT02
EVDD
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
EVDD
Note
MA17/Reserved
Note
MA16/Reserved
Note
MA15/Reserved
Note
MA14/SDDAT0
Note
MA13/SDMON
MA12
MA11
MA10
GND
EVDD
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
GND
IVDD
GND
EVDD
MA1
MA0
TSIAK
TSORQ
TSI
TSIEN
TSCK
TSO
TSOEN
ASI
ASIEN/MCLK
ASCK/BCLK
GND
µPD77210, 77213
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1
GND
37
EVDD
73
GND
109
GND
2
TCK
38
GND
74
ASCK/BCLK
110
EVDD
3
TDI
39
P8/HD8/INT02
75
ASIEN/MCLK
111
MA18/SDCRNote
4
TMS
40
P9/HD9/INT12
76
ASI
112
MA19/SDCLKNote
5
TRST
41
P10/HD10/INT22
77
TSOEN
113
MHOLDRQ
6
I.C.
42
P11/HD11/INT32
78
TSO
114
MHOLDAK
7
I.C.
43
P12/HD12/INT03
79
TSCK
115
MRD
8
EVDD
44
P13/HD13/INT13
80
TSIEN
116
MWR
9
GND
45
P14/HD14/INT23
81
TSI
117
MWAIT
10
RESET
46
P15/HD15/INT33
82
TSORQ
118
MBSTB
11
STOPS
47
EVDD
83
TSIAK
119
MD0
12
CSTOP
48
GND
84
MA0
120
MD1
13
HALTS
49
HD0
85
MA1
121
EVDD
14
PLL0
50
HD1
86
EVDD
122
GND
15
PLL1
51
HD2
87
GND
123
IVDD
16
PLL2
52
HD3
88
IVDD
124
GND
17
PLL3
53
HD4
89
GND
125
MD2
18
IVDD
54
HD5
90
MA2
126
MD3
19
GND
55
HD6
91
MA3
127
MD4
20
CLKIN
56
HD7
92
MA4
128
MD5
21
IVDD
57
IVDD
93
MA5
129
MD6
22
GND
58
GND
94
MA6
130
MD7
23
IVDD
59
EVDD
95
MA7
131
MD8
24
GND
60
GND
96
MA8
132
MD9
25
CLKOUT
61
HCS
97
MA9
133
EVDD
26
EVDD
62
HA0
98
EVDD
134
GND
27
GND
63
HA1
99
GND
135
MD10
28
P0/INT00
64
HRD
100
MA10
136
MD11
29
P1/INT10
65
HRE
101
MA11
137
MD12
30
P2/INT20
66
HWR
102
MA12
138
MD13
139
MD14
31
P3/INT30
67
HWE
103
Note
MA13/SDMON
Note
32
P4/INT01
68
TIMOUT
104
MA14/SDDAT0
140
MD15
33
P5/INT11
69
ASOEN/LRCLK
105
MA15/ReservedNote
141
TDO
106
Note
142
TICE
Note
34
P6/INT21
70
ASO
MA16/Reserved
35
P7/INT31
71
EVDD
107
MA17/Reserved
143
GND
36
GND
72
GND
108
EVDD
144
EVDD
Note MA13 to MA19 pins of the µPD77213 are alternate function pins.
Data Sheet U15203EJ3V0DS
9
µPD77210, 77213
Pin Name
ASCK
:Audio Serial Clock Input/Output
ASI
:Audio Serial Data Input
MWAIT
:External Data Memory Access Wait
Input
ASIEN
:Audio Serial Input Enable
NC
:Non-Connection
ASO
:Audio Serial Data Output
P0 to P15
:Port
ASOEN
:Audio Serial Output Enable
PLL0-PLL3
:PLL Multiple Rate Set
BCLK
:Bit Clock Input/Output
Reserved
:Reserved
CLKIN
:Clock Input
RESET
:Reset
CLKOUT
:Clock Output
SDCLK
:SD Card Clock Output
CSTOP
:Clear Stop Mode
SDCR
:SD Card Command Output/Response
EVDD
:Power Supply for I/O Pins
GND
:Ground
SDDAT0
:SD Card Data Input/Output
HALTS
:Halt Status Signal Output
SDMON
:SD Card Access Monitor
HD0 to HD15
:Host Data Bus
STOPS
:Stop Status Signal Output
HCS
:Host Chip Select
TCK
:Test Clock Input
HA0, HA1
:Host Data Access
TDI
:Test Data Input
HRD
:Host Read
TDO
:Test Data Output
HRE
:Host Read Enable
TICE
:Test In-Circuit Emulator
HWE
:Host Write Enable
TIMOUT
:Timer Time Out Monitor Output
HWR
:Host Write
TMS
:Test Mode Select
I.C.
:Internal Connection
TRST
:Test Reset
IVDD
:Power Supply for DSP Core
TSCK
:Time Division Multiplex Serial Clock
INTmn
:Interrupt (m,n=0 to 3)
LRCLK
:Left Right Clock Input/Output
Input
Input
MA0 to MA19 :External Data Memory Address Bus
MBSTB
:External Data Memory Bus Strobe
MCLK
:Master Clock Input
TSI
:Time Division Multiplex Serial Data Input
TSIAK
:Time Division Multiplex Serial Input
TSIEN
:Time Division Multiplex Serial Input
TSO
:Time Division Multiplex Serial Data
TSOEN
:Time Division Multiplex Serial Output
Acknowledge
Enable
MD0 to MD15 :External Data Memory Bus
MHOLDAK
:External Data Memory Bus Hold
MHOLDRQ
:External Data Memory Bus Hold
Output
Acknowledge
Request
Enable
MRD
:External Data Memory Read Output
MWR
:External Data Memory Write Output
10
TSORQ
Data Sheet U15203EJ3V0DS
:Time Division Multiplex Serial Output
Request
µPD77210, 77213
CONTENTS
1. PIN FUNCTIONS....................................................................................................................................13
1.1 Description of Pin Functions ........................................................................................................................13
1.2 Connection of Unused Pins ..........................................................................................................................21
1.2.1 Connection of functional pins ..................................................................................................................21
1.2.2 Connection of non-functional pin .............................................................................................................22
2. FUNCTIONAL OUTLINE .......................................................................................................................23
2.1 Program Control Unit.....................................................................................................................................23
2.1.1 CPU control .............................................................................................................................................23
2.1.2 Interrupt control .......................................................................................................................................23
2.1.3 Loop control stack ...................................................................................................................................23
2.1.4 PC stack ..................................................................................................................................................23
2.1.5 Clock control............................................................................................................................................23
2.1.6 Instruction memory ..................................................................................................................................24
2.2 Operation Unit ................................................................................................................................................24
2.2.1 General-purpose registers (R0 to R7) .....................................................................................................24
2.2.2 Multiply accumulator (MAC) ....................................................................................................................24
2.2.3 Arithmetic logic unit (ALU) .......................................................................................................................24
2.2.4 Barrel shifter (BSFT)................................................................................................................................24
2.3 Data Memory Unit...........................................................................................................................................24
2.3.1 Data memory ...........................................................................................................................................24
2.3.2 Data addressing unit................................................................................................................................25
2.4 Peripheral Unit................................................................................................................................................25
2.4.1 Serial interface (SIO) ...............................................................................................................................25
2.4.2 Host interface (HIO).................................................................................................................................25
2.4.3 General-purpose I/O port (PIO) ...............................................................................................................26
2.4.4 External memory interface (MIO).............................................................................................................26
2.4.5 Timers (TIM1 and TIM2) ..........................................................................................................................26
2.4.6 Interrupt controller (INTC)........................................................................................................................26
2.4.7 DMA controller (PMT) ..............................................................................................................................26
2.4.8 SD card interface (SDCIF).......................................................................................................................26
2.4.9 Debug interface (IEIO).............................................................................................................................26
3. CLOCK GENERATOR...........................................................................................................................27
4. RESET FUNCTION ................................................................................................................................28
4.1 Hardware Reset ..............................................................................................................................................28
5. FUNCTION OF BOOT-UP ROM...........................................................................................................28
5.1 Boot at Reset ..................................................................................................................................................28
5.1.1 Memory boot............................................................................................................................................28
5.1.2 Host boot .................................................................................................................................................29
5.1.3 Serial boot ...............................................................................................................................................29
5.2 Reboot.............................................................................................................................................................29
5.2.1 Memory reboot ........................................................................................................................................29
Data Sheet U15203EJ3V0DS
11
µPD77210, 77213
5.2.2 Host reboot ............................................................................................................................................. 30
5.2.3 Serial reboot ........................................................................................................................................... 30
6. STANDBY MODE.................................................................................................................................. 31
6.1 Halt Mode ....................................................................................................................................................... 31
6.2 Stop Mode ...................................................................................................................................................... 31
7. MEMORY MAP...................................................................................................................................... 32
7.1 Instruction Memory ....................................................................................................................................... 32
7.1.1 Instruction memory map ......................................................................................................................... 32
7.1.2 Interrupt vector table............................................................................................................................... 33
7.2 Data Memory .................................................................................................................................................. 34
7.2.1 Data memory map .................................................................................................................................. 34
7.2.2 Internal peripherals ................................................................................................................................. 35
8. GENERAL-PURPOSE PORT AND INTERRUPT ............................................................................... 38
8.1 General-purpose Port Pins ........................................................................................................................... 38
8.2 Interrupt Pin ................................................................................................................................................... 38
9. INSTRUCTION ....................................................................................................................................... 39
9.1 Outline of Instruction .................................................................................................................................... 39
9.2 Instruction Set and Its Operation................................................................................................................. 40
10. ELECTRICAL SPECIFICATIONS....................................................................................................... 46
11. PACKAGE DRAWINGS...................................................................................................................... 69
12. RECOMMENDED SOLDERING CONDITIONS................................................................................. 71
12
Data Sheet U15203EJ3V0DS
µPD77210, 77213
1. PIN FUNCTIONS
Because the pin numbers differ depending on the package, see the column for the package to be used in the
tables below.
1.1 Description of Pin Functions
• Power supply pins
Pin Name
Pin No.
144-pin LQFP
IVDD
EVDD
I/O
Function
Alternate
Pin
161-pin FBGA
−
18,21,23,57,
A7,A8,B7,H1,
88,123
J14, P7
8,26,37,47,59,
A6,A11,C1,
71,86,98,108,
C14,F1,F14,
These pins supply power to the external interface
110,121,133,
J1,K14,M1,
pins.
144
M14,P6,P10,
Power supply for DSP core (+1.5 V)
−
These pins supply power to the DSP core.
−
Power supply for I/O (+3.3 V)
−
P12
GND
1,9,19,22,24,
A5,C13,D4,D5,
27,36,38,48,
D7,D8,D9,D10,
58,60,72,73,
E4,E11,G4,
87,89,99,109,
G11,H4,J11,
122,124,134,
K11,L3,L4,L6,
143
L7,L9,L11
−
Ground
−
These are ground pins.
Remark Please supply voltage to the IVDD and EVDD pins simultaneously.
Data Sheet U15203EJ3V0DS
13
µPD77210, 77213
• Clock and system control pins
Pin Name
Pin No.
144-pin LQFP
CLKIN
20
I/O
Function
Alternate
Pin
161-pin FBGA
C6
Input
−
Clock input
This pin inputs a clock to operate the µPD77210
Family.
CLKOUT
25
B6
Output
−
Internal system clock output
This pin outputs the internal system clock that is the
clock input from CLKIN and which is multiplied by the
PLL circuit.
PLL0 to
14 to 17
A9,B9,C7,B8
Input
PLL3
−
PLL multiple setting input
These pins set a clock multiple of the PLL circuit.
• PLL3: PLL2: PLL1: PLL0
0000: x10
0001: x12
0010: x14
0011: x16
0100: x18
0101: x20
0110: x22
0111: x24
1000: x26
1001: x28
1010: x30
1011: x32
1100: x40
1101: x48
1110: x56
1111: x64
HALTS
13
C8
Output
HALT mode status output
−
This pin is asserted active in halt mode and stop
mode.
STOPS
11
A10
Output
Stop mode status output
−
This pin is asserted active in stop mode.
CSTOP
12
B10
Input
Stop mode clear signal input
Stop mode is cleared when this pin is asserted
active.
14
Data Sheet U15203EJ3V0DS
−
µPD77210, 77213
• Reset and interrupt pins
Pin Name
RESET
Pin No.
144-pin LQFP
161-pin FBGA
10
C9
I/O
Function
Alternate
Pin
Input
Internal system reset signal input
−
This pin initializes the µPD77210 Family.
INT00
28
C5
Input
Maskable external interrupt input
P0
These pins input external interrupts.
P4
INT01
32
C4
Input
INT02
39
C2
Input
P8/HD8
INT03
43
D3
Input
P12/HD12
INT10
29
D6
Input
P1
INT11
33
A3
Input
P5
INT12
40
C3
Input
P9/HD9
INT13
44
E3
Input
P13/HD13
INT20
30
A4
Input
P2
INT21
34
B4
Input
P6
INT22
41
D1
Input
P10/HD10
INT23
45
E1
Input
P14/HD14
INT30
31
B5
Input
P3
INT31
35
B3
Input
P7
INT32
42
D2
Input
P11/HD11
INT33
46
E2
Input
P15/HD15
Data Sheet U15203EJ3V0DS
15
µPD77210, 77213
• External data memory interface
Pin Name
Pin No.
I/O
Function
Alternate
Pin
144-pin LQFP
161-pin FBGA
MA0 to
84, 85,
M6,N6,N7,P8,
Output
MA19Note
90 to 97,
M7,M8,P9,N8,
(3S)
100 to 107,
L8,N9,M9,N10,
111, 112
M10,P11,L10,
Address bus of external data memory
SDCLK,
These pins output an address when the external data
SDCR,
memory is accessed.
SDDAT0,
SDMON
M11,N11,N12,
M13,M12
MD0 to
119,120,
J12,H13,G13,
I/O
16-bit data bus
MD15
125 to 132,
H14,H12,H11,
(3S)
These pins input/output data when the external data
135 to 140
G14,F13,G12,
−
memory is accessed.
E13,F11,E14,
D13,F12,E12,
D14
MWR
116
K12
Output
(3S)
Write output
−
This pin outputs a write strobe signal for the external
data memory.
MRD
115
L13
Output
(3S)
Read output
−
This pin outputs a read strobe signal for the external
data memory.
MHOLDAK
114
L14
Output
Hold acknowledge signal
−
This pin goes low when the external device is
granted use of the external data memory bus of the
µPD77210 Family.
MHOLDRQ
113
L12
Input
Hold request signal
−
The external device inputs a low level to this pin
when it uses the external data memory bus of the
µPD77210 Family.
MWAIT
117
K13
Input
Wait signal input
−
This pin inserts wait cycles when the µPD77210
Family accesses the external data memory.
• 0: Inserts wait cycles.
• 1: Does not insert wait cycles.
MBSTB
118
J13
Output
Bus strobe signal
−
This pin goes low while the µPD77210 Family uses
the external data memory bus.
Note MA13 to MA19 pins of the µPD77213 are alternate function pins.
Remark Those pins marked “3S” in the above table enter the high-impedance state under the following
conditions:
MA0 to MA19, MRD, and MWR: When the bus is released (MHOLDAK = low level)
MD0 to MD15: When the external data memory is not accessed and when the bus is released
(MHOLDAK = low level)
16
Data Sheet U15203EJ3V0DS
µPD77210, 77213
• Timer
Pin Name
TIMOUT
Pin No.
144-pin LQFP
161-pin FBGA
68
K3
I/O
Function
Alternate
Pin
Output
−
Time out monitor
This pin is asserted active when the timer times out.
• Serial interface
Pin Name
ASCK/
Pin No.
144-pin LQFP
161-pin FBGA
74
M2
I/O
Function
Alternate
Pin
I/O
BCLK
Audio serial clock input/output
−
ASCK:Audio serial clock input
BCLK:Serial clock I/O
ASO
70
K4
Output
Audio serial data output
−
Audio serial data input
−
Audio serial output enable/left right clock input output
−
(3S)
ASI
76
P3
Input
ASOEN/
69
M3
I/O
LRCLK
ASOEN:Audio serial output enable input
LRCLK:Left right clock I/O
ASIEN/
75
N3
Input
MCLK
Audio serial input enable/master clock input output
−
ASIEN:Audio serial input enable input
MCLK:Master clock input (in master mode)
TSCK
79
N4
Input
TSO
78
P4
Output
Clock input for time division serial
−
Time-division serial data output
−
Time-division serial data input
−
(3S)
TSI
81
P5
Input
TSORQ
82
M5
Output
Time-division serial output request
−
TSOEN
77
M4
Input
Time-division serial output enable
−
TSIEN
80
L5
Input
Time-division serial input enable
−
TSIAK
83
N5
Output
Time-division serial input acknowledge
−
Remark Those pins marked “3S” in the above table enter the high-impedance state when data transmission is
completed and when the hardware reset (RESET) signal is input.
Data Sheet U15203EJ3V0DS
17
µPD77210, 77213
• Host interface
Pin Name
HA1
Pin No.
144-pin LQFP
161-pin FBGA
63
J3
I/O
Function
Alternate
Pin
Input
Host address 1
−
This pin specifies a register that is accessed by the
host interface pins (HD7 to HD0, or HD15 to HD0).
• 1: The host interface status register (HST) is
accessed.
• 0: The host transmit data register (HDT (out)) is
accessed for read (HRD = 0) and the host receive
data register (HDT (in)) is accessed for write (HWR
= 0).
HA0
62
K1
Input
Host address 0
−
This pin specifies a register that is accessed by HD7
to HD0 in 8-bit mode. This pin is invalid in 16-bit
mode.
• 1: Bits 15 to 8 of HST, HDT (in), and HDT (out) are
accessed.
• 0: Bits 7 to 0 of HST, HDT (in), and HDT (out)
are accessed.
HCS
61
J2
Input
Chip select input
−
HRD
64
K2
Input
Host read input
−
HWR
66
J4
Input
Host write input
−
HRE
65
L2
Output
Host read enable output
−
HWE
67
L1
Output
Host write enable output
−
HD0 to
49 to 56
F4,F2,F3,G1,
I/O
8-bit host data bus
−
G3,G2,H3,H2
(3S)
These pins constitute a host data bus in 8-bit host
HD7
mode. Access to 16-bit data for input/output is
controlled by the HA0 pin, and the data is accessed
two times such that it is divided into two blocks of 8bit data.
In 16-bit mode, the lower 8 bits of the data are
input/output.
HD8 to
39 to 46
HD15
C2,C3,D1,D2,
I/O
Host data bus
D3,E3,E1,E2
(3S)
These pins constitute a host data bus in 16-bit host
INT02,
mode. They input/output 16-bit data with HD0 to
INT12,
HD7.
INT22,
P8 to P15/
INT32,
INT03,
INT13,
INT23,
INT33
Remark Those pins marked “3S” in the above table enter the high-impedance state while the host interface is not
being accessed.
18
Data Sheet U15203EJ3V0DS
µPD77210, 77213
• I/O port
Pin Name
Pin No.
I/O
Function
Alternate
Pin
144-pin LQFP
161-pin FBGA
P0
28
C5
I/O
P1
29
D6
I/O
INT10
P2
30
A4
I/O
INT20
P3
31
B5
I/O
INT30
P4
32
C4
I/O
INT01
P5
33
A3
I/O
INT11
P6
34
B4
I/O
INT21
P7
35
B3
I/O
INT31
P8
39
C2
I/O
INT02/HD8
P9
40
C3
I/O
INT12/HD9
P10
41
D1
I/O
INT22/HD10
P11
42
D2
I/O
INT32/HD11
P12
43
D3
I/O
INT03/HD12
P13
44
E3
I/O
INT13/HD13
P14
45
E1
I/O
INT23/HD14
P15
46
E2
I/O
INT33/HD15
Pin No.
I/O
General-purpose I/O port
INT00
• Debugging interface
Pin Name
Function
Alternate
Pin
144-pin LQFP
161-pin FBGA
TDO
141
C12
Output
TICE
142
D12
Output
TCK
2
B12
Input
−
TDI
3
C11
Input
−
TMS
4
D11
Input
−
TRST
5
A12
Input
−
(3S)
For debugging
−
This interface pins are used when a debugger is
used.
−
Remark Those pins marked “3S” in the above table enter the high-impedance state while the debugging interface
is not being accessed.
Data Sheet U15203EJ3V0DS
19
µPD77210, 77213
•SD card interface (µPD77213 only)
Pin Name
Pin No.
144-pin LQFP
SDCLK
112
I/O
Function
Pin
161-pin FBGA
M12
Alternate
Output
SD card clock output
MA19
• Leave this pin open.
SDCR
111
M13
I/O
SD cord command/response
(3S)
Input: Response
MA18
Output: Command
• Leave pull-up.
SDDAT0
104
L10
I/O
SD card data input/output
(3S)
Input: Read data
MA14
Output: Write data
• Leave pull-up.
SDMON
103
P11
Output
SD card interface access monitor
MA13
This pin outputs a high level when the SD card
interface is being accessed.
1: SD card interface being accessed
0: SD card interface not being accessed
Reserved
105 to 107
M11, N11, N12
−
Reserved for future function expansion.
MA15 to
This pin becomes high impedance when the SD card
MA17
interface is being used.
Remark Those pins marked “3S” in the above table enter the high-impedance state when the SD card interface is
not being accessed.
• Others
Pin Name
I.C.
Pin No.
144-pin LQFP
161-pin FBGA
6, 7
B11, C10
I/O
Function
Alternate
Pin
−
Internally connected.
−
Leave these pins open.
NC
−
A1,A2,A13,
A14,B1,B2,
−
No connection.
−
Leave these pins open.
B13,B14,E5,
N1,N2,N13,
N14,P1,P2,
P13,P14
Caution If any signal is input to these pins or if these pins are read, the correct operation of the µPD77210
Family is not guaranteed.
20
Data Sheet U15203EJ3V0DS
µPD77210, 77213
1.2 Connection of Unused Pins
1.2.1 Connection of functional pins
Connect the unused pins as shown in the table below.
Pin Name
STOPS, HALTS
CSTOP
I/O
Output
Input
CLKOUT
Output
P0 to P15
I/O
Note 1
HD0 to HD7
Recommended Connection
Leave open.
Connect to GND via a pull-down resistor.
Leave open.
Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor.
I/O
Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor.
HA0, HA1
Input
Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor.
HCS, HRD, HWR
Input
Connect to EVDD via a pull-up resistor.
HRE, HWE
Output
Leave open.
TIMOUT
Output
Leave open.
ASCK, TSCK
Input
ASI, TSI
Input
ASIEN, TSIEN
Input
ASOEN, TSOEN,
Input
Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor.
Connect to GND via a pull-down resistor.
LRCLK
ASO, TSO
Output
TSORQ
Output
TSIAK
Output
MA0 to MA19
Output
Note 2
MD0 to MD15
I/O
MRD, MWR
Output
MHOLDRQ
Input
MBSTB, MHOLDAK
MWAIT
Output
Input
TCK
Input
TDO, TICE
Output
Leave open.
Leave open.
Connect to EVDD via a pull-up resistor or to GND via a pull-down resistor.
Leave open.
Connect to EVDD via a pull-up resistor.
Leave open.
Connect to EVDD via a pull-up resistor.
Connect to GND via a pull-down resistor.
Leave open.
TMS, TDI
Input
Leave open (this pin is internally pulled up).
TRST
Input
Leave open (this pin is internally pulled down).
Notes 1. These pins may left opened if the HCS, HRD,and HWR are fixed to the high level.
However, connect these pins as recommended in the HALT and STOP modes when the power
consumption must be lowered.
2. These pins may leave opened if the external data memory is not accessed in the program.
However, connect these pins as recommended in the HALT and STOP modes when the power
consumption must be lowered.
Caution Unused alternate-function pins should be handled in accordance with the processing specified
for the pin function of the initial setting.
Data Sheet U15203EJ3V0DS
21
µPD77210, 77213
1.2.2 Connection of non-functional pin
Pin name
22
I/O
Recommended Connection
I.C.
−
Leave open.
NC
−
Leave open.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
2. FUNCTIONAL OUTLINE
2.1 Program Control Unit
This unit controls the execution of µPD77210 Family by executing instructions and controlling branching, loop,
interrupts, clock, and standby mode.
2.1.1 CPU control
A three-stage pipeline architecture is employed so that all instructions, except branch instructions and some
others, can be executed with one system clock.
2.1.2 Interrupt control
The interrupt control circuit services the interrupt requests input to the interrupt controller by an external pin
(INTmn) or internal peripherals (such as the serial interface, host interface, timer, and DMA controller). The interrupt
of each interrupt source can be individually enabled or disabled. In addition, multiple interrupts are also supported.
2.1.3 Loop control stack
A loop function without any hardware overhead is realized. A 4-level loop stack is provided to support multiple
loops.
2.1.4 PC stack
A 15-level PC stack that stacks the program counter supports multiple interrupts/subroutine calls.
2.1.5 Clock control
A PLL and a divider are internally provided as a clock generator so that an externally input clock is multiplied or
divided and supplied as the operating clock to the µPD77210 Family. The multiple of the PLL can be set by using
external pins (PLL0 to PLL3) within a range of ×10 to 64. The division ratio can be set by using a register in a range
of ÷1 to 16.
The clock control register (CLKC) controls the power (ON/OFF) to the PLL, selects a clock source, controls the
output divider, and controls the output of the CLKOUT pin.
Two types of standby modes are available so that the power consumption can be reduced when the µPD77210
Family is standing by.
•HALT mode: Current consumption falls to several mA upon execution of the HALT instruction.
This mode is released by an interrupt or hardware reset.
Note
•STOP mode: Current consumption falls to hundreds of µA
upon execution of the STOP instruction.
This mode is released by hardware reset or inputting a signal to CSTOP pin.
Note When the PLL is stopped
Data Sheet U15203EJ3V0DS
23
µPD77210, 77213
2.1.6 Instruction memory
Of the instruction RAM, 64 words are allocated as interrupt vectors.
The µPD77210 is provided with an instruction RAM of 31.5 Kwords. The µPD77213 is provided with an instruction
RAM of 15.5 Kwords and instruction ROM of 64 Kwords.
A boot-up ROM that boots up the instruction RAM is also provided, and the instruction RAM can be initialized or
rewritten by means of a memory boot (booting from an internal or external data space), host boot (booting via a host
interface), or serial boot (booting via a serial interface).
2.2 Operation Unit
This unit performs multiplication, addition, logic, and shift operations, and consists of a 40-bit multiply
accumulator, a 40-bit data ALU, a 40-bit barrel shifter, and eight 40-bit general-purpose registers.
2.2.1 General-purpose registers (R0 to R7)
These eight 40-bit registers input/output operands and load/store data to/from data memory.
Each register consists of three parts: R0L to R7L (bits 15 to 0), R0H to R7H (bits 31 to 16), and R0E to R7E (bits
39 to 32). Depending on the type of the operation, RnL, RnH, and RnE are used either as one register or in
combination.
2.2.2 Multiply accumulator (MAC)
The multiply accumulator performs multiplication of two 16-bit data items and addition or subtraction between the
result of the multiplication and one 40-bit data item, and then outputs 40-bit data.
A shifter (MSFT: MAC shifter) is provided at the preceding stage of the MAC, so that the 40-bit data that is to be
added to or subtracted from the multiplication result can be arithmetically shifted 1 bit or 16 bits to the right before
addition or subtraction.
2.2.3 Arithmetic logic unit (ALU)
The ALU accepts one or two 40-bit data items as input, performs an arithmetic or logical operation, and then
outputs 40-bit data.
2.2.4 Barrel shifter (BSFT)
The BFST accepts 40-bit data items as input, shifts the data to the left or right by an arbitrary number of bits, and
then outputs 40-bit data. The data can be shifted to the right arithmetically, in which case the sign of the data is
extended, or logically in which case 0 is inserted starting from the MSB.
2.3 Data Memory Unit
The data memory unit consists of two planes of data memory spaces and two pairs of data addressing units.
2.3.1 Data memory
Two data memory planes (X data memory and Y data memory) are provided. The data memory space includes a
64-word peripheral area.
The µPD77210 has a data RAM consisting of 30 Kwords × 2 planes. The µPD77213 has a data RAM consisting
of 18 Kwords × 2 planes, and has a data ROM consisting of 32 Kwords × 2 planes.
In addition, They also have an external data memory interface that is used to connect an external 1 Mword data
memory to the device.
24
Data Sheet U15203EJ3V0DS
µPD77210, 77213
2.3.2 Data addressing unit
An independent data addressing unit is provided for each of the X and Y data memory spaces.
Each data addressing unit has four data pointers (DPn), four index registers (DNn), one module register (DMX or
DMY), and an address ALU.
2.4 Peripheral Unit
The peripheral unit has serial interfaces, a host interface, general-purpose I/O ports, timers, an external memory
interface, and SD card interface (µPD77213 only). All these internal peripherals are mapped to the X and Y data
memory spaces and are accessed as memory-mapped I/Os by the program.
2.4.1 Serial interface (SIO)
Two serial interface channels, an audio serial interface (ASIO) and a time-division serial interface (TDMSIO), are
provided.
The audio serial interface can be used in either of two modes: audio mode and standard mode. The standard
mode is compatible with the existing µPD77111 Family. The audio mode is compatible with the µPD77115.
The features of the audio mode are as follows:
• Mode: Master mode and slave mode
Master mode: Supports master clock input (MCLK), bit clock output (BCLK), LR clock output (LRCLK), 256 fs,
384 fs, and 512 fs.
Slave mode: Bit clock input (BCLK) and LR clock input (LRCLK)
• Frame format: 32- or 64-bit audio formats (LRCLK format)
• Handshake: Handshaking with external devices by a dedicated frame signal (LRCLK) and with the internal
circuitry by polling, wait, or interrupt
The standard mode has the following features:
•Serial clock:
Supplied from an external source to each channel. The clock is shared for input and output by
each channel.
•Frame length:
8 or 16 bits, with MSB or LSB first selected for each channel.
•Handshake:
Handshaking with the external device by using a dedicated status signal and with the internal
circuitry by polling, wait, or interrupt.
The time-division serial interface divides the serial input/output signal into 1 to 32 time slots and allows several
devices to share the serial bus. Because the T1 and E1 frame signals are considered. The time slot can be extended
from 1 to 128.
2.4.2 Host interface (HIO)
This is a parallel port that inputs/outputs data from/to an external host CPU and DMA controller. It can be used in
either 8-bit parallel mode or 16-bit parallel mode. In the µPD77210 Family, 16-bit registers are mapped to memory
for input data, output data, and status. Handshaking with an external device is performed by using a dedicated
status signal, and the internal circuitry handshaking is done by means of polling, wait, or interrupts.
The 8-bit parallel mode is compatible with the existing members of the µPD77111 Family.
In 16-bit parallel mode, some port pins are used as host interface pins.
Data Sheet U15203EJ3V0DS
25
µPD77210, 77213
2.4.3 General-purpose I/O port (PIO)
This is a 16-bit I/O port that can be set to either input or output mode in 1-bit units.
The external pins alternate between interrupt pins and host interface pins. By setting the mode of 8 bits of the
port to host interface pin mode, the host interface can be set in the 16-bit parallel mode.
2.4.4 External memory interface (MIO)
This interface accesses an external 1 Mwords data memory area in either of two modes: direct access and DMA
access modes. In DMA access mode, access is made via a memory-mapped register.
In direct access mode, the data paging register (DPR) is set to 0x3F and a page area is accessed as an access
window. An address of the external memory consists of 20 bits with the 8-bit value of the index register added as bits
12 to 19.
In DMA access mode, the address is automatically updated when a memory-mapped register is accessed. The
address is updated in an increment addressing mode in which the address is simply incremented, or in twodimensional addressing mode in which an offset is added to each line length.
The number of wait cycles to be inserted when the external memory is accessed can be specified by a register
(MWAIT), within a range of 1 to 15. In addition, wait cycles can also be inserted by using the MWAIT pin.
2.4.5 Timers (TIM1 and TIM2)
The µPD77210 Family has two timer channels.
These timers can be used as interval timers, event counters, watchdog timers, and free-run timers.
The clock input to the timers is selected from the system clock, serial clock (ASCK or TSCK), external interrupt
(INT00, INT10, INT20, or INT30), or output of each timer.
The count value is 16 bits and the clock input by the prescaler can be divided by 1, 2, 4, 8, 16, 32, 64, or 128.
2.4.6 Interrupt controller (INTC)
The interrupt controller has functions for selecting and masking interrupt signals. It controls the interrupt signal to
be input to the DSP core.
2.4.7 DMA controller (PMT)
The DMA controller realizes data transfer between the peripherals and memory (peripheral-memory transfer) in
the background. It mitigates the software overhead generated by interrupt processing of the data input/output via
SIO, HIO, MIO, and SDCIF (µPD77213 only).
Data of 14 Kwords at addresses 0x0000 to 0x37FF of the internal data RAM can be transferred by means of
DMA.
2.4.8 SD card interface (SDCIF)
The µPD77213 supports SD Card interface. This interface is for access of SD card. It supports the DMA transfer
for input data to internal data RAM. The SD card is accessed by using a dedicated routine of system ROM.
2.4.9 Debug interface (IEIO)
The µPD77210 Family has the following functions that conform to the JTAG (Joint Test Action Group) interface as
a debug interface.
A device conforming to JTAG has an access port dedicated to testing and can be tested independently of the
internal logic.
The µPD77210 Family has registers and a control circuit for in-circuit emulation, in addition to the instruction
registers, bypass registers, and boundary scan registers that are required by the JTAG Recommendation.
26
Data Sheet U15203EJ3V0DS
µPD77210, 77213
3. CLOCK GENERATOR
The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and
supplies the clock to the µPD77210 Family. The configuration of the clock generator is as illustrated below.
Standby mode
Halt
CLKIN
Stop
Internal
system
clock
PLL controller
x m (m:10 to 64)
Output divider
÷ n (n:1 to 16)
CLKOUT
CLKC register
PLL0 to PLL3 Peripheral bus
The PLL is stopped immediately after reset. The clock input from the CLKIN pin is directly supplied to the
µPD77210 Family internal circuitry and bootup commences. The PLL is started up in the boot routine and booting is
carried out via the PLL output clock (except in the case of non-boot or external memory boot). In the case of nonboot or external memory boot, when booting has finished, after the PLL is started up by setting the CLKC register
from the user program, the clock source must be switched to the PLL, in which case the PLL must be locked. Note
that 300 µs are required between when the PLL is started up and when it is locked.
The PLL multiplication rate is specified by the external pins PLL0 to PLL3. The PLL also has two lock range
modes: 80 to 120 MHz and 120 to 160 MHz. The mode to be used is specified by the P3 pin during booting. The
CLKC register is used to control turning on/off the PLL, select the clock source (external clock/multiplied
clock/divided or non-divided output), control resetting the output divider, set the division ratio, and enable/disable
CLKOUT pin output.
When the output divider is selected, the high-level width of the clock output by the CLKOUT pin is equivalent to 1
cycle of the normal operation (which means that the clock does not have a duty factor of 50%).
In halt mode, output of the divider circuit is automatically selected as the clock source. When the divider circuit is
selected, the clock is not changed even if halt mode is set.
In stop mode, the system clock supplied to the internal circuitry is masked. Because the PLL is not stopped
automatically, it can recover from stop mode without PLL lock time. It is necessary to set the CLKC register by the
program to stop the PLL.
Data Sheet U15203EJ3V0DS
27
µPD77210, 77213
4. RESET FUNCTION
The device is initialized when a low level of the specified width is input to the RESET pin.
4.1 Hardware Reset
The internal circuitry of the µPD77210 Family is initialized when the RESET pin is asserted active (low level) for a
specific period. When the RESET pin is then deasserted inactive (high level), booting of the instruction RAM is
performed in accordance with the status of the port pins (P0, P1, P2, and P3), and then processing is executed
starting from the instruction at address 0x200 (reset entry) of the instruction memory.
5. FUNCTION OF BOOT-UP ROM
The instruction RAM is booted up by using the internal boot-up ROM when power is applied or when the contents
of the instruction memory are to be rewritten by the program.
5.1 Boot at Reset
Immediately after release of a hardware reset, the boot program first reads general-purpose I/O port pins P0 to
P3, and a boot mode (memory boot/host boot/serial boot) is determined by the bit patterns of these port pins. Once
the booting processing has been completed, processing is executed starting from the instruction at address 0x200
(reset entry) of the instruction memory.
P2
P1
P0
Boot Mode
0
0
0
Non-bootNote
0
0
1
X memory initial boot
0
1
0
Y memory initial boot
0
1
1
XY memory initial boot
1
0
0
External memory initial boot
1
0
1
Host boot
1
1
0
Serial boot
Note This setting is used when the µPD77210 Family must be reset upon restoration from standby mode after a
reset boot has been executed once.
P3
PLL lock range
0
120 to 160 MHz
1
80 to 120 MHz
5.1.1 Memory boot
The instruction code stored in data memory is transferred to the instruction RAM. Depending on the data memory
from which the instruction code is to be transferred, X memory boot (booting from the X data memory), Y memory
boot (booting from the Y data memory), XY memory boot (booting from the X and Y data memories), or external
memory boot (booting from the external data memory space) may be performed.
28
Data Sheet U15203EJ3V0DS
µPD77210, 77213
5.1.2 Host boot
The boot parameter and instruction code are obtained via the host interface and transferred to the instruction
RAM.
5.1.3 Serial boot
The boot parameter and instruction code are obtained via the serial interface and transferred to the instruction
RAM.
5.2 Reboot
The contents of the instruction RAM can be rewritten by calling the following reboot entries by the program.
Reboot Mode
Entry
Address
0x1
Parameter
Number
of
Transfer
Transfer
Transfer
Transfer
Instruction
Source Start
Destination
Destination
Destination
Steps
Address
Start
Page
Address
(DPR)
DP2
R5L
Memory
X memory
reboot
R7L
DP3
R6L
Y memory
0x2
R7L
DP7
R6L
DP6
R5L
XY memories
0x3
R7L
DP3, DP7
R6L
DP2
R5L
External memory
0x4
R7L
DP3
R6L
DP2
R5L
Host reboot
0x5
R7L
−
R6L
DP2
R5L
Serial reboot
0x6
R7L
−
R6L
DP2
R5L
5.2.1 Memory reboot
The instruction code stored into data memory is transferred to the instruction RAM. Depending on the data
memory from which the instruction code is to be transferred, X memory reboot (rebooting from the X data memory), Y
memory reboot (rebooting from the Y data memory), XY memory reboot (rebooting from the X and Y data memories),
or external memory reboot (rebooting from the external data memory space) may be performed.
Perform memory rebooting by setting the following parameters and calling the entry address by the corresponding
rebooting method.
• R7L: Number of instruction steps to be rebooted
• DP3: First address of X memory storing instruction code (to reboot from X, XY or external memories)
• DP7: First address of X memory storing instruction code (to reboot from Y or XY memories)
• R6L: Transfer source data page register (DPR) (Specify 0x00 in the case of the internal data RAM area.)
Index register (for external memory rebooting)
• DP2: Transfer destination address of the instruction to be rebooted (to reboot from X, XY or external memories)
• DP6: Transfer destination address of the instruction to be rebooted (to reboot from Y memories)
• R5L: Transfer destination page register (DPR) (Specify 0x80 in the case of the internal instruction RAM area.)
Data Sheet U15203EJ3V0DS
29
µPD77210, 77213
5.2.2 Host reboot
The instruction code is obtained via the host interface and transferred to the instruction RAM.
The entry address is 0x5. Host rebooting is executed by setting the following parameters and then calling this
address.
• R7L: Number of instruction steps to be rebooted
• R6L: Host status register (HST)
• DP2: Transfer destination address of instruction to be rebooted (offset 0x8000 in the case of internal instruction
RAM area)
• R5L: Transfer destination data page register (DPR) (Specify 0x80 of the internal instruction RAM area.)
5.2.3 Serial reboot
The instruction code is obtained via the serial interface (TDMSIO) and then transferred to the instruction RAM.
The entry address is 0x6. Host rebooting is executed by setting the following parameters and then calling this
address.
• R7L: Number of instruction steps to be rebooted
• R6L: Serial status register (SST) (Specify 0x0EC0.)
• DP2: Transfer destination address of instruction to be rebooted (offset 0x8000 in the case of internal instruction
RAM area)
• R5L: Transfer destination data page register (DPR) (Specify 0x80 of the internal instruction RAM area.)
30
Data Sheet U15203EJ3V0DS
µPD77210, 77213
6. STANDBY MODE
The µPD77210 Family can be set to either of two standby modes. Each mode can be set by executing the
corresponding instruction. The power consumption can be reduced in these modes.
6.1 Halt Mode
The halt mode can be set by executing the HALT instruction. In this mode, all the functions except the clock
circuit and PLL are stopped and, therefore, the current consumption can be reduced.
The device can be released from this mode by an interrupt or hardware reset. To release the device from halt
mode by issuing an interrupt, the contents of the internal registers and memories are retained. It takes 10 to 20
system clocks to release the µPD77210 Family from halt mode (if it is released by an interrupt).
When releasing the device from halt mode by using hardware reset, the external clock must be selected as the
clock source in advance that the contents of memories are retain.
In halt mode, the clock circuit of the µPD77210 Family supplies the clock divided by the ratio specified by the
CLKC register as the internal system clock. The same applies to the clock output by the CLKOUT pin.
6.2 Stop Mode
Stop mode is set when a STOP instruction is executed. In this mode, supply of the clock to the internal system is
stopped.
If the PLL is stopped before stop mode is set, all the functions, including the clock circuit and PLL, are stopped.
As a result, only a leakage current flows and, therefore, the current consumption can be minimized. In this case, the
external clock must be selected as the clock source in advance.
The device is released from stop mode by a hardware reset or the CSTOP pin.
To release the device from stop mode by using the CSTOP pin, the contents of the internal registers and
memories are retained. When releasing the device from stop mode by using hardware reset, the external clock must
be selected as the clock source in advance that the contents of memories are retain.
Data Sheet U15203EJ3V0DS
31
µPD77210, 77213
7. MEMORY MAP
The µPD77210 Family employs a Harvard architecture that separates the instruction memory space from the data
memory space.
7.1 Instruction Memory
7.1.1 Instruction memory map
The instruction memory space consists of 64 Kwords × 32 bits. The area at addresses 0x8000 to 0xFFFF is a
paging area that supports a memory space of 64 Kwords or more by specifying a page by using the instruction
paging register (IPR).
The instruction ROM of the µPD77213 exists in the paging area and is accessed as IPR=0x0 or 0x1.
The paging area of the µPD77210 is reserved for future expansion.
µ PD77210
0xFFFF
µ PD77213
Paging area
0xFFFF
Paging area
(32 Kwords)
0x8000
0x7FFF
Paging area
(32 Kwords)
Instruction ROM
(32 Kwords)
Note
(IPR=0x0)
0x8000
0x7FFF
(IPR=0x1)
System area
Instruction RAM
(31.5 Kwords)
0x4000
0x3FFF
Instruction RAM
(15.5 Kwords)
0x0200
0x01FF
0x0000
Boot-up ROM
(512 words)
0x0200
0x01FF
0x0000
Boot-up ROM
(512 words)
Note The higher 8 words of the instruction ROM (0xFFF8 to 0xFFFF) constitute system area.
Caution Programs and data cannot be allocated to the system area, and neither can it be accessed. If
these addresses are accessed, correct operation of
the
device
is
not
guaranteed.
A paging area in which no IPR page exists cannot be accessed. If this kind of paging area is
accessed, correct operation of the device is not guaranteed.
32
Data Sheet U15203EJ3V0DS
µPD77210, 77213
7.1.2 Interrupt vector table
Addresses 0x200 to 0x23F of the instruction memory are assigned to entry points (vectors) of interrupts. Four
instruction addresses are assigned to each interrupt source.
Four interrupt sources are assigned to each interrupt vector. There are 12 vectors. By identifying the source in
the vector, the µPD77210 can use 38 interrupt sources and µPD77213 can use 42 interrupt sources.
Each of these interrupt sources can be masked by using the interrupt control register (ICR0 to ICR11).
Vector
Interrupt Source
0
1
2
3
0x200
Reset
Reserved
Reserved
Reserved
0x204
Reserved
Reserved
Reserved
Reserved
0x208
Reserved
Reserved
Reserved
Reserved
0x20C
Reserved
Reserved
Reserved
Reserved
0x210
INT00
INT01
INT02
INT03
0x214
INT10
INT11
INT12
INT13
0x218
INT20
INT21
INT22
INT23
0x21C
INT30
INT31
INT32
INT33
0x220
TSI input
TSIEN
PMT ch0
SDCR input Note
(TSI input)
0x224
TSO output
TSOEN
PMT ch1
SDCR output Note
(TSO output)
0x228
0x22C
ASI input
ASIEN
ASO output
ASOEN
PMT ch2
SDDAT inputNote
(ASI input)
(busy release)
PMT ch3
SDDAT outputNote
(ASO output)
0x230
HI input
HWR
PMT ch4
Reserved
(HI input)
0x234
HO output
HRD
PMT ch5
Reserved
(HO output)
0x238
TIMER ch0
TIMER ch1
PMT ch6
Reserved
(MI input)
0x23C
TIMER ch1
TIMER ch0
PMT ch7
Reserved
(MO output)
Note
These interrupt sources are for the µPD77213 only. When using the µPD77210, they are reserved.
Cautions
1. Reset is not an interrupt but is used as an entry of a vector.
2. It is recommended that the vector of an interrupt source that is not used branch to an
abnormality processing routine.
Data Sheet U15203EJ3V0DS
33
µPD77210, 77213
7.2 Data Memory
7.2.1 Data memory map
The data memory space consists of two planes: the X and Y memory spaces, each of which consists of 64
Kwords × 16 bits. The area of 0x8000 to 0xFFFF is a paging area that supports a memory space of 64 Kwords or
more by specifying a page by using the data paging register (DPR). The DPR can be set in the same manner
regardless of whether the X or Y memory space is accessed.
Page 0x3F of DPR is a window to the external data memory. The Data ROM of the µPD77213 exists in the
paging area and is accessed as DPR=0x0.
Page 0x80 of the DPR is shared by 0x0000 to 0x7FFF of the internal instruction RAM. The lower 16 bits of the
32-bit instruction RAM constitute the X data memory, while the higher 16 bits are the Y data memory.
Because some pins of the µPD77213 are shared with the SD card interface, the area that can be accessed when
the SD card interface is being used is restricted. The address pins MA13 to MA19 are shared with the SD card
interface. When the SD card interface is being used, therefore, only the 13-bit address area of MA0 to MA12 (8
Kwords) can be accessed.
µ PD77210
µ PD77213
Paging area
0xFFFF
Paging area
0xFFFF
Note 1
Paging area
(32 Kwords)
(DPR=0x3F)
0x8000
0x7FFF
Note 2
External data
memory window
(32 Kwords)
Paging area
(32 Kwords)
External data
memory window
(32 Kwords)
Data ROM
(32 Kwords)
(DPR=0x0)
0x8000
0x7FFF
(DPR=0x3F)
System
Data RAM
(16 Kwords)
0x4000
0x3FFF
0x3800
0x37FF
0x5000
0x4FFF
0x4000
0x3FFF
Peripheral
(2 Kwords)
0x3800
0x37FF
Data RAM
(14 Kwords)
Data RAM
(4 Kwords)
Peripheral
(2 Kwords)
Data RAM
(14 Kwords)
0x0000
0x0000
Notes 1. If the paging register is set to a value other than 0x3F (external data memory window) or 0x80 (internal
instruction RAM area), programs and data cannot be stored to the addresses of the paging area, nor
can these addresses be accessed.
2. The higher 8 words of the data ROM (0xFFF8 to 0xFFFF) constitute system area.
Caution Programs and data cannot be allocated to the system area, and neither can it be accessed. If
these addresses are accessed, correct operation of
the
device
is
not
guaranteed.
A paging area in which no DPR page exists cannot be accessed. If this kind of paging area is
accessed, correct operation of the device is not guaranteed.
34
Data Sheet U15203EJ3V0DS
µPD77210, 77213
7.2.2 Internal peripherals
The internal peripherals are mapped to the internal data memory space.
Cautions
1. The register names shown in the above table are not reserved words in either assembler or
C. To use these names in assembler or C, therefore, the user must define them.
2. The same register is accessed regardless of whether the X memory space or Y memory
space is accessed, provided that the address is the same.
3. Different registers cannot be accessed simultaneously from the X and Y memory spaces.
Memory-Mapped Peripherals (1/3)
X/Y Memory Address
Register Name
Function
Peripheral
Name
0x3800
TSDT/SDT1
TDM serial data register/Serial data register 1
0x3801
SST1
Serial status register 1
0x3802
TSST
TDM serial status register
0x3803
TFMT
TDM frame format register
0x3804
TTXL
TDM transfer slot register (low)
0x3805
TTXH
TDM transfer slot register (high)
0x3806
TRXL
TDM receive slot register (low)
0x3807
TRXH
TDM receive slot register (high)
0x3808 to 0x380F
Reserved area
Caution Do not access this area.
0x3810
ASDT/SDT2
Audio serial data register/Serial data register 2
0x3811
SST2
Serial status register 2
0x3812
ASST
Audio serial status register
0x3813 to 0x381F
Reserved area
Caution Do not access this area.
0x3820
HDT
Host interface data register
0x3821
HST
Host interface status register
0x3822 to 0x383F
Reserved area
Caution Do not access this area.
0x3840
MDT
Memory data register
0x3841
MSHW
Memory I/F setup/hold width setting register
0x3842
MCST
Memory I/F control/status register
0x3843
MWAIT
Memory I/F wait register
0x3844
MIDX
Direct access index register
0x3845
MADRLI
Memory I/F input start address register (low)
0x3846
MADRHI
Memory I/F input start address register (high)
0x3847
MOFSI
Memory I/F input line offset register
0x3848
MLENI
Memory I/F input line length register
0x3849
MADRLO
Memory I/F output start address register (low)
0x384A
MADRHO
Memory I/F output start address register (high)
0x384B
MOFSO
Memory I/F output line offset register
0x384C
MLENO
Memory I/F output line length register
0x384D to 0x384F
Reserved area
Caution Do not access this area.
0x3850
PMSA0
PMT start address register 0
0x3851
PMS0
PMT size register 0
0x3852
PMC0
PMT control register 0
0x3853
PMP0
PMT address pointer 0
Data Sheet U15203EJ3V0DS
TSIO(SIO1)
−
ASIO(SIO2)
−
HIO
−
MIO
−
PMT ch0
35
µPD77210, 77213
Memory-Mapped Peripherals (2/3)
X/Y Memory Address
Register Name
Function
Peripheral
Name
PMSA1
PMT start address register 1
0x3855
PMS1
PMT size register 1
0x3856
PMC1
PMT control register 1
0x3857
PMP1
PMT address pointer 1
0x3858
PMSA2
PMT start address register 2
0x3859
PMS2
PMT size register 2
0x385A
PMC2
PMT control register 2
0x385B
PMP2
PMT address pointer 2
0x385C
PMSA3
PMT start address register 3
0x385D
PMS3
PMT size register 3
0x385E
PMC3
PMT control register 3
0x385F
PMP3
PMT address pointer 3
0x3860
PMSA4
PMT start address register 4
0x3861
PMS4
PMT size register 4
0x3862
PMC4
PMT control register 4
0x3863
PMP4
PMT address pointer 4
0x3864
PMSA5
PMT start address register 5
0x3865
PMS5
PMT size register 5
0x3866
PMC5
PMT control register 5
0x3867
PMP5
PMT address pointer 5
0x3868
PMSA6
PMT start address register 6
0x3869
PMS6
PMT size register 6
0x386A
PMC6
PMT control register 6
0x386B
PMP6
PMT address pointer 6
0x386C
PMSA7
PMT start address register 7
0x386D
PMS7
PMT size register 7
0x386E
PMC7
PMT control register 7
0x386F
PMP7
PMT address pointer 7
0x3870
PDT0
Port data register 0
0x3871
PCD0
Port command register 0
0x3872
PDT1
Port data register 1
0x3873
PCD1
Port command register 1
0x3874
PDT2
Port data register 2
0x3875
PCD2
Port command register 2
0x3876
PDT3
Port data register 3
0x3877
PCD3
Port command register 3
0x3878, 0x3879
Reserved area
Caution Do not access this area.
0x387A, 0x387B
POWC
Power control register
0x3854
PMT ch1
PMT ch2
PMT ch3
PMT ch4
PMT ch5
PMT ch6
PMT ch7
PIO
−
Peripheral
STOP mode
36
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Memory-Mapped Peripherals (3/3)
X/Y Memory Address
Register Name
Function
Peripheral
Name
0x387C to 0x387F
Reserved area
Caution Do not access this area.
0x3880
ICR0
Interrupt control register 0
0x3881
ICR1
Interrupt control register 1
0x3882
ICR2
Interrupt control register 2
0x3883
ICR3
Interrupt control register 3
0x3884
ICR4
Interrupt control register 4
0x3885
ICR5
Interrupt control register 5
0x3886
ICR6
Interrupt control register 6
0x3887
ICR7
Interrupt control register 7
0x3888
ICR8
Interrupt control register 8
0x3889
ICR9
Interrupt control register 9
0x388A
ICR10
Interrupt control register 10
0x388B
ICR11
Interrupt control register 11
0x388C to 0x388F
Reserved area
Caution Do not access this area.
0x3890
TIR0
Timer initial register 0
0x3891
TCR0
Timer count register 0
0x3892
TCSR0
Timer control/status register 0
0x3893
Reserved area
Caution Do not access this area.
0x3894
TIR1
Timer initial register 1
0x3895
TCR1
Timer count register 1
0x3896
TCSR1
Timer control/status register 1
0x3897 to 0x389F
Reserved area
Caution Do not access this area.
0x38A0
CEFR
Collect enable flag register
0x38A1
CPR0
Collect page register 0
0x38A2
CAR0
Collect address register 0
0x38A3
CLIR0
Collect instruction data register (high) 0
0x38A4
CUIR0
Collect instruction data register (low) 0
0x38A5
CPR1
Collect page register 1
0x38A6
CAR1
Collect address register 1
0x38A7
CLIR1
Collect instruction data register (high) 1
0x38A8
CUIR1
Collection instruction data register (low) 1
0x38A9 to 0x38AF
Reserved area
Caution Do not access this area.
0x38B0
CLKC
Clock control register
0x38B1 to 0x38BF
Reserved area
Caution Do not access this area.
0x38C0
IPR
Instruction paging register
0x38C1
DPR
Data paging register
0x38C2 to 0x38CF
Reserved area
Note
Caution Do not access this area.
0x38D0
ADCR
Additional I/F control register
0x38D1-0x3FFF
Reserved area
Caution Do not access this area.
−
INTC
−
TIM0
−
TIM1
−
IMC
−
CLKC
−
Page register
−
Additional IO
−
Note µPD77213 only. Do not access 0x38D0 of the µPD77210.
Data Sheet U15203EJ3V0DS
37
µPD77210, 77213
8. GENERAL-PURPOSE PORT AND INTERRUPT
8.1 General-purpose Port Pins
The general-purpose port pins alternate with the interrupt or host interface pins.
The configuration of the general-purpose port is illustrated below.
OE
Port pin
O
Port I/O
I
OE
Note
O Host I/O
I
Interrupt
controller
Note P0 to P7 do not alternate with the host interfave pins.
8.2 Interrupt Pin
The general-purpose port pin functions as an interrupt pin and the signal input to the port is always input to the
interrupt controller. The interrupt controller recognizes the interrupt by detecting a falling edge.
The output of the general-purpose port or host interface pin can be also used as an interrupt input.
Pins HRD, HWR, ASOEN, ASIEN, TSOEN, and TSIEN are connected to the interrupt controller and can be used
as interrupt pins.
38
Data Sheet U15203EJ3V0DS
µPD77210, 77213
9. INSTRUCTION
9.1 Outline of Instruction
One instruction consists of 32 bits. All the instructions, with some exceptions such as branch instructions, are
executed with one system clock. The instruction cycle of the µPD77210 is up to 6.25 ns. The instruction cycle of the
µPD77213 is up to 8.33 ns. The following nine types of instructions are available.
(1) Trinomial instructions
These instructions specify an operation by the MAC. As the operands, three general-purpose registers can
be specified.
(2) Binomial instructions
These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose
registers can be specified. Some of these instructions allow one immediate value to be specified instead of a
general-purpose register.
(3) Monomial instructions
These instructions specify an operation by the ALU. As the operand, a general-purpose register can be
specified.
(4) Load/store instructions
These instructions specify 16-bit data transfer between memory and a general-purpose register. As the
operand, any general-purpose register can be specified.
(5) Register-to-register transfer instructions
These instructions specify transfer between a general-purpose register and another register.
(6) Immediate value setting instructions
These instructions set an immediate value in the general-purpose registers and each register of the address
operation unit.
(7) Branch instructions
These instructions specify branching of the program.
(8) Hardware loop instructions
These instructions specify the repetitive execution of an instruction.
(9) Control instructions
These instructions specify program control.
Data Sheet U15203EJ3V0DS
39
µPD77210, 77213
9.2 Instruction Set and Its Operation
Describe an operation in the operation field of each instruction in accordance with the description method of the
operation representation format of the instruction. If two or more elements are available, select one of them.
(a) Correspondence between representation format and selectable register
The representation format and selectable register are as follows:
Representation
Selectable Register
Format
ro, ro’, ro”
R0 to R7
rl, rl’
R0L to R7L
rh, rh’
R0H to R7H
re
R0E to R7E
reh
R0EH to R7EH
dp
DP0 to DP7
dn
DN0 to DN7
dm
DMX, DMY
dpx
DP0 to DP3
dpy
DP4 to DP7
dpx_mod
DPn, DPn++, DPn−−, DPn##, DPn%%, !DPn## (n = 0 to 3)
dpy_mod
DPn, DPn++, DPn−−, DPn##, DPn%%, !DPn## (n = 4 to 7)
dp_imm
DPn## imm (n = 0 to 7)
*xxx
Contents of memory at address ×××
(Example)
If the contents of the DP0 register are 1000, *DP0 indicates
the contents of memory address 1000.
40
Data Sheet U15203EJ3V0DS
µPD77210, 77213
(b) Modifying data pointer
The data pointer is modified only after memory access. The result of the modification becomes valid starting
from the instruction that is executed immediately after. The data pointer cannot be modified without the
memory access.
Example
Operation
DPn
Nothing is executed (value of DPn is not changed).
DPn++
DPn ← DPn + 1
DPn−−
DPn ← DPn − 1
DPn##
DPn ← DPn + DNn
(Value of DN0 to DN7 corresponding to DP0 to DP7 is added.)
Example: DP0 ← DP0 + DN0
DPn%%
(n = 0 to 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DPH
(n = 4 to 7) DPn = ((DPL + DNn) mod (DMY + 1)) + DPH
!DPn##
Reverses bits of DPn and then accesses DPn.
After memory access, DPn ← DPn + DNn
DPn## imm
DPn ← DPn + imm
(c) Instructions that can be described simultaneously
Those instructions that can be described simultaneously are indicated by √.
(d) Status of overflow flag (OV)
The status of the overflow flag is indicated by the following symbols:
↔
: No change
: Set to 1 if an overflow occurs.
Caution If an overflow does not occur after an operation, the overflow flag is not reset and its status
remains the same as before the operation.
Data Sheet U15203EJ3V0DS
41
µPD77210, 77213
Instruction Set
Instructions That Can Be
Flag
Operation
ro ← ro + rh*rh’
√
Multiply sub
ro = ro − rh*rh’
ro ← ro − rh*rh’
√
Signed/unsigned
ro = ro + rh*rl
ro ← ro + rh*rl
√
multiply add
(rl is in positive integer format.)
Unsigned/unsigned
ro = ro + rl*rl’
ro ← ro + rl*rl’
√
multiply add
(rl and rl’ are in positive integer
Loop
Branch
Transfer
Control
↔↔↔
ro = ro + rh*rh’
↔
Multiply add
Immediate Value
Load/Store
Binomial
Monomial
Trinomial
Described Simultaneously
OV
Mnemonic
1-bit shift multiply add
ro = (ro >> 1) + rh*rh’
ro ← ro/2 + rh*rh’
√
16-bit shift multiply
ro = (ro >> 16) + rh*rh’
ro ← ro/2 + rh*rh’
√
Multiply
ro = rh*rh’
ro ← rh*rh’
√
Add
ro” = ro + ro’
ro” ← ro + ro’
√
Immediate add
ro’ = ro + imm
↔↔
↔
format.)
√
↔↔
Trinomial operation
Instruction Group
Instruction Name
add
ro’ ← ro + imm
(where imm ≠ 1)
Sub
ro” = ro − ro’
ro” ← ro − ro’
Immediate sub
ro’ = ro − imm
ro’ ← ro − imm
(where imm ≠ 1)
Arithmetic right shift
ro’ = ro SRA rl
ro’ ← ro >> rl
Immediate arithmetic
ro’ = ro SRA imm
ro’ ← ro >> imm
Logical right shift
ro’ = ro SRL rl
ro’ ← ro >> rl
Immediate logical right
ro’ = ro SRL imm
ro’ ← ro >> imm
Logical left shift
ro’ = ro SLL rl
ro’ ← ro << rl
Immediate logical left
ro’ = ro SLL imm
ro’ ← ro << imm
And
ro” = ro & ro’
ro” ← ro & ro’
Immediate and
ro’ = ro & imm
ro’ ← ro & imm
Or
ro” = ro | ro’
ro” ← ro | ro’
Immediate or
ro’ = ro | imm
ro’ ← ro | imm
Exclusive or
ro” = ro^ro’
ro” ← ro^ro’
Immediate exclusive
ro‘ = ro^imm
ro’ ← ro^imm
ro” = LT (ro, ro’)
if (ro < ro’)
√
Binomial operation
right shift
√
shift
√
shift
√
√
√
or
Less than
{ro” ← 0x0000000001}
else {ro” ← 0x0000000000}
42
Data Sheet U15203EJ3V0DS
√
Operation
Instructions That Can Be
Flag
Mnemonic
Clear
CLR (ro)
ro ← 0x0000000000
√
√
Increment
ro’ = ro + 1
ro’ ← ro + 1
√
√
Decrement
ro’ = ro − 1
ro’ ← ro − 1
√
√
Absolute value
ro’ = ABS (ro)
if (ro < 0)
√
√
↔↔↔
Loop
Control
Branch
Transfer
Immediate Value
Load/Store
Binomial
Monomial
Described Simultaneously
OV
Instruction Name
Trinomial
Instruction Group
µPD77210, 77213
{ro’ ← −ro}
1’s complement
ro’ ← ~ro
√
√
2’s complement
ro’ = −ro
ro’ ← −ro
√
√
Clip
ro’ = CLIP (ro)
if (ro > 0x007FFFFFFF)
√
√
√
√
↔
else {ro’ ← ro}
ro’ = ~ro
{ro’ ← 0x007FFFFFFF}
{ro’ ← 0xFF80000000}
else {ro’ ← ro}
Round
ro’ = ROUND (ro)
if (ro > 0x007FFF0000)
{ro’ ← 0x007FFF0000}
elseif (ro < 0xFF80000000)
{ro’ ← 0xFF80000000}
else {ro’ ← (ro + 0x8000)
& 0xFFFFFF0000}
Exponent
ro’ = EXP (ro)
ro’ ← log2 (1/ro)
√
√
Substitution
ro’ = ro
ro’ ← ro
√
√
Accumulated add
ro’ + = ro
ro’ ← ro’ + ro
√
√
Accumulated sub
ro’ − = ro
ro’ ← ro’ − ro
√
√
Division
ro’ / = ro
if (sign (ro’) = = sign (ro))
√
√
↔↔↔
Monomial operation
elseif (ro < 0xFF80000000)
{ro’ ← (ro’ − ro) << 1}
else
{ro’ ← (ro’ + ro) << 1}
if (sign (ro’) = = 0)
{ro’ ← ro’ + 1}
Data Sheet U15203EJ3V0DS
43
Instructions That Can Be
Notes 1, 2, 3
Partial load/store
ro = *dpx_mod ro’ = *dpy_mod
ro ← *dpx, ro’ ← *dpy
ro = *dpx_mod *dpy_mod = rh
ro ← *dpx, *dpy ← rh
*dpx_mod = rh ro = *dpy_mod
*dpx ← rh, ro ← *dpy
*dpx_mod = rh *dpy_mod = rh’
*dpx ← rh, *dpy ← rh’
dest = *dpx_mod
dest ← *dpx,
dest’ = *dpy_mod
dest’ ← *dpy
dest ← *dpx,
*dpy_mod = source
*dpy ← source
*dpx_mod = source
*dpx ← source,
dest = *dpy_mod
dest ← *dpy
*dpx_mod = source
*dpx ← source,
*dpy_mod = source’
*dpy ← source’
dest = *addr
dest ← *addr
load/store
*addr = source
*addr ← source
Immediate index
Load/store
dest = *dpx_mod
Direct addressing
Note 4
dest = *dp_imm
dest ← *dp
load/store
*dp_imm = source
*dp ← source
Register-to-register
Note 5
dest = rl
dest ← rl
transfer
rl = source
rl ← source
Immediate value setting
rl = imm
rl ← mm
Immediate value setting
Note 6
Loop
Control
Branch
√
Transfer
√
Immediate Value
√
Load/Store
Binomial
Notes 1, 2
Monomial
Described Simultaneously
Parallel load/store
Registerto-register
transfer
Operation
Flag
Mnemonic
OV
Instruction Name
Trinomial
Instruction Group
µPD77210, 77213
√
(where imm = 0 to 0xFFFF)
dp ← imm
dp = imm
(where imm = 0 to 0xFFFF)
dn ← imm
dn = imm
(where imm = 0 to 0xFFFF)
dm ← imm
dm = imm
(where imm = 1 to 0xFFFF)
Notes 1. Of the two mnemonics, either or both can be described.
2. After transfer, modification specified by mod is performed.
3. dest, dest’ = {ro, reh, re, rh, rl}, source, source’ = {re, rh, rl}
4. dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr = {0: X-0xFFFF: X (X memory), or 0: Y-0xFFFF: Y
(Y memory)}
5. dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}
6. Select any of the registers (except the general-purpose registers) as dest and source.
44
Data Sheet U15203EJ3V0DS
Operation
Instructions That Can Be
Flag
Mnemonic
Loop
Control
Branch
Transfer
Immediate Value
Load/Store
Binomial
Monomial
Described Simultaneously
Jump
JMP imm
PC ← imm
√
Register-to-register
JMP dp
PC ← dp
√
CALL imm
SP ← SP + 1
√
OV
Instruction Name
Trinomial
Instruction Group
µPD77210, 77213
jump
Subroutine call
STK ← PC + 1
Branch
PC ← imm
Register-to-register
SP ← SP + 1
CALL dp
√
STK ← PC + 1
subroutine call
PC ← dp
Return
RET
Interrupt return
RETI
PC ← STK
√
SP ← SP − 1
PC ← STK
√
STK ← SP − 1
Restores interrupt enable flag.
Repeat
REP count
Start
RC ← count
RF ← 0
During repeat PC ← PC
RC ← RC − 1
End
PC ← PC + 1
RF ← 1
Hardware loop
Loop
LOOP count
Start
LC ← count
LF ← 0
(Instruction of 2 lines or more)
During loop
PC ←
PC + 1 (while PC < LEA)
if (PC = LEA) PC ← LSA
LC ← LC − 1
End
PC ← PC + 1
LF ← 1
Loop pop
LPOP
LC ← LSR3
LE ← LSR2
LS ← LSR1
Control
LSP ← LSP − 1
No operation
NOP
PC ← PC + 1
Halt
HALT
CPU stops.
Stop
STOP
CPU stops, PLL, and OSC
can be stopped by a user
Condition
IF (ro cond)
Condition judgment
Forget interrupt
FINT
Discards interrupt request.
Data Sheet U15203EJ3V0DS
√
√
√
45
µPD77210, 77213
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°°C)
Parameter
Symbol
Condition
Rating
Unit
IVDD
For DSP core
− 0.5 to + 2.0
V
EVDD
For I/O pins
− 0.5 to + 4.6
V
Input voltage
VI
VI < EVDD + 0.5 V
− 0.5 to + 4.6
V
Output voltage
VO
− 0.5 to + 4.6
V
Storage temperature
Tstg
− 65 to + 150
°C
Operating ambient
temperature
TA
− 20 to + 70
°C
Supply voltage
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Operating voltage
Symbol
IVDD
EVDD
Input voltage
Note
Condition
MIN.
TYP.
MAX.
Unit
For DSP core (operating
speed 120 MHz Max.)
1.425
1.50
1.65
V
For DSP core (operating
Note
speed 160 MHz Max.)
1.55
1.60
1.65
V
For I/O pins
2.7
3.3
3.6
V
EVDD
V
MAX.
Unit
VI
0
µPD77210 only
Capacitance (TA = +25°°C, IVDD = 0 V, EVDD = 0 V)
Parameter
Symbol
Input capacitance
CI
Output capacitance
CO
I/O capacitance
CIO
46
Condition
f = 1 MHz,
Pins other than those
tested: 0 V
Data Sheet U15203EJ3V0DS
MIN.
TYP.
10
pF
10
pF
10
pF
µPD77210, 77213
DC Characteristics (Unless otherwise specified, TA = − 20 to + 70°°C, with IVDD and EVDD within recommended
operating condition range)
Parameter
High level input voltage
Symbol
Condition
MIN.
TYP.
MAX.
Unit
VIHN
Pins other than below
0.7 EVDD
EVDD
V
VIHC
CLKIN
0.7 EVDD
EVDD
V
VIHS
RESET, P0 to P15, TSCK,
TSIEN,TSOEN, ASCK, ASIEN,
ASOEN
0.8 EVDD
EVDD
V
VILN
Pins other than below
0
0.2 EVDD
V
VILC
CLKIN
0
0.2 EVDD
V
VILS
RESET, P0 to P15, TSCK,
TSIEN,TSOEN, ASCK, ASIEN,
ASOEN
0
0.2 EVDD
V
High level output voltage
VOH
IOH = −100 µA
Low level output voltage
VOL
IOL = 2.0 mA
High level input leakage
current
ILHN
VI = EVDD
Low level input leakage
current
ILLN
VI = 0 V
High impedance leakage
current
ILZ
Pull-up pin current
Pull-down pin current
Low level input voltage
Internal supply current
[fclkin = 10 MHz,
IVDD = 1.5 V,
VIHN = VIHC = VIHS = EVDD,
VIL = 0 V, no load,
0.8 EVDD
V
0.2 EVDD
V
0
10
µA
−10
0
µA
0 V ≤ VI ≤ EVDD
0
−10
µA
IPUI
TDI, TMS, 0 V ≤ VI ≤ EVDD
20
70
200
µA
IPDI
TRST, 0 V ≤ VI ≤ EVDD
−20
−70
−200
µA
Note 1
Note 2
IDD
During operating,
fclk = 100 MHz,
PLL multiple rate x10
35
IDDH
In halt mode,
fclk = 100 MHz,
PLL multiple rate x 10,
division rate 1/1
20Note 3
mA
µA
TA = 25°C]
IDDS
In stop modeNote 4,
µPD77210
240
fclk = 0 Hz,
PLL stop
µPD77213
120
70
mA
Notes 1. The value is when MAC with Dual Load instruction 50% + nop instruction 50% are executed. It is
roughly estimated at 0.35 mA/MHz.
2. The value is when a special program that brings about frequent switching inside the device is
executed.
It is roughly estimated at 0.7 mA/MHz.
3. The value is when the division rate is 1/1. It is roughly estimated at 0.2 mA/MHz + IDDS using the
divided clock.
4. The value in stop mode is the value when PLL is stopped.
Data Sheet U15203EJ3V0DS
47
µPD77210, 77213
Common Test Criteria of Switching Characteristics
48
RESET, P0 to P15,
TSCK, TSIEN, TSOEN,
ASCK, ASIEN, ASOEN
0.8 EVDD
0.5 EVDD
0.2 EVDD
Test Points
0.8 EVDD
0.5 EVDD
0.2 EVDD
Input
(other than above)
0.7 EVDD
0.5 EVDD
0.2 EVDD
Test Points
0.7 EVDD
0.5 EVDD
0.2 EVDD
Output
0.5 EVDD
Test Points
0.5 EVDD
Data Sheet U15203EJ3V0DS
µPD77210, 77213
AC Characteristics (TA = − 20 to + 70°°C, with IVDD and EVDD within recommended operating condition range)
Clock
Timing requirements
Parameter
Note 1
Symbol
Condition
MIN.
TYP.
MAX.
Unit
CLKIN cycle time
tcCX
62.5
ns
CLKIN high level width
twCXH
12.5
ns
CLKIN low level width
twCXL
12.5
ns
CLKIN rise/fall time
trfCX
Internal clock cycle time
tcC
requirements
PLL lock-up time
tLPLL
PLL lock frequency Note 1
tcPLL
5
ns
Over 120 MHz(µPD77210
only)
6.25
ns
Under 120 MHz
8.33
ns
300
µs
When boot:P3 = 0 Note 2
120
160
MHz
When boot:P3 = 1
80
120
MHz
Notes 1. The CLKIN cycle time must accord with the PLL lock frequency. It is therefore necessary to satisfy both
the CLKIN cycle time condition of 62.5 ns (MIN.) and the PLL lock frequency condition of a multiplied
frequency in the range of 80 to 160 MHz.
2. In the µPD77213, it can be set only when an external memory boot is being used.
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Internal clock cycle
tcC
tcCX ÷ m × n
ns
CLKOUT cycle time
tcCO
tcC
ns
CLKOUT width
twCO
tcC ÷ 2
ns
High level width
tcC ÷ n
ns
Low level width
tcC −
tcC ÷ n
ns
Note
n=1
n≥2
CLKOUT rise/fall time
trfCO
5
ns
CLKOUT delay time
tdCO
6.25
ns
Note m: Multiple ratio, n: Division ratio (PLL, divider)
Data Sheet U15203EJ3V0DS
49
µPD77210, 77213
Clock I/O timing
tcCX
twCXH
trfCX
twCXL
trfCX
CLKIN
tcC, tcPLL
Internal clock
tdCO
tcCO
twCO
twCO
CLKOUT
50
Data Sheet U15203EJ3V0DS
trfCO
trfCO
µPD77210, 77213
Reset, Interrupt, System Control, Timer
Timing requirements
Parameter
Symbol
RESET low level width
Condition
MIN.
tw(RL)
ns
ns
ns
12 tcC
CSTOP recovery time
trec(CSTOP)
12 tcC Note 2
tw (INTL)
Note 3
ns
Note 3
ns
6 tcC
trec (INT)
6 tcC
Unit
Note 2
tw(CSTOPH)
INTmn recovery time
MAX.
6 tcCX
CSTOP high level width
INTmn low level width
TYP.
Note 1
Notes 1. When reset timing, it is specified by input clock.
2. When STOP or HALT mode, it is specified by divided clock.
3. Interrupt can input by TSIEN, TSOEN, ASIEN, and ASOEN pins other than interrupt pins. The interrupt
pins function alternately as pins P0 to P15.
Remark
INTmn m, n = 0 to 3
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
STOPS output delay time
tdSTP
0
6.25
ns
HALTS output delay time
tdHLT
0
6.25
ns
TIMOUT output delay time
tdTIM
0
6.25
ns
TIMOUT output width
twTIM
4 tcC
ns
Reset timing
tw(RL)
RESET
WAKEUP timing
tw(CSTOPH)
trec(CSTOP)
CSTOP
Interrupt timing
trec(INT)
tw(INTL)
INTmn
Data Sheet U15203EJ3V0DS
51
µPD77210, 77213
Standby mode status output timing
Internal clock
Fetch Next Instruction
of STOP or HALT
Execution STOP or
HALT Instruction
Internal status
CSTOP
tdSTP
STOPS
tdHLT
tdHLT
HALTS
Remarks 1. Internal clock cycle is changed or stopped to be fixed to low level when STOP or HALT mode.
2. STOPS pin is become low level asynchronously by CSTOP pin rising edge.
Timer time out status output timing
Internal clock
Internal status
Detect Time out
twTIM
tdTIM
TIMOUT
52
Data Sheet U15203EJ3V0DS
tdTIM
µPD77210, 77213
External Data Memory Access
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
MD setup time
tsuMDI
17.5
ns
MD hold time
thMDI
0
ns
MHOLDRQ setup time
tsuHRQ
11.25
ns
MHOLDRQ hold time
thHRQ
0
ns
MWAIT setup time
tsuWAIT
11.25
ns
MWAIT hold time
thWAIT
0
ns
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
MA output delay time
tdMA
0
6.25
ns
MRD output delay time
tdMRD
0
6.25
ns
MWR output delay time
tdMWR
0
6.25
ns
MD output delay time
tdMDO
0
6.25
ns
MBSTB output delay time
tdBS
0
6.25
ns
MHOLDAK output delay time
tdHAK
0
6.25
ns
Data Sheet U15203EJ3V0DS
53
µPD77210, 77213
External data memory access timing (Read)
Internal colck
tdMA
tdMA
MA0 to MA19
tsuMDI
thMDI
MD0 to MD15
tdMRD
tdMRD
MRD
tsuWAIT
thWAIT
tsuWAIT
thWAIT
MWAIT
tdBS
tdBS
MBSTB
Remark In the µPD77213, it is possible to shift fall timing of MRD pin by cycle unit, by setting of MSHW register.
External data memory access timing (Write)
Internal clock
tdMA
tdMA
MA0 to MA19
tdMDO
tdMDO
tdMDO
Hi-Z
Hi-Z
MD0 to MD15
tdMWR
tdMWR
MWR
tsuWAIT
thWAIT
tsuWAIT
thWAIT
MWAIT
tdBS
tdBS
MBSTB
Remark It is possible to shift rise/fall timing of MWR pin by cycle unit, by setting of MSHW register.
54
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Bus arbitration timing
Internal colck
(Bus busy)
Bus busy
Bus idle
Bus release
Bus idle
(Bus busy)
thHRQ
tsuHRQ
tsuHRQ
thHRQ
MHOLDRQ
tdHAK
tdHAK
MHOLDAK
tdMA,tdMDO,tdMRD,tdMWR
MA0 to MA19,
MD0 to MD15,
MRD, MWR
tdMA,tdMDO,tdMRD,tdMWR
Hi-Z
Data Sheet U15203EJ3V0DS
55
µPD77210, 77213
General-purpose I/O Port
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Port input setup time
tsuPI
11.25
ns
Port input hold time
thPI
6.25
ns
Switching characteristics
Parameter
Port output delay time
Symbol
Condition
MIN.
tdPO
0
General-purpose I/O port timing
Internal clock
tdPO
P0 to P15
(output)
tsuPI
thPI
P0 to P15
(input)
56
Data Sheet U15203EJ3V0DS
TYP.
MAX.
Unit
6.25
ns
µPD77210, 77213
Host Interface
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
HRD low level width, recovery
time
twHRD
3 tcC
ns
HWR low level width,
recovery time
twHWR
3 tcC
ns
HD setup time
tsuHDI
6.25
ns
HD hold time
thHDI
6.25
ns
HA, HCS setup time
tsuHA
3
ns
HA,HCS hold time
thHA
0
ns
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
HRE output delay time
tdRE
0
11.25
ns
HWE output delay time
tdWE
0
11.25
ns
HD output delay time
tdHD
0
11.25
ns
Data Sheet U15203EJ3V0DS
57
µPD77210, 77213
Host read interface timing
Interanal clock
HCS, HA0, HA1
thHA
tsuHA
twHRD
twHRD
HRD
tdHD
tdHD
Hi-Z
HD0 to HD15
tdRE
Hi-Z
tdRE
HRE
Host write interface timing
Internal clock
HCS, HA0, HA1
thHA
tsuHA
twHWR
twHWR
HWR
thHDI
tsuHDI
HD0 to HD15
tdWE
tdWE
HWE
58
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Serial Interface (Standard Serial mode/ TDM serial mode)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
ASCK cycle time
tcSC
50 and
2 tcC
ns
ASCK high /low level width
twSC
25
ns
ASCK rise/fall time
trfSC
Serial input setup time
tsuSER
12.5
ns
Serial input hold time
thSER
12.5
ns
20
ns
Switching characteristics
Parameter
Serial output delay time
Symbol
Condition
tdSER
MIN.
0
Data Sheet U15203EJ3V0DS
TYP.
MAX.
Unit
17.5
ns
59
µPD77210, 77213
Serial output timing 1
tcSC
twSC
ASCK,
TSCK
trfSC
trfSC
twSC
tdSER
tdSER
TSORQ
tsuSER
tsuSER
thSER
thSER
ASOEN,
TSOEN
tdSER
tdSER
Hi-Z
ASO,
TSO
thSER
1st
Last
Note When TDM mode, TSO output value is delay for a bit according to TDM setting value.
Serial output timing 2 (during successive output)
tcSC
twSC
ASCK,
TSCK
trfSC
trfSC
twSC
tdSER
tdSER
TSORQ
tsuSER
thSER
ASOEN,
TSOEN
tdSER
ASO,
TSO
Last
thSER
1st
Last
Hi-Z
Note When TDM mode, TSO output value is delay for a bit or dummy cycle (high impedance) is inserted,
according to TDM setting value.
60
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Serial input timing 1
tcSC
twSC
ASCK,
TSCK
trfSC
twSC
tdSER
trfSC
tdSER
TSIAK
tsuSER
tsuSER
thSER
thSER
ASIEN,
TSIEN
tsuSER
thSER
ASI,
TSI
1st
3rd
2nd
Note When TDM mode, TSI input value is delay for a bit according to TDM setting value.
Serial input timing 2 (during successive input)
tcSC
twSC
trfSC
twSC
ASCK,
TSCK
tdSER
trfSC
tdSER
TSIAK
tsuSER
thSER
ASIEN,
TSIEN
tsuSER
ASI,
TSI
Last–1
Last
thSER
1st
2nd
3rd
Note When TDM mode, TSI input value is delay for a bit or skip cycle is input, according to TDM setting value.
Data Sheet U15203EJ3V0DS
61
µPD77210, 77213
Serial Interface (Audio Serial mode)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
MCLK cycle time
tcMC
Master mode
50 and
2 tcC
ns
MCLK high/low level width
twMC
Master mode
25
ns
MCLK rise/fall time
trfMC
Master mode
BCLK cycle time
tcBC
Slave mode
50 and
8 tcC
ns
BCLK high/low level width
twBC
Slave mode
25
ns
BCLK rise/fall time
trfBC
Slave mode
Serial input setup time
tsuASER
Slave mode
12.5
ns
Master mode
25.0
ns
Slave mode
12.5
ns
Master mode
25.0
ns
Serial input hold time
thASER
20
20
ns
ns
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
BCLK cycle time
tcBC
Master mode
50 and
8 tcC
ns
BCLK high/low level width
twBC
Master mode
25
ns
BCLK rise/fall time
trfBC
Master mode
Serial output delay time
tdASER
Master mode
Slave mode
62
Data Sheet U15203EJ3V0DS
5
ns
−12.5
+25.0
ns
0
17.5
ns
µPD77210, 77213
Audio serial clock timing
tcMC
twMC
trfMC
twMC
trfMC
MCLK
Audio serial master mode timing
tcBC
twBC
trfBC
trfBC
twBC
BCLK
(output)
tdASER
tdASER
LRCLK
(output)
tdASER
ASO
tsuASER
thASER
ASI
Audio serial slave mode timing
tcBC
twBC
trfBC
trfBC
twBC
BCLK
(input)
tsuASER
tsuASER
LRCLK
(input)
tdASER
ASO
tsuASER
thASER
ASI
Data Sheet U15203EJ3V0DS
63
µPD77210, 77213
Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in
mind the following points when designing your system:
• Reinforce the wiring for power supply and ground (if noise is superimposed on the power and
ground lines, it has the same effect as if noise were superimposed on the serial clock).
• Shorten the wiring between the device's ASCK, TSCK, BCLK pins, and clock supply source.
• Do not cross the signal lines of the serial clock with any other signal lines. Do not route the
serial clock line in the vicinity of a line through which a high alternating current flows.
• Supply the clock to the ASCK, TSCK, BCLK pins of the device from the clock source on a oneto-one basis. Do not supply clock to several devices from one clock source.
• Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure
that the rising and falling of the serial clock waveform are clear.
×
Make sure that the serial clock
rises and falls linearly.
64
The serial clock must not bound. Noise
must not be superimposed on the serial clock.
Data Sheet U15203EJ3V0DS
×
The serial clock must not rise or
fall step-wise.
µPD77210, 77213
SD card Interface (µPD77213 only)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
SDCR input setup time
tsuSDCR
Input response
10
ns
SDCR input hold time
thSDCR
Input response
0
ns
SDDAT input setup time
tsuSDD
Input data
10
ns
SDDAT input hold time
thSDD
Input data
0
ns
Switching characteristics
Parameter
Symbol
Condition
MIN.
TYP.
nx
MAX.
Note
tcC
Unit
SDCLK cycle time
tcSDC
ns
SDCLK high level width
twSDC(H)
2 tcC
ns
SDCLK low level width
twSDC(L)
tcSDC −
twSDC(H)
ns
SDCLK rise/fall time
trfSDC
SDCR output delay time
tdSDCR
Output command
SDCR output valid time
tvSDCR
Output command
SDDAT output delay time
tdSDD
Output data
SDDAT output valid time
tvSDD
Output data
5
ns
10
ns
0
ns
10
0
ns
ns
Note n:SD card clock division ratio
Data Sheet U15203EJ3V0DS
65
µPD77210, 77213
SDCR timing
tcSDC
twSDC(L)
twSDC(H)
trfSDC
trfSDC
trfSDC
trfSDC
SDCLK
tdSDCR
tvSDCR
SDCR
(Output)
tsuSDCR
thSDCR
SDCR
(Input)
SDDAT timing
tcSDC
twSDC(H)
twSDC(L)
SDCLK
tdSDD
tvSDD
SDDAT0
(Output)
tsuSDD
thSDD
SDDAT0
(Input)
Remark The SDMON pin functions alternately as the external data memory interface pin MA13. When accessing
a peripheral register related to the SD card interface, the SDMON (MA13) pin becomes high level, and
the MA0 to MA12 pins become low level. For the timing of these pins, refer to External Data Memory
Access.
66
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Debugging Interface (JTAG)
Timing requirements
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
TCK cycle time
tcTCK
50 and
Note
2 tcC
ns
TCK high/low level width
twTCK
25
ns
TCK rise/fall time
trfTCK
TDI input setup time
tsuTDI
12.5
ns
TDI input hold time
thTDI
12.5
ns
Input pin setup time
tsuJIN
12.5
ns
Input pin hold time
thJIN
12.5
ns
TRST low level width
twTRST
100
ns
20
ns
Note When using debugger, the value is 50 and 2 tcCX (MIN.).
Switching characteristics
Parameter
Symbol
TDO output delay time
tdTDO
Output pin output delay time
tdJOUT
Condition
MIN.
0
Data Sheet U15203EJ3V0DS
TYP.
MAX.
Unit
17.5
ns
17.5
ns
67
µPD77210, 77213
Debugging interface timing
tcTCK
twTCK
trfTCK
twTCK
TCK
twTRST
TRST
tsuTDI
thTDI
TMS, TDI
Valid
Valid
Valid
tdTDO
TDO
tsuJIN
thJIN
Capture state
Valid
tdJOUT
Update state
Remark For details of JTAG, refer to IEEE1149.1.
68
Data Sheet U15203EJ3V0DS
trfTCK
µPD77210, 77213
11. PACKAGE DRAWINGS
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A
B
108
109
73
72
detail of lead end
S
C
D
R
Q
144
1
F
G
37
36
H
I
J
M
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
22.0±0.2
B
20.0±0.2
C
20.0±0.2
D
22.0±0.2
F
1.25
G
H
1.25
0.22±0.05
I
0.08
J
0.5 (T.P.)
K
1.0±0.2
L
0.5±0.2
M
0.17 +0.03
−0.07
N
P
0.08
1.4±0.05
Q
0.10±0.05
R
+4°
3° −3°
S
1.6 MAX.
S144GJ-50-8EN-1
Data Sheet U15203EJ3V0DS
69
µPD77210, 77213
161-PIN PLASTIC FBGA (10x10)
ZD
w
E
S B
ZE
B
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
D
P NML K J HG F EDC B A
INDEX MARK
w
S A
A
y1
A2
S
S
y
e
S
φb
A1
φx
M
S A B
ITEM
MILLIMETERS
D
E
w
10.00±0.10
10.00±0.10
0.20
1.23±0.10
A
A1
0.30±0.05
A2
e
b
0.93
0.65
0.40±0.05
x
0.08
y
y1
ZD
0.10
0.20
0.775
ZE
0.775
P161F1-65-DA2
70
Data Sheet U15203EJ3V0DS
µPD77210, 77213
12. RECOMMENDED SOLDERING CONDITIONS
The µPD77210 Family should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Surface Mounting Type Soldering Conditions
µPD77210F1-DA2::161-pin plastic fine pitch BGA (10 x 10)
µPD77213F1-xxx-DA2::161-pin plastic fine pitch BGA (10 x 10)
Soldering method
Infrared reflow
Soldering conditions
Recommended
condition symbol
Package peak temperature: 235 °C, Time: 30 sec. Max. (at 210 °C or higher).
Count: two times or less
Exposure limit: 7 days Note (after that prebaking is necessary at 125 °C for 10 to 72
hours)
IR35-107-2
µPD77210GJ-8EN::144-pin plastic LQFP (fine pitch) (20 x 20)
µPD77213GJ-xxx-8EN::144-pin plastic LQFP (fine pitch) (20 x 20)
Soldering method
Soldering conditions
Recommended
condition symbol
Infrared reflow
Package peak temperature: 235 °C, Time: 30 sec. Max. (at 210 °C or higher).
Count: two times or less
Exposure limit: 3 days Note (after that prebaking is necessary at 125 °C for 10 to 72
hours)
IR35-103-2
Partial heating
Pin temperature: 300 °C Max. , Time: 3 sec. Max. (per pin row)
−
Note After opening the dry pack, store it at 25 °C or less and 65 % RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for the partial heating).
Data Sheet U15203EJ3V0DS
71
µPD77210, 77213
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
72
Data Sheet U15203EJ3V0DS
µPD77210, 77213
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet U15203EJ3V0DS
73
µPD77210,77213
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:
µPD77210F1-DA2, µPD77210GJ-8EN
The customer must judge the µPD77213F1-xxx-DA2, µPD77213GJ-xxx-8EN
• The information in this document is current as of November, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4