ETC UPD780021AGC-XXX-ABB

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD780021A, 780022A, 780023A, 780024A,
780021AY, 780022AY, 780023AY, 780024AY
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD780021A, 780022A, 780023A, and 780024A are members of the µPD780024A Subseries of the 78K/0
Series. Only selected functions of the existing µPD78054 Subseries are provided, and the serial interface is enhanced.
The µPD780021AY, 780022AY, 780023AY, and 780024AY are the µPD780024A Subseries with a multimaster
supporting I2C bus interface, which makes them suitable for AV equipment.
Flash memory versions, the µPD78F0034A and 78F0034AY, that can operate in the same power supply voltage
range as the mask ROM versions, and various development tools, are also supported.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780024A, 780034A, 780024AY, 780034AY
Subseries User’s Manual:
U14046E
78K/0 Series User’s Manual Instructions:
U12326E
FEATURES
• Internal ROM and RAM
Item
Program Memory
(Internal ROM)
Data Memory
(Internal High-Speed RAM)
Package
µPD780021A, 780021AY
8 KB
512 bytes
• 64-pin plastic SDIP (19.05mm (750))
µPD780022A, 780022AY
16 KB
µPD780023A, 780023AY
24 KB
µPD780024A, 780024AY
32 KB
Part Number
• 64-pin plastic QFP (14 × 14)
1024 bytes
• 64-pin plastic TQFP (12 × 12)
• External memory expansion space: 64 KB
• Minimum instruction execution time: 0.24 µs (@ fx = 8.38 MHz operation)
• I/O ports: 51 (N-ch open-drain 5 V withstand voltage: 4)
• 8-bit resolution A/D converter: 8 channels (AVDD = 1.8 to 5.5 V)
• Serial interface: 3 channels
• µPD780021A, 780022A, 780023A, 780024A: UART mode, 3-wire serial I/O mode (2 channels)
• µPD780021AY, 780022AY, 780023AY, 780024AY: UART mode, 3-wire serial I/O mode, I2C bus mode
• Timer: 5 channels
• Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Telephones, household electrical appliances, pagers, AV equipment, car audios, office automation equipment, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14042EJ3V0DS00 (3rd edition)
Date Published December 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999, 2000
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
ORDERING INFORMATION
Part Number
Package
µPD780021ACW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780021AGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780021AGK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780022ACW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780022AGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780022AGK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780023ACW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780023AGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780023AGK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780024ACW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780024AGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780024AGK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780021AYCW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780021AYGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780021AYGK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780022AYCW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780022AYGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780022AYGK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780023AYCW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780023AYGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780023AYGK-×××-9ET
64-pin plastic TQFP (12 × 12)
µPD780024AYCW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780024AYGC-×××-AB8
64-pin plastic QFP (14 × 14)
µPD780024AYGK-×××-9ET
64-pin plastic TQFP (12 × 12)
Remark ××× indicates ROM code suffix.
2
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
µ PD78075B
µ PD78078
µ PD78070A
100-pin
80-pin
80-pin
µ PD780058
µ PD78058F
80-pin
µPD78054
µPD780065
64-pin
µ PD780078
64-pin
64-pin
64-pin
µ PD780034A
µ PD780024A
µPD78014H
64-pin
µPD78018F
µ PD78083
80-pin
42-/44-pin
EMI-noise reduced version of the µPD78078
µPD78078Y
µPD78054 with added timer and enhanced external interface
µ PD78070AY
ROM-less version of the µPD78078
µPD78078Y with enhanced serial I/O and limited function
µ PD780018AY
µ PD780058Y
µPD78054 with enhanced serial I/O
EMI-noise reduced version of the µ PD78054
µ PD78058FY
µPD78018F with added UART and D/A converter and enhanced I/O
RAM capacity of the µ PD780024A increased
µPD780034A with added timer and enhanced serial I/O
µ PD780078Y
µPD780024A with enhanced A/D converter
PD780034AY
µ
µ
PD78018F with enhanced serial I/O
µ PD780024AY
EMI-noise reduced version of the µPD78018F
µ PD78054Y
µ PD78018FY
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
64-pin
µPD780988
On-chip inverter controller and UART. EMI-noise reduced.
VFD drive
78K/0
Series
100-pin
µ PD780208
µPD78044F with enhanced I/O and VFD C/D. Display output total: 53
80-pin
For panel control. On-chip VFD and C/D. Display output total: 53
80-pin
µ PD780232
µPD78044H
80-pin
µPD78044F
Basic subseries for VFD drive. Display output total: 34
µPD78044F with added N-ch open-drain I/O. Display output total: 34
LCD drive
120-pin
µ PD780338
120-pin
µ PD780328
µPD780318
µ PD780308
µPD78064B
µPD78064
120-pin
100-pin
100-pin
100-pin
µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
µPD780308Y
µ PD78064 with enhanced SIO, and increased ROM, RAM capacity
EMI-noise reduced version of the µ PD78064
µ PD78064Y
Basic subseries for LCD drive, on-chip UART
Bus interface supported
100-pin
80-pin
µ PD780948
µ PD78098B
On-chip D-CAN controller
µPD78054 with added IEBusTM controller. EMI-noise reduced.
80-pin
µ PD780701Y
On-chip D-CAN/IEBus controller
80-pin
µ PD780833Y
On-chip controller compliant with J1850 (Class 2)
Meter control
100-pin
µPD780958
For industrial meter control
80-pin
µPD780852
µPD780824
On-chip automobile meter controller/driver
For automobile meter driver. On-chip D-CAN controller
80-pin
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are same.
Data Sheet U14042EJ3V0DS
3
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
The major functional differences between the subseries are listed below.
•
Non Y subseries
Function
Subseries Name
Control
ROM
Capacity
Timer
8-bit 10-bit 8-bit
8-bit 16-bit Watch WDT A/D A/D D/A
µPD78075B
32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch
µPD78078
48 K to 60 K
µPD78070A
–
2 ch 3 ch (UART: 1ch)
–
88
1.8 V
61
2.7 V
3ch (time division UART: 1ch) 68
1.8 V
µPD78058F
48 K to 60 K
3 ch (UART: 1ch)
2.7 V
µPD78054
16 K to 60 K
µPD780065
40 K to 48 K
µPD780078
48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
69
–
–
8 ch
8 K to 60 K
µPD78083
8 K to 16 K
Inverter
control
µPD780988
16 K to 60 K 3 ch Note
VFD
drive
µPD780208
32 K to 60 K 2 ch 1 ch 1ch
µPD780232
16 K to 24 K 3 ch
µPD78044H
32 K to 48 K 2 ch 1 ch 1ch
µPD78044F
16 K to 40 K
µPD780338
48 K to 60 K 3 ch 2ch
8 ch
–
–
60
2.7 V
3 ch (UART: 2ch)
52
1.8 V
3 ch (UART: 1ch)
51
2 ch
53
1 ch (UART: 1ch)
33
–
–
–
4 ch (UART: 1ch)
–
1 ch
–
8 ch
–
3 ch (UART: 2ch)
47
4.0 V
√
1ch
8 ch
–
–
2 ch
74
2.7 V
–
40
4.5 V
68
2.7 V
54
1.8 V
–
2.0 V
–
79
4.0 V
√
69
2.7 V
–
–
4 ch
8ch
1 ch
2 ch
1ch
1ch
–
10 ch 1 ch 2 ch (UART: 2 ch)
µPD780328
62
µPD780318
70
µPD780308
48 K to 60 K 2 ch 1 ch
µPD78064B
32 K
µPD78064
16 K to 32 K
60 K
√
2.0 V
µPD78018F
Bus
µPD780948
interface
supported µPD78098B
8 ch
–
–
3 ch (Time division UART: 1 ch) 57
2 ch (UART: 1 ch)
2 ch 2 ch 1 ch 1 ch 8 ch
40 K to 60 K
–
1 ch
–
3 ch (UART: 1 ch)
2 ch
Meter
control
µPD780958
48 K to 60 K 4 ch 2 ch
Dash
board
control
µPD780852
32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch
µPD780824
32 K to 60 K
–
1 ch
–
–
–
2 ch (UART: 1 ch)
69
2.2 V
–
–
–
3 ch (UART: 1 ch)
56
4.0 V
–
2 ch (UART: 1 ch)
59
16-bit timer: 2 channels
10-bit timer: 1 channel
4
VDD MIN. External
Value Expansion
24 K to 60 K 2 ch
µPD78014H
Note
I/O
µPD780058
µPD780024A
LCD
drive
Serial Interface
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
•
Y subseries
Function
Subseries Name
Control
µPD78078Y
ROM
Capacity
Timer
8-bit 10-bit 8-bit
8-bit 16-bit Watch WDT A/D A/D D/A
48 K to 60 K 4 ch 1 ch 1 ch 1 ch 8 ch
µPD78070AY
–
2 ch 3 ch (UART: 1ch,
–
µPD780018AY 48 K to 60 K
–
µPD780058Y 24 K to 60 K 2 ch
I2C: 1 ch)
61
2.7 V
3 ch (I2C 1 ch)
88
3 ch (UART: 1 ch,
µPD78054Y
I2C: 1 ch)
µPD780078Y 48 K to 60 K
2 ch
µPD780034AY 8 K to 32 K
1 ch
–
8 ch
8 ch
–
–
µPD78064Y
–
–
16 K to 32 K
For bus µPD780701Y 60 K
interface
µPD780833Y
68
1.8 V
69
2.7 V
√
2.0 V
4 ch (UART: 2 ch,
I2C: 1 ch)
52
3 ch (UART: 1 ch,
51
1.8 V
I2C: 1 ch)
µPD78018FY 8 K to 60 K
µPD780308Y 48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
VDD MIN. External
Value Expansion
1.8 V
2 ch 3 ch (Time division
UART: 1 ch, I2C: 1 ch)
16 K to 60 K
I/O
88
µPD78058FY 48 K to 60 K
µPD780024AY
LCD
drive
Serial Interface
2 ch (I2C: 1 ch)
53
3 ch (Time division
UART: 1 ch, I2C: 1 ch)
57
2.0 V
–
4 ch (UART: 1 ch,
67
3.5 V
–
I2C: 1 ch)
65
4.5 V
2 ch (UART: 1 ch,
I2C: 1 ch)
3 ch 2 ch 1 ch 1 ch 16 ch
–
–
Remark The functions of non Y subseries and Y subseries products are the same, except for the serial interface.
Data Sheet U14042EJ3V0DS
5
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
OVERVIEW OF FUNCTIONS
µPD780021A
µPD780021AY
Part Number
Item
Internal
ROM
8 KB
memory
High-speed RAM
512 bytes
µPD780022A
µPD780022AY
16 KB
µPD780023A
µPD780023AY
24 KB
32 KB
1024 bytes
Memory space
64 KB
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
On-chip minimum instruction execution time cycle variable function
time
µPD780024A
µPD780024AY
When main system 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation)
clock selected
When subsystem
clock selected
122 µs (@ 32.768 kHz operation)
Instruction set
•
•
•
•
16-bit operation
Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjust, etc.
I/O ports
Total:
51
• CMOS input:
8
• CMOS I/O:
39
• N-ch open-drain I/O (5-V withstand voltage): 4
A/D converter
• 8-bit resolution x 8 channels
• Low-voltage operation available: AVDD = 1.8 to 5.5 V
Serial interface
• µPD780021A, 780022A, 780023A, 780024A
UART mode:
1 channel
3-wire serial I/O mode: 2 channels
• µPD780021AY, 780022AY, 780023AY, 780024AY
UART mode:
1 channel
3-wire serial I/O mode:
1 channel
I2C bus mode (multimaster supporting): 1 channel
Timers
•
•
•
•
Timer outputs
3 (8-bit PWM output capable: 2)
Clock output
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system clock )
• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock)
Vectored
Maskable
Internal: 13, external: 5
interrupt
Non-maskable
Internal: 1
Software
1
sources
6
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
1
2
1
1
channel
channels
channel
channel
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 64-pin plastic SDIP (19.05 mm (750))
• 64-pin plastic QFP (14 × 14)
• 64-pin plastic TQFP (12 × 12)
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 8
2. BLOCK DIAGRAM ............................................................................................................................. 11
3. PIN FUNCTIONS ................................................................................................................................12
3.1
Port Pins .................................................................................................................................................... 12
3.2
Non-Port Pins ............................................................................................................................................ 13
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 15
4. MEMORY SPACE ...............................................................................................................................17
5. PERIPHERAL HARDWARE FUNCTION FEATURES .......................................................................18
5.1
Ports ........................................................................................................................................................... 18
5.2
Clock Generator ........................................................................................................................................ 19
5.3
Timer/Counter ........................................................................................................................................... 20
5.4
Clock Output/Buzzer Output Controller ................................................................................................ 24
5.5
A/D Converter ........................................................................................................................................... 25
5.6
Serial Interface .......................................................................................................................................... 26
6. INTERRUPT FUNCTIONS .................................................................................................................29
7. EXTERNAL DEVICE EXPANSION FUNCTION ...............................................................................32
8. STANDBY FUNCTION .......................................................................................................................32
9. RESET FUNCTION ............................................................................................................................32
10. MASK OPTION ...................................................................................................................................32
11. INSTRUCTION SET ...........................................................................................................................33
12. ELECTRICAL SPECIFICATIONS ......................................................................................................35
13. PACKAGE DRAWINGS .....................................................................................................................57
14. RECOMMENDED SOLDERING CONDITIONS ................................................................................60
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................62
APPENDIX B. RELATED DOCUMENTS ................................................................................................65
Data Sheet U14042EJ3V0DS
7
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
1. PIN CONFIGURATION (TOP VIEW)
• 64-pin plastic SDIP (19.05 mm (750))
µPD780021ACW-×××, 780022ACW-×××, 780023ACW-×××, 780024ACW-×××
µPD780021AYCW-×××, 780022AYCW-×××, 780023AYCW-×××, 780024AYCW-×××
P40/AD0
1
64
P67/ASTB
P41/AD1
2
63
P66/WAIT
P42/AD2
3
62
P65/WR
P43/AD3
4
61
P64/RD
P44/AD4
5
60
P75/BUZ
P45/AD5
6
59
P74/PCL
P46/AD6
7
58
P73/TI51/TO51
P47/AD7
8
57
P72/TI50/TO50
P50/A8
9
56
P71/TI01
P51/A9
10
55
P70/TI00/TO0
P52/A10
11
54
P03/INTP3/ADTRG
P53/A11
12
53
P02/INTP2
P54/A12
13
52
P01/INTP1
P55/A13
14
51
P00/INTP0
P56/A14
15
50
VSS1
P57/A15
16
49
X1
VSS0
17
48
X2
VDD0
18
47
IC
P30
19
46
XT1
P31
P32/SDA0Note1
20
21
45
44
XT2
RESET
P33/SCL0Note1
22
43
AVDD
P34/SI31Note2
23
42
AVREF
P35/SO31Note2
24
41
P10/ANI0
P36/SCK31Note2
25
40
P11/ANI1
P20/SI30
26
39
P12/ANI2
P21/SO30
27
38
P13/ANI3
P22/SCK30
28
37
P14/ANI4
P23/RxD0
29
36
P15/ANI5
P24/TxD0
30
35
P16/ANI6
P25/ASCK0
31
34
P17/ANI7
VDD1
32
33
AVSS
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When the µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY
are used in applications where the noise generated inside the microcontroller needs to be reduced, the
implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually
and connecting VSS0 and VSS1 to different ground lines, is recommended.
8
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
• 64-pin plastic QFP (14 × 14)
µPD780021AGC-×××-AB8, 780022AGC×××-AB8, 780023AGC-×××-AB8, 780024AGC-×××-AB8,
µPD780021AYGC-×××-AB8, 780022AYGC×××-AB8, 780023AYGC-×××-AB8, 780024AYGC-×××-AB8
• 64-pin plastic TQFP (12 × 12)
µPD780021AGK-×××-9ET, 780022AGK×××-9ET, 780023AGK-×××-9ET, 780024AGK-×××-9ET,
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
µPD780021AYGK-×××-9ET, 780022AYGK×××-9ET, 780023AYGK-×××-9ET, 780024AYGK-×××-9ET
P50/A8
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P51/A9
2
47
P70/TI00/TO0
P52/A10
3
46
P03/INTP3/ADTRG
P53/A11
4
45
P02/INTP2
P54/A12
5
44
P01/INTP1
P55/A13
6
43
P00/INTP0
P56/A14
7
42
VSS1
P57/A15
8
41
X1
VSS0
9
40
X2
VDD0
10
39
IC
P30
11
38
XT1
P71/TI01
P31
12
37
XT2
P32/SDA0Note1
13
36
RESET
P33/SCL0Note1
14
35
AVDD
P34/SI31Note2
15
34
AVREF
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AVSS
VDD1
P25/ASCK0
P24/TxD0
P23/RxD0
P22/SCK30
P21/SO30
P20/SI30
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P36/SCK31Note2
P35/SO31Note2
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
Cautions 1. Connect the IC (Internally Connected) pin directory to VSSO or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When the µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY
are used in applications where the noise AYgenerated inside the microcontroller needs to be reduced,
the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually
and connecting VSS0 and VSS1 to different ground lines, is recommended.
Data Sheet U14042EJ3V0DS
9
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
A8 to A15:
Address Bus
P64 to P67:
AD0 to AD7:
Address/Data Bus
P70 to P75:
Port 7
ADTRG:
AD Trigger Input
PCL:
Programmable Clock
ANI0 to ANI7:
Analog Input
RD:
Read Strobe
ASCK0:
Asynchronous Serial Clock
RESET:
Reset
ASTB:
Address Strobe
RxD0:
Receive Data
AVDD:
Analog Power Supply
SCK30, SCK31, SCL0: Serial Clock
AVREF:
Analog Reference Voltage
SDA0:
Serial Data
AVSS:
Analog Ground
SI30, SI31:
Serial Input
BUZ:
Buzzer Clock
SO30, SO31:
Serial Output
IC:
Internally Connected
TI00, TI01, TI50, TI51: Timer Input
INTP0 to INTP3:
External Interrupt Input
TO0, TO50, TO51:
Timer Output
P00 to P03:
Port 0
TxD0:
Transmit Data
P10 to P17:
Port 1
V DD0, VDD1:
Power Supply
P20 to P25:
Port 2
V SS0, V SS1:
Ground
P30 to P36:
Port 3
WAIT:
Wait
P40 to P47:
Port 4
WR:
Write Strobe
P50 to P57:
Port 5
X1, X2:
Crystal (Main System Clock)
XT1, XT2:
Crystal (Subsystem Clock)
10
Data Sheet U14042EJ3V0DS
Port 6
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
2. BLOCK DIAGRAM
TI00/TO0/P70
16-bit timer/
event counter
Port 0
P00 to P03
TI50/TO50/P72
8-bit timer/
event counter 50
Port 1
P10 to P17
TI51/TO51/P73
8-bit timer/
event counter 51
Port 2
P20 to P25
Watchdog timer
Port 3
P30 to P36
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P64 to P67
Port 7
P70 to P75
TI01/P71
Watch timer
SI30/P20
SO30/P21
SCK30/P22
SI31/P34
SO31/P35
SCK31/P36
RxD0/P23
TxD0/P24
ASCK0/P25
SDA0/P32
SCL0/P33
ANI0/P10 to
ANI7/P17
AVDD
AVSS
AVREF
INTP0/P00 to
INTP3/P03
78K/0
CPU core
ROM
Serial
interface 30
Serial
interface 31Note1
RAM
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
UART0
External
access
I2C busNote2
RD/P64
WR/P65
WAIT/P66
ASTB/P67
A/D converter
System
control
Interrupt
control
BUZ/P75
Buzzer output
PCL/P74
Clock output
control
VDD0 VDD1 VSS0 VSS1
RESET
X1
X2
XT1
XT2
IC
Notes 1. Incorporated only in the µPD780024A Subseries.
2. Incorporated only in the µPD780024AY Subseries.
Remark The internal ROM and RAM capacities vary depending on the product.
Data Sheet U14042EJ3V0DS
11
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
I/O
P00 to P02
I/O
Function
After
Alternate
Reset
Function
Port 0
Input
4-bit I/O port
INTP2
Input/output can be specified in 1-bit units.
P03
INTP3/ADTRG
An on-chip pull-up resistor can be connected by means of software.
P10 to P17
Input
INTP0 to
Port 1
Input
ANI0 to ANI7
Input
SI30
8-bit input only port
P20
I/O
Port 2
6-bit I/O port
P21
SO30
Input/output can be specified in 1-bit units.
P22
SCK30
An on-chip pull-up resistor can be connected by means of software.
P23
RxD0
P24
TxD0
P25
ASCK0
P30
I/O
P31
P32
Port 3
N-ch open-drain I/O port
7-bit I/O port
An on-chip pull-up resistor can be
Input/output can be specified in
specified by the mask option.
1-bit units.
LEDs can be driven directly.
Input
—
SDA0Note 1
SCL0Note 1
P33
P34
An on-chip pull-up resistor can be
SI31Note 2
P35
connected by means of software.
SO31Note 2
SCK31Note 2
P36
P40 to P47
I/O
Port 4
Input
AD0 to AD7
Input
A8 to A15
Input
RD
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
The interrupt request flag (KRIF) is set to 1 by falling edge detection.
P50 to P57
I/O
Port 5
8-bit I/O port
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be connected by means of software.
P64
P65
P66
I/O
Port 6
4-bit I/O port
WR
Input/output can be specified in 1-bit units.
WAIT
An on-chip pull-up resistor can be connected by means of software.
P67
ASTB
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
12
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.1 Port Pins (2/2)
Pin Name
P70
I/O
I/O
Function
Port 7
After
Alternate
Reset
Function
Input
6-bit I/O port
P71
TI01
Input/output can be specified in 1-bit units.
P72
TI00/TO0
TI50/TO50
An on-chip pull-up resistor can be connected by means of software.
P73
TI51/TO51
P74
PCL
P75
BUZ
3.2 Non-Port Pins (1/2)
Pin Name
INTP0
I/O
Input
INTP2
Function
External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
After
Alternate
Reset
Function
Input
P01
INTP2
P02
INTP3
SI30
P03/ADTRG
Input
Serial interface serial data input
Input
SI31Note 1
SO30
P00
P20
P34
Output
Serial interface serial data output
Input
SO31Note 1
P21
P35
SDA0Note 2
I/O
Serial Interface serial data input/output
Input
P32
SCK30
I/O
Serial interface serial clock input/output
Input
P22
SCK31Note 1
P36
SCL0Note 2
P33
RxD0
Input
Serial data input for asynchronous serial interface
Input
P23
TxD0
Output
Serial data output for asynchronous serial interface
Input
P24
ASCK0
Input
Serial clock input for asynchronous serial interface
Input
P25
TI00
Input
External count clock input to 16-bit timer/event counter 0
Input
P70/TO0
Capture trigger input to capture register 01 (CR01) of 16-bit timer/event counter 0
TI01
Capture trigger input to capture register 00 (CR00) of 16-bit timer/event counter 0
P71
TI50
External count clock input to 8-bit timer/event counter 50
P72/TO50
TI51
External count clock input to 8-bit timer/event counter 51
P73/TO51
TO0
16-bit timer/event counter 0 output
Input
P70/TI00
TO50
Output
8-bit timer/event counter 50 output (also used for 8-bit PWM output)
Input
P72/TI50
TO51
8-bit timer/event counter 51 output (also used for 8-bit PWM output)
P73/TI51
PCL
Output
Clock output (for trimming of main system clock and subsystem clock)
Input
P74
BUZ
Output
Buzzer output
Input
P75
Lower address/data bus for expanding memory externally
Input
P40 to P47
AD0 to AD7
I/O
A8 to A15
Output
Higher address bus for expanding memory externally
Input
P50 to P57
RD
Output
Strobe signal output for reading from external memory
Input
P64
WR
Strobe signal output for writing to external memory
WAIT
Input
ASTB
Output
P65
Wait insertion at external memory access
Input
P66
Strobe output that externally latches address information output to
ports 4 and 5 to access external memory
Input
P67
Notes 1. SI31, SO31, SCK31 are incorporated only in the µPD780024A Subseries.
2. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
Data Sheet U14042EJ3V0DS
13
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.2 Non-Port Pins (2/2)
Pin Name
I/O
Function
After
Alternate
Reset
Function
ANI0 to ANI7
Input
A/D converter analog input
Input
P10 to P17
ADTRG
Input
A/D converter trigger signal input
Input
P03/INTP3
AVREF
Input
A/D converter reference voltage input
—
—
AVDD
—
A/D converter analog power supply. Set potential to that of VDD0 or VDD1
—
—
AVSS
—
A/D converter ground potential. Set potential to that of VSS0 or VSS1
—
—
RESET
Input
System reset input
—
—
X1
Input
Connecting crystal resonator for main system clock oscillation
—
—
X2
—
—
—
XT1
Input
—
—
XT2
—
—
—
VDD0
—
Positive power supply for ports
—
—
VSS0
—
Ground potential of ports
—
—
VDD1
—
Positive power supply (except ports)
—
—
VSS1
—
Ground potential (except ports)
—
—
IC
—
Internally connected. Connect directly to VSS0 or VSS1.
—
—
14
Connecting crystal resonator for subsystem clock oscillation
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Types of Pin I/O Circuits
Pin Name
I/O
Circuit Type
I/O
P00/INTP0 to P02/INTP2
8-C
I/O
P10/ANI0 to P17/ANI7
25
Input
P20/S130
8-C
I/O
P21/SO30
5-H
P22/SCK30
8-C
P03/INTP3/ADTRG
Recommended Connection of Unused Pins
Input: Independently connect to VSS0 via a resistor.
Output: Leave open.
Connect to VDD0 or VSS0 via a resistor.
Input: Independently connect to VDD0 or VSS0 via a resistor.
Output: Leave open.
P23/RxD0
P24/TxD0
5-H
P25/ASCK0
8-C
P30, P31
13-Q
P32, P33
(µPD780024A Subseries only)
13-S
P32/SDA0
(µPD780024AY Subseries only)
13-R
I/O
Input: Independently connect to VDD0 via resistor.
Output: Leave open.
P33/SCL0
(µPD780024AY Subseries only)
P34/SI31Note
8-C
Input: Independently connect to VDD0 or VSS0 via a resistor.
P35/SO31Note
5-H
Output: Leave open.
P36/SCK31Note
8-C
P40/AD0 to P47/AD7
5-H
I/O
Input: Independently connect to VDD0 via a resistor.
P50/A8 to P57/A15
I/O
Input: Independently connect to VDD0 or VSS0 via a resistor.
P64/RD
I/O
Output: Leave open.
Output: Leave open.
P65/WR
P66/WAIT
P67/ASTB
P70/TI00/TO0
8-C
P71/TI01
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
5-H
P75/BUZ
RESET
2
XT1
16
XT2
AVDD
AVREF
Input
Connect to VDD0.
—
—
—
Leave open.
Connect to VDD0 or VDD1.
Connect to VSS0 or VSS1.
AVSS
IC
Note
Connect directly to VSS0 or VSS1.
SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
Data Sheet U14042EJ3V0DS
15
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 3-1. Pin I/O Circuits
TYPE 2
TYPE 13-R
IN/OUT
Data
Output disable
N-ch
IN
VSS0
Schmitt-triggered input with hysteresis characteristics
TYPE 5-H
Pull-up
enable
TYPE 13-S
VDD0



Mask 
option 
VDD0
IN/OUT
P-ch
Data
Output disable
VDD0
Data
N-ch
P-ch
VSS0
IN/OUT
Output
disable
N-ch
VSS0
Input
enable
TYPE 16
TYPE 8-C
VDD0
Feedback
cut-off
Pull-up
enable
P-ch
P-ch
VDD0
Data
P-ch
IN/OUT
Output
disable
N-ch
VSS0
TYPE 13-Q
XT1
TYPE 25
VDD0



XT2
Mask 
option 
P-ch
IN/OUT
Data
Output disable
Comparator
N-ch
–
N-ch
VSS0
VREF (threshold voltage)
VSS0
Input
enable
Input
enable
16
+
Data Sheet U14042EJ3V0DS
IN
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
4. MEMORY SPACE
Figure 4-1 shows the memory map of the µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY,
780023AY, and 780024AY.
Figure 4-1. Memory Map
FFFFH
Special function registers (SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 × 8 bits
Internal high-speed
RAMNote
mmmmH
mmmmH – 1
nnnnH
Data memory
space
Reserved
Program area
1000H
0FFFH
CALLF entry area
F800H
F7FFH
0800H
07FFH
Program area
External memory
0080H
007FH
Program memory
space
nnnnH + 1
nnnnH
CALLT table area
Note
Internal ROM
0040H
003FH
Vector table area
0000H
0000H
Note
The internal ROM and internal high-speed RAM capacities vary depending on the products (see the
following table).
Part Number
Last Address of Internal ROM
nnnnH
Start Address of Internal High-Speed RAM
mmmmH
µPD780021A, 780021AY
1FFFH
FD00H
µPD780022A, 780022AY
3FFFH
µPD780023A, 780023AY
5FFFH
µPD780024A, 780024AY
7FFFH
Data Sheet U14042EJ3V0DS
FB00H
17
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following 3 types of I/O ports are available.
• CMOS input (Port 1):
8
• CMOS I/O (Ports 0, 2, 4 to 7, P34 to P36):
39
• N-channel open-drain I/O (P30 to P33):
4
Total:
51
Table 5-1. Port Functions
Name
Pin Name
Function
Port 0
P00 to P03
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Port 1
P10 to P17
Input-only port.
Port 2
P20 to P25
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Port 3
P30 to P33
N-channel open-drain I/O port. Input/output can be specified in 1-bit units.
A pull-up resistor can be specified by mask option.
LEDs can be driven directly.
P34 to P36
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
P40 to P47
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Port 4
The interrupt request flag (KRIF) is set to 1 by falling edge detection.
Port 5
P50 to P57
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
LEDs can be driven directly.
Port 6
P64 to P67
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
Port 7
P70 to P75
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of software.
18
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.2 Clock Generator
A system clock generator is incorporated.
The minimum instruction execution time can be changed.
• 0.24 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation with main system clock)
• 122 µs (@ 32.768 kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1
XT2
Subsystem
clock
oscillator
fXT
Watch timer, clock
output function
Prescaler
1
X1
X2
Main system
clock
oscillator
STOP
Prescaler
fX
fX
2
fX
22
fX
23
2
fXT
2
Clock to peripheral
hardware
fX
24
Selector
Data Sheet U14042EJ3V0DS
Standby
controller
Wait
controller
CPU clock
(fCPU)
19
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.3 Timer/Counter
Five timer/counter channels are incorporated.
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter:
2 channels
• Watch timer:
1 channel
• Watchdog timer:
1 channel
Table 5-2. Operations of Timer/Event Counter
16-Bit Timer/
Event Counter 0
8-Bit Timer/
Event Counters 50, 51
Watch Timer
Watchdog Timer
Interval timer
1 channel
2 channels
1 channelNote 1
1 channelNote 2
External event counter
1 channel
2 channels
—
—
Timer outputs
1
2
—
—
PPG outputs
1
—
—
—
PWM output
—
2
—
—
2 inputs
—
—
—
Square wave outputs
1
2
—
—
Interrupt sources
2
2
2
1
Operation mode
Function
Pulse width measurement
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or the interval timer function.
20
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter 0
TI01/P71
Selector
Noise
eliminator
Selector
Internal bus
16-bit capture/compare
register 00 (CR00)
INTTM00
fX
fX/22
fX/26
TI00/TO0/P70
16-bit timer counter 0
(TM0)
Clear
Output
controller
TO0/TI00/P70
Match
Noise
eliminator
Noise
eliminator
16-bit capture/compare
register 01 (CR01)
Selector
fX/23
Selector
Match
INTTM01
Internal bus
Data Sheet U14042EJ3V0DS
21
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
Selector
INTTM50
S
Q
INV
8-bit timer
OVF
counter 50 (TM50)
Selector
Match
Selector
TI50/TO50/P72
fX
fX/22
fX/24
fX/26
fX/28
fX/210
Mask circuit
8-bit compare
register 50 (CR50)
R
TO50/TI50/P72
Clear
S
3
Level
inversion
R
Selector
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
Timer mode control
register 50 (TMC50)
TCL502 TCL501 TCL500
Timer clock selection
register 50 (TCL50)
Internal bus
Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
8-bit timer
counter51
(TM51)
Selector
S
Q
INV
OVF
R
INTTM51
Selector
Match
Selector
TI51/TO51/P73
fX/2
fX/23
fX/25
fX/27
fX/29
fX/211
Mask circuit
8-bit compare
register 51
(CR51)
Clear
S
3
R
Selector
TCL512 TCL511 TCL510
Timer clock selection
register 51 (TCL51)
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
Timer mode control
register 51 (TMC51)
Internal bus
22
Level
inversion
Data Sheet U14042EJ3V0DS
TO51/TI51/P73
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-5. Watch Timer Block Diagram
Clear
Selector
fX/2
7
fW
24
fW
25
fW
26
fW
27
fW
28
fW
29
INTWT
Clear
Selector
fXT
5-bit counter
9-bit prescaler
fW
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer mode
control register (WTM)
Internal bus
Figure 5-6. Watchdog Timer Block Diagram
fX
fX/28
Clock
input
controller
Divider
Divided
clock
selector
Output
controller
INTWDT
RESET
RUN
Division mode
selector
3
WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation
stabilization time
selection register
(OSTS)
WDCS2 WDCS1 WDCS0
Watchdog timer
clock selection
register (WDCS)
RUN WDTM4 WDTM3
Watchdog timer
mode register
(WDTM)
Internal bus
Data Sheet U14042EJ3V0DS
23
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.4 Clock Output/Buzzer Output Controller
A clock output/buzzer output controller (CKU) is incorporated.
Clocks with the following frequencies can be output as clock output.
• 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (@ 8.38 MHz operation with main
system clock)
• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Clocks with the following frequencies can be output as buzzer output.
• 1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (@ 8.38 MHz operation with main system clock)
Figure 5-7. Block Diagram of Clock Output/Buzzer Output Control Circuit CKU
Prescaler
8
4 fX/210 to fX/213
Selector
fX
BZOE
BUZ/P75
BCS0, BCS1
Selector
fX to fX/27
fXT
Clock
controller
CLOE
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output selection register (CKS)
Internal bus
24
Data Sheet U14042EJ3V0DS
PCL/P74
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.5 A/D Converter
An A/D converter consisting of eight 8-bit resolution channels is incorporated.
The following two A/D conversion operation startup methods are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series resistor string
AVDD
Sample & hold circuit
ANI0/P10
AVREF
ANI1/P11
Voltage comparator
ANI2/P12
Tap
selector
ANI3/P13
ANI4/P14
Selector
ANI5/P15
ANI6/P16
Succesive approximation
register (SAR)
ANI7/P17
INTP3/ADTRG/P03
Edge
detector
Edge
detector
AVSS
INTAD
Controller
A/D conversion
result register (ADCR0)
INTP3
Internal bus
Data Sheet U14042EJ3V0DS
25
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.6 Serial Interface
Three serial interface channels are incorporated.
• µPD780024A Subseries
Serial interface UART0:
1 channel
Serial interface 30, 31:
2 channels
• µPD780024AY Subseries
Serial interface UART0:
1 channel
Serial interface 30:
1 channel
Serial interface IIC0
1 channel
(1) Serial interface UART0
Serial interface UART0 has two modes: asynchronous serial interface (UART) mode and infrared data transfer
mode.
• Asynchronous serial interface (UART) mode
This mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted
and received.
The on-chip UART-dedicated baud-rate generator enables communication using a wide range of selectable
baud rates. In addition, a baud rate can be also defined by dividing the clock input to the ASCK0 pin.
The UART-dedicated baud-rate generator can also be used to generate a MIDI-standard baud rate (31.25
kbps).
• Infrared data transfer mode
This mode enables pulse output and pulse reception in data format.
This mode can be used for office equipment applications such as personal computers.
Figure 5-9. Block Diagram of Serial Interface UART0
Internal bus
Asynchronous serial
interface mode
register0 (ASIM0)
Receive
RXB0 buffer
register0
RxD0/P23
RX0
Receive
shift
register0
TXE0 RXE0 PS01 PS00 CL0
SL0 ISRM0 IRDAM0
Asynchronous serial
interface status
register0
(ASIS0)
TXS0 Transmit
shift
PE0 FE0 OVE0
register0
TxD0/P24
Receive
controller
(parity
check)
Transmit
INTSER0 controller
INTSR0
(parity
addition)
INTST0
Baud rate
generator
26
Data Sheet U14042EJ3V0DS
P25/ASCK0
fX/2 to fX/27
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Serial interface 3nNote
Serial interface 3n has one mode: 3-wire serial I/O mode.
• 3-wire serial I/O mode (fixed as MSB first)
This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3n), serial output line (SO3n),
and serial input line (SI3n).
Since simultaneous transmit and receive operations are enabled in the 3-wire serial I/O mode, the
processing time for data transfer is reduced.
The first bit in 8-bit data in the serial transfer is fixed as MSB.
The 3-wire serial I/O mode is useful for connection to a peripheral I/O devices, and display controllers, etc.,
that include a clocked serial interface.
Figure 5-10. Block Diagram of Serial Interface 3n
Internal bus
8
Serial I/O shift register
3n (SIO3n)
SI3n
SO3n
Serial clock
counter
SCK3n
Serial clock
controller
Interrupt request
signal generator
Selector
INTCSI3n
fX/23
fX/24
fX/25
Remark µPD780024A Subseries: n = 0, 1
µPD780024AY Subseries: n = 0
Data Sheet U14042EJ3V0DS
27
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(3) Serial interface IIC0 (µPD780024AY Subseries only)
Serial interface IIC0 has one mode: I2C (Inter IC) bus mode (supporting multimaster).
• I2C bus mode (supporting multimaster)
This is an 8-bit data transfer mode using two lines: a serial clock line (SCL0) and a serial data bus line
(SDA0).
This mode complies with the I2C bus format, and can output a “start condition”, “data”, and a “stop condition”
during transmission via the serial data bus. This data is automatically detected by hardware during
reception.
Since SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the serial
data bus line are required.
Figure 5-11. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0
(IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0
(IICC0)
Slave address
register 0 (SVA0)
SDA0/P32
Noise eliminator
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0
Matched
signal
IIC shift register 0
(IIC0)
SPT0
CLEAR
SET
SO0 latch
D
CL00
Acknowledge
detector
Data hold
time corrector
N-ch opendrain output
Wake-up controller
Acknowledge
detector
Start condition
detector
Stop condition
detector
SCL0/P33
Noise eliminator
Interrupt request
signal generator
Serial clock counter
Serial clock wait
controller
Serial clock controller
N-ch open-drain
output
fX
Prescaler
CLD0 DAD0 SMC0 DFC0 CL00
IIC transfer clock select
register 0 (IICCL0)
Internal bus
28
Data Sheet U14042EJ3V0DS
INTIIC0
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
6. INTERRUPT FUNCTIONS
A total of 20 interrupt sources are provided, divided into the following three types.
• Non-maskable: 1
• Maskable:
18
• Software:
1
Table 6-1. Interrupt Source List
Interrupt Source
Default
Type
PriorityNote 1
Name
Nonmaskable
—
INTWDT
Watchdog timer overflow
(with watchdog timer mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow
(with interval timer mode selected)
1
INTP0
Pin input edge detection
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTSER0
Serial interface UART0 reception error
generation
6
INTSR0
End of serial interface UART0 reception
0010H
7
INTST0
End of serial interface UART0 transmission
0012H
8
INTCSI30
End of serial interface 30 transfer
0014H
9
INTCSI31
End of serial interface 31 transfer
0016H
Trigger
Internal/
Vector
Table
Address
Interrupt
External
Internal
0004H
Basic
Configuration
TypeNote 2
(A)
(B)
External
Internal
0006H
000EH
(C)
(B)
[Only for µPD780024A Subseries]
10
INTIIC0
End of serial interface IIC0 transfer
[Only for µPD780024AY Subseries]
0018H
11
INTWTI
Reference time interval signal from watch timer
001AH
12
INTTM00
Match between TM0 and CR00
(when CR00 is specified as compare register)
Detection of TI01 valid edge
001CH
(when CR00 is specified as capture register)
Software
13
INTTM01
Match between TM0 and CR01
(when CR01 is specified as compare register)
Detection of TI00 valid edge
(when CR01 is specified as capture register)
001EH
14
INTTM50
Match between TM50 and CR50
0020H
15
INTTM51
Match between TM51 and CR51
0022H
16
INTAD0
End of A/D conversion
0024H
17
INTWT
Watch timer overflow
0026H
18
INTKR
Port 4 falling edge detection
—
BRK
BRK instruction execution
External
0028H
(D)
—
003EH
(E)
Notes 1. The default priority is the priority when several maskable interrupt requests are generated at the same
time. 0 is the highest order, and 18 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Remark Two watchdog timer interrupt sources (INTWDT): a non-maskable interrupt and a maskable interrupt
(internal), are available, either of which can be selected.
Data Sheet U14042EJ3V0DS
29
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 6-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Vector table
address
generator
Priority
controller
Interrupt
request
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR
ISP
Vector table
address
generator
Priority
controller
IF
Standby release
signal
(C) External maskable interrupt (INTP0 to INTP3)
Internal bus
External interrupt
edge enable register
(EGP, EGN)
Interrupt
request
Edge
detector
MK
IE
IF
PR
Priority
controller
ISP
Vector table
address
generator
Standby release
signal
30
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 6-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (INTKR)
Internal bus
MK
Interrupt
request
Falling edge
detector
IE
PR
ISP
Priority
controller
IF
Vector table
address
generator
Standby release
signal
(E) Software interrupt
Internal bus
Priority
controller
Interrupt
request
IF:
Vector table
address
generator
Interrupt request flag
IE:
Interrupt enable flag
ISP:
In-service priority flag
MK:
Interrupt mask flag
PR:
Priority specification flag
Data Sheet U14042EJ3V0DS
31
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function is for connecting external devices to areas other than the internal ROM,
RAM, and SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby modes are available for further reduction of system current consumption.
• HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be
reduced by intermittent operation by combining this mode with the normal operation mode.
• STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on
the main system clock are suspended, and only the subsystem clock is used, resulting in
extremely small power consumption. This can be used only when the main system clock is
operating (the subsystem clock oscillation cannot be stopped).
Figure 8-1. Standby Function
CSS = 1
Main system clock
operation
Interrupt
request
CSS = 0
HALT
instruction
STOP
instruction
HALT
instruction
Interrupt
request
STOP mode
Main system clock
operation is stopped
Note
Subsystem clock
operationNote
Interrupt
request
HALT mode
HALT modeNote
Clock supply for CPU is stopped,
oscillation is maintained
Clock supply for CPU is stopped,
oscillation is maintained
The current consumption can be reduced by stopping the main system clock. When the CPU is operating
on the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction
cannot be used.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back to
the main system clock.
9. RESET FUNCTION
The following two reset methods are available.
• External reset by RESET signal input
• Internal reset by watchdog timer runaway time detection
10. MASK OPTION
Table 10.1 Pin Mask Option Selection
Subseries Name
Pins
Mask Option
µPD780024A Subseries
P30 to P33
µPD780024AY Subseries
P30 and P33
An on-chip pull-up resistor can be specified in 1-bit units.
The mask option can be used to specify the connection of an on-chip pull-up resistor to P30 to P33Note, in 1-bit units.
Note
32
The µPD780024AY Subseries has P30 and P31 only.
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
11. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd
Operand
[HL + byte]
#byte
1st
Operand
A
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B]
$addr16
1
None
[HL + C]
A
ADD
MOV
MOV
ADDC
XCH
XCH
SUB
ADD
SUBC
ADDC
AND
MOV
XCH
XCH
ADD
ADD
ADDC
SUB
SUB
MOV
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
RORC
ADDC
ADDC
ADDC
ROLC
SUB
SUB
SUB
SUBC
OR
SUBC
SUBC
SUBC
SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
r
MOV
INC
DEC
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
B, C
sfr
MOV
MOV
saddr
MOV
ADD
MOV
DBNZ
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
MOV
MOV
PSW
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note
Except r = A
Data Sheet U14042EJ3V0DS
33
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
1st Operand
rpNote
AX
MOVW
ADDW
SUBW
CMPW
AX
MOVW
MOVWNote
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
Note
MOVW
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
XCHW
rp
SP
sfrp
INCW, DECW
PUSH, POP
MOVW
MOVW
MOVW
Only when rp = BC, DE or HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
1st Operand
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
None
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
CY
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
SET1
CLR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
NOT1
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
1st Operand
Basic instruction
AX
BR
!addr16
CALL
BR
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
Compound
instruction
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
34
$addr16
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
AVDD
AVREF
AVSS
Input voltage
VI1
P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2,
Ratings
Unit
–0.3 to +6.5
V
–0.3 to VDD +
0.3Note
V
–0.3 to VDD +
0.3Note
V
–0.3 to +0.3
V
–0.3 to VDD + 0.3Note
V
–0.3 to + 6.5
V
RESET
VI2
P30 to P33
N-ch open-drain Without pull-up resistor
With pull-up resistor
Output voltage
VO
Analog input voltage
VAN
P10 to P17
Output current,
high
IOH
Output current,
low
IOL
–0.3 to VDD +
0.3Note
V
–0.3 to VDD +
0.3Note
V
AVSS – 0.3 to AVREF0 + 0.3Note
and –0.3 to VDD + 0.3Note
V
Per pin
–10
mA
Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75
–15
mA
Total for P20 to P25, P30 to P36
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to
20
mA
Per pin for P30 to P33, P50 to P57
30
mA
Total for P00 to P03, P40 to P47,
50
mA
Total for P20 to P25
20
mA
Total for P30 to P36
100
mA
Total for P50 to P57
100
mA
–40 to +85
°C
–65 to +150
°C
Analog input pin
P36, P40 to P47, P64 to P67, P70 to P75
P64 to P67, P70 to P75
Operating ambient
TA
temperature
Storage
temperature
Note
Tstg
6.5 V or below
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Data Sheet U14042EJ3V0DS
35
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input
Symbol
Conditions
TYP.
f = 1 MHz
CIN
capacitance
I/O
capacitance
MIN.
Unit
15
pF
15
pF
20
pF
Unmeasured pins returned to 0 V.
CIO
f = 1 MHz
Unmeasured pins
returned to 0 V.
P00
P34
P50
P70
to
to
to
to
P03, P20 to P25,
P36, P40 to P47,
P57, P64 to P67,
P75
P30 to P33
Remark
MAX.
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (TA = –40 to 85°C, VDD = 1.8 to 5.5 V)
Resonator
Ceramic
resonator
Recommended
Circuit
X1
C1
Crystal
resonator
X1
C1
X2 IC
C2
X2 IC
C2
Parameter
Conditions
Oscillation
frequency (fX)Note 1
VDD = 4.0 to 5.5 V
Oscillation
stabilization timeNote 2
After VDD reaches
oscillation voltage range
MIN.
Oscillation
frequency (fX)Note 1
VDD = 4.0 to 5.5 V
Oscillation
VDD = 4.0 to 5.5 V
MIN.
TYP.
MAX.
Unit
1.0
8.38
MHz
1.0
5.0
4
ms
1.0
8.38
MHz
1.0
5.0
10
stabilization timeNote 2
External
clock
X1
X2
µ PD74HCU04
ms
30
X1 input
frequency (fX)Note 1
VDD = 4.0 to 5.5 V
X1 input
high-/low-level width
(tXH, tXL)
VDD = 4.0 to 5.5 V
1.0
8.38
1.0
5.0
50
500
85
500
MHz
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
36
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
resonator
Recommended Circuit
XT2
R
C4
External
clock
XT1 IC
C3
XT2
µPD74HCU04
Parameter
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
XT1
Conditions
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
VDD = 4.0 to 5.5 V
10
XT1 input
frequency (fXT)Note 1
32
38.5
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
5
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Data Sheet U14042EJ3V0DS
37
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Recommended Oscillator Constant
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Manufacturer
Part Number
Frequency
Recommended Circuit Constant
(MHz)
C1 (pF)
Oscillation Voltage Range
C2 (pF)
MIN. (V)
MAX. (V)
Murata Mfg.
CSB1000J
1.00
100
100
1.8
5.5
Co., Ltd.
CSA2.00MG040
2.00
100
100
1.8
5.5
CST2.00MG040
2.00
On-chip
On-chip
1.8
5.5
CSA3.58MG
3.58
30
30
1.8
5.5
CST3.58MGW
3.58
On-chip
On-chip
1.8
5.5
CSA4.19MG
4.19
30
30
1.8
5.5
CST4.19MGW
4.19
On-chip
On-chip
1.8
5.5
CSA5.00MG
5.00
30
30
1.8
5.5
CST5.00MGW
5.00
On-chip
On-chip
1.8
5.5
CSA8.00MTZ
8.00
30
30
4.0
5.5
CST8.00MTW
8.00
On-chip
On-chip
4.0
5.5
CSA8.00MTZ093
8.00
30
30
4.0
5.5
CST8.00MTW093
8.00
On-chip
On-chip
4.0
5.5
CSA8.38MTZ
8.38
30
30
4.0
5.5
CST8.38MTW
8.38
On-chip
On-chip
4.0
5.5
CSA8.38MTZ093
8.38
30
30
4.0
5.5
TDK
CST8.38MTW093
8.38
On-chip
On-chip
4.0
5.5
CCR3.58MC3
3.58
On-chip
On-chip
1.8
5.5
CCR4.19MC3
4.19
On-chip
On-chip
1.8
5.5
CCR5.0MC3
5.00
On-chip
On-chip
1.8
5.5
CCR8.0MC5
8.00
On-chip
On-chip
2.0
5.5
CCR8.38MC5
8.38
On-chip
On-chip
2.0
5.5
Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed.
For applications requiring oscillation
frequency precision, the oscillation frequency must be adjusted on the implementation circuit.
For details, contact directly the manufacturer of the resonator used.
38
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Output current,
Symbol
IOH
high
Output current,
IOL
low
Conditions
MIN.
TYP.
MAX.
Unit
Per pin
–1
mA
All pins
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to P36,
10
mA
Per pin for P30 to P33, P50 to P57
15
mA
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
20
mA
Total for P20 to P25
10
mA
Total for P30 to P36
70
mA
Total for P50 to P57
70
mA
0.7VDD
VDD
V
0.8VDD
VDD
V
0.8VDD
VDD
V
0.85VDD
VDD
V
0.7VDD
5.5
V
0.8VDD
5.5
V
VDD – 0.5
VDD
V
VDD – 0.2
VDD
V
0.8VDD
VDD
V
0.9VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
0
0.2VDD
V
P40 to P47, P64 to P67, P70 to P75
Input voltage,
VIH1
high
P10 to P17, P21, P24, P35,
VDD = 2.7 to 5.5 V
P40 to P47, P50 to P57,
P64 to P67, P74, P75
VIH2
P00 to P03, P20, P22, P23, P25,
VDD = 2.7 to 5.5 V
P34, P36, P70 to P73, RESET
VIH3
P30 to P33
VDD = 2.7 to 5.5 V
(N-ch open-drain)
Input voltage,
VIH4
X1, X2
VDD = 2.7 to 5.5 V
VIH5
XT1, XT2
VDD = 4.0 to 5.5 V
VIL1
low
P10 to P17, P21, P24, P35,
VDD = 2.7 to 5.5 V
P40 to P47, P50 to P57,
P64 to P67, P74, P75
VIL2
P00 to P03, P20, P22, P23, P25,
VDD = 2.7 to 5.5 V
P34, P36, P70 to P73, RESET
VIL3
VIL4
Output voltage,
X1, X2
0
0.15VDD
V
4.0 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.0 V
0
0.2VDD
V
1.8 V ≤ VDD < 2.7 V
0
0.1VDD
V
VDD = 2.7 to 5.5 V
0
0.4
V
0
0.2
V
0
0.2VDD
V
VIL5
XT1, XT2
0
0.1VDD
V
VOH1
VDD = 4.0 to 5.5 V, IOH = –1 mA
VDD – 1.0
VDD
V
IOH = –100 µA
VDD – 0.5
VDD
V
high
Output voltage,
P30 to P33
VOL1
low
VDD = 4.0 to 5.5 V
P30 to P33
VDD = 4.0 to 5.5 V,
P50 to P57
IOL = 15 mA
P00 to P03, P20 to P25, P34 to P36, VDD = 4.0 to 5.5 V,
P40 to P47, P64 to P67, P70 to P75
VOL2
Remark
0.4
2.0
V
2.0
V
0.4
V
0.5
V
IOL = 1.6 mA
IOL = 400 µA
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ3V0DS
39
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
Conditions
TYP.
MAX.
Unit
VIN = VDD
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P60 to P67, P70 to P75,
RESET
3
µA
X1, X2, XT1, XT2
20
µA
ILIH3
VIN = 5.5 V
P30 to P33Note
3
µA
ILIL1
VIN = 0 V
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
µA
X1, X2, XT1, XT2
–20
µA
ILIH1
ILIH2
Input leakage
MIN.
current, low
ILIL2
–3
µA
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
current, low
ILOL
VOUT = 0 V
–3
µA
Mask option
pull-up resistance
R1
VIN = 0 V,
P30, P31, P32Note2, P33Note2
15
30
90
kΩ
Software pullup resistance
R2
VIN = 0 V,
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
15
30
90
kΩ
ILIL3
P30 to P33
Note1
Notes 1. µPD780021A, 780022A, 780023A, 780024A: When pull-up resistors are not connected to P30 to P33
(specified by the mask option).
µPD780021AY, 780022AY, 780023AY, 780024AY: When pull-up resistors are not connected to P30
and P31 (specified by the mask option).
2. Only for the µPD780021A, 780022A, 780023A, and 780024A.
Remark
40
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Power supply
currentNote 1
Symbol
IDD1
IDD2
Conditions
8.38 MHz
VDD = 5.0 V ±10%Note 2
crystal oscillation
operating mode
MIN.
TYP.
5.5
MAX.
11
Unit
mA
When A/D converter is
operating
6.5
13
mA
5.00 MHz
VDD = 3.0 V ±10%Note 2
crystal oscillation
operating mode
When A/D converter is
stopped
2
4
mA
When A/D converter is
operating
3
6
mA
VDD = 2.0 V ±10%Note 3
When A/D converter is
stopped
0.4
1.5
mA
When A/D converter is
operating
1.4
4.2
mA
8.38 MHz
VDD = 5.0 V ±10%Note 2
crystal oscillation
HALT mode
When peripheral functions
are stopped
1.1
2.2
mA
4.7
mA
VDD = 3.0 V ±10%Note 2
5.00 MHz
crystal oscillation
HALT mode
When peripheral functions
are stopped
0.7
mA
1.7
mA
VDD = 2.0 V ±10%Note 3
When peripheral functions
are stopped
0.4
mA
1.1
mA
80
40
20
60
18
10
30
10
10
µA
µA
µA
µA
µA
µA
µA
µA
µA
When A/D converter is
stopped
When peripheral functions
are operating
0.35
When peripheral functions
are operating
0.15
When peripheral functions
are operating
IDD3
32.768 kHz crystal oscillation
operating modeNote 4
IDD4
32.768 kHz crystal oscillation
HALT modeNote 4
IDD5
XT1 = VDD STOP mode
When feedback resistor is not used
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
=
=
=
=
=
=
=
=
=
5.0
3.0
2.0
5.0
3.0
2.0
5.0
3.0
2.0
V
V
V
V
V
V
V
V
V
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
40
20
10
30
6
2
0.1
0.05
0.05
Notes 1. Total current through the internal power supply (VDD0, VDD1), including the peripheral operation current
(except the current through pull-up resistors of ports and the AVREF pin).
2. When the processor clock control register (PCC) is set to 00H.
3. When PCC is set to 02H.
4. When main system clock operation is stopped.
Data Sheet U14042EJ3V0DS
41
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
(Min. instruction
Conditions
MIN.
tTIH0, tTIL0
high-/low-level
4.0 V ≤ VDD ≤ 5.5 V
0.24
16
µs
2.7 V ≤ VDD < 4.0 V
0.4
16
µs
1.6
16
µs
125
µs
Operating with subsystem clock
103.9Note 1
4.0 V ≤ VDD ≤ 5.5 V
2/fsam+0.1Note2
µs
2.7 V ≤ VDD < 4.0 V
2/fsam+0.2Note2
µs
2/fsam+0.5Note2
µs
VDD = 2.7 to 5.5 V
0
4
MHz
0
275
kHz
tTIH5, tTIL5
VDD = 2.7 to 5.5 V
100
ns
1.8
ns
1
µs
2
µs
10
µs
20
µs
high-/low-level
width
Interrupt request
tINTH, tINTL
input high-/lowlevel width
RESET
122
fTI5
frequency
TI50, TI51 input
Unit
main system clock
width
TI50, TI51 input
MAX.
Operating with
execution time)
TI00, TI01 input
TYP.
INTP0 to INTP3,
VDD = 2.7 to 5.5 V
P40 to P47
tRSL
VDD = 2.7 to 5.5 V
low-level width
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register
0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
42
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
TCY vs. VDD (main system clock operation)
16.0
Cycle time TCY [ µ s]
10.0
Operation
guaranteed
range
5.0
2.0
1.6
1.0
0.4
0.24
0.1
0
1.0
2.0
1.8
3.0
4.0
5.0 5.5 6.0
2.7
Supply voltage VDD [V]
Data Sheet U14042EJ3V0DS
43
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Parameter
Symbol
Conditions
(1/3)
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6
ns
Data input time from address
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
100
ns
Address output time from RD↓
tRDAD
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 87
ns
tRDD2
(3 + 2n)tCY – 93
ns
0
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
tWRWT
tCY – 25
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 15
ns
Delay time from ASTB↓ to RD↓
tASTRD
6
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 15
ns
Delay time from
tRDAST
0.8tCY – 15
1.2tCY
ns
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
10
60
ns
Address hold time from WR↑
tWRADH
0.8tCY – 15
1.2tCY + 30
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.8tCY
2.5tCY + 25
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.8tCY
2.5tCY + 25
ns
RD↑ to ASTB↑ at external fetch
Address hold time from
RD↑ at external fetch
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and
ASTB pins.)
44
ns
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)
(2/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
30
ns
Address hold time
tADH
10
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 108
ns
tADD2
(3 + 2n)tCY – 120
ns
200
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 148
ns
tRDD2
(3 + 2n)tCY – 162
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 40
ns
tRDL2
(2.5 + 2n)tCY – 40
ns
Input time from RD↓ to WAIT↓
tRDWT1
tCY – 75
ns
tRDWT2
tCY – 60
ns
Input time from WR↓ to WAIT↓
tWRWT
tCY – 50
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
(2 + 2n)tCY
ns
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
10
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 30
ns
Delay time from ASTB↓ to RD↓
tASTRD
10
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 30
ns
Delay time from
tRDAST
0.8tCY – 30
1.2tCY
ns
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
20
120
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 30
1.2tCY + 60
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 50
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 50
ns
RD↑ to ASTB↑ at external fetch
Hold time from
RD↑ to address at external fetch
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
ns
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,
and ASTB pins.)
Data Sheet U14042EJ3V0DS
45
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
(3/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
120
ns
Address hold time
tADH
20
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 233
ns
tADD2
(3 + 2n)tCY – 240
ns
400
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 325
ns
tRDD2
(3 + 2n)tCY – 332
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 92
ns
tRDL2
(2.5 + 2n)tCY – 92
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 350
ns
tRDWT2
tCY – 132
ns
tWRWT
tCY – 100
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 60
ns
Delay time from ASTB↓ to RD↓
tASTRD
20
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 60
ns
Delay time from
tRDAST
0.8tCY – 60
1.2tCY
ns
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
40
240
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 60
1.2tCY + 120
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 100
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 100
ns
RD↑ to ASTB↑ at external fetch
Hold time from
RD↑ to address at external fetch
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT, and
ASTB pins.)
46
ns
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter
SCK3n
Symbol
tKCY1
cycle time
SCK3n high-/
tKH1, tKL1
Conditions
tSIK1
(to SCK3n↑)
SI3n hold time
(from SCK3n↑)
tKSI1
Delay time from
SCK3n↓ to SO3n
output
tKSO1
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
954
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
3200
ns
tKCY1/2 – 50
ns
tKCY1/2 – 100
ns
4.0 V ≤ VDD ≤ 5.5V
100
ns
2.7 V ≤ VDD < 4.0V
150
ns
300
ns
400
ns
VDD = 4.0 to 5.5 V
low-level width
SI3n setup time
MIN.
C = 100 pFNote
300
ns
MAX.
Unit
Note C is the load to SO3n output capacitance of the SCK3n and SO3n output lines.
(b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
3200
ns
4.0 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.0 V
800
ns
1600
ns
tSIK2
100
ns
SI3n hold time
(from SCK3n↑)
tKSI2
400
ns
Delay time from
SCK3n↓ to SO3n
output
tKSO2
SCK3n
tKCY2
cycle time
SCK3n high-/
tKH2, tKL2
low-level width
SI3n setup time
(to SCK3n↑)
C = 100 pFNote
300
ns
Note C is the load capacitance of the SO3n output line.
Remark µPD780021A, 780022A, 780023A, 780024A:
n = 0, 1
µPD780021AY, 780022AY, 780023AY, 780024AY: n = 0
Data Sheet U14042EJ3V0DS
47
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(c) UART mode (dedicated baud-rate generator output)
Parameter
Symbol
Transfer rate
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
131031
bps
2.7 V ≤ VDD < 4.0 V
78125
bps
39063
bps
MAX.
Unit
(d) UART mode (external clock input)
Parameter
ASCK0 cycle time
ASCK0 high-/low-level width
Symbol
tKCY3
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
3200
ns
tKH3,
4.0 V ≤ VDD ≤ 5.5 V
400
ns
tKL3
2.7 V ≤ VDD < 4.0 V
800
ns
1600
ns
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
39063
bps
2.7 V ≤ VDD < 4.0 V
19531
bps
9766
bps
MAX.
Unit
(e) UART mode (infrared data transfer mode)
Parameter
Conditions
MIN.
Transfer rate
VDD = 4.0 to 5.5 V
131031
bps
Bit rate allowable error
VDD = 4.0 to 5.5 V
±0.87
%
Output pulse width
VDD = 4.0 to 5.5 V
1.2
0.24/fbrNote
µs
Input pulse width
VDD = 4.0 to 5.5 V
4/fX
Note
48
Symbol
fbr: Specified baud rate
Data Sheet U14042EJ3V0DS
µs
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(f) I2C bus mode (µPD780021AY, 780022AY, 780023AY, 780024AY only)
Parameter
Symbol
Standard Mode
MIN.
MAX.
High-Speed Mode
MIN.
MAX.
Unit
SCL0 clock frequency
fCLK
0
100
0
400
kHZ
Bus free time
tBUF
4.7
—
1.3
—
µs
Hold timeNote 1
tHD:STA
4.0
—
0.6
—
µs
SCL0 clock low-level width
tLOW
4.7
—
1.3
—
µs
SCL0 clock high-level width
tHIGH
4.0
—
0.6
—
µs
Start/restart condition setup time
tSU:STA
4.7
—
0.6
—
µs
Data hold time CBUS-compatible master
tHD:DAT
(between stop and start conditions)
I2C bus
5.0
—
0Note 2
—
0Note 2
—
—
µs
0.9Note 3
µs
Data setup time
tSU:DAT
250
—
100Note 4
—
ns
SDA0 and SCL0 signal rise time
tR
—
1000
20 + 0.1CbNote 5
300
ns
—
300
0.1CbNote 5
300
ns
4.0
—
—
µs
SDA0 and SCL0 signal fall time
tF
Stop condition setup time
tSU:STO
20 +
0.6
Spike pulse width controlled by input filter
tSP
—
—
0
50
ns
Capacitive load per bus line
Cb
—
400
—
400
pF
Notes 1. In the start condition, the first clock pulse is generated after this hold time.
2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide
at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal).
3. If the device does not extend the SCL0 signal low hold time (tLOW), only the maximum data hold time
tHD:DAT needs to be fulfilled.
4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the conditions
described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT
= 1000 + 250 = 1250 ns by standard mode I2C bus specification).
5. Cb: Total capacitance per bus line (unit: pF)
Data Sheet U14042EJ3V0DS
49
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
AC Timing Measurement Points (Excluding X1, XT1 Inputs)
0.8VDD
0.2VDD
0.8VDD
Point of measurement
0.2VDD
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 Input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 Input
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fT5
tTIL5
TI50, TI51
50
Data Sheet U14042EJ3V0DS
tTIH5
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
Data Sheet U14042EJ3V0DS
51
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
tADD1
AD0 to AD7
Lower 8-bit address
tADS
tADH
Hi-Z
Instruction code
tRDAD
tRDD1
tRDADH
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1
AD0 to AD7
Hi-Z
Lower 8-bit address
tADS
tADH
tRDAD
Instruction code
tRDADH
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
52
tWTL
Data Sheet U14042EJ3V0DS
tWTRD
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Lower 8-bit address
tADS
tADH
Hi-Z
tRDAD
tRDD2
tASTH
Hi-Z
Write data
Read Data
tRDH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDS
tWDH
tWRADH
tWRWD
WR
tASTWR
tWRL1
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Lower 8-bit
address
tADS tADH
tASTH
Hi-Z
Read data
Hi-Z
Write data
tRDAD
tRDH
tRDD2
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDH
tWDS
tWRWD
WR
tASTWR
tWRL1
tWRADH
WAIT
tRDWT2
tWTL
tWTRD
tWTL
tWRWT
Data Sheet U14042EJ3V0DS
tWTWR
53
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
SCK3n
tSIKm
tKSIm
Input data
SI3n
tKSOm
SO3n
Output data
Remarks 1. m = 1, 2
2. µPD780021A, 780022A, 780023A, 780024A:
n = 0, 1
µPD780021AY, 780022AY, 780023AY, 780024AY: n = 0
UART mode (external clock input):
t KCY3
t KL3
t KH3
ASCK0
I2C bus mode (µPD780021AY, 780022AY, 780023AY, 780024AY only):
tLOW
tR
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:DAT
tF
tSU:STA
tHD:STA
tSP
tSU:STO
SDA0
tBUF
Stop
condition
54
Start
condition
Restart
condition
Data Sheet U14042EJ3V0DS
Stop
condition
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bit
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
Resolution
Overall errorNote
Conversion time
tCONV
Analog input voltage
VIAN
Reference voltage
AVREF
Resistance between AVREF and AVSS
RREF
4.0 V ≤ AVREF ≤ 5.5 V
14
96
µs
2.7 V ≤ AVREF < 4.0 V
19
96
µs
1.8 V ≤ AVREF < 2.7 V
28
96
µs
0
AVREF
V
1.8
AVDD
V
When A/D converter not operating
20
40
kΩ
Note Excludes quantization error (±1/2 LSB). This value is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Data retention power
Symbol
Conditions
MIN.
VDDDR
TYP.
1.6
MAX.
Unit
5.5
V
30
µA
supply voltage
Data retention power
supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
tWAIT
time
Subsystem clock stop (XT1 = VDD) and
feed-back resistor disconnected
0.1
µs
0
Release by RESET
217/fx
s
Release by interrupt request
Note
s
Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Sheet U14042EJ3V0DS
55
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP Instruction execution
Standby release signal
(interrupt request)
tWAIT
56
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
13. PACKAGE DRAWINGS
64-PIN PLASTIC SDIP (19.05mm(750))
64
33
1
32
A
K
J
L
I
M
F
D
N
C
M
R
B
H
G
NOTES
1. Each lead centerline is located within 0.17 mm of
its true position (T.P.) at maximum material condition.
2. Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
A
58.0+0.68
-0.20
B
1.78 MAX.
C
1.778 (T.P.)
D
0.50±0.10
F
0.9 MIN.
G
3.2±0.3
H
0.51 MIN.
I
4.05+0.26
-0.20
J
5.08 MAX.
K
19.05 (T.P.)
L
17.0±0.2
M
0.25+0.10
-0.05
N
0.17
R
0 ~ 15°
P64C-70-750A,C-4
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14042EJ3V0DS
57
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC QFP (14x14)
A
B
detail of lead end
33
32
48
49
S
C D
Q
64
1
R
17
16
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
17.6±0.4
B
14.0±0.2
C
14.0±0.2
D
17.6±0.4
F
1.0
G
1.0
H
0.37 +0.08
-0.07
I
J
0.15
0.8 (T.P.)
K
1.8±0.2
L
0.8±0.2
M
0.17 +0.08
-0.07
N
0.10
P
2.55±0.1
Q
0.1±0.1
R
5°± 5°
S
2.85 MAX.
P64GC-80-AB8-5
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
58
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC TQFP (12x12)
A
B
48
detail of lead end
33
32
49
S
P
T
C
D
R
L
U
64
Q
17
16
1
F
G
J
H
I
M
ITEM
K
S
M
N
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
14.0±0.2
B
12.0±0.2
C
12.0±0.2
D
F
14.0±0.2
1.125
G
1.125
H
0.32 +0.06
−0.10
I
0.13
J
0.65 (T.P.)
K
1.0±0.2
L
0.5
M
0.17 +0.03
−0.07
N
0.10
P
1.0
Q
0.1±0.05
R
3° +4°
−3°
S
1.1±0.1
T
0.25
U
0.6±0.15
P64GK-65-9ET-3
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14042EJ3V0DS
59
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Table 14-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD780021AGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780022AGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780023AGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780024AGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780021AYGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780022AYGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780023AYGC-×××-AB8: 64-pin plastic QFP (14 × 14)
µPD780024AYGC-×××-AB8: 64-pin plastic QFP (14 × 14)
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max.
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
Recommended
Condition Symbol
IR35-00-3
(at 210°C or higher), Count: Three times or less
VP15-00-3
(at 200°C or higher), Count: Three times or less
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
WS60-00-1
Count: Once, Preheating temperature: 120°C Max. (package surface
temperature)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
60
Data Sheet U14042EJ3V0DS
––
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Table 14-1. Surface Mounting Type Soldering Conditions (2/2)
(2) µPD780021AGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780022AGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780023AGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780024AGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780021AYGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780022AYGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780023AYGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
µPD780024AYGK-×××-9ET: 64-pin plastic TQFP (12 × 12)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max.
Recommended
Condition Symbol
IR35-107-2
(at 210°C or higher), Count: Two times or less, Exposure limit:
7 daysNote (after that, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
VP15-107-2
(at 200°C or higher), Count: Two times or less, Exposure limit:
7 daysNote (after that, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
––
Note After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage
period.
Caution Do not use different soldering methods together (except for partial heating).
Table 14-2. Insertion Type Soldering Conditions
µPD780021ACW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780022ACW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780023ACW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780024ACW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780021AYCW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780022AYCW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780023AYCW-×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780024AYCW-×××: 64-pin plastic SDIP (19.05 mm (750))
Soldering Method
Wave soldering
Soldering Conditions
Solder bath temperature: 260°C max., Time: 10 seconds max.
(only for pins)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with
the package.
Data Sheet U14042EJ3V0DS
61
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780024A, 780024AY
Subseries.
Also refer to (5) Cautions on Using Development Tools.
(1) Language Processing Software
RA78K0
Assembler package common to 78K/0 Series
CC78K0
C compiler package common to 78K/0 Series
DF780024
Device file for µPD780024A, 780024AY Subseries
CC78K0-L
C compiler library source file common to 78K/0 Series
(2) Flash Memory Writing Tools
Flashpro II (FL-PR2)
Flashpro III (FL-PR3, PG-FP3)
Flash programmer dedicated to microcontrollers with on-chip flash memory
FA-64CW
FA-64GC
FA-64GK-9ET
Adapter for flash memory writing
(3) Debugging Tools
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Performance board to enhance and expand the functions of IE-78K0-NS
IE-70000-98-IF-C
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported)
IE-70000-PC-IF-C
Adapter required when using IBM PC/ATTM or compatible as host machine (ISA bus supported)
IE-70000-PCI-IF-A
Adapter required when using PC in which PCI bus is incorporated as host machine
IE-780034-NS-EM1
Emulation board to emulate µPD780024A, 780024AY Subseries
NP-64CW
Emulation probe for 64-pin plastic SDIP (CW type)
NP-64GC
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
NP-64GC-TQ
NP-64GK
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
EV-9200GC-64
Conversion socket to connect the NP64GC and a target system board on which a 64-pin plastic
QFP (GC-AB8 type) can be mounted.
TGC-064SAP
Conversion adapter to connect the NP-64GC-TQ and a target system board on which a 64-pin
plastic QFP (GK-AB8 type) can be mounted
TGK-064SBP
Conversion adapter to connect the NP-64GK and a target system on which a 64-pin plastic
TQFP (GK-9ET type) can be mounted
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF780024
Device file for µPD780024A, 780024AY Subseries
62
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported)
IE-70000-PCI-IF-A
Adapter required when using PC in which PCI bus is incorporated as host machine
IE-78000-R-SV3
Interface adapter and cable when using EWS as host machine
IE-780034-NS-EM1
Emulation board to emulate µPD780024A, 780024AY Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A
EP-78240CW-R
Emulation probe for 64-pin plastic SDIP (CW type)
EP-78240GC-R
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EP-78012GK-R
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
EV-9200GC-64
Conversion socket to connect the EP-78240GC-R and a target system board on which a 64-pin
plastic QFP (GC-AB8 type) can be mounted
TGK-064SBP
Conversion adapter to connect the EP-78012GK-R and a target system board on which a 64-pin plastic
TQFP (GK-9ET type) can be mounted
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF780024
Device file for µPD780024A, 780024AY Subseries
(4) Real-Time OS
RX78K0
Real-time OS for 78K/0 Series
MX78K0
OS for 78K/0 Series
Data Sheet U14042EJ3V0DS
63
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(5) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combinaiton with the DF780024.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780024.
• FL-PR2, FL-PR3, FA-64CW, FA-64GC, FA-64GK-9ET, NP-64CW, NP-64GC, NP-64GC-TQ and NP-64GK are
products made by Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813).
• The TGC-064SAP, and TGK-064SBP are products made by TOKYO ELETECH CORPORATION.
Refer to: Daimaru Kogyo, Ltd.
Tokyo Electronic Division (+81-3-3820-7112)
Osaka Electronic Division (+81-6-6244-6672)
• For third-party development tools, see the Single-chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machines and OSs supporting each software are as follows.
Host Machine
PC
EWS
Software
PC-9800 series [Japanese WindowsTM]
IBM PC/AT and compatibles
[Japanese/English Windows]
HP9000 series 700TM [HP-UXTM]
SPARCstationTM [SunOSTM, SolarisTM]
NEWSTM (RISC) [NEWS-OSTM]
RA78K0
√ Note
√
CC78K0
√
Note
√
ID78K0-NS
√
–
ID78K0
√
√
SM78K0
√
–
RX78K0
√ Note
√
MX78K0
√
√
[OS]
Note
64
Note
DOS-based software
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet
µPD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A),
U14046E
This document
U15131E
780024AY(A) Data Sheet
µPD78F0034A, 78F0034AY Data Sheet
U14040E
78K/0 Series User’s Manual Instructions
U12326E
Documents Related to Development Tools (User’s Manuals)
Document Name
RA78K0 Assembler Package
CC78K0 C Compiler
Document No.
Operation
U11802E
Assembly Language
U11801E
Structured Assembly Language
U11789E
Operation
U11517E
Language
U11518E
IE-78K0-NS In-circuit Emulator
U13731E
IE-780034-NS-EM1 Emulation Board
U14642E
EP-78240 Emulation Probe
U10332E
SM78K0S, SM78K0 System Simulator Ver.2.10 or Later Windows
Operation
U14611E
based
SM78K Series System Simulator Ver.2.10 or Later
External Part User Open
Interface Specifications
To be prepared
ID78K0-NS Integrated Debugger Ver.2.00 Later Windows based
Operation
U14379E
ID78K0-NS, ID78K0S-NS Integrated Debugger Ver.2.20 or Later
Operation
U14910E
Reference
U11539E
Guide
U11649E
Windows based
ID78K0 Integrated Debugger Windows based
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U14042EJ3V0DS
65
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Documents Related to Embedded Software (User’s Manuals)
Document Name
78K/0 Series Real-time OS
78K/0 Series OS MX78K0
Document No.
Fundamentals
U11537E
Installation
U11536E
Fundamental
U12257E
Other Related Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
66
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
[MEMO]
Data Sheet U14042EJ3V0DS
67
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Note: Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
FIP and IEBus are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
68
Data Sheet U14042EJ3V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
Data Sheet U14042EJ3V0DS
69
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of November, 2000. The information is subject
to change without notice. For actual design-in, refer to the latest publications of NEC's data
sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor
products. Not all products and/or types are available in every country. Please check with an
NEC sales representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4