NEC UPD780024AF1-XXX-CN3

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD780021A, 780022A, 780023A, 780024A
780021AY, 780022AY, 780023AY, 780024AY
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD780021A, 780022A, 780023A, and 780024A are members of the µPD780024A Subseries of the 78K/0
Series. Only selected functions of the existing µPD78054 Subseries are provided, and the serial interface is enhanced.
The µPD780021AY, 780022AY, 780023AY, and 780024AY are the µPD780024A Subseries with a multimaster
supporting I2C bus interface, which makes them suitable for AV equipment.
Flash memory versions, the µPD78F0034A, 78F0034B, 78F0034AY, and 78F0034BY, that can operate in the same
power supply voltage range as the mask ROM versions, and various development tools, are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780024A, 780034A, 780024AY, 780034AY
Subseries User’s Manual:
U14046E
78K/0 Series Instructions User’s Manual:
U12326E
FEATURES
• Internal ROM and RAM
Item
Program Memory
(Internal ROM)
Data Memory
(Internal High-Speed RAM)
Package
µPD780021A, 780021AY
8 KB
512 bytes
• 64-pin plastic SDIP (19.05 mm (750))
µPD780022A, 780022AY
16 KB
µPD780023A, 780023AY
24 KB
µPD780024A, 780024AY
32 KB
Part Number
• 64-pin plastic QFP (14 x 14)
• 64-pin plastic LQFP (14 x 14)
1024 bytes
• 64-pin plastic TQFP (12 x 12)
• 64-pin plastic LQFP (10 x 10)
• 73-pin plastic FBGA (9 x 9)
• External memory expansion space: 64 KB
• Minimum instruction execution time
• Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A: 0.166 µs (fX = 12 MHz, VDD
= 4.5 to 5.5 V)
• µPD780021AY, 780022AY, 780023AY, 780024AY and conventional products of µPD780021A, 780022A,
780023A, 780024A: 0.238 µs (fX = 8.38 MHz, VDD = 4.0 to 5.5 V)
• I/O ports: 51 (N-ch open-drain (5 V withstanding voltage): 4)
• 8-bit resolution A/D converter: 8 channels (AVDD = 1.8 to 5.5 V)
• Serial interface: 3 channels
• µPD780021A, 780022A, 780023A, 780024A: UART mode, 3-wire serial I/O mode (2 channels)
• µPD780021AY, 780022AY, 780023AY, 780024AY: UART mode, 3-wire serial I/O mode, I2C bus mode
• Timer: 5 channels
• Power supply voltage: VDD = 1.8 to 5.5 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U14042EJ4V0DS00 (4th edition)
Date Published December 2002 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
©
2000
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
APPLICATIONS
Telephones, household electrical appliances, pagers, AV equipment, car audios, office automation equipment, etc.
ORDERING INFORMATION (1/2)
(1) µPD780024A Subseries
Part Number
Package
µPD780021ACW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780021AGC-×××-AB8
64-pin plastic QFP (14 x 14)
µPD780021AGC-×××-8BS
64-pin plastic LQFP (14 x 14)
µPD780021AGK-×××-9ET
64-pin plastic TQFP (12 x 12)
µPD780021AGB-×××-8EU
64-pin plastic LQFP (10 x 10)
µPD780021AF1-×××-CN3
73-pin plastic FBGA (9 x 9)
µPD780022ACW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780022AGC-×××-AB8
64-pin plastic QFP (14 x 14)
µPD780022AGC-×××-8BS
64-pin plastic LQFP (14 x 14)
µPD780022AGK-×××-9ET
64-pin plastic TQFP (12 x 12)
µPD780022AGB-×××-8EU
64-pin plastic LQFP (10 x 10)
µPD780022AF1-×××-CN3
73-pin plastic FBGA (9 x 9)
µPD780023ACW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780023AGC-×××-AB8
64-pin plastic QFP (14 x 14)
µPD780023AGC-×××-8BS
64-pin plastic LQFP (14 x 14)
µPD780023AGK-×××-9ET
64-pin plastic TQFP (12 x 12)
µPD780023AGB-×××-8EU
64-pin plastic LQFP (10 x 10)
µPD780023AF1-×××-CN3
73-pin plastic FBGA (9 x 9)
µPD780024ACW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780024AGC-×××-AB8
64-pin plastic QFP (14 x 14)
µPD780024AGC-×××-8BS
64-pin plastic LQFP (14 x 14)
µPD780024AGK-×××-9ET
64-pin plastic TQFP (12 x 12)
µPD780024AGB-×××-8EU
64-pin plastic LQFP (10 x 10)
µPD780024AF1-×××-CN3
73-pin plastic FBGA (9 x 9)
Remark ××× indicates ROM code suffix.
2
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
ORDERING INFORMATION (2/2)
(2) µPD780024AY Subseries
Part Number
Package
µPD780021AYCW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780021AYGC-×××-AB8
64-pin plastic QFP (14 x 14)
µPD780021AYGC-×××-8BS
64-pin plastic LQFP (14 x 14)
µPD780021AYGK-×××-9ET
64-pin plastic TQFP (12 x 12)
µPD780021AYGB-×××-8EU
64-pin plastic LQFP (10 x 10)
µPD780021AYF1-×××-CN3
73-pin plastic FBGA (9 x 9)
µPD780022AYCW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780022AYGC-×××-AB8
64-pin plastic QFP (14 x 14)
µPD780022AYGC-×××-8BS
64-pin plastic LQFP (14 x 14)
µPD780022AYGK-×××-9ET
64-pin plastic TQFP (12 x 12)
µPD780022AYGB-×××-8EU
64-pin plastic LQFP (10 x 10)
µPD780022AYF1-×××-CN3
73-pin plastic FBGA (9 x 9)
µPD780023AYCW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780023AYGC-×××-AB8
64-pin plastic QFP (14 x 14)
µPD780023AYGC-×××-8BS
64-pin plastic LQFP (14 x 14)
µPD780023AYGK-×××-9ET
64-pin plastic TQFP (12 x 12)
µPD780023AYGB-×××-8EU
64-pin plastic LQFP (10 x 10)
µPD780023AYF1-×××-CN3
73-pin plastic FBGA (9 x 9)
µPD780024AYCW-×××
64-pin plastic SDIP (19.05 mm (750))
µPD780024AYGC-×××-AB8
64-pin plastic QFP (14 x 14)
µPD780024AYGC-×××-8BS
64-pin plastic LQFP (14 x 14)
µPD780024AYGK-×××-9ET
64-pin plastic TQFP (12 x 12)
µPD780024AYGB-×××-8EU
64-pin plastic LQFP (10 x 10)
µPD780024AYF1-×××-CN3
73-pin plastic FBGA (9 x 9)
Remark ××× indicates ROM code suffix.
Data Sheet U14042EJ4V0DS
3
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
EXPANDED-SPECIFICATION PRODUCTS AND CONVENTIONAL PRODUCTS
The expanded-specification product and conventional product refer to the following products.
Expanded-specification product: µPD780021A, 780022A, 780023A, 780024A for which orders were
received after December 1, 2001.
(Products with a rankNote other than K, E, P, X)
Conventional product:
Products other than the above expanded specification products.
(Products with rankNote K, E, P, X)
µPD780021AY, 780022AY, 780023AY, 780024AY
Note
The rank is indicated by the 5th digit from the left in the lot number marked on the package.
Lot number
Year
code
Week
code
NEC Electronics
control code
Rank
Expanded-specification products and conventional products differ in the power supply voltage range and
operating frequency ratings.
Power Supply Voltage (VDD)
Guaranteed Operating Speed (Operating Frequency)
Conventional Products
Expanded-Specification Products
4.5 to 5.5 V
8.38 MHz (0.238 µs)
12 MHz (0.166 µs)
4.0 to 5.5 V
8.38 MHz (0.238 µs)
8.38 MHz (0.238 µs)
3.0 to 5.5 V
5 MHz (0.4 µs)
8.38 MHz (0.238 µs)
2.7 to 5.5 V
5 MHz (0.4 µs)
5 MHz (0.4 µs)
1.8 to 5.5 V
1.25 MHz (1.6 µs)
1.25 MHz (1.6 µs)
Remark The parenthesized values indicates the minimum instruction execution time.
CORRESPONDENCE BETWEEN MASK ROM PRODUCTS AND FLASH MEMORY PRODUCTS
Mask ROM Products
Flash Memory Products
Expanded-specification products of µPD780021A,
µPD78F0034B
780022A, 780023A, 780024A
Conventional products of µPD780021A, 780022A,
µPD78F0034A
780023A, 780024A
µPD780021AY, 780022AY, 780023AY, 780024AY
Remark
µPD78F0034AY, 78F0034BY
The µPD78F0034A and 78F0034B differ in the operating frequency ratings and communication
mode of flash memory programming. The µPD78F0034AY and 78F0034BY only differ in
the communication mode of flash memory programming. Refer to the data sheet of the
products.
4
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
EMI-noise reduced version of the µPD78078
µ PD78075B
µ PD78078
µ PD78070A
µPD78078Y
µ PD78054 with timer and enhanced external interface
µ PD78070AY
80-pin
µ PD780058
µ PD780018AY
µ PD780058Y
ROMless version of the µ PD78078
µ PD78078Y with enhanced serial I/O and limited function
80-pin
µ PD78058F
µPD78054
µPD780065
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
64-pin
µ PD780078
64-pin
64-pin
52-pin
µ PD780034A
µ PD780024A
µ PD780034AS
52-pin
64-pin
µ PD780024AS
µPD78014H
64-pin
42/44-pin
µPD78018F
µ PD78083
64-pin
µPD780988
µ PD78058FY
µ PD78054 with enhanced serial I/O
EMI-noise reduced version of the µ PD78054
µ PD78018F with UART and D/A converter, and enhanced I/O
µ PD780024A with expanded RAM
µ PD780034A with timer and enhanced serial I/O
µ PD780078Y
µ PD780034AY µ PD780024A with enhanced A/D converter
µ PD780024AY µ PD78018F with enhanced serial I/O
52-pin version of the µ PD780034A
µ PD78054Y
52-pin version of the µ PD780024A
EMI-noise reduced version of the µ PD78018F
µ PD78018FY
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
On-chip inverter control circuit and UART. EMI-noise reduced.
VFD drive
78K/0
Series
100-pin
µ PD780208
µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53
80-pin
For panel control. On-chip VFD C/D. Display output total: 53
80-pin
µ PD780232
µPD78044H
80-pin
µPD78044F
Basic subseries for driving VFD. Display output total: 34
µ PD78044F with N-ch open-drain I/O. Display output total: 34
LCD drive
100-pin
µ PD780354
µPD780354Y
µ PD780344 with enhanced A/D converter
100-pin
120-pin
µ PD780344
µ PD780338
µ PD780328
µ PD780344Y
µ PD780308 with enhanced display function and timer.
µ PD780308 with enhanced display function and timer.
µ PD780308 with enhanced display function and timer.
µ PD780308 with enhanced display function and timer.
µPD780308Y
µ PD78064 with enhanced SIO, and expanded ROM and RAM
EMI-noise reduced version of the µ PD78064
µ PD78064Y
Basic subseries for driving LCDs, on-chip UART
120-pin
120-pin
100-pin
100-pin
100-pin
µPD780318
µ PD780308
µPD78064B
µPD78064
Segment signal output: 40 pins max.
Segment signal output: 40 pins max.
Segment signal output: 32 pins max.
Segment signal output: 24 pins max.
Bus interface supported
100-pin
80-pin
µ PD780948
µ PD78098B
µ PD78054 with IEBusTM controller
µ PD780702Y
µPD780703Y
µ PD780833Y
80-pin
80-pin
80-pin
64-pin
On-chip CAN controller
µPD780816
On-chip IEBus controller
On-chip CAN controller
On-chip controller compliant with J1850 (Class 2)
Specialized for CAN controller function
Meter control
100-pin
µPD780958
80-pin
µPD780852
µPD780828B
80-pin
For industrial meter control
On-chip automobile meter controller/driver
For automobile meter driver. On-chip CAN controller
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are same.
Data Sheet U14042EJ4V0DS
5
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
The major functional differences among the subseries are listed below.
• Non-Y subseries
Function
Subseries Name
Control
ROM
Timer
8-Bit 10-Bit 8-Bit
Capacity
(Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A
µPD78075B 32 K to 40 K 4 ch
µPD78078
µPD78070A
1 ch
1 ch
1 ch
8 ch
–
Serial Interface
2 ch 3 ch (UART: 1 ch)
I/O
VDD External
MIN.
Value Expansion
88
1.8 V
61
2.7 V
48 K to 60 K
–
µPD780058 24 K to 60 K 2 ch
3 ch (time-division UART: 1 ch)
68
1.8 V
µPD78058F 48 K to 60 K
3 ch (UART: 1 ch)
69
2.7 V
µPD78054
√
16 K to 60 K
2.0 V
µPD780065 40 K to 48 K
–
µPD780078 48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
–
8 ch
µPD780024A
8 ch
–
µPD780034AS
–
4 ch
µPD780024AS
4 ch
–
µPD78014H
8 ch
4 ch (UART: 1 ch)
60
2.7 V
3 ch (UART: 2 ch)
52
1.8 V
3 ch (UART: 1 ch)
51
39
–
2 ch
53
√
1 ch (UART: 1 ch)
33
–
µPD78018F 8 K to 60 K
µPD78083
8 K to 16 K
–
Inverter
control
µPD780988 16 K to 60 K 3 ch Note
VFD
drive
µPD780208 32 K to 60 K 2 ch
–
–
1 ch
–
8 ch
–
3 ch (UART: 2 ch)
47
4.0 V
√
1 ch
1 ch
1 ch
8 ch
–
–
2 ch
74
2.7 V
–
µPD780232 16 K to 24 K 3 ch
–
–
4 ch
40
4.5 V
µPD78044H 32 K to 48 K 2 ch
1 ch
1 ch
8 ch
68
2.7 V
3 ch (UART: 1 ch)
66
1.8 V
10 ch 1 ch 2 ch (UART: 1 ch)
54
1 ch
µPD78044F 16 K to 40 K
LCD
drive
2 ch
µPD780354 24 K to 32 K 4 ch
1 ch
1 ch
1 ch
µPD780344
µPD780338 48 K to 60 K 3 ch
2 ch
–
8 ch
8 ch
–
–
–
µPD780328
62
µPD780318
70
µPD780308 48 K to 60 K 2 ch
1 ch
8 ch
–
–
µPD78064B 32 K
µPD78064
57
2.0 V
79
4.0 V
√
69
2.7 V
–
2 ch (UART: 1 ch)
16 K to 32 K
Bus
µPD780948 60 K
interface
µPD78098B 40 K to 60 K
1 ch
supported µPD780816 32 K to 60 K
2 ch
2 ch
2 ch
1 ch
1 ch
8 ch
–
–
3 ch (UART: 1 ch)
2 ch
12 ch
–
2 ch (UART: 1 ch)
46
4.0 V
Meter
control
µPD780958 48 K to 60 K 4 ch
2 ch
–
1 ch
–
–
–
2 ch (UART: 1 ch)
69
2.2 V
–
Dashboard
control
µPD780852 32 K to 40 K 3 ch
1 ch
1 ch
1 ch
5 ch
–
–
3 ch (UART: 1 ch)
56
4.0 V
–
µPD780828B 32 K to 60 K
59
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
6
3 ch (time-division UART: 1 ch)
–
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
• Y subseries
Function
Subseries Name
Control
ROM
Capacity
(Bytes)
Timer
8-Bit 16-Bit Watch WDT A/D
µPD78078Y 48 K to 60 K 4 ch
µPD78070AY
1 ch
D/A
VDD External
MIN.
Value Expansion
2 ch 3 ch (UART: 1 ch, I2C: 1 ch) 88
1.8 V
61
2.7 V
8-Bit 10-Bit 8-Bit
1 ch
1 ch
8 ch
A/D
–
Serial Interface
–
µPD780018AY 48 K to 60 K
–
µPD780058Y 24 K to 60 K 2 ch
2
3 ch (I C: 1 ch)
2 ch 3 ch (time-division UART: 1 ch, I C: 1 ch)
2
3 ch (UART: 1 ch, I C: 1 ch)
68
1.8 V
69
2.7 V
µPD78054Y 16 K to 60 K
2.0 V
µPD780078Y 48 K to 60 K
2 ch
µPD780034AY 8 K to 32 K
–
8 ch
–
1 ch
1 ch
µPD780344Y
1 ch
–
8 ch
8 ch
–
–
µPD780308Y 48 K to 60 K 2 ch
µPD78064Y 16 K to 32 K
Bus
µPD780701Y 60 K
interface
µPD780703Y
supported
µPD780833Y
Remark
52
1.8 V
–
µPD78018FY 8 K to 60 K
1 ch
4 ch (UART: 2 ch, I C: 1 ch)
3 ch (UART: 1 ch, I C: 1 ch) 51
8 ch
µPD780354Y 24 K to 32 K 4 ch
2
2
µPD780024AY
LCD
drive
√
88
2
µPD78058FY 48 K to 60 K
I/O
2 ch (I2C: 1 ch)
53
4 ch (UART: 1 ch,
I2C: 1 ch)
66
1.8 V
3 ch (time-division UART: 1 ch, I2C: 1 ch)
57
2.0 V
67
3.5 V
65
4.5 V
–
2
2 ch (UART: 1 ch, I C: 1 ch)
3 ch
2 ch
1 ch
1 ch 16 ch
–
–
4 ch (UART: 1 ch, I2C: 1 ch)
–
The functions of non-Y subseries and Y subseries products are the same, except for the serial interface.
Data Sheet U14042EJ4V0DS
7
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
OVERVIEW OF FUNCTIONS (1/2)
µPD780021A
µPD780021AY
Part Number
Item
Internal
ROM
8 KB
memory
High-speed RAM
512 bytes
µPD780022A
µPD780022AY
16 KB
µPD780023A
µPD780023AY
24 KB
64 KB
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution
On-chip minimum instruction execution time cycle variable function
When main system • Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A:
clock selected
0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs (@12 MHz, VDD = 4.5 to 5.5 V operation)
• µPD780021AY, 780022AY, 780023AY, 780024AY and conventional products of µPD780021A,
780022A, 780023A, 780024A:
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@8.38 MHz, VDD = 4.0 to 5.5 V operation)
When subsystem
clock selected
Instruction set
122 µs (@ 32.768 kHz operation)
• 16-bit operation
• Multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc.
I/O ports
Total:
51
• CMOS input:
8
• CMOS I/O:
39
• N-ch open-drain I/O (5 V withstanding voltage): 4
A/D converter
• 8-bit resolution × 8 channels
• Low-voltage operation available: AVDD = 1.8 to 5.5 V
8
32 KB
1024 bytes
Memory space
time
µPD780024A
µPD780024AY
Serial interface
• µPD780021A, 780022A, 780023A, 780024A
UART mode:
1 channel
3-wire serial I/O mode: 2 channels
• µPD780021AY, 780022AY, 780023AY, 780024AY
UART mode:
1 channel
3-wire serial I/O mode:
1 channel
I2C bus mode (multimaster supporting): 1 channel
Timers
•
•
•
•
Timer outputs
3 (8-bit PWM output capable: 2)
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
1
2
1
1
channel
channels
channel
channel
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
OVERVIEW OF FUNCTIONS (2/2)
µPD780021A
µPD780021AY
Part Number
Item
µPD780022A
µPD780022AY
µPD780023A
µPD780023AY
µPD780024A
µPD780024AY
Clock output
• Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A:
93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz, 1.25 MHz, 3 MHz, 6 MHz, 12 MHz
(@12MHz operation with main system clock)
32.768 kHz (@ 32.768 kHz operation with subsystem clock)
• µPD780021AY, 780022AY, 780023AY, 780024AY and conventional products of µPD780021A,
780022A, 780023A, 780024A:
65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system clock)
32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output
• Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A:
1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz (@ 12 MHz operation with main system clock)
• µPD780021AY, 780022AY, 780023AY, 780024AY and conventional products of µPD780021A,
780022A, 780023A, 780024A:
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock)
Vectored
Maskable
Internal: 13, external: 5
interrupt
Non-maskable
Internal: 1
Software
1
sources
Power supply voltage
VDD = 1.8 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
• 64-pin plastic SDIP (19.05 mm (750))
• 64-pin plastic QFP (14 x 14)
• 64-pin plastic LQFP (14 x 14)
• 64-pin plastic TQFP (12 x 12)
• 64-pin plastic LQFP (10 x 10)
• 73-pin plastic FBGA (9 x 9)
Data Sheet U14042EJ4V0DS
9
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................. 11
2. BLOCK DIAGRAM .............................................................................................................................15
3. PIN FUNCTIONS ................................................................................................................................16
3.1
Port Pins .................................................................................................................................................... 16
3.2
Non-Port Pins ............................................................................................................................................ 17
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 19
4. MEMORY SPACE ...............................................................................................................................21
5. PERIPHERAL HARDWARE FUNCTION FEATURES...................................................................... 22
5.1
Ports ........................................................................................................................................................... 22
5.2
Clock Generator ........................................................................................................................................ 23
5.3
Timer/Counter ........................................................................................................................................... 24
5.4
Clock Output/Buzzer Output Controller ................................................................................................ 28
5.5
A/D Converter ........................................................................................................................................... 29
5.6
Serial Interface .......................................................................................................................................... 30
6. INTERRUPT FUNCTIONS .................................................................................................................33
7. EXTERNAL DEVICE EXPANSION FUNCTION ...............................................................................36
8. STANDBY FUNCTION .......................................................................................................................36
9. RESET FUNCTION ............................................................................................................................36
10. MASK OPTION ...................................................................................................................................36
11. INSTRUCTION SET ...........................................................................................................................37
12. ELECTRICAL SPECIFICATIONS ......................................................................................................39
12.1 Expanded-Specification Products of µPD780021A, 780022A, 780023A, 780024A .......................... 39
12.2 µPD780021AY, 780022AY, 780023AY, 780024AY, and Conventional Products of µPD780021A, 780022A,
780023A, 780024A .................................................................................................................................... 55
12.3 Timing Chart .............................................................................................................................................. 71
13. PACKAGE DRAWINGS .....................................................................................................................77
14. RECOMMENDED SOLDERING CONDITIONS ................................................................................83
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................87
APPENDIX B. RELATED DOCUMENTS ...............................................................................................91
10
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
1. PIN CONFIGURATION (TOP VIEW)
• 64-pin plastic SDIP (19.05 mm (750))
P40/AD0
1
64
P67/ASTB
P41/AD1
2
63
P66/WAIT
P42/AD2
3
62
P65/WR
P43/AD3
4
61
P64/RD
P44/AD4
5
60
P75/BUZ
P45/AD5
6
59
P74/PCL
P46/AD6
7
58
P73/TI51/TO51
P47/AD7
8
57
P72/TI50/TO50
P50/A8
9
56
P71/TI01
P51/A9
10
55
P70/TI00/TO0
P52/A10
11
54
P03/INTP3/ADTRG
P53/A11
12
53
P02/INTP2
P54/A12
13
52
P01/INTP1
P55/A13
14
51
P00/INTP0
P56/A14
15
50
VSS1
P57/A15
16
49
X1
VSS0
17
48
X2
VDD0
18
47
IC
P30
19
46
XT1
P31
P32/SDA0Note 1
20
21
45
44
XT2
RESET
P33/SCL0Note 1
22
43
AVDD
P34/SI31Note 2
23
42
AVREF
P35/SO31Note 2
24
41
P10/ANI0
P36/SCK31Note 2
25
40
P11/ANI1
P20/SI30
26
39
P12/ANI2
P21/SO30
27
38
P13/ANI3
P22/SCK30
28
37
P14/ANI4
P23/RxD0
29
36
P15/ANI5
P24/TxD0
30
35
P16/ANI6
P25/ASCK0
31
34
P17/ANI7
VDD1
32
33
AVSS
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When the µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY
are used in applications where the noise generated inside the microcontroller needs to be reduced, the
implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually
and connecting VSS0 and VSS1 to different ground lines, is recommended.
Data Sheet U14042EJ4V0DS
11
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
• 64-pin plastic QFP (14 x 14)
• 64-pin plastic LQFP (14 x 14)
• 64-pin plastic TQFP (12 x 12)
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
• 64-Pin plastic LQFP (10 x 10)
P50/A8
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P51/A9
2
47
P70/TI00/TO0
P52/A10
3
46
P03/INTP3/ADTRG
P53/A11
4
45
P02/INTP2
P54/A12
5
44
P01/INTP1
P55/A13
6
43
P00/INTP0
P56/A14
7
42
VSS1
P57/A15
8
41
X1
VSS0
9
40
X2
VDD0
10
39
IC
P30
11
38
XT1
P31
12
37
XT2
P32/SDA0Note 1
13
36
RESET
P33/SCL0Note 1
14
35
AVDD
P34/SI31Note 2
15
34
AVREF
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AVSS
VDD1
P25/ASCK0
P24/TxD0
P23/RxD0
P22/SCK30
P21/SO30
P20/SI30
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P36/SCK31Note 2
P35/SO31
Note 2
P71/TI01
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
Cautions 1. Connect the IC (Internally Connected) pin directory to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When the µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY
are used in applications where the noise generated inside the microcontroller needs to be reduced, the
implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually
and connecting VSS0 and VSS1 to different ground lines, is recommended.
12
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
• 73-pin plastic FBGA (9 x 9)
Top View
Bottom View
9
8
7
6
5
4
3
2
1
A B C D E F G H J
J H G F E D C B A
Index mark
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
A1
NC
C1
P52/A10
E1
P57/A15
G1
P33/SCL0Note 1
J1
NC
A2
P46/AD6
C2
P53/A11
E2
VDD0
G2
P32/SDA0Note 1
J2
P36/SCK31Note 2
A3
P44/AD4
C3
P45/AD5
E3
P54/A12
G3
P20/SI30
J3
NC
A4
P41/AD1
C4
P42/AD2
E4
−
G4
P21/SO30
J4
P25/ASCK0
A5
P67/ASTB
C5
P64/RD
E5
−
G5
P24/TxD0
J5
NC
A6
P65/WR
C6
P73/TI51/TO51
E6
−
G6
VDD1
J6
P17/ANI7
A7
P74/PCL
C7
P03/INTP3/ADTRG
E7
P00/INTP0
G7
P16/ANI6
J7
P12/ANI2
A8
NC
C8
P01/INTP1
E8
XT1
G8
AVDD
J8
P13/ANI3
A9
NC
C9
VSS1
E9
X2
G9
NC
J9
NC
B1
P51/A9
D1
P55/A13
F1
P30
H1
P34/SI31Note 2
B2
P47/AD7
D2
P56/A14
F2
P31
H2
P35/SO31Note 2
B3
P43/AD3
D3
P50/A8
F3
VSS0
H3
P23/RxD0
B4
P40/AD0
D4
NC
F4
−
H4
P22/SCK30
B5
P66/WAIT
D5
−
F5
−
H5
AVSS
B6
P75/BUZ
D6
−
F6
−
H6
P15/ANI5
B7
P72/TI50/TO51
D7
P02/INTP2
F7
P14/ANI4
H7
P11/ANI1
B8
P71/TI01
D8
IC
F8
RESET
H8
P10/ANI0
B9
P70/TI00/TO0
D9
X1
F9
XT2
H9
AVREF
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
Cautions 1. Connect the IC (Internally Connected) pin directory to VSS0 or VSS1.
2. Connect the AVSS pin to VSS0.
Remark When the µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, and 780024AY
are used in applications where the noise generated inside the microcontroller needs to be reduced, the
implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually
and connecting VSS0 and VSS1 to different ground lines, is recommended.
Data Sheet U14042EJ4V0DS
13
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
A8 to A15:
Address bus
P64 to P67:
Port 6
AD0 to AD7:
Address/data bus
P70 to P75:
Port 7
ADTRG:
AD trigger input
PCL:
Programmable clock
ANI0 to ANI7:
Analog input
RD:
Read strobe
ASCK0:
Asynchronous serial clock
RESET:
Reset
ASTB:
Address strobe
RxD0:
Receive data
AVDD:
Analog power supply
SCK30, SCK31, SCL0: Serial clock
AVREF:
Analog reference voltage
SDA0:
Serial data
AVSS:
Analog ground
SI30, SI31:
Serial input
BUZ:
Buzzer clock
SO30, SO31:
Serial output
IC:
Internally connected
TI00, TI01, TI50, TI51: Timer input
INTP0 to INTP3:
External interrupt input
TO0, TO50, TO51:
Timer output
NC:
No connection
TxD0:
Transmit data
P00 to P03:
Port 0
VDD0, V DD1:
Power supply
P10 to P17:
Port 1
VSS0, VSS1:
Ground
P20 to P25:
Port 2
WAIT:
Wait
P30 to P36:
Port 3
WR:
Write strobe
P40 to P47:
Port 4
X1, X2:
Crystal (main system clock)
P50 to P57:
Port 5
XT1, XT2:
Crystal (subsystem clock)
14
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
2. BLOCK DIAGRAM
TI00/TO0/P70
16-bit timer/
event counter
Port 0
P00 to P03
TI50/TO50/P72
8-bit timer/
event counter 50
Port 1
P10 to P17
TI51/TO51/P73
8-bit timer/
event counter 51
Port 2
P20 to P25
Watchdog timer
Port 3
P30 to P36
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P64 to P67
Port 7
P70 to P75
TI01/P71
Watch timer
SI30/P20
SO30/P21
SCK30/P22
Serial
interface 30
SI31/P34
SO31/P35
SCK31/P36
Serial
interface 31Note 1
RxD0/P23
TxD0/P24
ASCK0/P25
SDA0/P32
SCL0/P33
ANI0/P10 to
ANI7/P17
AVDD
AVSS
AVREF
INTP0/P00 to
INTP3/P03
78K/0
CPU core
ROM
RAM
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
UART0
External
access
I2C busNote 2
RD/P64
WR/P65
WAIT/P66
ASTB/P67
A/D converter
System
control
Interrupt
control
BUZ/P75
Buzzer output
PCL/P74
Clock output
control
VDD0 VDD1 VSS0 VSS1
RESET
X1
X2
XT1
XT2
IC
Notes 1. Incorporated only in the µPD780024A Subseries.
2. Incorporated only in the µPD780024AY Subseries.
Remark The internal ROM and RAM capacities vary depending on the product.
Data Sheet U14042EJ4V0DS
15
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
I/O
P00 to P02
I/O
Function
After
Alternate
Reset
Function
Port 0
Input
4-bit I/O port
INTP2
Input/output can be specified in 1-bit units.
P03
INTP3/ADTRG
An on-chip pull-up resistor can be used by setting software.
P10 to P17
Input
INTP0 to
Port 1
Input
ANI0 to ANI7
Input
SI30
8-bit input only port
P20
I/O
Port 2
6-bit I/O port
P21
SO30
Input/output can be specified in 1-bit units.
P22
SCK30
An on-chip pull-up resistor can be used by setting software.
P23
RxD0
P24
TxD0
P25
ASCK0
P30
I/O
P31
P32
Port 3
N-ch open-drain I/O port
7-bit I/O port
An on-chip pull-up resistor can be
Input/output can be specified in
specified by the mask option.
1-bit units.
LEDs can be driven directly.
Input
—
SDA0Note 1
SCL0Note 1
P33
P34
An on-chip pull-up resistor can be
SI31Note 2
P35
used by setting software.
SO31Note 2
SCK31Note 2
P36
P40 to P47
I/O
Port 4
Input
AD0 to AD7
Input
A8 to A15
Input
RD
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
The interrupt request flag (KRIF) is set to 1 by falling edge detection.
P50 to P57
I/O
Port 5
8-bit I/O port
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
P64
P65
P66
I/O
Port 6
4-bit I/O port
WR
Input/output can be specified in 1-bit units.
WAIT
An on-chip pull-up resistor can be used by setting software.
P67
ASTB
Notes 1. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
16
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.1 Port Pins (2/2)
Pin Name
P70
I/O
I/O
Function
After
Alternate
Reset
Function
Port 7
Input
6-bit I/O port
P71
TI01
Input/output can be specified in 1-bit units.
P72
TI00/TO0
TI50/TO50
An on-chip pull-up resistor can be used by setting software.
P73
TI51/TO51
P74
PCL
P75
BUZ
3.2 Non-Port Pins (1/2)
Pin Name
INTP0
I/O
Input
INTP2
Function
After
Alternate
Reset
Function
External interrupt request input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified
Input
INTP2
P02
INTP3
SI30
P03/ADTRG
Input
Serial interface serial data input
Input
SI31Note 1
SO30
P00
P01
P20
P34
Output
Serial interface serial data output
Input
SO31Note 1
P21
P35
SDA0Note 2
I/O
Serial Interface serial data input/output
Input
SCK30
I/O
Serial interface serial clock input/output
Input
P32
P22
SCK31Note 1
P36
SCL0Note 2
P33
RxD0
Input
Serial data input for asynchronous serial interface
Input
P23
TxD0
Output
Serial data output for asynchronous serial interface
Input
P24
ASCK0
Input
Serial clock input for asynchronous serial interface
Input
P25
TI00
Input
External count clock input to 16-bit timer/event counter 0
Input
P70/TO0
Capture trigger input to capture register 01 (CR01) of 16-bit timer/event counter 0
TI01
Capture trigger input to capture register 00 (CR00) of 16-bit timer/event counter 0
P71
TI50
External count clock input to 8-bit timer/event counter 50
P72/TO50
TI51
External count clock input to 8-bit timer/event counter 51
P73/TO51
TO0
16-bit timer/event counter 0 output
Input
P70/TI00
TO50
Output
8-bit timer/event counter 50 output (also used for 8-bit PWM output)
Input
P72/TI50
TO51
8-bit timer/event counter 51 output (also used for 8-bit PWM output)
P73/TI51
PCL
Output
Clock output (for trimming of main system clock and subsystem clock)
Input
P74
BUZ
Output
Buzzer output
Input
P75
Lower address/data bus for expanding memory externally
Input
P40 to P47
AD0 to AD7
I/O
A8 to A15
Output
Higher address bus for expanding memory externally
Input
P50 to P57
RD
Output
Strobe signal output for reading from external memory
Input
P64
WR
Strobe signal output for writing to external memory
WAIT
Input
ASTB
Output
P65
Wait insertion at external memory access
Input
P66
Strobe output that externally latches address information output to
ports 4 and 5 to access external memory
Input
P67
Notes 1. SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
2. SDA0 and SCL0 are incorporated only in the µPD780024AY Subseries.
Data Sheet U14042EJ4V0DS
17
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.2 Non-Port Pins (2/2)
Pin Name
I/O
Function
After
Alternate
Reset
Function
ANI0 to ANI7
Input
A/D converter analog input
Input
P10 to P17
ADTRG
Input
A/D converter trigger signal input
Input
P03/INTP3
AVREF
Input
A/D converter reference voltage input
—
—
AVDD
—
A/D converter analog power supply. Set potential to that of VDD0 or VDD1
—
—
AVSS
—
A/D converter ground potential. Set potential to that of VSS0 or VSS1
—
—
RESET
Input
System reset input
—
—
X1
Input
Connecting crystal resonator for main system clock oscillation
—
—
X2
—
—
—
XT1
Input
—
—
XT2
—
—
—
VDD0
—
Positive power supply for ports
—
—
VSS0
—
Ground potential of ports
—
—
VDD1
—
Positive power supply (except ports)
—
—
VSS1
—
Ground potential (except ports)
—
—
IC
—
Internally connected. Connect directly to VSS0 or VSS1.
—
—
—
Not internally connected. Leave open.
—
—
NC
Note
Note
18
Connecting crystal resonator for subsystem clock oscillation
NC pins are incorporated only in the 73-pin plastic FBGA.
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the I/O circuit configuration of each type, see Figure 3-1.
Table 3-1. Types of Pin I/O Circuits
Pin Name
I/O
Circuit Type
I/O
Recommended Connection of Unused Pins
P00/INTP0 to P02/INTP2
8-C
I/O
Input: Independently connect to VSS0 or VSS1 via a resistor.
P10/ANI0 to P17/ANI7
25
Input
Connect directly to VDD0, VDD1, VSS0, or VSS1 via a resistor.
P20/S130
8-C
I/O
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via
P21/SO30
5-H
a resistor.
P22/SCK30
8-C
Output: Leave open.
P03/INTP3/ADTRG
Output: Leave open.
P23/RxD0
P24/TxD0
5-H
P25/ASCK0
8-C
P30, P31
13-Q
Input: Connect directly to VSS0 or VSS1.
P32, P33
(µPD780024A Subseries only)
13-S
Output: Leave open at low-level output.
P32/SDA0
(µPD780024AY Subseries only)
13-R
P33/SCL0
(µPD780024AY Subseries only)
P34/SI31Note
8-C
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via
P35/SO31Note
5-H
a resistor.
P36/SCK31Note
8-C
Output: Leave open.
P40/AD0 to P47/AD7
5-H
Input: Independently connect to VDD0 or VDD1 via a resistor.
Output: Leave open.
P50/A8 to P57/A15
Input: Independently connect to VDD0, VDD1, VSS0, or VSS1 via
P64/RD
a resistor.
P65/WR
Output: Leave open.
P66/WAIT
P67/ASTB
P70/TI00/TO0
8-C
P71/TI01
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
5-H
P75/BUZ
RESET
2
XT1
16
XT2
AVDD
AVREF
Input
Connect directly to VDD0 or VDD1.
—
—
—
Leave open.
Connect to directly VDD0 or VDD1.
Connect to directly VSS0 or VSS1.
AVSS
IC
Note
SI31, SO31, and SCK31 are incorporated only in the µPD780024A Subseries.
Data Sheet U14042EJ4V0DS
19
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 3-1. Pin I/O Circuits
TYPE 2
TYPE 13-R
IN/OUT
Data
Output disable
N-ch
IN
VSS0
Schmitt-triggered input with hysteresis characteristics
TYPE 5-H
Pull-up
enable
TYPE 13-S
VDD0



Mask 
option 
VDD0
IN/OUT
P-ch
Data
Output disable
VDD0
Data
N-ch
P-ch
VSS0
IN/OUT
Output
disable
N-ch
VSS0
Input
enable
TYPE 16
TYPE 8-C
VDD0
Feedback
cut-off
Pull-up
enable
P-ch
P-ch
VDD0
Data
P-ch
IN/OUT
Output
disable
N-ch
VSS0
TYPE 13-Q
XT1
TYPE 25
VDD0



XT2
Mask 
option 
P-ch
IN/OUT
Data
Output disable
Comparator
N-ch
–
N-ch
VSS0
VREF (threshold voltage)
VSS0
Input
enable
Input
enable
20
+
Data Sheet U14042EJ4V0DS
IN
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
4. MEMORY SPACE
Figure 4-1 shows the memory map of the µ PD780021A, 780022A, 780023A, 780024A, 780021AY,
780022AY, 780023AY, and 780024AY.
Figure 4-1. Memory Map
FFFFH
Special function registers (SFR)
256 × 8 bits
FF00H
FEFFH
FEE0H
FEDFH
General-purpose
registers
32 × 8 bits
Internal high-speed
RAMNote
mmmmH
mmmmH – 1
nnnnH
Data memory
space
Reserved
Program area
1000H
0FFFH
CALLF entry area
F800H
F7FFH
0800H
07FFH
Program area
External memory
0080H
007FH
Program memory
space
nnnnH + 1
nnnnH
CALLT table area
0040H
003FH
Note
Internal ROM
Vector table area
0000H
0000H
Note
The internal ROM and internal high-speed RAM capacities vary depending on the product (see the following
table).
Part Number
Last Address of Internal ROM
nnnnH
Start Address of Internal High-Speed RAM
mmmmH
µPD780021A, 780021AY
1FFFH
FD00H
µPD780022A, 780022AY
3FFFH
µPD780023A, 780023AY
5FFFH
µPD780024A, 780024AY
7FFFH
Data Sheet U14042EJ4V0DS
FB00H
21
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following 3 types of I/O ports are available.
• CMOS input (port 1):
8
• CMOS I/O (ports 0, 2, 4 to 7, P34 to P36):
39
• N-channel open-drain I/O (P30 to P33):
4
Total:
51
Table 5-1. Port Functions
Name
Pin Name
Function
Port 0
P00 to P03
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
Port 1
P10 to P17
Input-only port.
Port 2
P20 to P25
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
Port 3
P30 to P33
N-channel open-drain I/O port. Input/output can be specified in 1-bit units.
A pull-up resistor can be specified by mask option.
LEDs can be driven directly.
P34 to P36
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
P40 to P47
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
Port 4
The interrupt request flag (KRIF) is set to 1 by falling edge detection.
Port 5
P50 to P57
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
LEDs can be driven directly.
Port 6
P64 to P67
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
Port 7
P70 to P75
I/O port. Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be used by setting software.
22
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.2 Clock Generator
A system clock generator is incorporated.
The minimum instruction execution time can be changed.
• Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A
0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs
(@12 MHz, VDD = 4.5 to 5.5 V operation with main system clock)
122 µs (@32.768 kHz, VDD = 4.0 to 5.5 V operation with subsystem clock)
• µPD780021AY, 780022AY, 780023AY, 780024AY, and conventional products of µPD780021A, 780022A,
780023A, 780024A
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@8.38 MHz, VDD = 4.0 to 5.5 V operation with main system clock)
122 µs (@32.768 kHz, VDD = 4.0 to 5.5 V operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1
XT2
Subsystem
clock
oscillator
fXT
Watch timer, clock
output function
Prescaler
1
X1
X2
Main system
clock
oscillator
STOP
Prescaler
fX
fX
2
fX
22
fX
23
2
fXT
2
Clock to peripheral
hardware
fX
24
Selector
Standby
controller
Wait
controller
CPU clock
(fCPU)
HALT
Data Sheet U14042EJ4V0DS
23
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.3 Timer/Counter
Five timer/counter channels are incorporated.
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter:
2 channels
• Watch timer:
1 channel
• Watchdog timer:
1 channel
Table 5-2. Operations of Timer/Event Counter
16-Bit Timer/
Event Counter 0
8-Bit Timer/
Event Counters 50, 51
Watch Timer
Watchdog Timer
Interval timer
1 channel
2 channels
1 channelNote 1
1 channelNote 2
External event counter
1 channel
2 channels
—
—
Timer outputs
1
2
—
—
PPG outputs
1
—
—
—
PWM output
—
2
—
—
2 inputs
—
—
—
Square wave outputs
1
2
—
—
Interrupt sources
2
2
2
1
Operation mode
Function
Pulse width measurement
Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer has watchdog timer and interval timer functions. However, use the watchdog timer
by selecting either the watchdog timer function or the interval timer function.
24
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-2. Block Diagram of 16-Bit Timer/Event Counter 0
TI01/P71
Selector
Noise
eliminator
Selector
Internal bus
16-bit capture/compare
register 00 (CR00)
INTTM00
fX
fX/22
fX/26
TI00/TO0/P70Note
16-bit timer counter 0
(TM0)
Clear
Output
controller
TO0/TI00/P70Note
Match
Noise
eliminator
Noise
eliminator
16-bit capture/compare
register 01 (CR01)
Selector
fX/23
Selector
Match
INTTM01
Internal bus
Note
TI00 input and TO0 output cannot be used at the same time.
Data Sheet U14042EJ4V0DS
25
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-3. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
Selector
INTTM50
Note 1
S
Q
INV
8-bit timer
OVF
counter 50 (TM50)
R
Clear
Selector
Match
Selector
TI50/TO50/P72
fX
fX/22
fX/24
fX/26
fX/28
fX/210
Mask circuit
8-bit compare
register 50 (CR50)
TO50/TI50/P72
Note 2
S
3
Level
inversion
R
Selector
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
Timer mode control
register 50 (TMC50)
TCL502 TCL501 TCL500
Timer clock selection
register 50 (TCL50)
Internal bus
Figure 5-4. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
8-bit timer
counter 51
(TM51)
Selector
Note 1
S
Q
INV
OVF
R
Clear
Note 2
S
3
R
Selector
TCL512 TCL511 TCL510
Timer clock selection
register 51 (TCL51)
Level
inversion
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
Timer mode control
register 51 (TMC51)
Internal bus
Notes 1. Timer output F/F
2. PWM output F/F
26
INTTM51
Selector
Match
Selector
TI51/TO51/P73
fX/2
fX/23
fX/25
fX/27
fX/29
fX/211
Mask circuit
8-bit compare
register 51
(CR51)
Data Sheet U14042EJ4V0DS
TO51/TI51/P73
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 5-5. Watch Timer Block Diagram
Clear
Selector
fX/2
7
fW
24
fW
25
fW
26
fW
27
fW
28
fW
29
INTWT
Clear
Selector
fXT
5-bit counter
9-bit prescaler
fW
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Watch timer mode
control register (WTM)
Internal bus
Figure 5-6. Watchdog Timer Block Diagram
fX
fX/28
Clock
input
controller
Divider
Divided
clock
selector
Output
controller
INTWDT
RESET
RUN
Division mode
selector
3
WDT mode signal
OSTS2 OSTS1 OSTS0
Oscillation
stabilization time
selection register
(OSTS)
WDCS2 WDCS1 WDCS0
Watchdog timer
clock selection
register (WDCS)
RUN WDTM4 WDTM3
Watchdog timer
mode register
(WDTM)
Internal bus
Data Sheet U14042EJ4V0DS
27
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.4 Clock Output/Buzzer Output Controller
A clock output/buzzer output controller is incorporated.
Clocks with the following frequencies can be output as clock output.
• Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A
• 93.75 kHz/187.5 kHz/375 kHz/750 kHz/1.25 MHz/3 MHz/6 MHz/12 MHz (@12 MHz operation with main
system clock)
• 32.768 kHz (@32.768 kHz operation with subsystem clock)
• µPD780021AY, 780022AY, 780023AY, 780024AY, and conventional products of µPD780021A,
780022A, 780023A, 780024A
• 65.5 kHz/131 kHz/262 kHz/524 kHz/1.05 MHz/2.10 MHz/4.19 MHz/8.38 MHz (@8.38 MHz operation with
main system clock)
• 32.768 kHz (@32.768 kHz operation with subsystem clock)
Clocks with the following frequencies can be output as buzzer output.
• Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A
1.46 kHz/2.93 kHz/5.86 kHz/11.7 kHz (@12 MHz operation with main system clock)
• µPD780021AY, 780022AY, 780023AY, 780024AY, and conventional products of µPD780021A,
780022A, 780023A, 780024A
1.02 kHz/2.05 kHz/4.10 kHz/8.19 kHz (@8.38 MHz operation with subsystem clock)
Figure 5-7. Block Diagram of Clock Output/Buzzer Output Control Circuit
Prescaler
8
Selector
fX
4 fX/210 to fX/213
BZOE
BUZ/P75
BCS0, BCS1
Selector
fX to fX/27
fXT
Clock
controller
CLOE
BZOE
BCS1
BCS0
CLOE
CCS3
CCS2
CCS1
CCS0
Clock output selection register (CKS)
Internal bus
28
Data Sheet U14042EJ4V0DS
PCL/P74
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.5 A/D Converter
An A/D converter consisting of eight 8-bit resolution channels is incorporated.
The following two A/D conversion operation startup methods are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series resistor string
AVDD
Sample & hold circuit
ANI0/P10
AVREF
ANI1/P11
Voltage comparator
ANI2/P12
Tap
selector
ANI3/P13
ANI4/P14
Selector
ANI5/P15
ANI6/P16
Successive approximation
register (SAR)
ANI7/P17
INTP3/ADTRG/P03
Edge
detector
Edge
detector
AVSS
INTAD
Controller
A/D conversion
result register (ADCR0)
INTP3
Internal bus
Data Sheet U14042EJ4V0DS
29
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
5.6 Serial Interface
Three serial interface channels are incorporated.
• µPD780024A Subseries
Serial interface UART0:
1 channel
Serial interface SIO30, SIO31:
2 channels
• µPD780024AY Subseries
Serial interface UART0:
1 channel
Serial interface SIO30:
1 channel
Serial interface IIC0
1 channel
(1) Serial interface UART0
Serial interface UART0 has two modes: asynchronous serial interface (UART) mode and infrared data transfer
mode.
• Asynchronous serial interface (UART) mode
This mode enables full-duplex operation wherein one byte of data starting from the start bit is transmitted
and received.
The on-chip UART-dedicated baud-rate generator enables communication using a wide range of selectable
baud rates. In addition, a baud rate can also be defined by dividing the clock input to the ASCK0 pin.
The UART-dedicated baud-rate generator can also be used to generate a MIDI-standard baud rate (31.25
kbps).
• Infrared data transfer mode
This mode enables pulse output and pulse reception in data format.
This mode can be used for office equipment applications such as personal computers.
Figure 5-9. Block Diagram of Serial Interface UART0
Internal bus
Asynchronous serial
interface mode
register 0 (ASIM0)
Receive
RXB0 buffer
register 0
RxD0/P23
RX0 Receive
shift
register 0
TXE0 RXE0 PS01 PS00 CL0
SL0 ISRM0 IRDAM0
Asynchronous serial
interface status
register 0
(ASIS0)
TXS0 Transmit
shift
PE0 FE0 OVE0
register 0
TxD0/P24
Receive
controller
(parity
check)
Transmit
INTSER0 controller
INTSR0
(parity
addition)
INTST0
Baud rate
generator
30
Data Sheet U14042EJ4V0DS
P25/ASCK0
fX/2 to fX/27
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Serial interface SIO3n
Serial interface SIO3n has one mode: 3-wire serial I/O mode.
• 3-wire serial I/O mode (fixed as MSB first)
This is an 8-bit data transfer mode using three lines: a serial clock line (SCK3n), serial output line (SO3n),
and serial input line (SI3n).
Since simultaneous transmit and receive operations are enabled in the 3-wire serial I/O mode, the
processing time for data transfer is reduced.
The first bit in 8-bit data in the serial transfer is fixed as MSB.
The 3-wire serial I/O mode is useful for connection to peripheral I/O devices, and display controllers, etc.,
that include a clocked serial interface.
Figure 5-10. Block Diagram of Serial Interface SIO3n
Internal bus
8
Serial I/O shift register
3n (SIO3n)
SI3n
SO3n
Serial clock
counter
SCK3n
Serial clock
controller
Interrupt request
signal generator
Selector
INTCSI3n
fX/23
fX/24
fX/25
Remark µPD780024A Subseries: n = 0, 1
µPD780024AY Subseries: n = 0
Data Sheet U14042EJ4V0DS
31
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(3) Serial interface IIC0 (µPD780024AY Subseries only)
Serial interface IIC0 has one mode: I2C (Inter IC) bus mode (supporting multimaster).
• I2C bus mode (supporting multimaster)
This is an 8-bit data transfer mode using two lines: a serial clock line (SCL0) and a serial data bus line
(SDA0).
This mode complies with the I2C bus format, and can output a “start condition”, “data”, and a “stop condition”
during transmission via the serial data bus. This data is automatically detected by hardware during
reception.
Since SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the serial
data bus line are required.
Figure 5-11. Block Diagram of Serial Interface IIC0
Internal bus
IIC status register 0
(IICS0)
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
IIC control register 0
(IICC0)
Slave address
register 0 (SVA0)
SDA0/P32
Noise eliminator
IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0
Match
signal
IIC shift register 0
(IIC0)
SPT0
CLEAR
SET
SO0 latch
D
CL00
Acknowledge
detector
Data hold
time corrector
N-ch opendrain output
Wake-up controller
Acknowledge
detector
Start condition
detector
Stop condition
detector
SCL0/P33
Noise eliminator
Interrupt request
signal generator
Serial clock counter
Serial clock wait
controller
Serial clock controller
N-ch open-drain
output
fX
Prescaler
CLD0 DAD0 SMC0 DFC0 CL00
IIC transfer clock select
register 0 (IICCL0)
Internal bus
32
Data Sheet U14042EJ4V0DS
INTIIC0
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
6. INTERRUPT FUNCTIONS
A total of 20 interrupt sources are provided, divided into the following three types.
• Non-maskable: 1
• Maskable:
18
• Software:
1
Table 6-1. Interrupt Source List
Interrupt Source
Default
Type
PriorityNote 1
Name
Nonmaskable
—
INTWDT
Watchdog timer overflow
(with watchdog timer mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow
(with interval timer mode selected)
1
INTP0
Pin input edge detection
2
INTP1
0008H
3
INTP2
000AH
4
INTP3
000CH
5
INTSER0
Serial interface UART0 reception error
generation
6
INTSR0
End of serial interface UART0 reception
0010H
7
INTST0
End of serial interface UART0 transmission
0012H
8
INTCSI30
End of serial interface SIO30 transfer
0014H
9
INTCSI31
End of serial interface SIO31 transfer
0016H
Trigger
Internal/
Vector
Table
Address
Interrupt
External
Internal
0004H
Basic
Configuration
TypeNote 2
(A)
(B)
External
Internal
0006H
000EH
(C)
(B)
[Only for µPD780024A Subseries]
10
INTIIC0
End of serial interface IIC0 transfer
[Only for µPD780024AY Subseries]
0018H
11
INTWTI
Reference time interval signal from watch timer
001AH
12
INTTM00
Match between TM0 and CR00
(when CR00 is specified as compare register)
Detection of TI01 valid edge
001CH
(when CR00 is specified as capture register)
Software
13
INTTM01
Match between TM0 and CR01
(when CR01 is specified as compare register)
Detection of TI00 valid edge
(when CR01 is specified as capture register)
001EH
14
INTTM50
Match between TM50 and CR50
0020H
15
INTTM51
Match between TM51 and CR51
0022H
16
INTAD0
End of A/D conversion
0024H
17
INTWT
Watch timer overflow
0026H
18
INTKR
Port 4 falling edge detection
—
BRK
BRK instruction execution
External
0028H
(D)
—
003EH
(E)
Notes 1. The default priority is the priority when several maskable interrupt requests are generated at the same
time. 0 is the highest, and 18 is the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1.
Remark The watchdog timer interrupt (INTWDT) can be selected from a non-maskable interrupt or a maskable
interrupt (internal).
Data Sheet U14042EJ4V0DS
33
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 6-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Vector table
address
generator
Priority
controller
Interrupt
request
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
Interrupt
request
IE
PR
ISP
Vector table
address
generator
Priority
controller
IF
Standby release
signal
(C) External maskable interrupt (INTP0 to INTP3)
Internal bus
External interrupt
edge enable register
(EGP, EGN)
Interrupt
request
Edge
detector
MK
IE
IF
PR
Priority
controller
ISP
Vector table
address
generator
Standby release
signal
34
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Figure 6-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (INTKR)
Internal bus
MK
Interrupt
request
Falling edge
detector
PR
IE
Priority
controller
IF
ISP
Vector table
address
generator
Standby release
signal
(E) Software interrupt
Internal bus
Interrupt
request
IF:
Vector table
address
generator
Interrupt request flag
IE:
Interrupt enable flag
ISP:
In-service priority flag
MK:
Interrupt mask flag
PR:
Priority specification flag
Data Sheet U14042EJ4V0DS
35
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
7. EXTERNAL DEVICE EXPANSION FUNCTION
The external device expansion function is for connecting external devices to areas other than the internal ROM,
RAM, and SFR areas. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
The following two standby modes are available for further reduction of system power consumption.
• HALT mode: In this mode, the CPU operation clock is stopped. The average power consumption can be
reduced by intermittent operation by combining this mode with the normal operation mode.
• STOP mode: In this mode, oscillation of the main system clock is stopped. All the operations performed on
the main system clock are suspended, and only the subsystem clock is used, resulting in
extremely small power consumption. This can be used only when the main system clock is
operating (the subsystem clock oscillation cannot be stopped).
Figure 8-1. Standby Function
CSS = 1
Main system clock
operation
Interrupt
request
CSS = 0
HALT
instruction
STOP
instruction
HALT
instruction
Interrupt
request
STOP mode
Main system clock
operation is stopped
Note
Subsystem clock
operationNote
Interrupt
request
HALT mode
HALT modeNote
Clock supply for CPU is stopped,
oscillation is maintained
Clock supply for CPU is stopped,
oscillation is maintained
The power consumption can be reduced by stopping the main system clock. When the CPU is operating
on the subsystem clock, set bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction
cannot be used.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back to
the main system clock.
9. RESET FUNCTION
The following two reset methods are available.
• External reset by RESET signal input
• Internal reset by watchdog timer program loop time detection
10. MASK OPTION
Table 10-1 Pin Mask Option Selection
Subseries Name
Pins
Mask Option
µPD780024A Subseries
P30 to P33
µPD780024AY Subseries
P30 and P31
An on-chip pull-up resistor can be specified in 1-bit units.
The mask option can be used to specify the connection of an on-chip pull-up resistor to P30 to P33Note, in 1-bit units.
Note
36
The µPD780024AY Subseries has P30 and P31 only.
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
11. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd
Operand
1st
Operand
A
[HL + byte]
#byte
r
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B]
$addr16
1
None
[HL + C]
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
ADD
SUBC
ADDC
ADDC
ADDC
AND
SUB
SUB
SUB
SUB
SUB
MOV
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
RORC
ADDC
ADDC
ROLC
SUBC
OR
SUBC
SUBC
SUBC
SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
r
A
Note
INC
DEC
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
B, C
sfr
MOV
MOV
saddr
MOV
ADD
MOV
DBNZ
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
MOV
MOV
PSW
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note
Except r = A
Data Sheet U14042EJ4V0DS
37
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
#word
1st Operand
rpNote
AX
MOVW
ADDW
SUBW
CMPW
AX
MOVW
MOVWNote
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
Note
MOVW
saddrp
!addr16
MOVW
MOVW
SP
None
MOVW
XCHW
rp
SP
sfrp
INCW, DECW
PUSH, POP
MOVW
MOVW
MOVW
Only when rp = BC, DE or HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
A.bit
1st Operand
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
None
A.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
sfr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
saddr.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
PSW.bit
MOV1
BT
BF
BTCLR
SET1
CLR1
[HL].bit
MOV1
BT
BF
BTCLR
SET1
CLR1
CY
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
MOV1
AND1
SET1
CLR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
OR1
XOR1
NOT1
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
1st Operand
Basic instruction
AX
BR
!addr16
CALL
BR
!addr11
CALLF
[addr5]
CALLT
$addr16
BR, BC, BNC
BZ, BNZ
BT, BF
BTCLR
DBNZ
Compound
instruction
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
38
$addr16
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
12. ELECTRICAL SPECIFICATIONS
12.1 Expanded-Specification Products of µ PD780021A, 780022A, 780023A, 780024A
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Input voltage
Symbol
Conditions
Ratings
Unit
–0.3 to +6.5
V
AVDD
–0.3 to VDD + 0.3Note
V
AVREF
–0.3 to VDD + 0.3Note
V
AVSS
–0.3 to +0.3
V
VDD
VI1
P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2,
–0.3 to VDD +
0.3Note
V
RESET
VI2
P30 to P33
N-ch open-drain Without pull-up resistor
With pull-up resistor
Output voltage
VO
V
–0.3 to VDD + 0.3Note
V
0.3Note
V
–0.3 to VDD +
Analog input voltage
VAN
P10 to P17
Output current,
high
IOH
Output current,
low
–0.3 to + 6.5
AVSS – 0.3 to AVREF0 +
and –0.3 to VDD + 0.3Note
V
Per pin
–10
mA
Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75
–15
mA
Total for P20 to P25, P30 to P36
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to
20
mA
Per pin for P30 to P33, P50 to P57
30
mA
Total for P00 to P03, P40 to P47,
50
mA
Total for P20 to P25
20
mA
Total for P30 to P36
100
mA
Total for P50 to P57
100
mA
TA
–40 to +85
°C
Tstg
–65 to +150
°C
IOL
Analog input pin
0.3Note
P36, P40 to P47, P64 to P67, P70 to P75
P64 to P67, P70 to P75
Operating ambient
temperature
Storage
temperature
Note
6.5 V or below
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
39
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input
Symbol
CIN
MIN.
TYP.
f = 1 MHz
capacitance
I/O
capacitance
Conditions
Unit
15
pF
15
pF
20
pF
Unmeasured pins returned to 0 V.
f = 1 MHz
Unmeasured pins
returned to 0 V.
CIO
P00
P34
P50
P70
to
to
to
to
P03, P20 to P25,
P36, P40 to P47,
P57, P64 to P67,
P75
P30 to P33
Remark
MAX.
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended
Circuit
Ceramic
resonator
Parameter
Oscillation
IC
X2
C2
X1
C1
frequency (fX)
Note 1
Oscillation
stabilization
Conditions
MIN.
TYP.
Unit
MHz
4.5 V ≤ VDD ≤ 5.5 V
1.0
12.0
3.0 V ≤ VDD < 4.5 V
1.0
8.38
1.8 V ≤ VDD < 3.0 V
1.0
5.0
After VDD reaches
timeNote 2
MAX.
4
ms
MHz
oscillation voltage range
MIN.
Crystal
IC
X2
X1
resonator
C2
X2
4.5 V ≤ VDD ≤ 5.5 V
1.0
12.0
frequency (fX)Note 1
3.0 V ≤ VDD < 4.5 V
1.0
8.38
1.8 V ≤ VDD < 3.0 V
1.0
5.0
C1
External
clock
Oscillation
X1
Oscillation
4.0 V ≤ VDD ≤ 5.5 V
10
stabilization timeNote 2
1.8 V ≤ VDD < 4.0 V
30
X1 input
4.5 V ≤ VDD ≤ 5.5 V
1.0
12.0
frequency (fX)Note 1
3.0 V ≤ VDD < 4.5 V
1.0
8.38
1.8 V ≤ VDD < 3.0 V
1.0
5.0
4.5 V ≤ VDD ≤ 5.5 V
38
500
high-/low-level width
3.0 V ≤ VDD < 4.5 V
50
500
(tXH, tXL)
1.8 V ≤ VDD < 3.0 V
85
500
X1 input
ms
MHz
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
40
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
resonator
Recommended Circuit
XT2
C4
External
clock
XT1 IC
R
XT2
C3
XT1
Parameter
Conditions
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
10
XT1 input
frequency (fXT)Note 1
32
38.5
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
12
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14042EJ4V0DS
41
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Recommended Oscillator Constant
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Manufacturer
Part Number
Frequency
Recommended Circuit Constant
Oscillation Voltage Range
(MHz)
C1 (pF)
C2 (pF)
R1 (kΩ)
MIN. (V)
MAX. (V)
Murata Mfg.
CSBFB1M00J58
1.00
100
100
2.2
1.8
5.5
Co., Ltd.
CSBLA1M00J58
1.00
100
100
2.2
1.8
5.5
CSTCC2M00G56
2.00
On-chip
On-chip
0
1.8
5.5
CSTLS2M00G56
2.00
On-chip
On-chip
0
1.8
5.5
CSTCC3M58G53
3.58
On-chip
On-chip
0
1.8
5.5
CSTLS3M58G53
3.58
On-chip
On-chip
0
1.8
5.5
CSTCR4M00G53
4.00
On-chip
On-chip
0
1.8
5.5
TDK
CSTLS4M00G53
4.00
On-chip
On-chip
0
1.8
5.5
CSTCR4M19G53
4.19
On-chip
On-chip
0
1.8
5.5
CSTLS4M19G53
4.19
On-chip
On-chip
0
1.8
5.5
CSTCR4M91G53
4.91
On-chip
On-chip
0
1.8
5.5
CSTLS4M91G53
4.91
On-chip
On-chip
0
1.8
5.5
CSTCR5M00G53
5.00
On-chip
On-chip
0
1.8
5.5
CSTLS5M00G53
5.00
On-chip
On-chip
0
1.8
5.5
CSTCE8M00G52
8.00
On-chip
On-chip
0
3.0
5.5
CSTLS8M00G53
8.00
On-chip
On-chip
0
3.0
5.5
CSTCE8M38G52
8.38
On-chip
On-chip
0
3.0
5.5
CSTLS8M38G53
8.38
On-chip
On-chip
0
3.0
5.5
CSTCE10M0G52
10.00
On-chip
On-chip
0
4.5
5.5
CSTLS10M0G53
10.00
On-chip
On-chip
0
4.5
5.5
CSTCE12M0G52
12.00
On-chip
On-chip
0
4.5
5.5
CSTLA12M0T55
12.00
On-chip
On-chip
0
4.5
5.5
CCR3.58MC3
3.58
On-chip
On-chip
0
1.8
5.5
CCR4.19MC3
4.19
On-chip
On-chip
0
1.8
5.5
CCR5.0MC3
5.00
On-chip
On-chip
0
1.8
5.5
CCR8.0MC5
8.00
On-chip
On-chip
0
2.0
5.5
CCR8.38MC5
8.38
On-chip
On-chip
0
2.0
5.5
Caution The oscillator constant is a reference value based on evaluation in specific environments by the
resonator manufacturer. If the oscillator characteristics need to be optimized in the actual
application, request the resonator manufacturer for evaluation on the implementation circuit.
Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of
the oscillator. Use the internal operation conditions of the µPD780024A Subseries within the
specifications of the DC and AC characteristics.
42
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Output current,
Symbol
MIN.
TYP.
MAX.
Unit
mA
IOH
Per pin
–1
All pins
–15
mA
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36,
10
mA
Per pin for P30 to P33, P50 to P57
15
mA
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
20
mA
Total for P20 to P25
10
mA
Total for P30 to P36
70
mA
high
Output current,
Conditions
low
P40 to P47, P64 to P67, P70 to P75
Total for P50 to P57
Input voltage,
70
mA
P10 to P17, P21, P24, P35,
2.7 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
V
P40 to P47, P50 to P57,
1.8 V ≤ VDD < 2.7 V
0.8VDD
VDD
V
P00 to P03, P20, P22, P23, P25,
2.7 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
0.85VDD
VDD
V
P30 to P33
2.7 V ≤ VDD ≤ 5.5 V
0.7VDD
5.5
V
(N-ch open-drain)
1.8 V ≤ VDD < 2.7 V
0.8VDD
5.5
V
VIH4
X1, X2
2.7 V ≤ VDD ≤ 5.5 V
VDD – 0.5
VDD
V
1.8 V ≤ VDD < 2.7 V
VDD – 0.2
VDD
V
VIH5
XT1, XT2
4.0 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
1.8 V ≤ VDD < 4.0 V
0.9VDD
VDD
V
P10 to P17, P21, P24, P35,
2.7 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
P40 to P47, P50 to P57,
1.8 V ≤ VDD < 2.7 V
0
0.2VDD
V
VIH1
high
P64 to P67, P74, P75
VIH2
VIH3
Input voltage,
VIL1
low
P64 to P67, P74, P75
VIL2
VIL3
VIL4
VIL5
Output voltage,
VOH1
high
Output voltage,
VOL1
low
P00 to P03, P20, P22, P23, P25,
2.7 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
0
0.15VDD
V
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.0 V
0
0.2VDD
V
1.8 V ≤ VDD < 2.7 V
0
0.1VDD
V
2.7 V ≤ VDD ≤ 5.5 V
0
0.4
V
1.8 V ≤ VDD < 2.7 V
0
0.2
V
4.0 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
1.8 V ≤ VDD < 4.0 V
0
0.1VDD
V
4.0 V ≤ VDD ≤ 5.5 V, IOH = –1 mA
VDD – 1.0
VDD
V
1.8 V ≤ VDD < 4.0 V, IOH = –100 µA
VDD – 0.5
VDD
V
X1, X2
XT1, XT2
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V,
P50 to P57
IOL = 15 mA
P00 to P03, P20 to P25, P34 to P36, 4.0 V ≤ VDD ≤ 5.5 V,
P40 to P47, P64 to P67, P70 to P75
VOL2
Remark
0.4
2.0
V
2.0
V
0.4
V
0.5
V
IOL = 1.6 mA
IOL = 400 µA
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
43
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
ILIH1
Conditions
VIN = VDD
TYP.
MAX.
Unit
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P60 to P67, P70 to P75,
RESET
3
µA
X1, X2, XT1, XT2
20
µA
ILIH3
VIN = 5.5 V
P30 to P33Note
3
µA
ILIL1
VIN = 0 V
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
µA
X1, X2, XT1, XT2
–20
µA
ILIH2
Input leakage
MIN.
current, low
ILIL2
–3
µA
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
current, low
ILOL
VOUT = 0 V
–3
µA
Mask option
pull-up resistance
R1
VIN = 0 V,
P30, P31, P32, P33
15
30
90
kΩ
Software pullup resistance
R2
VIN = 0 V,
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
15
30
90
kΩ
ILIL3
P30 to P33
Note
Note When pull-up resistors are not connected to P30 to P33 (specified by the mask option).
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
44
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
Power supply
currentNote 1
IDD1Note 2
±10%Note 3
12.0 MHz
VDD = 5.0 V
crystal oscillation
operating mode
MIN.
When A/D converter is
stopped
When A/D converter is
operatingNote 7
MAX.
Unit
8.5
17
mA
9.5
19
mA
8.38 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
When A/D converter is
stopped
5.5
11
mA
operating mode
When A/D converter is
operatingNote 7
6.5
13
mA
3
6
mA
When A/D converter is
operatingNote 7
4
8
mA
5.00 MHz
VDD = 3.0 V ±10%Note 3
crystal oscillation
When A/D converter is
stopped
2
4
mA
operating mode
When A/D converter is
operatingNote 7
3
6
mA
When A/D converter is
stopped
0.4
1.5
mA
When A/D converter is
operatingNote 7
1.4
4.2
mA
2
4
mA
10
mA
2.2
mA
4.7
mA
1
mA
4
mA
0.7
mA
1.7
mA
0.4
mA
1.1
mA
VDD = 3.0 V + 10%Notes 3, 6 When A/D converter is
stopped
VDD = 2.0 V ±10%Note 4
IDD2
TYP.
12.0 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
When peripheral functions
are stopped
HALT mode
When peripheral functions
are operating
8.38 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
When peripheral functions
are stopped
HALT mode
When peripheral functions
are operating
VDD = 3.0 V + 10%Notes 3, 6 When peripheral functions
are stopped
1.1
0.5
When peripheral functions
are operating
5.00 MHz
VDD = 3.0 V ±10%Note 3
crystal oscillation
When peripheral functions
are stopped
HALT mode
When peripheral functions
are operating
VDD = 2.0 V ±10%Note 4
When peripheral functions
are stopped
0.35
0.15
When peripheral functions
are operating
IDD3
IDD4
32.768 kHz crystal oscillation
VDD = 5.0 V ±10%
40
80
µA
operating modeNote 5
VDD = 3.0 V ±10%
20
40
µA
VDD = 2.0 V ±10%
10
20
µA
32.768 kHz crystal oscillation
VDD = 5.0 V ±10%
30
60
µA
Note 5
VDD = 3.0 V ±10%
6
18
µA
VDD = 2.0 V ±10%
2
10
µA
VDD = 5.0 V ±10%
0.1
30
µA
VDD = 3.0 V ±10%
0.05
10
µA
VDD = 2.0 V ±10%
0.05
10
µA
HALT mode
IDD5
XT1 = VDD STOP mode
When feedback resistor is not used
Data Sheet U14042EJ4V0DS
45
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors
of ports).
2. IDD1 includes the peripheral operation current.
3. When the processor clock control register (PCC) is set to 00H.
4. When PCC is set to 02H.
5. When main system clock operation is stopped.
6. The values show the specifications when VDD = 3.0 to 3.3 V. The value in the TYP. column show the
specifications when VDD = 3.0 V.
7. Includes the current through the AVDD pin.
46
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Cycle time
TCY
(Min. instruction
Conditions
MIN.
TYP.
MAX.
Unit
Operating with
4.5 V ≤ VDD ≤ 5.5 V
0.166
16
µs
main system clock
3.0 V ≤ VDD ≤ 4.5 V
0.238
16
µs
2.7 V ≤ VDD ≤ 3.0 V
0.4
16
µs
1.8 V ≤ VDD ≤ 2.7 V
1.6
16
µs
125
µs
execution time)
Operating with subsystem clock
103.9Note 1
122
µs
3.0 V ≤ VDD ≤ 5.5 V
2/fsam+0.1Note 2
high-/low-level
2.7 V ≤ VDD < 3.0 V
2/fsam+0.2Note 2
µs
width
1.8 V ≤ VDD < 2.7 V
2/fsam+0.5Note 2
µs
2.7 V ≤ VDD ≤ 5.5 V
0
4
MHz
1.8 V ≤ VDD < 2.7 V
0
275
kHz
2.7 V ≤ VDD ≤ 5.5 V
100
ns
1.8 V ≤ VDD < 2.7 V
1.8
ns
TI00, TI01 input
TI50, TI51 input
tTIH0, tTIL0
fTI5
frequency
TI50, TI51 input
tTIH5, tTIL5
high-/low-level
width
Interrupt request
tINTH, tINTL
input high-/lowlevel width
RESET
tRSL
low-level width
INTP0 to INTP3,
2.7 V ≤ VDD ≤ 5.5 V
1
µs
P40 to P47
1.8 V ≤ VDD < 2.7 V
2
µs
2.7 V ≤ VDD ≤ 5.5 V
10
µs
1.8 V ≤ VDD < 2.7 V
20
µs
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode
register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes
fsam = fX/8.
Data Sheet U14042EJ4V0DS
47
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
TCY vs. VDD (main system clock operation)
16.0
Cycle time TCY [ µ S]
10.0
5.0
Operation
guaranteed
range
2.0
1.6
1.0
0.4
0.238
0.166
0.1
0
1.0
2.0
1.8
3.0
2.7
4.0
4.5
Supply voltage VDD [V]
48
Data Sheet U14042EJ4V0DS
5.0 5.5 6.0
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Parameter
Symbol
(1/3)
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6
ns
Data input time from address
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
100
ns
Address output time from RD↓
tRDAD
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 87
ns
tRDD2
(3 + 2n)tCY – 93
ns
0
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
tWRWT
tCY – 25
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 15
ns
Delay time from ASTB↓ to RD↓
tASTRD
6
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 15
ns
Delay time from
tRDAST
0.8tCY – 15
1.2tCY
ns
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
10
60
ns
Address hold time from WR↑
tWRADH
0.8tCY – 15
1.2tCY + 30
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.8tCY
2.5tCY + 25
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.8tCY
2.5tCY + 25
ns
RD↑ to ASTB↑ at external fetch
Address hold time from
RD↑ at external fetch
Caution
TCY can only be used when the MIN. value is 0.238 µs.
Remarks
1.
ns
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and
ASTB pins.)
Data Sheet U14042EJ4V0DS
49
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)
(2/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
30
ns
Address hold time
tADH
10
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 108
ns
tADD2
(3 + 2n)tCY – 120
ns
200
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 148
ns
tRDD2
(3 + 2n)tCY – 162
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 40
ns
tRDL2
(2.5 + 2n)tCY – 40
ns
Input time from RD↓ to WAIT↓
tRDWT1
tCY – 75
ns
tRDWT2
tCY – 60
ns
Input time from WR↓ to WAIT↓
tWRWT
tCY – 50
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
(2 + 2n)tCY
ns
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
10
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 30
ns
Delay time from ASTB↓ to RD↓
tASTRD
10
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 30
ns
Delay time from
tRDAST
0.8tCY – 30
1.2tCY
ns
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
20
120
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 30
1.2tCY + 60
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 50
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 50
ns
RD↑ to ASTB↑ at external fetch
Hold time from
RD↑ to address at external fetch
Caution
Remarks
TCY can only be used when the MIN. value is 0.4 µs.
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,
and ASTB pins.)
50
ns
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
(3/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
120
ns
Address hold time
tADH
20
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 233
ns
tADD2
(3 + 2n)tCY – 240
ns
400
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 325
ns
tRDD2
(3 + 2n)tCY – 332
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 92
ns
tRDL2
(2.5 + 2n)tCY – 92
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 350
ns
tRDWT2
tCY – 132
ns
tWRWT
tCY – 100
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 60
ns
Delay time from ASTB↓ to RD↓
tASTRD
20
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 60
ns
Delay time from
tRDAST
0.8tCY – 60
1.2tCY
ns
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
40
240
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 60
1.2tCY + 120
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 100
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 100
ns
RD↑ to ASTB↑ at external fetch
Hold time from
RD↑ to address at external fetch
ns
Caution
TCY can only be used when the MIN. value is 1.6 µs.
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,
and ASTB pins.)
Data Sheet U14042EJ4V0DS
51
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter
SCK3n
Symbol
tKCY1
cycle time
SCK3n high-/
tKH1, tKL1
low-level width
SI3n setup time
tSIK1
(to SCK3n↑)
SI3n hold time
tKSI1
(from SCK3n↑)
Delay time from
tKSO1
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
666
ns
3.0 V ≤ VDD < 4.5 V
954
ns
2.7 V ≤ VDD < 3.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
3.0 V ≤ VDD ≤ 5.5 V
tKCY1/2 – 50
ns
1.8 V ≤ VDD < 3.0 V
tKCY1/2 – 100
ns
3.0 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 3.0 V
150
ns
1.8 V ≤ VDD < 2.7 V
300
ns
4.5 V ≤ VDD ≤ 5.5 V
300
ns
1.8 V ≤ VDD < 4.5 V
400
ns
C = 100 pF
Note
SCK3n↓ to SO3n
4.5 V ≤ VDD ≤ 5.5 V
200
ns
1.8 V ≤ VDD < 4.5 V
300
ns
MAX.
Unit
output
Note C is the load capacitance of the SCK3n and SO3n output lines.
(b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter
SCK3n
Symbol
tKCY2
cycle time
SCK3n high-/
tKH2, tKL2
low-level width
SI3n setup time
Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
666
ns
3.0 V ≤ VDD < 4.5 V
800
ns
2.7 V ≤ VDD < 3.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
4.5 V ≤ VDD ≤ 5.5 V
333
ns
3.0 V ≤ VDD < 4.5 V
400
ns
2.7 V ≤ VDD < 3.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
100
ns
4.5 V ≤ VDD ≤ 5.5 V
300
ns
1.8 V ≤ VDD < 4.5 V
400
ns
tSIK2
(to SCK3n↑)
SI3n hold time
tKSI2
(from SCK3n↑)
Delay time from
SCK3n↓ to SO3n
tKSO2
C = 100 pF
Note
4.5 V ≤ VDD ≤ 5.5 V
200
ns
1.8 V ≤ VDD < 4.5 V
300
ns
output
Note C is the load capacitance of the SO3n output line.
Remark n = 0, 1
52
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(c) UART mode (dedicated baud-rate generator output)
Parameter
Symbol
Transfer rate
Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
187500
bps
3.0 V ≤ VDD < 4.5 V
131031
bps
2.7 V ≤ VDD < 3.0 V
78125
bps
1.8 V ≤ VDD < 2.7 V
39063
bps
MAX.
Unit
(d) UART mode (external clock input)
Parameter
ASCK0 cycle time
ASCK0 high-/low-level width
Symbol
tKCY3
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
tKH3,
4.0 V ≤ VDD ≤ 5.5 V
400
ns
tKL3
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
39063
bps
2.7 V ≤ VDD < 4.0 V
19531
bps
1.8 V ≤ VDD < 2.7 V
9766
bps
MAX.
Unit
(e) UART mode (infrared data transfer mode)
Parameter
Symbol
Conditions
MIN.
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
131031
bps
Allowable bit rate error
4.0 V ≤ VDD ≤ 5.5 V
±0.87
%
Output pulse width
4.0 V ≤ VDD ≤ 5.5 V
1.2
0.24/fbrNote
µs
Input pulse width
4.0 V ≤ VDD ≤ 5.5 V
4/fX
µs
Note fbr: Specified baud rate
Data Sheet U14042EJ4V0DS
53
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bit
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
Resolution
Overall
errorNote
Conversion time
tCONV
Analog input voltage
VIAN
Reference voltage
AVREF
Resistance between AVREF and AVSS
RREF
4.5 V ≤ AVDD ≤ 5.5 V
12
96
µs
4.0 V ≤ AVDD < 4.5 V
14
96
µs
2.7 V ≤ AVDD < 4.0 V
17
96
µs
1.8 V ≤ AVDD < 2.7 V
28
96
µs
0
AVREF
V
1.8
AVDD
V
When A/D converter not operating
20
40
kΩ
Note Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value.
Remark The impedance of the analog input pins is shown below.
[Equivalent circuit]
R1
R2
ANIn
(n = 0 to 3)
C1
C2
C3
[Parameter value]
(TYP.)
AVDD
R1
R2
C1
C2
C3
2.7 V
12 kΩ
8.0 kΩ
3.0 pF
3.0 pF
2.0 pF
4.5 V
4 kΩ
2.7 kΩ
3.0 pF
1.4 pF
2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention power
supply voltage
VDDDR
Data retention power
supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
tWAIT
time
Conditions
MIN.
TYP.
1.6
Subsystem clock stop (XT1 = VDD) and
feed-back resistor disconnected
0.1
MAX.
Unit
5.5
V
30
µA
µs
0
Release by RESET
217/fx
s
Release by interrupt request
Note
s
Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
54
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
12.2 µPD780021AY, 780022AY, 780023AY, 780024AY, and Conventional Products of µPD780021A, 780022A,
780023A,780024A
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Conditions
VDD
AVDD
AVREF
AVSS
Input voltage
VI1
P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2,
Ratings
Unit
–0.3 to +6.5
V
–0.3 to VDD +
0.3Note
V
–0.3 to VDD +
0.3Note
V
–0.3 to +0.3
V
–0.3 to VDD + 0.3Note
V
–0.3 to + 6.5
V
RESET
VI2
P30 to P33
N-ch open-drain Without pull-up resistor
With pull-up resistor
Output voltage
VO
Analog input voltage
V AN
P10 to P17
Output current,
high
IOH
Output current,
low
–0.3 to VDD +
0.3Note
V
–0.3 to VDD +
0.3Note
V
AVSS – 0.3 to AVREF0 + 0.3Note
and –0.3 to VDD + 0.3Note
V
Per pin
–10
mA
Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75
–15
mA
Total for P20 to P25, P30 to P36
–15
mA
20
mA
Per pin for P30 to P33, P50 to P57
30
mA
Total for P00 to P03, P40 to P47,
50
mA
Total for P20 to P25
20
mA
Total for P30 to P36
100
mA
Total for P50 to P57
100
mA
TA
–40 to +85
°C
Tstg
–65 to +150
°C
IOL
Analog input pin
Per pin for P00 to P03, P20 to P25, P34 to
P36, P40 to P47, P64 to P67, P70 to P75
P64 to P67, P70 to P75
Operating ambient
temperature
Storage
temperature
Note
6.5 V or below
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
55
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input
Symbol
Conditions
capacitance
I/O
capacitance
MIN.
TYP.
f = 1 MHz
CIN
Unit
15
pF
15
pF
20
pF
Unmeasured pins returned to 0 V.
CIO
f = 1 MHz
Unmeasured pins
returned to 0 V.
P00
P34
P50
P70
to
to
to
to
P03, P20 to P25,
P36, P40 to P47,
P57, P64 to P67,
P75
P30 to P33
Remark
MAX.
Unless otherwise specified, the characteristic of alternate-function pins are the same as those of port pins.
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended
Circuit
Ceramic
resonator
Parameter
Oscillation
IC
X2
C2
X1
frequency
(fX)Note 1
Conditions
MIN.
TYP.
MAX.
Unit
MHz
4.0 V ≤ VDD ≤ 5.5 V
1.0
8.38
1.8 V ≤ VDD < 4.0 V
1.0
5.0
Oscillation
After VDD reaches
stabilization timeNote 2
oscillation voltage range
4
ms
MHz
C1
MIN.
Crystal
IC
X2
X1
resonator
C2
C1
External
clock
X2
X1
Oscillation
4.0 V ≤ VDD ≤ 5.5 V
1.0
8.38
frequency (fX)Note 1
1.8 V ≤ VDD < 4.0 V
1.0
5.0
Oscillation
4.0 V ≤ VDD ≤ 5.5 V
10
stabilization timeNote 2
1.8 V ≤ VDD < 4.0 V
30
X1 input
4.0 V ≤ VDD ≤ 5.5 V
1.0
8.38
1.8 V ≤ VDD < 4.0 V
1.0
5.0
X1 input
4.0 V ≤ VDD ≤ 5.5 V
50
500
high-/low-level width
1.8 V ≤ VDD < 4.0 V
85
500
frequency
(fX)Note 1
ms
MHz
ns
(tXH, tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
56
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Crystal
resonator
Recommended Circuit
XT2
R
C4
External
clock
XT1 IC
XT2
C3
XT1
Parameter
Conditions
Oscillation
frequency (fXT)Note 1
Oscillation
stabilization timeNote 2
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
10
XT1 input
frequency (fXT)Note 1
32
38.5
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
12
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14042EJ4V0DS
57
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Recommended Oscillator Constant
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Manufacturer
Part Number
Frequency
Recommended Circuit Constant
Oscillation Voltage Range
(MHz)
C1 (pF)
C2 (pF)
R1 (kΩ)
MIN. (V)
MAX. (V)
100
100
2.2
1.8
5.5
Murata Mfg.
CSBFB1M00J58
1.00
Co., Ltd.
CSBLA1M00J58
1.00
100
100
2.2
1.8
5.5
CSTCC2M00G56
2.00
On-chip
On-chip
0
1.8
5.5
TDK
CSTLS2M00G56
2.00
On-chip
On-chip
0
1.8
5.5
CSTCC3M58G53
3.58
On-chip
On-chip
0
1.8
5.5
CSTLS3M58G53
3.58
On-chip
On-chip
0
1.8
5.5
CSTCR4M00G53
4.00
On-chip
On-chip
0
1.8
5.5
CSTLS4M00G53
4.00
On-chip
On-chip
0
1.8
5.5
CSTCR4M19G53
4.19
On-chip
On-chip
0
1.8
5.5
CSTLS4M19G53
4.19
On-chip
On-chip
0
1.8
5.5
CSTCR4M91G53
4.91
On-chip
On-chip
0
1.8
5.5
CSTLS4M91G53
4.91
On-chip
On-chip
0
1.8
5.5
CSTCR5M00G53
5.00
On-chip
On-chip
0
1.8
5.5
CSTLS5M00G53
5.00
On-chip
On-chip
0
1.8
5.5
CSTCE8M00G52
8.00
On-chip
On-chip
0
3.0
5.5
CSTLS8M00G53
8.00
On-chip
On-chip
0
3.0
5.5
CSTCE8M38G52
8.38
On-chip
On-chip
0
3.0
5.5
CSTLS8M38G53
8.38
On-chip
On-chip
0
3.0
5.5
CSTCE10M0G52
10.00
On-chip
On-chip
0
4.5
5.5
CSTLS10M0G53
10.00
On-chip
On-chip
0
4.5
5.5
CCR3.58MC3
3.58
On-chip
On-chip
0
1.8
5.5
CCR4.19MC3
4.19
On-chip
On-chip
0
1.8
5.5
CCR5.0MC3
5.00
On-chip
On-chip
0
1.8
5.5
CCR8.0MC5
8.00
On-chip
On-chip
0
2.0
5.5
CCR8.38MC5
8.38
On-chip
On-chip
0
2.0
5.5
Caution The oscillator constant is a reference value based on evaluation in specific environments by the
resonator manufacturer. If the oscillator characteristics need to be optimized in the actual
application, request the resonator manufacturer for evaluation on the implementation circuit.
Note that the oscillation voltage and oscillation frequency merely indicate the characteristics of
the oscillator. Use the internal operation conditions of the µPD780024A, 780024AY Subseries
within the specifications of the DC and AC characteristics.
58
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Output current,
Symbol
IOH
high
Output current,
IOL
low
Conditions
MIN.
TYP.
MAX.
Unit
Per pin
–1
mA
All pins
–15
mA
Per pin for P00 to P03, P20 to P25, P34 to P36,
10
mA
Per pin for P30 to P33, P50 to P57
15
mA
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
20
mA
Total for P20 to P25
10
mA
Total for P30 to P36
70
mA
Total for P50 to P57
70
mA
P40 to P47, P64 to P67, P70 to P75
Input voltage,
VIH1
high
P10 to P17, P21, P24, P35,
2.7 V ≤ VDD ≤ 5.5 V
0.7VDD
VDD
V
P40 to P47, P50 to P57,
1.8 V ≤ VDD < 2.7 V
0.8VDD
VDD
V
V
P64 to P67, P74, P75
VIH2
VIH3
VIH4
VIH5
Input voltage,
VIL1
low
2.7 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
0.85VDD
VDD
V
P30 to P33
2.7 V ≤ VDD ≤ 5.5 V
0.7VDD
5.5
V
(N-ch open-drain)
1.8 V ≤ VDD < 2.7 V
0.8VDD
5.5
V
X1, X2
2.7 V ≤ VDD ≤ 5.5 V
VDD – 0.5
VDD
V
1.8 V ≤ VDD < 2.7 V
VDD – 0.2
VDD
V
4.0 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
1.8 V ≤ VDD < 4.0 V
0.9VDD
VDD
V
P10 to P17, P21, P24, P35,
2.7 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
P40 to P47, P50 to P57,
1.8 V ≤ VDD < 2.7 V
0
0.2VDD
V
P00 to P03, P20, P22, P23, P25,
XT1, XT2
P64 to P67, P74, P75
VIL2
VIL3
VIL4
VIL5
Output voltage,
VOH1
P00 to P03, P20, P22, P23, P25,
2.7 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
0
0.15VDD
V
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.0 V
0
0.2VDD
V
1.8 V ≤ VDD < 2.7 V
0
0.1VDD
V
2.7 V ≤ VDD ≤ 5.5 V
0
0.4
V
1.8 V ≤ VDD < 2.7 V
0
0.2
V
4.0 V ≤ VDD ≤ 5.5 V
0
0.2VDD
V
1.8 V ≤ VDD < 4.0 V
0
0.1VDD
V
VDD – 1.0
VDD
V
VDD – 0.5
VDD
V
2.0
V
2.0
V
0.4
V
0.5
V
X1, X2
XT1, XT2
4.0 V ≤ VDD ≤ 5.5 V, IOH = –1 mA
1.8 V ≤ VDD < 4.0 V, IOH = –100 µA
high
Output voltage,
VOL1
low
P30 to P33
4.0 V ≤ VDD ≤ 5.5 V,
P50 to P57
IOL = 15 mA
P00 to P03, P20 to P25, P34 to P36, 4.0 V ≤ VDD ≤ 5.5 V,
P40 to P47, P64 to P67, P70 to P75
VOL2
Remark
0.4
IOL = 1.6 mA
IOL = 400 µA
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
59
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Input leakage
current, high
Symbol
ILIH1
Conditions
VIN = VDD
TYP.
MAX.
Unit
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P60 to P67, P70 to P75,
RESET
3
µA
X1, X2, XT1, XT2
20
µA
ILIH3
VIN = 5.5 V
P30 to P33Note 1
3
µA
ILIL1
VIN = 0 V
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
µA
X1, X2, XT1, XT2
–20
µA
ILIH2
Input leakage
current, low
MIN.
ILIL2
–3
µA
Output leakage
current, high
ILOH
VOUT = VDD
3
µA
Output leakage
current, low
ILOL
VOUT = 0 V
–3
µA
Mask option
pull-up resistance
R1
VIN = 0 V,
P30, P31, P32Note 2, P33Note 2
15
30
90
kΩ
Software pullup resistance
R2
VIN = 0 V,
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
15
30
90
kΩ
ILIL3
P30 to
P33Note 1
Notes 1. µPD780021A, 780022A, 780023A, 780024A: When pull-up resistors are not connected to P30 to P33
(specified by the mask option).
µPD780021AY, 780022AY, 780023AY, 780024AY: When pull-up resistors are not connected to P30
and P31 (specified by the mask option).
2. Only for the µPD780021A, 780022A, 780023A, and 780024A.
Remark
60
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Power supply
currentNote 1
Symbol
Conditions
IDD1Note 2 8.38 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
operating mode
IDD2
TYP.
5.5
MAX.
11
Unit
mA
When A/D converter is
operatingNote 6
6.5
13
mA
5.00 MHz
VDD = 3.0 V ±10%Note 3
crystal oscillation
operating mode
When A/D converter is
stopped
2
4
mA
When A/D converter is
operatingNote 6
3
6
mA
VDD = 2.0 V ±10%Note 4
When A/D converter is
stopped
0.4
1.5
mA
When A/D converter is
operatingNote 6
1.4
4.2
mA
8.38 MHz
VDD = 5.0 V ±10%Note 3
crystal oscillation
HALT mode
When peripheral functions
are stopped
1.1
2.2
mA
4.7
mA
VDD = 3.0 V ±10%Note 3
When peripheral functions
are stopped
0.7
mA
1.7
mA
0.4
mA
1.1
mA
5.00 MHz
crystal oscillation
HALT mode
MIN.
When A/D converter is
stopped
When peripheral functions
are operating
0.35
When peripheral functions
are operating
VDD = 2.0 V ±10%Note 4
When peripheral functions
are stopped
0.15
When peripheral functions
are operating
I DD3
IDD4
IDD5
32.768 kHz crystal oscillation
VDD = 5.0 V ±10%
40
80
µA
operating modeNote 5
VDD = 3.0 V ±10%
20
40
µA
VDD = 2.0 V ±10%
10
20
µA
32.768 kHz crystal oscillation
VDD = 5.0 V ±10%
30
60
µA
HALT modeNote 5
VDD = 3.0 V ±10%
6
18
µA
VDD = 2.0 V ±10%
2
10
µA
VDD = 5.0 V ±10%
0.1
30
µA
VDD = 3.0 V ±10%
0.05
10
µA
VDD = 2.0 V ±10%
0.05
10
µA
XT1 = VDD STOP mode
When feedback resistor is not used
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors
of ports).
2. IDD1 includes the peripheral operation current.
3. When the processor clock control register (PCC) is set to 00H.
4. When PCC is set to 02H.
5. When main system clock operation is stopped.
6. Includes the current through the AVDD pin.
Data Sheet U14042EJ4V0DS
61
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
(Min. instruction
Conditions
Operating with
main system clock
execution time)
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
0.238
MIN.
16
µs
2.7 V ≤ VDD < 4.0 V
0.4
16
µs
1.8 V ≤ VDD < 2.7 V
Operating with subsystem clock
TYP.
1.6
103.9Note 1
122
16
µs
125
µs
4.0 V ≤ VDD ≤ 5.5 V
2/fsam+0.1Note 2
µs
high-/low-level
2.7 V ≤ VDD < 4.0 V
2/fsam+0.2Note 2
µs
width
1.8 V ≤ VDD < 2.7 V
2/fsam+0.5Note 2
µs
2.7 V ≤ VDD ≤ 5.5 V
0
4
MHz
1.8 V ≤ VDD < 2.7 V
0
275
kHz
2.7 V ≤ VDD ≤ 5.5 V
100
ns
1.8 V ≤ VDD < 2.7 V
1.8
ns
TI00, TI01 input
TI50, TI51 input
tTIH0, tTIL0
fTI5
frequency
TI50, TI51 input
tTIH5, tTIL5
high-/low-level
width
Interrupt request
tINTH, tINTL
input high-/lowlevel width
RESET
tRSL
low-level width
INTP0 to INTP3,
2.7 V ≤ VDD ≤ 5.5 V
1
µs
P40 to P47
1.8 V ≤ VDD < 2.7 V
2
µs
2.7 V ≤ VDD ≤ 5.5 V
10
µs
1.8 V ≤ VDD < 2.7 V
20
µs
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register
0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
62
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
TCY vs. VDD (main system clock operation)
16.0
Cycle time TCY [ µ S]
10.0
5.0
Operation
guaranteed
range
2.0
1.6
1.0
0.4
0.238
0.1
0
1.0
2.0
1.8
3.0
4.0
5.0 5.5 6.0
2.7
Supply voltage VDD [V]
Data Sheet U14042EJ4V0DS
63
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
Parameter
Symbol
(1/3)
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
20
ns
Address hold time
tADH
6
ns
Data input time from address
tADD1
(2 + 2n)tCY – 54
ns
tADD2
(3 + 2n)tCY – 60
ns
100
ns
Address output time from RD↓
tRDAD
0
Data input time from RD↓
tRDD1
(2 + 2n)tCY – 87
ns
tRDD2
(3 + 2n)tCY – 93
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 33
ns
tRDL2
(2.5 + 2n)tCY – 33
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 43
ns
tRDWT2
tCY – 43
ns
tWRWT
tCY – 25
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
6
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 15
ns
Delay time from ASTB↓ to RD↓
tASTRD
6
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 15
ns
Delay time from
tRDAST
0.8tCY – 15
1.2tCY
ns
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
10
60
ns
Address hold time from WR↑
tWRADH
0.8tCY – 15
1.2tCY + 30
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.8tCY
2.5tCY + 25
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.8tCY
2.5tCY + 25
ns
RD↑ to ASTB↑ at external fetch
Address hold time from
RD↑ at external fetch
Caution
TCY can only be used when the MIN. value is 0.238 µs.
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and
ASTB pins.)
64
ns
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)
(2/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
30
ns
Address hold time
tADH
10
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 108
ns
tADD2
(3 + 2n)tCY – 120
ns
200
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 148
ns
tRDD2
(3 + 2n)tCY – 162
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 40
ns
tRDL2
(2.5 + 2n)tCY – 40
ns
Input time from RD↓ to WAIT↓
tRDWT1
tCY – 75
ns
tRDWT2
tCY – 60
ns
Input time from WR↓ to WAIT↓
tWRWT
tCY – 50
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
(2 + 2n)tCY
ns
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
10
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 30
ns
Delay time from ASTB↓ to RD↓
tASTRD
10
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 30
ns
Delay time from
tRDAST
0.8tCY – 30
1.2tCY
ns
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
20
120
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 30
1.2tCY + 60
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 50
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 50
ns
RD↑ to ASTB↑ at external fetch
Hold time from
RD↑ to address at external fetch
ns
Caution
TCY can only be used when the MIN. value is 0.4 µs.
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,
and ASTB pins.)
Data Sheet U14042EJ4V0DS
65
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
(3/3)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.3tCY
ns
Address setup time
tADS
120
ns
Address hold time
tADH
20
ns
Input time from address to data
tADD1
(2 + 2n)tCY – 233
ns
tADD2
(3 + 2n)tCY – 240
ns
400
ns
Output time from RD↓ to address
tRDAD
0
Input time from RD↓ to data
tRDD1
(2 + 2n)tCY – 325
ns
tRDD2
(3 + 2n)tCY – 332
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5 + 2n)tCY – 92
ns
tRDL2
(2.5 + 2n)tCY – 92
ns
Input time from RD↓ to WAIT↓
Input time from WR↓ to WAIT↓
tRDWT1
tCY – 350
ns
tRDWT2
tCY – 132
ns
tWRWT
tCY – 100
ns
(2 + 2n)tCY
ns
WAIT low-level width
tWTL
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
ns
Write data hold time
tWDH
20
ns
WR low-level width
tWRL1
(1.5 + 2n)tCY – 60
ns
Delay time from ASTB↓ to RD↓
tASTRD
20
ns
Delay time from ASTB↓ to WR↓
tASTWR
2tCY – 60
ns
Delay time from
tRDAST
0.8tCY – 60
1.2tCY
ns
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
Write data output time from RD↑
tRDWD
40
Write data output time from WR↓
tWRWD
40
240
ns
Hold time from WR↑ to address
tWRADH
0.8tCY – 60
1.2tCY + 120
ns
Delay time from WAIT↑ to RD↑
tWTRD
0.5tCY
2.5tCY + 100
ns
Delay time from WAIT↑ to WR↑
tWTWR
0.5tCY
2.5tCY + 100
ns
RD↑ to ASTB↑ at external fetch
Hold time from
RD↑ to address at external fetch
ns
Caution
TCY can only be used when the MIN. value is 1.6 µs.
Remarks
1.
tCY = TCY/4
2.
n indicates the number of waits.
3.
CL = 100 pF (CL indicates the load capacitance of the AD0 to AD7, AD8 to AD15, RD, WR, WAIT,
and ASTB pins.)
66
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter
SCK3n
Symbol
tKCY1
cycle time
SCK3n high-/
tKH1, tKL1
low-level width
SI3n setup time
tSIK1
(to SCK3n↑)
SI3n hold time
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
954
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
4.0 V ≤ VDD ≤ 5.5 V
tKCY1/2 – 50
ns
1.8 V ≤ VDD < 4.0 V
tKCY1/2 – 100
ns
4.0 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.0 V
150
ns
1.8 V ≤ VDD < 2.7 V
300
ns
400
ns
tKSI1
(from SCK3n↑)
Delay time from
SCK3n↓ to SO3n
output
tKSO1
C = 100 pF
Note
300
ns
MAX.
Unit
Note C is the load capacitance of the SCK3n and SO3n output lines.
(b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter
SCK3n
Symbol
TYP.
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
4.0 V ≤ VDD ≤ 5.5 V
400
ns
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
ns
tSIK2
100
ns
tKSI2
400
ns
cycle time
tKH2, tKL2
low-level width
SI3n setup time
MIN.
4.0 V ≤ VDD ≤ 5.5 V
tKCY2
SCK3n high-/
Conditions
(to SCK3n↑)
SI3n hold time
(from SCK3n↑)
Delay time from
SCK3n↓ to SO3n
output
tKSO2
C = 100 pF
Note
300
ns
Note C is the load capacitance of the SO3n output line.
Remark Conventional products of µPD780021A, 780022A, 780023A, 780024A: n = 0 or 1
µPD780021AY, 780022AY, 780023AY, 780024AY: n = 0
Data Sheet U14042EJ4V0DS
67
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(c) UART mode (dedicated baud-rate generator output)
Parameter
Symbol
Transfer rate
Conditions
MIN.
TYP.
MAX.
Unit
4.0 V ≤ VDD ≤ 5.5 V
131031
bps
2.7 V ≤ VDD < 4.0 V
78125
bps
1.8 V ≤ VDD < 2.7 V
39063
bps
MAX.
Unit
(d) UART mode (external clock input)
Parameter
ASCK0 cycle time
ASCK0 high-/low-level width
Symbol
Conditions
MIN.
TYP.
4.0 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
3200
ns
tKH3,
4.0 V ≤ VDD ≤ 5.5 V
400
ns
tKL3
2.7 V ≤ VDD < 4.0 V
800
ns
1.8 V ≤ VDD < 2.7 V
1600
tKCY3
Transfer rate
ns
4.0 V ≤ VDD ≤ 5.5 V
39063
bps
2.7 V ≤ VDD < 4.0 V
19531
bps
1.8 V ≤ VDD < 2.7 V
9766
bps
MAX.
Unit
(e) UART mode (infrared data transfer mode)
Parameter
Conditions
MIN.
Transfer rate
4.0 V ≤ VDD ≤ 5.5 V
131031
bps
Allowable bit rate error
4.0 V ≤ VDD ≤ 5.5 V
±0.87
%
Output pulse width
4.0 V ≤ VDD ≤ 5.5 V
1.2
0.24/fbrNote
µs
Input pulse width
4.0 V ≤ VDD ≤ 5.5 V
4/fX
Note
68
Symbol
fbr: Specified baud rate
Data Sheet U14042EJ4V0DS
µs
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(f) I2C bus mode (µPD780021AY, 780022AY, 780023AY, 780024AY only)
Parameter
Symbol
Standard Mode
MIN.
MAX.
High-Speed Mode
MIN.
MAX.
Unit
SCL0 clock frequency
fCLK
0
100
0
400
kHZ
Bus free time
tBUF
4.7
—
1.3
—
µs
Hold timeNote 1
tHD:STA
4.0
—
0.6
—
µs
SCL0 clock low-level width
tLOW
4.7
—
1.3
—
µs
SCL0 clock high-level width
tHIGH
4.0
—
0.6
—
µs
Start/restart condition setup time
tSU:STA
4.7
—
0.6
—
µs
Data hold time CBUS-compatible master
tHD:DAT
5.0
—
—
—
µs
0.9 Note 3
µs
(between stop and start conditions)
I2C bus
0Note 2
0Note 2
—
Data setup time
tSU:DAT
250
—
100Note 4
—
ns
SDA0 and SCL0 signal rise time
tR
—
1000
20 + 0.1CbNote 5
300
ns
SDA0 and SCL0 signal fall time
tF
—
300
20 + 0.1CbNote 5
300
ns
Stop condition setup time
tSU:STO
4.0
—
0.6
—
µs
Spike pulse width controlled by input filter
tSP
—
—
0
50
ns
Capacitive load per bus line
Cb
—
400
—
400
pF
Notes 1. In the start condition, the first clock pulse is generated after this hold time.
2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide
at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal).
3. If the device does not extend the SCL0 signal low hold time (tLOW), only the maximum data hold time
tHD:DAT needs to be fulfilled.
4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the conditions
described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT
= 1000 + 250 = 1250 ns by standard mode I2C bus specification).
5. Cb: Total capacitance per bus line (unit: pF)
Data Sheet U14042EJ4V0DS
69
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bit
4.0 V ≤ AVREF ≤ 5.5 V
±0.4
%FSR
2.7 V ≤ AVREF < 4.0 V
±0.6
%FSR
1.8 V ≤ AVREF < 2.7 V
±1.2
%FSR
Resolution
Overall
errorNote
Conversion time
tCONV
Analog input voltage
VIAN
Reference voltage
AVREF
Resistance between AVREF and AVSS
RREF
4.0 V ≤ AVDD ≤ 5.5 V
14
96
µs
2.7 V ≤ AVDD < 4.0 V
19
96
µs
1.8 V ≤ AVDD < 2.7 V
28
96
µs
0
AVREF
V
1.8
AVDD
V
When A/D converter not operating
20
40
kΩ
Note Excludes quantization error (±1/2 LSB). This value is indicated as a ratio (%FSR) to the full-scale value.
Remark The impedance of the analog input pins is shown below.
[Equivalent circuit]
R1
R2
ANIn
(n = 0 to 3)
C1
C2
C3
[Parameter value]
(TYP.)
AVDD
R1
R2
C1
C2
C3
2.7 V
12 kΩ
8.0 kΩ
3.0 pF
3.0 pF
2.0 pF
4.5 V
4 kΩ
2.7 kΩ
3.0 pF
1.4 pF
2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention power
supply voltage
VDDDR
Data retention power
supply current
IDDDR
Release signal set time
tSREL
Oscillation stabilization
tWAIT
time
Conditions
MIN.
TYP.
1.6
Subsystem clock stop (XT1 = VDD) and
feed-back resistor disconnected
0.1
MAX.
Unit
5.5
V
30
µA
µs
0
Release by RESET
217/fx
s
Release by interrupt request
Note
s
Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
70
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
12.3 Timing Chart
AC Timing Test Points (excluding X1, XT1 inputs)
0.8VDD
0.2VDD
0.8VDD
Point of measurement
0.2VDD
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 input
TI Timing
tTIL0
tTIH0
TI00, TI01
1/fT5
tTIL5
tTIH5
TI50, TI51
Data Sheet U14042EJ4V0DS
71
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP3
RESET Input Timing
tRSL
RESET
72
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
tADD1
AD0 to AD7
Lower 8-bit address
tADS
Hi-Z
Instruction code
tRDAD
tRDD1
tADH
tRDADH
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
tADD1
AD0 to AD7
Hi-Z
Lower 8-bit address
tADS
tADH
tRDAD
Instruction code
tRDADH
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
tWTL
Data Sheet U14042EJ4V0DS
tWTRD
73
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
External data access (no wait):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Lower 8-bit address
tADS
tADH
Hi-Z
tRDAD
tRDD2
tASTH
Hi-Z
Write data
Read Data
tRDH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDS
tWDH
tWRADH
tWRWD
WR
tASTWR
tWRL1
External data access (wait insertion):
A8 to A15
Higher 8-bit address
tADD2
AD0 to AD7
Lower 8-bit
address
tADS tADH
tASTH
Hi-Z
Read data
Hi-Z
Write data
tRDAD
tRDH
tRDD2
ASTB
tASTRD
RD
tRDWD
tRDL2
tWDH
tWDS
tWRWD
WR
tASTWR
tWRL1
tWRADH
WAIT
tRDWT2
tWTL
tWTRD
tWTL
tWRWT
74
Data Sheet U14042EJ4V0DS
tWTWR
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
SCK3n
tSIKm
tKSIm
Input data
SI3n
tKSOm
SO3n
Output data
Remarks 1. m = 1, 2
2. µPD780021A, 780022A, 780023A, 780024A:
n = 0, 1
µPD780021AY, 780022AY, 780023AY, 780024AY: n = 0
UART mode (external clock input):
t KCY3
t KL3
t KH3
ASCK0
I2C bus mode (µPD780021AY, 780022AY, 780023AY, 780024AY only):
tLOW
tR
SCL0
tHD:DAT
tHD:STA
tHIGH
tSU:DAT
tF
tSU:STA
tHD:STA
tSP
tSU:STO
SDA0
tBUF
Stop
condition
Start
condition
Restart
condition
Data Sheet U14042EJ4V0DS
Stop
condition
75
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP Instruction execution
Standby release signal
(interrupt request)
tWAIT
76
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
13. PACKAGE DRAWINGS
64-PIN PLASTIC SDIP (19.05mm(750))
64
33
1
32
A
K
J
L
I
M
F
D
N
C
M
R
B
H
G
NOTES
1. Each lead centerline is located within 0.17 mm of
its true position (T.P.) at maximum material condition.
2. Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
A
58.0+0.68
-0.20
B
1.78 MAX.
C
1.778 (T.P.)
D
0.50±0.10
F
0.9 MIN.
G
3.2±0.3
H
0.51 MIN.
I
4.05+0.26
-0.20
J
5.08 MAX.
K
19.05 (T.P.)
L
17.0±0.2
M
0.25+0.10
-0.05
N
0.17
R
0 ~ 15°
P64C-70-750A,C-4
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14042EJ4V0DS
77
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC QFP (14x14)
A
B
detail of lead end
33
32
48
49
S
C D
Q
64
1
R
17
16
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
17.6±0.4
B
14.0±0.2
C
14.0±0.2
D
17.6±0.4
F
1.0
G
1.0
H
0.37 +0.08
-0.07
I
J
0.15
0.8 (T.P.)
K
1.8±0.2
L
0.8±0.2
M
0.17 +0.08
-0.07
N
0.10
P
2.55±0.1
Q
0.1±0.1
R
5°± 5°
S
2.85 MAX.
P64GC-80-AB8-5
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
78
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC LQFP (14x14)
A
B
48
49
33
32
detail of lead end
S
P
C
D
T
R
64
1
L
17
16
U
Q
F
G
J
H
I
M
ITEM
K
S
N
M
S
MILLIMETERS
A
17.2±0.2
B
14.0±0.2
C
14.0±0.2
D
17.2±0.2
F
1.0
G
1.0
H
0.37 +0.08
−0.07
I
0.20
J
K
0.8 (T.P.)
NOTE
L
0.8
Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
M
0.17 +0.03
−0.06
N
0.10
P
1.4±0.1
Q
0.127±0.075
+4°
3° −3°
R
S
T
U
1.6±0.2
1.7 MAX.
0.25
0.886±0.15
P64GC-80-8BS
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14042EJ4V0DS
79
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC TQFP (12x12)
A
B
48
detail of lead end
33
32
49
S
P
T
C
D
R
L
U
64
Q
17
16
1
F
G
J
H
I
M
ITEM
K
S
M
N
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
14.0±0.2
B
12.0±0.2
C
12.0±0.2
D
F
14.0±0.2
1.125
G
1.125
H
0.32 +0.06
−0.10
I
0.13
J
0.65 (T.P.)
K
1.0±0.2
L
0.5
M
0.17 +0.03
−0.07
N
0.10
P
1.0
Q
0.1±0.05
R
3° +4°
−3°
S
1.1±0.1
T
0.25
U
0.6±0.15
P64GK-65-9ET-3
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
80
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
64-PIN PLASTIC LQFP (10x10)
A
B
48
detail of lead end
33
32
49
S
P
C
T
D
R
64
U
17
Q
16
1
L
F
G
J
H
I
M
ITEM
A
K
B
S
N
S
M
MILLIMETERS
12.0±0.2
10.0±0.2
C
10.0±0.2
D
12.0±0.2
F
1.25
G
1.25
H
0.22±0.05
I
0.08
J
0.5 (T.P.)
K
1.0±0.2
L
0.5
M
0.17 +0.03
−0.07
N
0.08
P
1.4
Q
0.1±0.05
R
3° +4°
−3°
S
1.5±0.10
T
0.25
U
0.6±0.15
S64GB-50-8EU-1
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
Data Sheet U14042EJ4V0DS
81
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
73-PIN PLASTIC FBGA (9x9)
D
w S A
ZE
ZD
A
9
8
7
6
5
4
3
2
1
B
E
J H G F E D C B A
w S B
INDEX MARK
A
y1
A2
S
(UNIT:mm)
S
y
S
e
φb
A1
φx
M
S AB
ITEM
D
DIMENSIONS
9.00±0.10
E
9.00±0.10
w
0.20
A
1.28±0.10
A1
0.35±0.06
A2
0.93
e
0.80
b
0.50 +0.05
–0.10
x
0.08
y
0.10
y1
0.20
ZD
1.30
ZE
1.30
P73F1-80-CN3
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
82
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
Table 14-1. Surface Mounting Type Soldering Conditions (1/3)
×××
(1) µPD780021AGC-×××
×××-AB8: 64-pin plastic QFP (14 x 14)
µPD780022AGC-×××
×××
×××-AB8: 64-pin plastic QFP (14 x 14)
µPD780023AGC-×××
×××
×××-AB8: 64-pin plastic QFP (14 x 14)
µPD780024AGC-×××
×××
×××-AB8: 64-pin plastic QFP (14 x 14)
µPD780021AYGC-×××
×××
×××-AB8: 64-pin plastic QFP (14 x 14)
µPD780022AYGC-×××
×××
×××-AB8: 64-pin plastic QFP (14 x 14)
µPD780023AYGC-×××
×××
×××-AB8: 64-pin plastic QFP (14 x 14)
µPD780024AYGC-×××
×××
×××-AB8: 64-pin plastic QFP (14 x 14)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max.
Recommended
Condition Symbol
IR35-00-3
(at 210°C or higher), Count: Three times or less
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
VP15-00-3
(at 200°C or higher), Count: Three times or less
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
WS60-00-1
Count: Once, Preheating temperature: 120°C Max. (package surface
temperature)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Caution Do not use different soldering methods together (except for partial heating).
×××
(2) µPD780021AGC-×××
×××-8BS: 64-pin plastic LQFP (14 x 14)
×××
µPD780022AGC-×××
×××-8BS: 64-pin plastic LQFP (14 x 14)
µPD780023AGC-×××
×××
×××-8BS: 64-pin plastic LQFP (14 x 14)
µPD780024AGC-×××
×××
×××-8BS: 64-pin plastic LQFP (14 x 14)
×××
µPD780021AYGC-×××
×××-8BS: 64-pin plastic LQFP (14 x 14)
µPD780022AYGC-×××
×××
×××-8BS: 64-pin plastic LQFP (14 x 14)
µPD780023AYGC-×××
×××
×××-8BS: 64-pin plastic LQFP (14 x 14)
µPD780024AYGC-×××
×××
×××-8BS: 64-pin plastic LQFP (14 x 14)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max.
Recommended
Condition Symbol
IR35-00-2
(at 210°C or higher), Count: Two times or less
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
VP15-00-2
(at 200°C or higher), Count: Two times or less
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
WS60-00-1
Count: Once, Preheating temperature: 120°C Max. (package surface
temperature)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U14042EJ4V0DS
83
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Table 14-1. Surface Mounting Type Soldering Conditions (2/3)
×××
×××-9ET: 64-pin plastic TQFP (12 x 12)
(3) µ PD780021AGK-×××
µPD780022AGK-×××
×××
×××-9ET: 64-pin plastic TQFP (12 x 12)
×××
µPD780023AGK-×××
×××-9ET: 64-pin plastic TQFP (12 x 12)
×××-9ET: 64-pin plastic TQFP (12 x 12)
×××
µPD780024AGK-×××
µPD780021AYGK-×××
×××
×××-9ET: 64-pin plastic TQFP (12 x 12)
×××
µPD780022AYGK-×××
×××-9ET: 64-pin plastic TQFP (12 x 12)
×××-9ET: 64-pin plastic TQFP (12 x 12)
×××
µPD780023AYGK-×××
µPD780024AYGK-×××
×××
×××-9ET: 64-pin plastic TQFP (12 x 12)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max.
Recommended
Condition Symbol
IR35-107-2
(at 210°C or higher), Count: Two times or less, Exposure limit:
7 daysNote (after that, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
VP15-107-2
(at 200°C or higher), Count: Two times or less, Exposure limit:
7 daysNote (after that, prebake at 125°C for 10 hours)
Wave soldering
Solder bath temperature: 260°C max., Time: 10 seconds max.,
WS60-107-1
Count: Once, Preheating temperature: 120°C Max. (package surface
temperature), Exposure limit: 7 daysNote (after that, prebake at 125°C
for 10 hours)
Partial heating
Note
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
84
—
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Table 14-1. Surface Mounting Type Soldering Conditions (3/3)
×××
×××-8EU: 64-pin plastic LQFP (10 x 10)
(4) µPD780021AGB-×××
µPD780022AGB-×××
×××
×××-8EU: 64-pin plastic LQFP (10 x 10)
µPD780023AGB-×××
×××
×××-8EU: 64-pin plastic LQFP (10 x 10)
µPD780024AGB-×××
×××
×××-8EU: 64-pin plastic LQFP (10 x 10)
µPD780021AYGB-×××
×××
×××-8EU: 64-pin plastic LQFP (10 x 10)
×××-8EU: 64-pin plastic LQFP (10 x 10)
µPD780022AYGB-×××
×××
µPD780023AYGB-×××
×××
×××-8EU: 64-pin plastic LQFP (10 x 10)
µPD780024AYGB-×××
×××
×××-8EU: 64-pin plastic LQFP (10 x 10)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 235°C, Time: 30 seconds max.
Recommended
Condition Symbol
IR35-00-2
(at 210°C or higher), Count: Twice or less
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
VP15-00-2
(at 200°C or higher), Count: Twice or less
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
––
Caution Do not use different soldering methods together (except for partial heating).
×××
×××-CN3: 73-pin plastic FBGA (9 x 9)
(5) µPD780021AF1-×××
µPD780022AF1-×××
×××
×××-CN3: 73-pin plastic FBGA (9 x 9)
×××-CN3: 73-pin plastic FBGA (9 x 9)
µPD780023AF1-×××
×××
µPD780024AF1-×××
×××
×××-CN3: 73-pin plastic FBGA (9 x 9)
µPD780021AYF1-×××
×××
×××-CN3: 73-pin plastic FBGA (9 x 9)
×××-CN3: 73-pin plastic FBGA (9 x 9)
µPD780022AYF1-×××
×××
µPD780023AYF1-×××
×××
×××-CN3: 73-pin plastic FBGA (9 x 9)
µPD780024AYF1-×××
×××
×××-CN3: 73-pin plastic FBGA (9 x 9)
Soldering Method
Infrared reflow
Soldering Conditions
Package peak temperature: 260°C, Time: 60 seconds max.
Recommended
Condition Symbol
IR60-203-3
(at 220°C or higher), Count: Three times or less, Exposure limit:
3 daysNote (after that, prebake at 125°C for 20 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max.
VP15-203-3
(at 200°C or higher), Count: Three times or less, Exposure limit:
3 daysNote (after that, prebake at 125°C for 20 hours)
Note
After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together.
Data Sheet U14042EJ4V0DS
85
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Table 14-2. Insertion Type Soldering Conditions
µPD780021ACW-×××
×××
×××: 64-pin plastic SDIP (19.05 mm (750))
×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780022ACW-×××
×××
µPD780023ACW-×××
×××
×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780024ACW-×××
×××
×××: 64-pin plastic SDIP (19.05 mm (750))
×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780021AYCW-×××
×××
µPD780022AYCW-×××
×××
×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780023AYCW-×××
×××
×××: 64-pin plastic SDIP (19.05 mm (750))
×××: 64-pin plastic SDIP (19.05 mm (750))
µPD780024AYCW-×××
×××
Soldering Method
Wave soldering
Soldering Conditions
Solder bath temperature: 260°C max., Time: 10 seconds max.
(only for pins)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with
the package.
86
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780024A, 780024AY
Subseries.
Also refer to (6) Cautions on Using Development Tools.
(1) Software Package
SP78K0
CD-ROM in which various software tools for 78K/0 development are integrated in one
package
(2) Language Processing Software
RA78K0
Assembler package common to 78K/0 Series
CC78K0
C compiler package common to 78K/0 Series
DF780024
Device file for µPD780024A, 780024AY Subseries
CC78K0-L
C compiler library source file common to 78K/0 Series
(3) Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flash programmer dedicated to microcontrollers with on-chip flash memory
Flashpro IV (FL-PR4, PG-FP4)
FA-64CW
FA-64GC
FA-64GC-8BS-A
FA-64GK-9ET
FA-64GB-8EU
FA-73F1-CN3-A
Adapter for flash memory writing used connected to the Flashpro III/Flashpro IV.
• FA-64CW:
64-pin plastic SDIP (CW type)
• FA-64GC:
64-pin plastic QFP (GC-AB8 type)
• FA-64GC-8BS-A: 64-pin plastic LQFP (GC-8BS type)
• FA-64GK-9ET:
64-pin plastic TQFP (GK-9ET type)
• FA-64GB-8EU: 64-pin plastic LQFP (GB-8EU type)
• FA-73F1-CN3-A: 73-pin plastic FBGA (F1-CN3 type)
Data Sheet U14042EJ4V0DS
87
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(4) Debugging Tools
• When using in-circuit emulator IE-78K0-NS or IE-78K0-NS-A
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-78K0-NS-PA
Performance board to enhance and expand the functions of IE-78K0-NS
IE-78K0-NS-A
Combination of IE-78K-NS and IE-78K0-NS-PA
IE-70000-MC-PS-B
Power supply unit for IE-78K0-N and IE-78K0-NS-A
IE-70000-98-IF-C
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported)
IE-70000-PC-IF-C
Adapter required when using IBM PC/ATTM or compatible as host machine (ISA bus supported)
IE-70000-PCI-IF-A
Adapter required when using PC in which PCI bus is incorporated as host machine
IE-780034-NS-EM1
Emulation board to emulate µPD780024A, 780024AY Subseries
NP-64CW
Emulation probe for 64-pin plastic SDIP (CW type)
NP-H64CW
NP-64GC
Emulation probe for 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type)
NP-64GC-TQ
NP-H64GC-TQ
NP-64GK
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
NP-H64GK-TQ
NP-H64GB-TQ
Emulation probe for 64-pin plastic LQFP (GB-8EU type)
NP-73F1-CN3Note
Emulation probe for 73-pin plastic FBGA (F1-CN3 type)
EV-9200GC-64
Conversion socket to connect the NP64GC and a target system board on which a 64-pin plastic
QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) can be mounted.
TGC-064SAP
Conversion adapter to connect the NP-64GC-TQ or NP-H64GC-TQ and a target system board on
which a 64-pin plastic QFP (GC-AB8 type), 64-pin plastic LQFP (GC-8BS type) can be mounted
TGK-064SBW
Conversion adapter to connect the NP-64GK or NP-H64GK-TQ and a target system on which a 64pin plastic TQFP (GK-9ET type) can be mounted
TGB-064SDP
Conversion socket to connect the NP-H64GB-TQ and a target system board on which a 64-pin
plastic LQFP (GB-8EU type) can be mounted
CSICE73A0909N01,
Conversion socket to connect the NP-73F1-CN3 and a target system board on which a 73-pin plastic
LSPACK73A0909N01,
FBGA (F1-CN3 type) can be mounted
CSSOCKET73A0909N01
ID78K0-NS
Integrated debugger for IE-78K0-NS and IE-78K0-NS-A
SM78K0
System simulator common to 78K/0 Series
DF780024
Device file for µPD780024A, 780024AY Subseries
Note
The conversion socket (CSICE73A0909N01, LSPACK73A0909N01, or CSSOCKET73A0909N01) is supplied
with the emulation probe (NP-73F1-CN3).
88
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported)
IE-70000-PCI-IF-A
Adapter required when using PC in which PCI bus is incorporated as host machine
IE-780034-NS-EM1
Emulation board to emulate µPD780024A, 780024AY Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A
EP-78240CW-R
Emulation probe for 64-pin plastic SDIP (CW type)
EP-78240GC-R
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EP-78012GK-R
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
EV-9200GC-64
Conversion socket to connect the EP-78240GC-R and a target system board on which a 64-pin
plastic QFP (GC-AB8 type) can be mounted
TGK-064SBW
Conversion adapter to connect the EP-78012GK-R and a target system board on which a 64-pin plastic
TQFP (GK-9ET type) can be mounted
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF780024
Device file for µPD780024A, 780024AY Subseries
(5) Real-Time OS
RX78K0
Real-time OS for 78K/0 Series
Caution The 64-pin plastic LQFP (GB-8EU type) and 73-pin plastic FBGA (F1-CN3 type) do not support
the IE-78001-R-A.
Data Sheet U14042EJ4V0DS
89
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
(6) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780024.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780024.
• FL-PR3, FL-PR4, FA-64CW, FA-64GC, FA-64GC-8BS-A, FA-64GK-9ET, FA-64GB-8EU, FA-73F1-CN3-A,
NP-64CW, NP-H64CW, NP-64GC, NP-64GC-TQ, NP-H64GC-TQ, NP-64GK, NP-H64GK-TQ, NP-H64GB-TQ,
and NP-73F1-CN3 are products made by Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191).
• TGC-064SAP, TGK-064SBW, TGB-064SDP, CSICE73A0909N01, LSPACK73A0909N01, and
CSSOCKET73A0909N01 are products made by TOKYO ELETECH CORPORATION.
Refer to: Daimaru Kogyo, Ltd.
Tokyo Electronic Division (+81-3-3820-7112)
Osaka Electronic Division (+81-6-6244-6672)
• For third-party development tools, see the Single-chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machines and OSs supporting each software are as follows.
Host Machine
PC
EWS
HP9000 series 700TM [HP-UXTM]
SPARCstationTM [SunOSTM, SolarisTM]
Software
PC-9800 series [Japanese WindowsTM]
IBM PC/AT and compatibles
[Japanese/English Windows]
RA78K0
√ Note
√
CC78K0
√
[OS]
Note
√
ID78K0-NS
√
–
ID78K0
√
–
SM78K0
√
–
RX78K0
√ Note
√
Note
90
DOS-based software
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual
U14046E
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Data Sheet
This document
µPD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A),
780024AY(A) Data Sheet
U15131E
µPD78F0034A, 78F0034AY Data Sheet
U14040E
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A) Data Sheet
To be prepared
78K/0 Series Instructions User’s Manual
U12326E
Documents Related to Development Software Tools (User’s Manuals)
Document Name
RA78K0 Assembler Package
Document No.
Operation
U14445E
Language
U14446E
Structured Assembly Language
U11789E
Operation
U14297E
Language
U14298E
Operation (Windows Based)
U15373E
External Part User Open Interface Specifications
U15802E
ID78K Series Integrated Debugger Ver. 2.30 or Later
Operation (Windows Based)
U15185E
RX78K0 Real-time OS
Fundamentals
U11537E
Installation
U11536E
CC78K0 C Compiler
SM78K Series System Simulator Ver. 2.30 or Later
Project Manager Ver. 3.12 or Later (Windows Based)
U14610E
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
Document No.
IE-78K0-NS In-Circuit Emulator
U13731E
IE-78K0-NS-A In-Circuit Emulator
U14889E
IE-780034-NS-EM1 Emulation Board
U14642E
IE-78001-R-A In-Circuit Emulator
U14142E
IE-78K0-R-EX1 In-Circuit Emulator
To be prepared
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Data Sheet U14042EJ4V0DS
91
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Documents Related to Flash Memory Writing
Document Name
Document No.
PG-FP3 Flash Memory Programmer User’s Manual
U13502E
PG-FP4 Flash Memory Programmer User’s Manual
U15260E
Other Related Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE - Products & Packages -
X13769E
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
92
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
[MEMO]
Data Sheet U14042EJ4V0DS
93
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Note: Purchase of NEC Electronics l 2 C components conveys a license under the Philips I 2C Patent Rights
to use these components in an I 2C system, provided that the system conforms to the I 2C Standard
Specification as defined by Philips.
FIP and IEBus are trademarks of NEC Electronics Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United Status
and/ or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
94
Data Sheet U14042EJ4V0DS
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 0211-65 03 327
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Fax: 091-504 28 60
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Shanghai, Ltd.
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 021-6841-1137
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
Fax: 6250-3583
J02.11
Data Sheet U14042EJ4V0DS
95
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
• The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1