ETC UPD78P018FYCW

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78P018FY
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78P018FY is a member of the µPD78018FY Subseries of 78K/0 Series products. The internal mask ROM
of the µPD78018FY is replaced with one-time PROM or EPROM.
Because the µPD78P018FY can be programmed by users, it is ideally suited for applications involving the evaluation
of systems in development stages, small-scale production of many different products, and rapid development and timeto-market of new products.
Caution
The µPD78P018FYDW and 78P018FYKK-S are not guaranteed to maintain the reliability level
required for mass production of the customer's devices. Please use only experimentally or for
evaluation purposes during trial manufacture.
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing.
µPD78018F, 78018FY Subseries User's Manual: U10659E
78K/0 Series User's Manual – Instructions: U12326E
FEATURES
• Pin compatible with mask ROM version (except VPP pin)
• Internal PROM: 60 Kbytes Note 1
µPD78P018FYDW, 78P018FYKK-S: Re-programmable (suited for system evaluation)
µPD78P018FYCW, 78P018FYGC-AB8: Programmable only once (suited for small-scale production)
• Internal high-speed RAM: 1024 bytes Note 1
• Internal expansion RAM: 1024 bytes Note 2
• Internal buffer RAM: 32 bytes
• Supports the I2C bus interface
• Operable over same supply voltage range as mask ROM version: VDD = 1.8 to 5.5 V (except an A/D converter)
• QTOP™ microcontroller supported
Notes 1. The capacities of internal PROM and internal high-speed RAM can be changed by means of the internal
memory size switching register (IMS).
2. The capacity of the internal expansion RAM can be changed by means of the internal expansion RAM size
switching register (IXS).
Remarks 1. QTOP Microcontroller is a general term for microcontrollers which incorporate one-time PROM and are totally
supported by NEC's programming service (from programming to marking, screening, and verification).
2. For the differences between the PROM version and mask ROM versions, refer to 1. DIFFERENCES BETWEEN
THE µPD78P018FY AND MASK ROM VERSIONS.
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U10989EJ3V0DS00 (3rd edition)
Date Published December 1998 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1994
µPD78P018FY
ORDERING INFORMATION
Part Number
µPD78P018FYCW
µPD78P018FYDW
µPD78P018FYGC-AB8
µPD78P018FYKK-S
Package
Internal ROM
64-pin plastic shrink DIP (750 mils)
One-time PROM
64-pin ceramic shrink DIP (with window) (750 mils)
64-pin plastic QFP (14 × 14 mm)
EPROM
One-time PROM
64-pin ceramic WQFN (14 × 14 mm)
EPROM
QUALITY GRADE
Part Number
µPD78P018FYCW
µPD78P018FYDW
µPD78P018FYGC-AB8
µPD78P018FYKK-S
Package
Quality Grades
64-pin plastic shrink DIP (750 mils)
64-pin ceramic shrink DIP (with window) (750 mils)
Standard
Not applicable
64-pin plastic QFP (14 × 14 mm)
(for function evaluation)
Standard
64-pin ceramic WQFN (14 × 14 mm)
Not applicable
(for function evaluation)
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number C11531E) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
2
µPD78P018FY
78K/0 SERIES PRODUCT LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in
mass production
Products under
development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
µPD78075B
µPD78078
µ PD78070A
µ PD780058
µ PD78058F
µ PD78054
µ PD780065
µ PD780034
µ PD780024
µ PD78014H
µPD78018F
µPD78083
EMI-noise reduced version of the µPD78078
µPD78078Y
µPD78070AY
µ PD780018AY
µ PD780058YNote
µ PD78058FY
µ PD78054Y
µ PD780034Y
µPD780024Y
µ PD78018FY
Timer was added to the µPD78054 and external interface was enhanced
ROM-less version of the µPD78078
Serial I/O of the µPD78078Y was enhanced and the function is limited
Serial I/O of the µPD78054 was enhanced and EMI-noise was reduced
EMI-noise reduced version of the µPD78054
UART and D/A converter were added to the µPD78018F and I/O was enhanced
RAM capacity of µPD780024 was expanded
A/D converter of the µPD780024 was enhanced
Serial I/O of the µPD78018F was enhanced
EMI-noise reduced version of the µPD78018F
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
64-pin
µ PD780988
On-chip inverter control circuit and UART. EMI-noise was reduced
FIPTM drive
78K/0
Series
100-pin
100-pin
80-pin
80-pin
80-pin
I/O and FIP C/D of the µPD78044F were enhanced, Display output total: 53
I/O and FIP C/D of the µPD78044H were enhanced, Display output total: 48
For panel control. On-chip FIP C/D. Display output total: 53
µPD780208
µ PD780228
µ PD780232
µPD78044H
µPD78044F
N-ch open drain was added to the µPD78044F, Display output total: 34
Basic subseries for driving FIP, Display output total: 34
LCD drive
100-pin
µ PD780308
µPD780308Y
SIO of the µPD78064 was enhanced and ROM, RAM capacity expanded
100-pin
100-pin
µ PD78064B
µPD78064
µ PD78064Y
EMI-noise reduced version of the µPD78064
Basic subseries for driving LCDs, On-chip UART
Bus interface supported
80-pin
80-pin
80-pin
80-pin
µPD78098B
µ PD780948
µ PD780701Y
µ PD780833Y
IEBusTM controller is added to µPD78054. EMI-noise was reduced.
On-chip DCAN controller
On-chip DCAN/IEBus controller
On-chip J1850 (CLASS2) controller
Meter control
80-pin
µ PD780973
80-pin
100-pin
µPD780955
µPD780958
On-chip controller/driver for automotive meter drive
Ultra-low power consumption and on-chip UART
For industrial meter control
Note Under planning
3
µPD78P018FY
The major functional differences among the Y subseries are shown below.
Function ROM Capacity
Configuration of Serial Interface
I/O VDD MIN.
Value
Subseries Name
Control
µPD78078Y
48 K to 60 K
88
1.8 V
61
2.7 V
µPD78070AY
–
µPD780018AY
48 K to 60 K
3-wire with automatic transmit/receive function: 1 ch
Time-division 3-wire:
1 ch
I2C bus (multimaster supported):
1 ch
88
µPD780058Y
24 K to 60 K
3-wire/2-wire/I2C:
1 ch
3-wire with automatic transmit/receive function: 1 ch
3-wire/time-division UART:
1 ch
68
1.8 V
µPD78058FY
48 K to 60 K
69
2.7 V
µPD78054Y
16 K to 60 K
3-wire/2-wire/I2C:
1 ch
3-wire with automatic transmit/receive function: 1 ch
3-wire/UART:
1 ch
µPD780034Y
8 K to 32 K
UART:
3-wire:
I2C bus (multimaster supported):
1 ch
1 ch
1 ch
51
µPD78018FY
8 K to 60 K
3-wire/2-wire/I2C:
1 ch
3-wire with automatic transmit/receive function: 1 ch
53
µPD780308Y
48 K to 60 K
3-wire/2-wire/I2C:
3-wire/time-division UART:
3-wire:
1 ch
1 ch
1 ch
57
µPD78064Y
16 K to 32 K
3-wire/2-wire/I2C:
3-wire/UART:
1 ch
1 ch
µPD780024Y
LCD
3-wire/2-wire/I2C:
1 ch
3-wire with automatic transmit/receive function: 1 ch
3-wire/UART:
1 ch
drive
Remark The functions other than the serial interface are common to the Subseries without Y.
4
2.0 V
1.8 V
2.0 V
µPD78P018FY
FUNCTION OVERVIEW (1/2)
Item
Expansion RAM
60 Kbytes Note 1
1024 bytes Note 1
1024 bytes Note 2
Buffer RAM
32 bytes
PROM
High-speed RAM
Internal
memory
Function
Memory space
64 Kbytes
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
Minimum instruction execution time cycle modification function provided.
When main system
clock selected
When subsystem
clock selected
Instruction set
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (@ 10.0-MHz operation)
122 µs (@ 32.768-kHz operation)
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, Boolean operation)
• BCD adjust, etc.
I/O ports
Total:
• CMOS input: 0
• CMOS I/O:
• N-channel open-drain I/O
(15-V withstand voltage):
53
2
47
4
A/D converter
• 8-bit resolution × 8 channels
• Operable over a wide power supply voltage range: VDD = 2.2 to 5.5 V
Serial interface
• 3-wire serial I/O mode/2-wire serial I/O mode/I2C bus mode selectable: 1 channel
• 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel
Timer
•
•
•
•
Timer output
3 (14-bit PWM output × 1)
Clock output
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (@ 10.0-MHz operation with main
system clock), 32.768 kHz (@ 32.768-kHz operation with subsystem clock)
Buzzer output
2.4 kHz, 4.9 kHz, 9.8 kHz (@ 10.0-MHz operation with main system clock)
Vectored
interrupt
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
Maskable
Internal: 8
Non-maskable
Internal: 1
Software
1
1
2
1
1
channel
channels
channel
channel
External: 4
sources
Notes 1. The internal PROM and internal high-speed RAM capacities can be changed with the internal memory size
switching register (IMS).
2. The internal expansion RAM capacity can be changed with the internal expansion RAM size switching
register (IXS).
5
µPD78P018FY
FUNCTION OVERVIEW (2/2)
Item
Function
Test input
Internal: 1
Supply voltage
VDD = 1.8 to 5.5 V
Operating ambient
temperature
TA = –40 to +85°C
Package
•
•
•
•
6
64-pin
64-pin
64-pin
64-pin
External: 1
plastic shrink DIP (750 mils)
ceramic shrink DIP (with window) (750 mils)
plastic QFP (14 × 14 mm)
ceramic WQFN (750 mils)
µPD78P018FY
PIN CONFIGURATION (Top View)
(1) Normal operating mode
• 64-pin Plastic Shrink DIP (750 mils)
µPD78P018FYCW
• 64-pin Ceramic Shrink DIP (with window) (750 mils)
µPD78P018FYDW
P20/SI1
1
64
AV REF
P21/SO1
2
63
AV DD
P22/SCK1
3
62
P17/ANI7
P23/STB
4
61
P16/ANI6
P24/BUSY
5
60
P15/ANI5
P25/SI0/SB0/SDA0
6
59
P14/ANI4
P26/SO0/SB1/SDA1
7
58
P13/ANI3
P27/SCK0/SCL
8
57
P12/ANI2
9
56
P11/ANI1
P31/TO1
10
55
P10/ANI0
P32/TO2
11
54
AV SS
P33/TI1
12
53
P04/XT1
P34/TI2
13
52
XT2
P30/TO0
P35/PCL
14
51
V PP
P36/BUZ
15
50
X1
P37
16
49
X2
V SS
17
48
V DD
P40/AD0
18
47
P03/INTP3
P41/AD1
19
46
P02/INTP2
P42/AD2
20
45
P01/INTP1
P43/AD3
21
44
P00/INTP0/TI0
P44/AD4
22
43
RESET
P45/AD5
23
42
P67/ASTB
P46/AD6
24
41
P66/WAIT
P47/AD7
25
40
P65/WR
P50/A8
26
39
P64/RD
P51/A9
27
38
P63
P52/A10
28
37
P62
P53/A11
29
36
P61
P54/A12
30
35
P60
P55/A13
31
34
P57/A15
V SS
32
33
P56/A14
Cautions 1. Connect the VPP pin directly to VSS.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
7
µPD78P018FY
• 64-pin Plastic QFP (14 × 14 mm)
µPD78P018FYGC-AB8
P27/SCK0/SCL
P26/SO0/SB1/SDA1
P25/SI0/SB0/SDA0
P24/BUSY
P23/STB
P22/SCK1
P21/SO1
P20/SI1
AV REF
AV DD
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
• 64-pin Ceramic WQFN (14 × 14 mm)
µPD78P018FYKK-S
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
5
44
XT2
P35/PCL
6
43
V PP
P36/BUZ
7
42
X1
P37
8
41
X2
V SS
9
40
V DD
P40/AD0
10
39
P03/INTP3
P41/AD1
11
38
P02/INTP2
P42/AD2
12
37
P01/INTP1
P43/AD3
13
36
P00/INTP0/TI0
P44/AD4
14
35
RESET
P45/AD5
15
34
P67/ASTB
P46/AD6
16
17
P66/WAIT
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
32
P65/WR
P34/TI2
P64/RD
P04/XT1
P63
45
P62
4
P61
P33/TI1
P60
AV SS
P57/A15
46
P56/A14
3
V SS
P32/TO2
P55/A13
P10/ANI0
P54/A12
47
P53/A11
2
P52/A10
P31/TO1
P51/A9
P11/ANI1
P50/A8
1
P47/AD7
P30/TO0
Cautions 1. Connect the VPP pin directly to VSS.
2. Connect the AVDD pin to VDD.
3. Connect the AVSS pin to VSS.
8
µPD78P018FY
A8 to A15:
Address Bus
AD0 to AD7:
ANI0 to ANI7:
Address/Data Bus
Analog Input
ASTB:
AVDD:
Address Strobe
Analog Power Supply
AVREF:
AVSS:
Analog Reference Voltage
Analog Ground
BUSY:
BUZ:
Busy
Buzzer Clock
INTP0 to INTP3:
P00 to P04:
P10 to P17:
Interrupt from Peripherals
Port 0
Port 1
P20 to P27:
P30 to P37:
RESET:
RD:
Reset
Read Strobe
SB0, SB1:
Serial Bus
SCK0, SCK1: Serial Clock
SCL:
Serial Clock
SDA0, SDA1: Serial Data
SI0, SI1:
SO0, SO1:
Serial Input
Serial Output
STB:
TI0 to TI2:
Strobe
Timer Input
TO0 to TO2:
VDD:
Timer Output
Power Supply
Port 2
Port 3
VPP:
VSS:
Programming Power Supply
Ground
P40 to P47:
P50 to P57:
Port 4
Port 5
WAIT:
WR:
Wait
Write Strobe
P60 to P67:
PCL:
Port 6
Programmable Clock
X1, X2:
XT1, XT2:
Crystal (Main System Clock)
Crystal (Subsystem Clock)
9
µPD78P018FY
(2) PROM programming mode
• 64-pin Plastic Shrink DIP (750 mils)
µPD78P018FYCW
• 64-pin Ceramic Shrink DIP (with window) (750 mils)
µPD78P018FYDW
1
64
V SS
2
63
V DD
3
62
4
61
5
60
6
59
7
58
8
57
D0
9
56
D1
10
55
D2
11
54
V SS
D3
12
53
(L)
D4
13
52
Open
D5
14
51
V PP
D6
15
50
(L)
D7
16
49
Open
V SS
17
48
V DD
A0
18
47
(L)
A1
19
46
PGM
A2
20
45
(L)
A3
21
44
A9
A4
22
43
RESET
A5
23
42
A6
24
41
A7
25
40
CE
A8
26
39
OE
A16
27
38
A10
28
37
A11
29
36
A12
30
35
A13
31
34
A15
V SS
32
33
A14
(L)
Cautions 1. (L):
10
(L)
(L)
Independently connect to VSS via a pull-down resistor.
Connect to GND.
2. VSS:
3. RESET: Set to low level.
4. Open:
(L)
Leave open.
µPD78P018FY
• 64-pin Plastic QFP (14 × 14 mm)
µPD78P018FYGC-AB8
63
62
61
60
59
58
57
56
55
(L)
V DD
64
V SS
(L)
• 64-pin Ceramic WQFN (14 × 14 mm)
µPD78P018FYKK-S
D0
1
54
53
52
51
50
49
48
D1
2
47
D2
3
46
V SS
D3
4
45
(L)
D4
5
44
Open
D5
6
43
V PP
D6
7
42
(L)
D7
8
41
Open
V SS
9
40
V DD
A0
10
39
(L)
A1
11
38
PGM
A2
12
37
(L)
A3
13
36
A9
A4
14
35
RESET
A5
15
34
A6
16
17
(L)
Cautions 1. (L):
21
22
23
24
25
26
A16
A10
A11
A12
A13
V SS
A14
A15
27
28
29
30
31
CE
20
OE
19
(L)
18
A8
A7
(L)
33
32
Independently connect to VSS via a pull-down resistor.
2. VSS:
3. RESET:
Connect to GND.
Set to low level.
4. Open:
Leave open.
A0 to A16:
CE:
Address
Chip Enable
RESET:
VDD:
Reset
Power Supply
D0 to D7:
OE:
Data Bus
Output Enable
VPP:
VSS:
Programming Power Supply
Ground
PGM:
Program
11
µPD78P018FY
BLOCK DIAGRAM
TO0/P30
TI0/INTP0/P00
P00
16-bit TIMER/
EVENT COUNTER
PORT0
P01 to P03
P04
TO1/P31
TI1/P33
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 1
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
WATCH TIMER
78K/0
CPU CORE
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
PORT1
P10 to P17
PORT2
P20 to P27
PORT3
P30 to P37
PORT4
P40 to P47
PORT5
P50 to P57
PORT6
P60 to P67
PROM
(60 Kbytes)
SERIAL
INTERFACE 0
SCK0/SCL/P27
SI1/P20
SO1/P21
SCK1/P22
AD0/P40 to
AD7/P47
SERIAL
INTERFACE 1
STB/P23
BUSY/P24
ANI0/P10ANI7/P17
AVDD
A8/P50 to
A15/P57
RAM
(2048 bytes)
EXTERNAL
ACCESS
RD/P64
WR/P65
WAIT/P66
A/D CONVERTER
AVSS
ASTB/P67
AVREF
RESET
INTP0/P00INTP3/P03
INTERRUPT
CONTROL
X1
SYSTEM
CONTROL
X2
XT1/P04
12
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT
CONTROL
XT2
VDD
VSS
VPP
µPD78P018FY
CONTENTS
1.
DIFFERENCES BETWEEN µPD78P018FY AND MASK ROM VERSIONS .................................. 14
2.
PIN FUNCTIONS ............................................................................................................................... 15
2.1 Pins During Normal Operating Mode .............................................................................................................. 15
2.2 Pins During PROM Programming Mode ......................................................................................................... 18
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ............................................................... 19
3.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) .......................................................... 21
4.
INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ............................................ 22
5.
PROM PROGRAMMING ................................................................................................................... 23
5.1 Operating Modes ................................................................................................................................................ 23
5.2 PROM Write Procedure ..................................................................................................................................... 25
5.3 PROM Read Procedure ...................................................................................................................................... 29
6.
PROGRAM ERASURE (FOR µPD78P018FYDW, 78P018FYKK-S) .............................................. 30
7.
OPAQUE FILM ON ERASURE WINDOW (FOR µPD78P018FYDW, 78P018FYKK-S) ................ 30
8.
ONE-TIME PROM VERSION SCREENING ..................................................................................... 30
9.
ELECTRICAL SPECIFICATIONS ..................................................................................................... 31
10. CHARACTERISTIC CURVE (REFERENCE VALUE) ..................................................................... 59
11. PACKAGE DRAWINGS .................................................................................................................... 60
12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 64
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 65
APPENDIX B. RELATED DOCUMENTS ............................................................................................... 70
13
µPD78P018FY
1. DIFFERENCES BETWEEN THE µPD78P018FY AND MASK ROM VERSIONS
The µPD78P018FY is a single-chip microcontroller with an on-chip one-time PROM or EPROM that has program
write, erase, and rewrite capability.
It is possible to make all the functions except for PROM specification and mask option of P60 to P63 pins, the same
as those of mask ROM versions ( µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, and 78018FY)
by setting the internal memory size switching register (IMS) and the internal expansion RAM size switching register
(IXS).
Differences between the µPD78P018FY and mask ROM versions are shown in Table 1-1.
Table 1-1. Differences Between µPD78P018FY and Mask ROM Version
µPD78P018FY
Item
Internal ROM type
Internal ROM capacity
One-time PROM or EPROM
60 Kbytes
Internal high-speed RAM capacity
1024 bytes
Internal expansion RAM capacity
1024 byte
Internal ROM, internal high-speed
RAM capacity changeable with internal
memory size switching register (IMS)
Internal expansion RAM capacity
changeable with internal expansion
RAM size switching register (IXS)
IC pin
VPP pin
On-chip pull-up resistor mask option of
P60 to P63 pins
Electrical specifications
Recommended soldering conditions
Yes
Note 1
Yes
Note 2
No
Yes
No
Mask ROM Versions
Mask ROM
µPD78011FY:
µPD78012FY:
µPD78013FY:
µPD78014FY:
µPD78015FY:
µPD78016FY:
µPD78018FY:
µPD78011FY:
µPD78012FY:
µPD78013FY:
µPD78014FY:
µPD78015FY:
µPD78016FY:
µPD78018FY:
µPD78011FY:
µPD78012FY:
µPD78013FY:
µPD78014FY:
µPD78015FY:
µPD78016FY:
µPD78018FY:
No
8 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
40 Kbytes
48 Kbytes
60 Kbytes
512 bytes
512 bytes
1024 bytes
1024 bytes
1024 bytes
1024 bytes
1024 bytes
No
No
No
No
512 bytes
512 bytes
1024 bytes
No
Yes
No
Yes
See respective data sheet of individual products.
Notes 1. The internal PROM capacity becomes 60 Kbytes and the internal high-speed RAM capacity becomes 1024
bytes by the RESET input.
2. The internal expansion RAM capacity becomes 1024 bytes by the RESET input.
Caution There are differences in noise immunity and noise radiation between the PROM and mask ROM
versions. When pre-producing an application set with the PROM version and then mass-producing
it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples
(not engineering samples) of the mask ROM version.
14
µPD78P018FY
2. PIN FUNCTIONS
2.1
Pins During Normal Operating Mode
(1) Port Pins (1/2)
Pin Name
I/O
Input
P00
Input/
output
P01
P02
P03
P04
Note1
Input
Function
Port 0
5-bit input/
output port
Alternate
Function
After Reset
Input only
Input
INTP0/TI0
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pullup resistor can be specified by means of
software.
Input
INTP1
Input only
INTP2
INTP3
Input
XT1
P10 to P17
Input/
output
Port 1
8-bit input/output port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can
be specified by means of software. Note 2
Input
ANI0 to ANI7
P20
Input/
output
Port 2
8-bit input/output port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can
be specified by means of software.
Input
SI1
P21
P22
P23
SO1
SCK1
STB
P24
BUSY
P25
SI0/SB0/SDA0
P26
SO0/SB1/SDA1
P27
SCK0/SCL
Input/
output
P30
P31
P32
P33
Port 3
8-bit input/output port.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can
be specified by means of software.
Input
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P40 to P47
Input/
output
Port 4
8-bit input/output port.
Input/output can be specified in 8-bit units.
When used as an input port, an on-chip pull-up resistor can
be specified by means of software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
Notes 1. When using the P04/XT1 pin as an input port, set bit 6 (FRC) of the processor clock control register (PCC)
to 1 (Do not use the on-chip feedback resistor of the subsystem clock oscillator).
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, set port 1 to the input
mode. At this time, on-chip pull-up resistors are automatically disconnected.
15
µPD78P018FY
(1) Port Pins (2/2)
I/O
P50 to P57
Input/
output
Port 5
8-bit input/output port.
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor
can be specified by means of software.
Input
A8 to A15
P60
Input/
output
Port 6
8-bit input/output port.
Input/output can be specified
in 1-bit units.
Input
—
P61
P62
Function
Alternate
Function
Pin Name
P63
N-ch open-drain input/
output port.
LEDs can be driven
directly.
After Reset
P64
RD
When used as an input
port, an on-chip pull-up
resistor can be specified
by means of software.
P65
P66
P67
WR
WAIT
ASTB
(2) Non-port Pins (1/2)
Pin Name
INTP0
I/O
Input
INTP1
INTP2
INTP3
SI0
Function
After Reset
External interrupt request input for which the effective
edge (rising edge, falling edge, or both rising edge and
falling edge) can be specified.
Input
Serial interface serial data input.
P02
P03
Input
SI1
SO0
SB1
P25/SB0/SDA0
P20
Output
Serial interface serial data output.
Input
SO1
SB0
P00/TI0
P01
Falling edge detection external interrupt request input.
Input
Alternate
Function
P26/SB1/SDA1
P21
Input/
output
Serial interface serial data input/output.
Input
P25/SI0/SDA0
P26/SO0/SDA1
SDA0
P25/SI0/SB0
SDA1
P26/SO0/SB1
SCK0
SCK1
Input/
output
Serial interface serial clock input/output.
Input
P27/SCL
P22
SCL
P27/SCK0
STB
Output
Serial interface automatic transmit/receive strobe output.
Input
P23
BUSY
Input
Serial interface automatic transmit/receive busy input.
Input
P24
16
µPD78P018FY
(2) Non-port Pins (2/2)
Pin Name
TI0
I/O
Input
Function
External count clock input to 16-bit timer (TM0).
After Reset
Input
Alternate
Function
P00/INTP0
TI1
External count clock input to 8-bit timer (TM1).
P33
TI2
External count clock input to 8-bit timer (TM2).
P34
TO0
Output
16-bit timer (TM0) output (shared as 14-bit PWM output).
Input
P30
TO1
8-bit timer (TM1) output.
P31
TO2
8-bit timer (TM2) output.
P32
Input
PCL
Output
Clock output (for main system clock, subsystem clock trimming).
BUZ
Output
Buzzer output.
AD0 to AD7
Input/
output
Lower address/data bus for expanding memory externally.
Input
P40 to P47
A8 to A15
Output
Higher address bus for expanding memory externally.
Input
P50 to P57
RD
Output
Strobe signal output for read from external memory.
Input
P64
WR
WAIT
P36
Strobe signal output for writing to external memory.
Input
P35
P65
Wait insertion at external memory access.
Input
P66
P67
P10 to P17
ASTB
Output
Strobe output that externally latches address information output to port
4 and port 5 to access external memory.
Input
ANI0 to ANI7
Input
A/D converter analog input.
Input
AVREF
Input
A/D converter reference voltage input.
—
—
AVDD
—
A/D converter analog power supply. Connect to VDD.
—
—
AVSS
—
A/D converter ground potential. Connect to VSS.
—
—
RESET
Input
System reset input.
—
—
X1
Input
Connecting crystal resonator for main system clock oscillation.
—
—
X2
—
—
—
XT1
Input
XT2
—
VDD
—
VPP
—
Connecting crystal resonator for subsystem clock oscillation.
Input
P04
—
—
Positive power supply.
—
—
High voltage applied during program write/verify. In normal operating
—
—
—
—
mode, connect to VSS directly.
VSS
—
Ground potential.
17
µPD78P018FY
2.2
Pins During PROM Programming Mode
Pin
I/O
Function
RESET
Input
Sets PROM programming mode.
When +5 V or +12.5 V is applied to the VPP and low level is applied to RESET pin, microcontroller
is shifted to PROM programming mode.
VPP
Input
Applies high voltage during PROM programming mode setting and program write/verify.
A0 to A16
Input
Address bus
D0 to D7
Input/
output
Data bus
CE
Input
PROM enable input/program pulse input.
OE
Input
Read strobe input to PROM.
PGM
Input
Program/program inhibit input in PROM programming mode.
VDD
—
Positive power supply
VSS
—
Ground potential
18
µPD78P018FY
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the input/output circuit configuration of each type, see Figure 2-1.
Table 2-1. Types of Pin I/O Circuits
Pin Name
Input/output
Circuit Type
I/O
Recommended Connection when Not Used
P00/INTP0/TI0
2
Input
Connect to VSS .
P01/INTP1
8-A
Input/output
Independently connect to VSS via a resistor.
P04/XT1
16
Input
Connect to VDD.
P10/ANI0 to P17/ANI7
11
Input/output
Independently connect to VDD or VSS via a resistor.
P20/SI1
8-A
P21/SO1
5-A
P22/SCK1
8-A
P23/STB
5-A
P24/BUSY
8-A
P25/SI0/SB0/SDA0
10-A
P02/INTP2
P03/INTP3
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/TO0
5-A
P31/TO1
P32/TO2
P33/TI1
8-A
P34/TI2
P35/PCL
5-A
P36/BUZ
P37
P40/AD0 to P47/AD7
5-E
Independently connect to VDD via a resistor.
P50/A8 to P57/A15
5-A
Independently connect to VDD or VSS via a resistor.
P60 to P63
13-D
Independently connect to VDD via a resistor.
P64/RD
5-A
Independently connect to VDD or VSS via a resistor.
P65/WR
P66/WAIT
P67/ASTB
RESET
2
XT2
16
AV REF
Input
—
—
—
Leave open.
Connect to VSS .
AV DD
Connect to VDD .
AV SS
Connect to VSS .
VPP
Connect directly to VSS.
19
µPD78P018FY
Figure 2-1. Pin Input/Output Circuits
Type 2
Type 10-A
V DD
pullup
enable
IN
P-ch
V DD
data
P-ch
IN / OUT
Schmitt-Triggered Input with Hysteresis Characteristic
V DD
Type 5-A
pullup
enable
open drain
output disable
Type 11
IN / OUT
P-ch
IN / OUT
N-ch
N-ch
P-ch
+
–
input
enable
Type 5-E
data
output
disable
Comparator
N-ch
VREF (Threshold Voltage)
input
enable
pullup
enable
P-ch
V DD
P-ch
data
V DD
output
disable
V DD
pullup
enable
P-ch
data
N-ch
Type 13-D
V DD
IN / OUT
P-ch
data
output disable
V DD
N-ch
P-ch
V DD
IN / OUT
output
disable
N-ch
RD
P-ch
Middle-Voltage Input Buffer
Type 8-A
Type 16
V DD
pullup
enable
feedback
cut-off
P-ch
P-ch
V DD
data
P-ch
IN / OUT
output
disable
N-ch
XT1
20
XT2
µPD78P018FY
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register is used to disable the use of part of the internal memory by software. By setting this register (IMS),
it is possible to get the same memory map as that of the mask ROM versions with a different internal memory (ROM,
RAM).
IMS is set with an 8-bit memory manipulate instruction.
RESET input sets IMS to CFH.
Figure 3-1. Internal Memory Size Switching Register Format
Symbol
IMS
7
6
5
RAM2 RAM1 RAM0
4
0
3
2
1
0
Address After Reset R/W
ROM3 ROM2 ROM1 ROM0
FFF0H
CFH
ROM3 ROM2 ROM1 ROM0
W
Selection of Internal ROM Capacity
0
0
1
0
8 Kbytes
0
1
0
0
16 Kbytes
0
1
1
0
24 Kbytes
1
0
0
0
32 Kbytes
1
0
1
0
40 Kbytes
1
1
0
0
48 Kbytes
1
1
1
0
56 Kbytes
1
1
1
1
60 Kbytes
Other than above
RAM2 RAM1 RAM0
Setting prohibited
Selection of Internal High-Speed RAM
Capacity
0
1
0
512 bytes
1
1
0
1024 bytes
Other than above
Note
Setting prohibited
Note If external device expansion functions are to be employed for the µPD78P018FY, set the size of the internal
ROM to 56 Kbytes or below using the internal memory size switching register (IMS).
Table 3-1 shows the setting values of IMS which make the memory map the same as that of the mask ROM versions.
Table 3-1. Internal Memory Size Switching Register Setting Values
Target Mask ROM Versions
IMS Setting Value
µPD78011FY
42H
µPD78012FY
44H
µPD78013FY
C6H
µPD78014FY
C8H
µPD78015FY
CAH
µPD78016FY
CCH
µPD78018FY
CFH
21
µPD78P018FY
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS)
This register is used to disable the use of part of the internal expansion RAM capacity by software. By setting this
register (IXS), it is possible to get the same memory map as that of the mask ROM versions with a different internal
expansion RAM.
IXS is set with an 8-bit memory manipulate instruction.
RESET input sets IXS to 0AH.
Figure 4-1. Internal Expansion RAM Size Switching Register Format
IXS
7
6
5
4
0
0
0
0
3
2
1
0
Address After Reset R/W
FFF4H
IX
IX
IX
IX
RAM3 RAM2 RAM1 RAM0
0AH
W
IX
IX
IX
IX
RAM3 RAM2 RAM1 RAM0
Selection of Internal Expansion
RAM Capacity
1
0
1
0
1024 bytes (F400H to F7FFH)
1
0
1
1
512 bytes (F600H to F7FFH)
1
1
0
0
0 bytes
Other than above
Setting prohibited
Table 4-1 shows the setting values of IXS which make the memory map the same as that of the mask ROM versions.
Table 4-1. Internal Expansion RAM Size Switching Register Setting Values
Target Mask ROM Versions
µPD78011FY
IXS Setting Value
0CH
Note
µPD78012FY
µPD78013FY
µPD78014FY
µPD78015FY
0BH
µPD78016FY
µPD78018FY
0AH
Note Even if a program for the µPD78P018FY in which "MOV IXS, #0CH"
is written is executed in the µPD78011FY, 78012FY, 78013FY, and
78014FY, the operations are not affected.
22
µPD78P018FY
5. PROM PROGRAMMING
The µPD78P018FY has an internal 60-Kbyte PROM as a program memory. For programming, set the PROM
programming mode by setting the VPP and RESET pins. For unused pin connection, refer to “PIN CONFIGURATION
(Top View) (2) PROM programming mode.”
Caution
5.1
When writing in a program, use locations 0000H-EFFFH (specify the last address as EFFFH). You
cannot write in using a PROM programmer that cannot specify the addresses to write.
Operating Modes
When +5 V or +12.5 V is applied to the VPP pin and the low-level signal is applied to the RESET pin, the PROM
programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE, and
PGM pins are set as shown.
Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 5-1. Operating Modes of PROM Programming
Pin
RESET
VPP
VDD
CE
OE
PGM
D0 to D7
L
+12.5 V
+6.5 V
H
L
H
Data input
Page write
H
H
L
High-impedance
Byte write
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
×
H
H
High-impedance
×
L
L
L
L
H
Data output
Output disable
L
H
×
High-impedance
Standby
H
×
×
High-impedance
Operating Mode
Page data latch
Read
+5 V
+5 V
× : L or H
23
µPD78P018FY
(1) Read mode
Read mode is set if CE = L, OE = L is set.
(2) Output disable mode
Data output becomes high-impedance, and is in the output disable mode, if OE = H is set.
Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µPD78P018FYs are
connected to the data bus.
(3) Standby mode
Standby mode is set if CE = H is set.
In this mode, data outputs become high-impedance irrespective of the OE status.
(4) Page data latch mode
Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode.
In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit.
(5) Page write mode
After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by
applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can
be performed, if CE = L, OE = L are set.
If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations should
be executed repeatedly.
(6) Byte write mode
Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L,
OE = H. Then, program verification can be performed if OE = L is set.
If programming is not performed by a one-time program pulse, X (X ≤ 10) write and verification operations should
be executed repeatedly.
(7) Program verify mode
Program verify mode is set if CE = L, PGM = H, OE = L are set. In this mode, check if a write operation is performed
correctly, after the write.
(8) Program inhibit mode
Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple µPD78P018FYs are connected
in parallel and a write is performed to one of those devices.
When a write operation is performed, the page write mode or byte write mode described above is used. At this time,
a write is not performed to a device which has the PGM pin driven high.
24
µPD78P018FY
5.2
PROM Write Procedure
Figure 5-1. Page Program Mode Flow Chart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Address = Address + 1
Latch
No
X=X+1
X = 10 ?
0.1-ms program pulse
Verify 4 bytes
Yes
Fail
Pass
No
Address = N ?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify all bytes
Fail
All Pass
Write end
Defective product
G = Start address
N = Program last address
25
µPD78P018FY
Figure 5-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
A2 to A16
A0, A1
Hi-Z
D0 to D7
Data Input
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
26
Data Output
µPD78P018FY
Figure 5-3. Byte Program Mode Flow Chart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
X=X+1
No
X = 10 ?
0.1-ms program pulse
Yes
Address = Address + 1
Fail
Verify
Pass
No
Address = N ?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
Verify all bytes
Fail
All Pass
Write end
Defective product
G = Start address
N = Program last address
27
µPD78P018FY
Figure 5-4. Byte Program Mode Timing
Program
Program Verify
A0 to A16
D0 to D7
Data Input
Hi-Z
Data Output
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
Cautions 1. VDD should be applied before VPP and cut after VPP.
2. VPP must not exceed +13.5 V including overshoot.
3. Removing and reinserting while +12.5 V is applied to VPP may adversely affect reliability.
28
µPD78P018FY
5.3
PROM Read Procedure
The contents of PROM are readable to the external data bus (D0 to D7) according to the read procedure shown
below.
(1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown
in “PIN CONFIGURATION (Top View) (2) PROM programming mode”.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input address of read data into the A0 to A16 pins.
(4) Read mode
(5) Output data to D0 to D7 pins.
The timings of the above steps (2) to (5) are shown in Figure 5-5.
Figure 5-5. PROM Read Timings
Address Input
A0 to A16
CE (Input)
OE (Input)
D0 to D7
Hi-Z
Data Output
Hi-Z
29
µPD78P018FY
6. PROGRAM ERASURE (FOR µPD78P018FYDW, 78P018FYKK-S)
The µPD78P018FYDW, 78P018FYKK-S are capable of erasing (FFH) the contents of data written in a program
memory and rewriting.
When erasing the contents of data, irradiate light having a wavelength of less than about 400 nm to the erasure
window. Normally, irradiate ultraviolet rays of 254 nm wavelength. Volume of irradiation required to completely erase
the contents of data is as follows:
• UV intensity × erasing time: 30 W • s/cm2 or more
• Erasing time: 40 min. or longer (When a UV lamp of 12 mW/cm2 is used. However, a longer time may
be needed because of deterioration in performance of the UV lamp, contamination of
the erasure window, etc.)
When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasing window. Further, if a filter
is provided for a UV lamp, irradiate the ultraviolet rays after removing the filter.
7. OPAQUE FILM ON ERASURE WINDOW (FOR µPD78P018FYDW, 78P018FYKK-S)
To protect from unintentional erasure by rays other than that of the lamp for erasing EPROM contents, or to protect
internal circuit other than EPROM from misoperating by rays, cover the erasure window with an opaque film when
EPROM contents erasure is not performed.
8. ONE-TIME PROM VERSION SCREENING
The one-time PROM versions (µPD78P018FYCW, 78P018FYGC-AB8) cannot be tested completely by NEC before
it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing necessary
data and performing high-temperature storage under the condition below.
Storage Temperature
Storage Time
125°C
24 hours
NEC provides for a fee one-time PROM writing, marking, screening, and verify service for products designated as
“QTOP Microcontrollers.” For details, contact an NEC sales representative.
30
µPD78P018FY
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Supply voltage
Ratings
Unit
VDD
–0.3 to +7.0
V
VPP
–0.3 to +13.5
V
AVDD
–0.3 to VDD + 0.3
V
AVREF
–0.3 to VDD + 0.3
V
AVSS
–0.3 to +0.3
V
Input voltage
Test Conditions
P00 to P04, P10 to P17, P20 to P27, P30 to P37,
VI1
P40 to P47, P50 to P57, P64 to P67, X1, X2,
–0.3 to V DD + 0.3
V
–0.3 to +16
V
–0.3 to +13.5
V
XT2, RESET
VI2
P60 to P63
VI3
A9
Open-drain
PROM
programming mode
Output voltage
Analog input
voltage
Output
current, high
VO
VAN
IOH
Output
current, low
–0.3 to VDD + 0.3
V
AVSS – 0.3 to AV REF + 0.3
V
1 pin
–10
mA
Total for P10 to P17, P20 to P27, P30 to P37
–15
mA
Total for P01 to P03, P40 to P47, P50 to P57, P60 to P67
P10 to P17
Analog input pin
–15
mA
Peak value
30
mA
rms value
15
mA
100
mA
rms value
70
mA
Total for P01 to P03, P56, P57,
Peak value
100
mA
P60 to P67
rms value
70
mA
Total for P01 to P03,
Peak value
50
mA
P64 to P67
rms value
20
mA
Total for P10 to P17, P20 to P27,
Peak value
50
mA
P30 to P37
rms value
20
mA
1 pin
Total for P40 to P47, P50 to P55 Peak value
IOLNote
Operating ambient
temperature
TA
–40 to +85
°C
Storage
temperature
Tstg
–65 to +150
°C
Note The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty
Caution Product quality may suffer if the absolute maximum rating is exceed even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
31
µPD78P018FY
Capacitance ( TA = 25°C, VDD = VSS = 0 V )
Parameter
Symbol
Input capacitance
CIN
Test Conditions
MIN.
TYP.
f = 1 MHz Unmeasured pins returned to 0 V.
I/O capacitance
Unit
15
pF
15
pF
20
pF
P01 to P03, P10 to P17,
CIO
f = 1 MHz
P20 to P27, P30 to P37,
Unmeasured pins
P40 to P47, P50 to P57,
returned to 0 V.
P64 to P67
P60 to P63
Remark
MAX.
Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port functions.
Main System Clock Oscillator Characteristics ( TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Circuit
Resonator
Ceramic
resonator
X2
C2
Crystal
resonator
X2
C2
X1 VPP
C1
X1 VPP
C1
Parameter
Oscillation
frequency (fX ) Note 1
Test Conditions
MIN.
TYP.
MAX.
2.7 V ≤ VDD ≤ 5.5 V
1
10
1.8 V ≤ VDD < 2.7 V
1
5
Unit
MHz
Oscillation
stabilization time Note 2
After VDD reaches oscillator voltage range MIN.
Oscillation
frequency (fX ) Note 1
2.7 V ≤ VDD ≤ 5.5 V
1
10
1.8 V ≤ VDD < 2.7 V
1
5
Oscillation
stabilization time Note 2
VDD = 4.5 to 5.5 V
4
ms
MHz
10
ms
30
External
clock
X2
X1
µPD74HCU04
X1 input
frequency (fX ) Note 1
1.0
10.0
MHz
X1 input
high-/low-level width
(tXH , tXL)
45
500
ns
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire the area enclosed by the broken line in
the above figures as follows to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
•
•
•
•
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always keep the ground point of the oscillator capacitor to the same potential as VSS.
Do not ground the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched again to the main system clock after the oscillation
stabilization time is secured by the program.
32
µPD78P018FY
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Circuit
Resonator
Crystal
resonator
VPP XT2
XT1
R1
C4
External
clock
µPD74HCU04
Test Conditions
Oscillation
frequency (fXT) Note 1
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
VDD = 4.5 to 5.5 V
Oscillation
Note
2
stabilization time
C3
XT2
Parameter
XT1
s
10
XT1 input
frequency (fXT) Note 1
32
100
kHz
XT1 input
high-/low-level width
(tXTH , tXTL)
5
15
µs
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wire the area enclosed by the broken line in the
above figures as follows to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
•
•
•
•
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always keep the ground point of the oscillator capacitor to the same potential as VSS.
Do not ground the capacitor to a ground pattern in which a high current flows.
Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to malfunction due to noise than the main system clock
oscillator.
Particular care is therefore required with the wiring method when the subsystem clock is
used.
33
µPD78P018FY
RECOMMENDED OSCILLATOR CONSTANTS
Main system clock: Ceramic resonator (TA = –40 to +85°C)
Manufacturer
TDK
Murata Mfg.
Co., Ltd.
Name
Recommended
Frequency Oscillator Constants
(MH Z)
C1 (pF)
C2 (pF)
Oscillation
Voltage Range
Remarks
MIN. (V) MAX. (V)
CCR4.0MC3
4.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, surface mounting type
FCR4.0MC5
4.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, insertion type
CCR4.19MC3
4.19
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, surface mounting type
FCR4.19MC5
4.19
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, insertion type
CCR5.00MC3
5.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, surface mounting type
FCR5.00MC5
5.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, insertion type
CCR8.00MC
8.00
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, surface mounting type
FCR8.00MC5
8.00
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, insertion type
CCR8.38MC
8.38
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, surface mounting type
FCR8.38MC5
8.38
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, insertion type
CCR10.00MC
10.00
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, surface mounting type
FCR10.00MC5
10.00
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, insertion type
CSA4.00MG
4.00
30
30
1.8
5.5
Insertion type
CST4.00MGW
4.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, insertion type
CSA4.19MG
4.19
30
30
1.8
5.5
Insertion type
CST4.19MGW
4.19
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, insertion type
CSA5.00MG
5.00
30
30
1.8
5.5
Insertion type
CST5.00MGW
5.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, insertion type
CSA8.00MTZ
8.00
30
30
2.7
5.5
Insertion type
CST8.00MTW
8.00
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, insertion type
CSA8.38MTZ
8.38
30
30
2.7
5.5
Insertion type
CST8.38MTW
8.38
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, insertion type
CSA10.00MTZ
10.00
30
30
2.7
5.5
Insertion type
CST10.00MTW
10.00
On-Chip
On-Chip
2.7
5.5
On-chip capacitor, insertion type
Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation, but
do not guarantee oscillation frequency accuracy. If oscillation frequency accuracy is required for
actual circuits, it is necessary to adjust the oscillation frequency of the oscillator in the actual circuit.
Please contact directly the manufacturer of the resonator to be used.
34
µPD78P018FY
Main system clock: Ceramic resonator (TA = –20 to +80°C)
Manufacturer
Kyocera
Corporation
Name
Recommended
Oscillation
Frequency Oscillator Constants Voltage Range
(MHZ)
C1 (pF) C2 (pF) MIN. (V) MAX. (V)
Remarks
PBRC4.00A
4.00
33
33
1.8
5.5
Surface mounting type
PBRC4.00B
4.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, surface mounting type
KBR-4.00MSA
4.00
33
33
1.8
5.5
Insertion type
KBR-4.00MKS
4.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, insertion type
PBRC5.00A
5.00
33
33
1.8
5.5
Surface mounting type
PBRC5.00B
5.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, surface mounting type
KBR-5.00MSA
5.00
33
33
1.8
5.5
Insertion type
KBR-5.00MKS
5.00
On-Chip
On-Chip
1.8
5.5
On-chip capacitor, insertion type
KBR-8M
8.00
33
33
2.7
5.5
Insertion type
KBR-10M
10.00
33
33
2.7
5.5
Insertion type
Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscillation. The
oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency
precision, the oscillation frequency must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.
35
µPD78P018FY
DC Characteristics (T A = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MAX.
Unit
0.7VDD
VDD
V
0.8VDD
VDD
V
P00 to P03, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V
0.8VDD
VDD
V
P33, P34, RESET
0.85V DD
VDD
V
VDD = 2.7 to 5.5 V
0.7VDD
15
V
0.8VDD
15
V
VDD = 2.7 to 5.5 V
VDD – 0.5
VDD
V
VDD – 0.2
VDD
V
4.5 V ≤ VDD ≤ 5.5 V
0.8VDD
VDD
V
2.7 V ≤ VDD < 4.5 V
0.9VDD
VDD
V
1.8 V ≤ VDD < 2.7 V Note
0.9VDD
VDD
V
0
0.3VDD
V
P50 to P57, P64 to P67
0
0.2V DD
V
P00 to P03, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V
0
0.2VDD
V
P33, P34, RESET
Input voltage, VIH1
P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V
high
P35 to P37, P40 to P47,
P50 to P57, P64 to P67
VIH2
VIH3
P60 to P63
(N-ch open-drain)
VIH4
VIH5
X1, X2
XT1/P04, XT2
Input voltage, VIL1
P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V
low
P35 to P37, P40 to P47,
VIL2
VIL3
VIL4
VIL5
Output
VOH1
voltage, high
Output
VOL1
P60 to P63
X1, X2
XT1/P04, XT2
MIN.
TYP.
0
0.15VDD
V
4.5 V ≤ VDD ≤ 5.5 V
0
0.3VDD
V
2.7 V ≤ VDD < 4.5 V
0
0.2VDD
V
0
0.1VDD
V
VDD = 2.7 to 5.5 V
4.5 V ≤ V DD ≤ 5.5 V
0
0.4
V
0
0.2
V
0
0.2VDD
V
2.7 V ≤ V DD < 4.5 V
0
0.1VDD
V
1.8 V ≤ V DD < 2.7 V Note
0
0.1VDD
V
VDD = 4.5 to 5.5 V, I OH = –1 mA
VDD – 1.0
V
IOH = –100 µA
VDD – 0.5
V
P50 to P57, P60 to P63
voltage, low
VDD = 4.5 to 5.5 V,
0.4
2.0
V
0.4
V
0.2VDD
V
0.5
V
IOL = 15 mA
VOL2
P01 to P03, P10 to P17, P20 to P27,
VDD = 4.5 to 5.5 V,
P30 to P37, P40 to P47, P64 to P67
IOL = 1.6 mA
SB0, SB1, SCK0
VDD = 4.5 to 5.5 V, opendrain pulled-up (R = 1 kΩ)
VOL3
Note
IOL = 400 µA
When using XT1/P04 as P04, input the inverse phase of P04 should be input to XT2 using an inverter.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
36
µPD78P018FY
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Input leakage ILIH1
Test Conditions
MIN.
TYP.
MAX.
Unit
3
µA
X1, X2, XT1/P04, XT2
20
µA
VIN = 15 V
P60 to P63
80
µA
VIN = 0 V
P00 to P03, P10 to P17,
–3
µA
VIN = VDD
current, high
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, RESET
ILIH2
ILIH3
Input leakage ILIL1
current, low
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67, RESET
–20
µA
–3 Note
µA
VOUT = VDD
3
µA
VOUT = 0 V
–3
µA
90
kΩ
ILIL2
X1, X2, XT1/P04, XT2
ILIL3
P60 to P63
Output leakage ILOH
current, high
Output leakage ILOL
current, low
Software
pull-up resistor
R
VIN = 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37,
15
40
P40 to P47, P50 to P57, P64 to P67
Note For pins P60 to P63, a low-level input leak current of –200 µA (MAX.) flows only during the 3 clocks (no-wait
time) after an instruction has been executed to read out port 6 (P6) or port mode register 6 (PM6). Outside
the period of 3 clocks following execution a read-out instruction, the current is –3 µA (MAX.).
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
37
µPD78P018FY
DC Characteristics (T A = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Supply
current
Symbol
IDD1
Note 1
IDD2
IDD3
Test Conditions
IDD6
MAX.
Unit
VDD = 5.0 V ± 10 % Note 2
12.0
24.0
mA
oscillation operation mode
VDD = 3.0 V ± 10 %
Note 3
1.4
2.8
mA
10.00-MHz crystal
VDD = 5.0 V ± 10 %
Note 2
4.0
8.0
mA
oscillation HALT mode
VDD = 3.0 V ± 10 % Note 3
1.4
2.8
mA
VDD = 5.0 V ± 10 %
150
300
µA
VDD = 3.0 V ± 10 %
100
200
µA
VDD = 2.0 V ± 10 %
60
120
µA
VDD = 5.0 V ± 10 %
25
50
µA
VDD = 3.0 V ± 10 %
5
15
µA
VDD = 2.0 V ± 10 %
2.5
10
µA
VDD = 5.0 V ± 10 %
2.0
30
µA
STOP mode when using feedback VDD = 3.0 V ± 10 %
1.0
10
µA
resistor
VDD = 2.0 V ± 10 %
0.5
10
µA
XT1 = VDD
VDD = 5.0 V ± 10 %
0.1
30
µA
STOP mode when not using
VDD = 3.0 V ± 10 %
0.05
10
µA
feedback resistor
VDD = 2.0 V ± 10 %
0.05
10
µA
32.768-kHz crystal
Note 4
32.768-kHz crystal
oscillation HALT mode
IDD5
TYP.
10.00-MHz crystal
oscillation operation mode
IDD4
MIN.
Note 4
XT1 = VDD
Notes 1. Refers to the current flowing to the VDD pin. The current flowing to the on-chip pull-up resistors, ports,
and A/D converter is not included.
2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H)
3. When operating at low-speed mode (when PCC is set to 04H)
4. When main system clock operation stopped.
38
µPD78P018FY
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
(Min. instruction
Test Conditions
MIN.
TYP.
Operating with main system
3.5 V ≤ VDD ≤ 5.5 V
0.4
64
µs
2.7 V ≤ VDD < 3.5 V
0.8
64
µs
1.8 V ≤ VDD < 2.7 V
2.0
64
µs
125
µs
40 Note 1
Operating with subsystem clock
µs
µs
3.5 V ≤ VDD ≤ 5.5 V
2/f sam+0.1
2.7 V ≤ VDD < 3.5 V
2/f sam+0.2 Note 2
width
1.8 V ≤ VDD < 2.7 V
2/f sam+0.5 Note 2
TI1, TI2 input
VDD = 4.5 to 5.5 V
0
4
MHz
0
275
kHz
tTIH1,
VDD = 4.5 to 5.5 V
100
ns
1.8
µs
high-/low-level tTIL1
width
Interrupt
tINTH,
request input
INTP0
tINTL
width
INTP1 to INTP3, KR0 to KR7
tRSL
3.5 V ≤ VDD ≤ 5.5 V 2/fsam+0.1 Note 2
µs
2.7 V ≤ VDD < 3.5 V 2/fsam+0.2
1.8 V ≤ VDD < 2.7 V 2/fsam+0.5 Note 2
µs
VDD = 2.7 to 5.5 V
10
µs
20
µs
10
µs
20
µs
Note 2
high-/low-level
RESET low-
µs
fTI1
frequency
TI1, TI2 input
122
Note 2
high-/low-level tTIL0
tTIH0,
Unit
clock
execution time)
TI0 input
MAX.
VDD = 2.7 to 5.5 V
level width
µs
Notes 1. Value when an external clock is used. This value is 114 µs (MIN.) when a crystal resonator is used.
2. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam
is possible between fX/2N+1, fX/64, and fX/128 (when N= 0 to 4).
TCY vs. VDD (At main system clock operation)
60.0
Operation Guaranteed
Range
Cycle Time TCY [µ s]
10.0
5.0
1.0
0.5
0.1
0
1.0
3.0 3.5 4.0
2.0
1.8
5.0 5.5 6.0
2.7
Supply Voltage VDD [V]
39
µPD78P018FY
(2) Read/Write Operation (TA = –40 to +85°C, VDD = 2.7 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
0.5tCY
ns
Address setup time
tADS
0.5tCY–30
ns
Address hold time
tADH
50
Data input time from address
tADD1
(2.5+2n)tCY–50
ns
tADD2
(3+2n)tCY–100
ns
Data input time from RD↓
ns
tRDD1
(1+2n)tCY–25
ns
tRDD2
(2.5+2n)tCY–100
ns
Read data hold time
tRDH
0
ns
RD low-level width
tRDL1
(1.5+2n)tCY–20
ns
tRDL2
(2.5+2n)tCY–20
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
ns
tRDWT1
0.5tCY
ns
tRDWT2
1.5tCY
ns
0.5tCY
ns
(2+2n)tCY
ns
tWRWT
WAIT low-level width
tWTL
(0.5+2n)tCY+10
Write data setup time
tWDS
100
ns
Write data hold time
tWDH
20
ns
WR low-level width
Load resistance ≥ 5 kΩ
tWRL
(2.5+2n)tCY –20
ns
RD↓ delay time from ASTB↓
tASTRD
0.5tCY–30
ns
WR↓ delay time from ASTB↓
tASTWR
1.5tCY–30
ns
ASTB↑ delay time from
RD↑ in external fetch
tRDAST
tCY–10
tCY+40
ns
Address hold time from
RD↑ in external fetch
tRDADH
tCY
tCY+50
ns
0.5tCY+5
0.5tCY+30
ns
0.5tCY+15
0.5tCY+90
ns
Write data output time from RD↑
Write data output time from WR↓
tRDWD
tWRWD
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
30
ns
90
ns
tCY
tCY+60
ns
Address hold time from WR↑
tWRADH
tCY
tCY+100
ns
RD↑ delay time from WAIT↑
tWTRD
0.5tCY
2.5tCY+80
ns
WR↑ delay time from WAIT↑
tWTWR
0.5tCY
2.5tCY+80
ns
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
40
VDD = 4.5 to 5.5 V
5
15
µPD78P018FY
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) Serial Interface Channel 0
(i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY1
SCK0 high-/low-level
tKH1,
width
tKL1
SI0 setup time
tSIK1
(to SCK0↑)
SI0 hold time
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
tKCY1/2–50
ns
VDD = 4.5 to 5.5 V
tKCY1/2–100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
tKSI1
(from SCK0↑)
SO0 output delay time
tKSO1
C = 100 pF Note
300
ns
MAX.
Unit
from SCK0↓
Note C is the load capacitance of SCK0 and SO0 output lines.
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
Symbol
tKCY2
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
SCK0 high-/low-level
tKH2,
4.5 V ≤ VDD ≤ 5.5 V
400
ns
width
tKL2
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
SI0 setup time
tSIK2
VDD = 2.0 to 5.5 V
(to SCK0↑)
SI0 hold time
tKSI2
1600
ns
2400
ns
100
ns
150
ns
400
ns
(from SCK0↑)
SO0 output delay time
tKSO2
C = 100 pF Note VDD = 2.0 to 5.5 V
300
500
ns
tR2,
When external device
160
ns
tF2
expansion function is used
700
ns
1000
ns
from SCK0↓
SCK0 rise/fall time
When external When 16-bit timer
ns
device expansion output function is
function is not
used
used
When 16-bit timer
output function is
not used
Note C is the load capacitance of SO0 output line.
41
µPD78P018FY
(iii) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY3
Test Conditions
R = 1 kΩ,
C = 100 pF
SCK0 high-level width
Note
tKH3
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 5.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
tKCY3/2–160
ns
VDD = 2.7 to 5.5 V
tKCY3/2–190
ns
tKCY3/2–50
ns
SCK0 low-level width
tKL3
VDD = 4.5 to 5.5 V
tKCY3/2–100
ns
SB0, SB1 setup time
tSIK3
4.5 V ≤ VDD ≤ 5.5 V
300
ns
2.7 V ≤ VDD < 4.5 V
350
ns
2.0 V ≤ VDD < 2.7 V
400
ns
500
ns
600
ns
(to SCK0↑)
SB0, SB1 hold time
tKSI3
(from SCK0↑)
0
SB0, SB1 output delay tKSO3
300
ns
time from SCK0↓
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output lines.
(iv) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
SCK0 cycle time
SCK0 high-level width
Symbol
tKCY4
tKH4
Test Conditions
SB0, SB1 setup time
tKL4
tSIK4
MAX.
Unit
1600
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
650
ns
2.7 V ≤ VDD ≤ 5.5 V
ns
1300
ns
2100
ns
2.7 V ≤ VDD ≤ 5.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1600
ns
2400
ns
100
ns
VDD = 2.0 to 5.5 V
(to SCK0↑)
SB0, SB1 hold time
TYP.
2.7 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 2.7 V
SCK0 low-level width
MIN.
tKSI4
150
ns
tKCY4/2
ns
(from SCK0↑)
SB0, SB1 output delay tKSO4
time from SCK0↓
SCK0 rise/fall time
R = 1 kΩ,
C = 100 pF
Note
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
2.0 V ≤ VDD < 4.5 V
0
500
ns
0
800
ns
160
ns
700
ns
1000
ns
tR4,
When external device
tF4
expansion function is used
When external
When 16-bit timer
device expansion
output function is
function is not
used
used
When 16-bit timer
output function is
not used
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines.
42
µPD78P018FY
(v) I2C bus mode (SCL... Internal clock output)
Parameter
SCL cycle time
SCL high-level width
SCL low-level width
Symbol
tKCY5
Test Conditions
MIN.
TYP.
MAX.
Unit
R = 1 kΩ,
2.7 V ≤ VDD ≤ 5.5 V
10
µs
C = 100 pF Note
2.0 V ≤ VDD < 2.7 V
20
µs
tKH5
VDD = 2.7 to 5.5 V
tKL5
VDD = 4.5 to 5.5 V
30
µs
tKCY5–160
ns
tKCY5–190
ns
tKCY5–50
ns
tKCY5–100
ns
SDA0, SDA1 setup time tSIK5
2.7 V ≤ VDD ≤ 5.5 V
200
ns
(to SCL↑)
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
0
ns
SDA0, SDA1 hold time tKSI5
(from SCL↓)
SDA0, SDA1 output
tKSO5
delay time from SCL↓
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
2.0 V ≤ VDD < 4.5 V
0
500
ns
0
600
SDA0, SDA1↓ from SCL↑ tKSB
ns
200
ns
400
ns
500
ns
500
ns
or SDA0, SDA1↑ from SCL↑
SCL↓ from SDA0, SDA1↓ tSBK
VDD = 2.0 to 5.5 V
SDA0, SDA1 high-level tSBH
width
Note R and C are the load resistance and load capacitance of the SCL, SDA0, and SDA1 output lines.
(vi) I2C bus mode (SCL... External clock input)
Parameter
Symbol
SCL cycle time
tKCY6
SCL high-/low-level
tKH6,
width
tKL6
SDA0, SDA1 setup time tSIK6
Test Conditions
VDD = 2.0 to 5.5 V
VDD = 2.0 to 5.5 V
(to SCL↑)
SDA0, SDA1 hold time tKSI6
MIN.
TYP.
MAX.
Unit
1000
ns
400
ns
600
ns
200
ns
300
ns
0
ns
(from SCL↓)
SDA0, SDA1 output
tKSO6
delay time from SCL↓
R = 1 kΩ,
C = 100 pF
Note
4.5 V ≤ VDD ≤ 5.5 V
0
300
ns
2.0 V ≤ VDD < 4.5 V
0
500
ns
0
600
ns
SDA0, SDA1↓ from SCL↑ tKSB
200
ns
400
ns
or SDA0, SDA1↑ from SCL↑
SCL↓ from SDA0, SDA1↓ tSBK
SDA0, SDA1 high-level tSBH
VDD = 2.0 to 5.5 V
VDD = 2.0 to 5.5 V
width
SCL rise/fall time
500
ns
500
ns
800
tR6,
When external device
tF6
expansion function is used
When external
When 16-bit timer
device expansion
output function is
function is not
used
used
When 16-bit timer
ns
160
ns
700
ns
1000
ns
output function is
not used
Note R and C are the load resistance and load capacitance of the SDA0 and SDA1 output lines.
43
µPD78P018FY
(b) Serial Interface Channel 1
(i) 3-wire serial I/O mode (SCK1... Internal clock output)
Parameter
SCK1 cycle time
Symbol
tKCY7
SCK1 high-/low-level
tKH7,
width
tKL7
SI1 setup time
tSIK7
(to SCK1↑)
SI1 hold time
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
VDD = 4.5 to 5.5 V
tKCY7/2–50
ns
tKCY7/2–100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
tKSI7
(from SCK1↑)
SO1 output delay time
tKSO7
C = 100 pF Note
300
ns
MAX.
Unit
from SCK1↓
Note C is the load capacitance of SCK1 and SO1 output lines.
(ii) 3-wire serial I/O mode (SCK1... External clock input)
Parameter
SCK1 cycle time
Symbol
tKCY8
Test Conditions
MIN.
TYP.
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
400
ns
SCK1 high-/low-level
tKH8,
4.5 V ≤ VDD ≤ 5.5 V
width
tKL8
2.7 V ≤ VDD < 4.5 V
800
ns
2.0 V ≤ VDD < 2.7 V
1600
ns
2400
ns
100
ns
150
ns
400
ns
SI1 setup time
tSIK8
VDD = 2.0 to 5.5 V
(to SCK1↑)
SI1 hold time
tKSI8
(from SCK1↑)
SO1 output delay time
tKSO8
C = 100 pF Note VDD = 2.0 to 5.5 V
from SCK1↓
SCK1 rise/fall time
tR8,
When external device
tF8
expansion function is used
When external
When 16-bit timer
device expansion
output function is
function is not
used
used
When 16-bit timer
output function is
not used
Note C is the load capacitance of the SO1 output line.
44
300
ns
500
ns
160
ns
700
ns
1000
ns
µPD78P018FY
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output)
Parameter
SCK1 cycle time
Symbol
tKCY9
SCK1 high-/low-level
tKH9,
width
tKL9
SI1 setup time
tSIK9
(to SCK1↑)
SI1 hold time
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ VDD ≤ 5.5 V
800
ns
2.7 V ≤ VDD < 4.5 V
1600
ns
2.0 V ≤ VDD < 2.7 V
3200
ns
4800
ns
VDD = 4.5 to 5.5 V
tKCY9/2–50
ns
tKCY9/2–100
ns
4.5 V ≤ VDD ≤ 5.5 V
100
ns
2.7 V ≤ VDD < 4.5 V
150
ns
2.0 V ≤ VDD < 2.7 V
300
ns
400
ns
400
ns
tKSI9
(from SCK1↑)
SO1 output delay time
tKSO9
C = 100 pF Note
300
ns
from SCK1↓
STB↑ from SCK1↑
tSBD
Strobe signal
tSBW
high-level width
tKCY9/2–100
tKCY9/2+100
ns
2.7 V ≤ VDD ≤ 5.5 V
tKCY9–30
tKCY9+30
ns
2.0 V ≤ VDD < 2.7 V
tKCY9–60
tKCY9+60
ns
tKCY9–90
tKCY9+90
ns
Busy signal setup time tBYS
100
ns
(to busy signal
detection timing)
4.5 V ≤ VDD ≤ 5.5 V
100
ns
(from busy signal
2.7 V ≤ VDD < 4.5 V
150
ns
detection timing)
2.0 V ≤ VDD < 2.7 V
200
ns
Busy signal hold time
tBYH
300
SCK1↓ from busy
tSPS
ns
2tKCY9
ns
inactive
Note C is the load capacitance of the SCK1 and SO1 output lines.
45
µPD78P018FY
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock input)
Parameter
SCK1 cycle time
Symbol
tKCY10
Test Conditions
MIN.
TYP.
MAX.
Unit
4.5 V ≤ V DD ≤ 5.5 V
800
ns
2.7 V ≤ V DD < 4.5 V
1600
ns
2.0 V ≤ V DD < 2.7 V
3200
ns
4800
ns
SCK1 high-/low-level
tKH10 ,
4.5 V ≤ V DD ≤ 5.5 V
400
ns
width
tKL10
2.7 V ≤ V DD < 4.5 V
800
ns
2.0 V ≤ V DD < 2.7 V
1600
ns
2400
ns
100
ns
150
ns
400
ns
SI1 setup time
tSIK10
VDD = 2.0 to 5.5 V
(to SCK1↑)
SI1 hold time
tKSI10
(from SCK1↑)
SO1 output delay time
tKSO10
C = 100 pF Note VDD = 2.0 to 5.5 V
from SCK1↓
SCK1 rise/fall time
tR10, tF10
When external device expansion
300
ns
500
ns
160
ns
1000
ns
function is used
When external device expansion
function is not used
Note C is the load capacitance of the SO1 output line.
46
µPD78P018FY
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.8 VDD
Test Points
0.2 VDD
0.2 VDD
Clock Timing
1/fX
tXL
tXH
VIH4 (MIN.)
VIL4 (MAX.)
X1 Input
1/fXT
tXTL
tXTH
VIH5 (MIN.)
VIL5 (MAX.)
XT1 Input
TI Timing
tTIH0
tTIL0
TI0
1/fTI1
tTIL1
tTIH1
TI1,TI2
47
µPD78P018FY
Read/Write Operation
External fetch (No wait):
A8 to A15
Higher 8-Bit Address
tADD1
Hi-Z
Lower 8-Bit
Address
AD0 to AD7
tADH
tADS
Operation Code
tRDD1
tRDADH
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
External fetch (Wait insertion):
A8 to A15
Higher 8-Bit Address
tADD1
Lower 8-Bit
Address
AD0 to AD7
tADS
tADH
Hi-Z
Operation Code
tRDADH
tRDD1
tASTH
tRDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
tRDWT1
48
tWTL
tWTRD
µPD78P018FY
External data access (No wait):
A8 to A15
Higher 8-Bit Address
tADD2
Lower 8-Bit
Address
AD0 to AD7
tADS
Hi-Z
Hi-Z
Read Data
Hi-Z
Write Data
tRDD2
tADH
tASTH
tRDH
ASTB
RD
tASTRD
tRDWD
tRDL2
tWDS
tWDH
tWRADH
tWRWD
WR
tASTWR
tWRL
External data access (Wait insertion):
A8 to A15
Higher 8-Bit Address
tADD2
Lower 8-Bit
Address
AD0 to AD7
Hi-Z
Read Data
Hi-Z
Hi-Z
Write Data
tADS
tADH
tASTH
tRDD2
tRDH
ASTB
tASTRD
RD
tRDL2
tRDWD
tWDS
tWDH
tWRWD
WR
tASTWR
tWRL
tWRADH
WAIT
tRDWT2
tWTL
tWTRD
tWTL
tWRWT
tWTWR
49
µPD78P018FY
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tFn
tRn
SCK0,SCK1
tSIKm
SI0,SI1
tKSIm
Input Data
tKSOm
Output Data
SO0,SO1
m = 1, 2, 7, 8
n = 2, 8
2-wire serial I/O mode:
tKCY3,4
tKL3,4
tR4
tKH3,4
tF4
SCK0
tSIK3,4
tKSO3,4
tKSI3,4
SB0, SB1
I2C bus mode:
tF6
tR6
tKCY5, 6
SCL
tKL5, 6
SDA0, SDA1
tSBH tSBK
50
tKH5, 6
tKSI5, 6
tSIK5, 6
tKSO5, 6
tKSB
tKSB
tSBK
µPD78P018FY
3-wire serial I/O mode with automatic transmit/receive function:
SO1
SI1
D2
D1
D2
D7
D0
D1
D7
D0
tSIK9,10
tKSI9,10
tKSO9,10
tKH9,10
tF10
SCK1
tKL9,10
tKCY9,10
tR10
tSBD
tSBW
STB
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
SCK1
7
8
9
Note
10
tBYS
Note
Note
1
10 + n
tBYH
tSPS
BUSY
(Active High)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
51
µPD78P018FY
A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 2.2 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
8
8
8
bit
2.7 V ≤ AVREF ≤ AVDD
0.6
%
2.2 V ≤ AVREF < 2.7 V
1.4
%
Resolution
Overall error Note
Conversion time
tCONV
2.7 V ≤ AVREF ≤ AVDD
19.1
200
µs
2.2 V ≤ AVREF < 2.7 V
38.2
200
µs
µs
Sampling time
tSAMP
24/fX
Analog input voltage
VIAN
AVSS
AVREF
V
Reference voltage
AVREF
2.2
AVDD
V
AVREF resistance
RAIREF
4
14
kΩ
Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Data retention supply
Test Conditions
VDDDR
MIN.
TYP.
1.8
MAX.
Unit
5.5
V
10
µA
voltage
Data retention supply
IDDDR
current
VDDDR = 1.8 V
0.1
Subsystem clock stops and feedback resistor disconnected
Release signal set time tSREL
µs
0
18
Oscillation stabilization tWAIT
Release by RESET
2 /f X
ms
wait time
Release by interrupt request
Note
ms
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS),
selection of 213/fX and 215/fX to 218/fX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
RESET
tWAIT
52
µPD78P018FY
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
Interrupt Input Request Timing
tINTL
tINTH
INTP0 to INTP2
tINTL
INTP3
RESET Input Timing
tRSL
RESET
53
µPD78P018FY
PROM PROGRAMMING CHARACTERISTICS
DC Characteristics
(1) PROM Write Mode (TA = 25 ± 5°C, VDD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V)
Parameter
Symbol
Symbol
Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Input voltage, high
VIH
VIH
0.7VDD
VDD
V
Input voltage, low
VIL
VIL
0
0.3VDD
V
Output voltage, high
VOH
VOH
IOH = –1 mA
Output voltage, low
VOL
VOL
IOL = 1.6 mA
ILI
ILI
0 ≤ VIN ≤ VDD
VPP supply voltage
VPP
VPP
12.2
VDD supply voltage
VDD
VCC
6.25
VPP supply current
IPP
IPP
VDD supply current
IDD
ICC
Input leakage current
Note
VDD – 1.0
V
0.4
V
+10
µA
12.5
12.8
V
6.5
6.75
V
50
mA
50
mA
MAX.
Unit
0.7VDD
VDD
V
0
0.3VDD
V
–10
PGM = VIL
Corresponding µPD27C1001A symbol
(2) PROM Read Mode (TA = 25 ± 5°C, VDD = 5.0 ± 0.5 V, VPP = VDD ± 0.6 V)
Parameter
Input voltage, high
Input voltage, low
Symbol
VIH
Symbol
Note
Test Conditions
VIH
MIN.
TYP.
VIL
VIL
VOH1
VOH1
IOH = –1 mA
VDD – 1.0
V
VOH2
VOH2
IOH = –100 µA
VDD – 0.5
V
VOL
VOL
IOL = 1.6 mA
Input leakage current
ILI
ILI
0 ≤ VIN ≤ VDD
Output leakage current
ILO
ILO
0 ≤ VOUT ≤ VDD, OE = VIH
VPP supply voltage
VPP
VPP
Output voltage, high
Output voltage, low
VDD supply voltage
VDD
VCC
VPP supply current
IPP
IPP
VDD supply current
IDD
ICCA1
Note
54
Corresponding µPD27C1001A symbol
0.4
V
–10
+10
µA
–10
+10
µA
VDD + 0.6
V
VDD – 0.6
VDD
4.5
5.0
5.5
V
VPP = VDD
100
µA
CE = VIL, VIN = VIH
50
mA
µPD78P018FY
AC Characteristics
(1) PROM Write Mode
(a)
Page program mode (TA = 25 ± 5°C, VDD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V)
Symbol
Symbol Note
tAS
tAS
2
µs
OE setup time
tOES
tOES
2
µs
CE setup time (to OE↓)
tCES
tCES
2
µs
Input data setup time (to OE↓)
tDS
tDS
2
µs
Parameter
Address setup time (to OE↓)
Address hold time (from OE↑)
Test Conditions
MIN.
TYP.
MAX.
Unit
tAH
tAH
2
µs
tAHL
tAHL
2
µs
µs
tAHV
tAHV
0
Input data hold time (from OE↑)
tDH
tDH
2
Data output float delay time from OE↑
tDF
tDF
0
VPP setup time (to OE↓)
tVPS
tVPS
1.0
VDD setup time (to OE↓)
tVDS
tVCS
1.0
Program pulse width
tPW
tPW
0.095
µs
250
ns
ms
ms
0.1
0.105
ms
1
µs
Valid data delay time from OE↓
tOE
tOE
OE pulse width during data latching
tLW
tLW
1
µs
PGM setup time
tPGMS
tPGMS
2
µs
CE hold time
tCEH
tCEH
2
µs
OE hold time
tOEH
tOEH
2
µs
Note
(b)
Corresponding µPD27C1001A symbol
Byte program mode (TA = 25 ± 5°C, VDD = 6.5 ± 0.25 V, VPP = 12.5 ± 0.3 V)
Parameter
Symbol
Symbol Note
Test Conditions
MIN.
TYP.
MAX.
Unit
Address setup time (to PGM↓)
tAS
tAS
2
µs
OE setup time
tOES
tOES
2
µs
CE setup time (to PGM↓)
tCES
tCES
2
µs
Input data setup time (to PGM↓)
tDS
tDS
2
µs
Address hold time (from OE↑)
tAH
tAH
2
µs
Input data hold time (from PGM↑)
tDH
tDH
2
Data output float delay time from OE↑
tDF
tDF
0
VPP setup time (to PGM↓)
tVPS
tVPS
1.0
VDD setup time (to PGM↓)
tVDS
tVCS
1.0
Program pulse width
tPW
tPW
0.095
Valid data delay time from OE↓
tOE
tOE
OE hold time
tOEH
—
Note
2
µs
250
ns
ms
ms
0.1
0.105
ms
1
µs
µs
Corresponding µPD27C1001A symbol
55
µPD78P018FY
(2) PROM Read Mode (TA = 25 ± 5 °C, VDD = 5.0 ± 0.5 V, VPP = VDD ± 0.6 V)
Symbol
Symbol Note
Data output time from address
tACC
tACC
Data output delay time from CE↓
tCE
Data output delay time from OE↓
Parameter
MAX.
Unit
CE = OE = VIL
800
ns
tCE
OE = VIL
800
ns
tOE
tOE
CE = VIL
200
ns
Data output float delay time from OE↑
tDF
tDF
CE = VIL
0
60
ns
Data hold time from address
tOH
tOH
CE = OE = VIL
0
Note
Test Conditions
MIN.
TYP.
ns
Corresponding µPD27C1001A symbol
(3) PROM Programming Mode Setting (TA = 25°C, VSS = 0 V)
Parameter
Symbol
PROM programming
mode setup time
Test Conditions
MIN.
tSMA
TYP.
MAX.
Unit
µs
10
PROM Write Mode Timing (Page program mode)
Page Data Latch
Page Program
Program Verify
A2 to A16
tAS
tAHL
tAHV
tDS
tDH
tDF
A0, A1
D0 to D7
Hi–Z
Hi–Z
Hi–Z
tPGMS
tVPS
Data Input
tOE
VPP
Data
Output
tAH
VPP
VDD
tVDS
VDD + 1.5
VDD
VDD
tCES
tOEH
VIH
CE
VIL
tCEH
tPW
VIH
PGM
VIL
tLW
tOES
VIH
OE
VIL
56
µPD78P018FY
PROM Write Mode Timing (Byte program mode)
Program
Program Verify
A0 to A16
t AS
D0 to D7
t DF
Hi-Z
Hi-Z
Data Input
t DS
Hi-Z
Data Output
t DH
t AH
VPP
VPP
VDD
t VPS
VDD + 1.5
VDD
VDD
t VDS
t OEH
VIH
CE
VIL
t CES
t PW
VIH
PGM
VIL
t OES
t OE
VIH
OE
VIL
Cautions 1. VDD must be applied before VPP and cut off after VPP.
2. VPP must not exceed +13.5 V including overshoot.
3. Removing and reinserting while +12.5 V is applied to VPP may adversely affect reliability.
PROM Read Mode Timing
Effective Address
A0 to A16
VIH
CE
VIL
t CE
VIH
OE
VIL
Note 1
t ACC
D0 to D7
Hi-Z
t OE
t DF
Note 1
Note 2
t OH
Data Output
Hi-Z
Notes 1. When reading within the tACC range, the OE input delay time from the CE fall time must be maximum of
tACC – t OE.
2. tDF is the time from the point at which either OE or CE (whichever is first) reaches VIH.
57
µPD78P018FY
PROM Programming Mode Setting Timing
VDD
VDD
0
RESET
VDD
VPP
0
t SMA
A0 to A16
58
Effective Address
µPD78P018FY
8. CHARACTERISTIC CURVE (REFERENCE VALUE)
IDD vs. VDD (Main System Clock: 10.0 MHz)
TA = 25 °C
10.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
5.0
HALT (X1 Oscillation, XT1 Halt)
1.0
Supply Current IDD [mA]
0.5
PCC = B0H
0.1
0.05
HALT (X1 Halt, XT1 Oscillation)
0.01
0.005
fX = 10.0 MHz
fXT = 32.768 kHz
0.001
0
1
2
3
4
5
6
7
8
Supply Voltage VDD [V]
59
µPD78P018FY
11. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mils)
64
33
1
32
A
K
H
G
J
I
L
F
D
N
M
NOTE
B
C
M
R
ITEM
MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
58.68 MAX.
2.311 MAX.
B
1.78 MAX.
0.070 MAX.
2) Item "K" to center of leads when formed parallel.
C
1.778 (T.P.)
0.070 (T.P.)
D
0.50±0.10
0.020+0.004
–0.005
F
0.9 MIN.
0.035 MIN.
G
3.2±0.3
0.126±0.012
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
J
5.08 MAX.
0.200 MAX.
K
19.05 (T.P.)
0.750 (T.P.)
L
17.0
0.669
M
0.25+0.10
–0.05
0.010+0.004
–0.003
N
0.17
0.007
R
0~15°
0~15°
P64C-70-750A,C-1
Remark
60
The dimensions and materials of ES (Engineering Sample) versions are the same as those of mass-produced
versions.
µPD78P018FY
64 PIN CERAMIC SHRINK DIP (750 mils)
S
64
33
1
32
A
K
J
I
L
H
C
F
G
D
N
M
NOTES
1) Each lead centerline is located within 0.25 mm (0.010 inch) of
its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
M
B
R
ITEM
MILLIMETERS
INCHES
A
B
58.68 MAX.
2.310 MAX.
C
1.78 MAX.
1.778 (T.P.)
0.070 MAX.
0.070 (T.P.)
D
F
0.46±0.05
0.8 MIN.
0.018±0.002
0.031 MIN.
G
H
3.5±0.3
1.0 MIN.
0.138±0.012
0.039 MIN.
I
3.0
0.118
J
K
L
5.08 MAX.
0.200 MAX.
19.05 (T.P.)
18.8
0.750 (T.P.)
0.740
M
0.25±0.05
0.010 +0.002
–0.003
N
0.25
R
0~15°
0.010
0~15°
S
φ 8.89
φ 0.350
P64DW-70-750A-1
61
µPD78P018FY
64 PIN PLASTIC QFP (14x14)
A
B
48
49
33
32
detail of lead end
S
C D
Q
64
1
R
17
16
F
J
G
H
I
M
P
K
S
N
S
L
M
NOTE
1. Controlling dimension
ITEM
millimeter.
2. Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
MILLIMETERS
INCHES
A
17.6±0.4
B
14.0±0.2
0.693±0.016
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.6±0.4
0.693±0.016
F
G
1.0
1.0
0.039
0.039
H
0.37 +0.08
–0.07
0.015 +0.003
–0.004
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8±0.2
0.071±0.008
L
0.8±0.2
0.031 +0.009
–0.008
M
0.17 +0.08
–0.07
0.007 +0.003
–0.004
N
0.10
0.004
P
2.55±0.1
0.100±0.004
Q
0.1±0.1
0.004±0.004
R
S
5°±5°
2.85 MAX.
5°±5°
0.113 MAX.
P64GC-80-AB8-4
Remark
62
The dimensions and materials of ES (Engineering Sample) versions are the same as those of mass-produced
versions.
µPD78P018FY
64 PIN CERAMIC WQFN
A
B
Q
D
C
U
T
S
64
1
K
W
U1
H
I
M
R
F
G
J
Z
X64KW-80A1
NOTE
Each lead centerline is located within 0.08
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
14.0 ± 0.18
0.551 ± 0.007
B
13.4
0.528
C
13.4
0.528
D
14.0 ± 0.18
0.551 ± 0.007
F
1.84
0.072
G
3.56 MAX.
0.141 MAX.
H
0.51 ± 0.1
0.02 ± 0.004
I
0.08
0.003
J
0.8 (T.P.)
0.031 (T.P.)
K
1.0 ± 0.15
0.039+0.007
–0.006
Q
C 0.3
C 0.012
R
1.0
0.039
S
1.0
0.039
T
R 3.0
R 0.118
U
10.8
0.425
U1
1.4
0.055
W
0.75 ± 0.15
0.03+0.006
–0.007
Z
0.10
0.004
63
µPD78P018FY
12. RECOMMENDED SOLDERING CONDITIONS
The µPD78P018FY should be soldered and mounted under the following recommended conditions.
For the recommended soldering conditions, refer to the document "Semiconductor Device Mounting Technology Manual" (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
µPD78P018FYGC-AB8: 64-pin Plastic QFP (14 × 14 mm)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds Max. (at 210°C or higher),
Count: Three times or less
IR35-00-3
VPS
Package peak temperature: 215°C, Time: 40 seconds Max. (at 200°C or higher),
Count: Three times or less
VP15-00-3
Wave soldering
Solder bath temperature: 260°C, Time: 10 seconds Max., Count: Once,
Preheating temperature: 120°C Max. (package surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300°C Max., Time: 3 seconds Max. (per pin row)
—
Caution Do not use different soldering methods together (except for partial heating).
Table 12-2. Insertion Type Soldering Conditions
µPD78P018FYCW: 64-pin Plastic Shrink DIP (750 mils)
µPD78P018FYDW: 64-pin Ceramic Shrink DIP (with window) (750 mils)
Soldering Method
Soldering Conditions
Wave soldering
(pin only)
Solder temperature: 260°C Max., Time: 10 seconds Max.
Partial heating
Pin temperature: 300°C Max., Time: 3 seconds Max. (per pin)
Caution
64
Apply wave soldering only to the pins and be careful not to bring solder into direct contact
with the package.
µPD78P018FY
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD78P018FY.
Read (5) Cautions on using developing tools for reference.
(1) Language Processing Software
RA78K/0
Assembler package common to 78K/0 Series
CC78K/0
C compiler package common to 78K/0 Series
DF78014
Device file common to µPD78018F Subseries
CC78K/0-L
C compiler library source file common to 78K/0 Series
(2) PROM Writing Tools
PG-1500
PROM programmer
PA-78P018CW
PA-78P018GC
PA-78P018KK-S
Programmer adapter connected to PG-1500
PG-1500 controller
PG-1500 control program
(3) Debugging Tool
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-70000-98-IF-C
Interface adapter required when using PC-9800 series as host machine (excluding notebook PCs, C
bus supported)
IE-70000-CD-IF-A
PC card and interface cable required when using notebook PC of PC-9800 series as host machine
(PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/ATTM compatible as host machine (ISA bus supported)
IE-70000-PCI-IF
Adapter when using PC that incorporates PCI bus as host machine
IE-78018-NS-EM1
Emulation board common to µPD78018F Subseries
NP-64CW
Emulation probe for 64-pin plastic shrink DIP (CW type)
NP-64GC
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EV-9200GC-64
Socket to be mounted on a target system board made for 64-pin plastic QFP (GC-AB8 type)
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF78014
Device file common to µPD78018F Subseries
65
µPD78P018FY
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
IE-70000-98-IF-C
In-circuit emulator common to 78K/0 Series
Interface adapter required when using PC-9800 series as host machine (excluding notebook PCs, C
bus supported)
IE-70000-PC-IF-C
Interface adapter required when using IBM PC/AT compatible as host machine (ISA bus supported)
IE-78000-R-SV3
Interface adapter and cable when using EWS as host machine
IE-70000-PCI-IF
Adapter when using PC that incorporates PCI bus as host machine
IE-78018-NS-EM1
Emulation board common to µPD78018F Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary to use IE-78018-NS-EM1 on IE-78001-R-A
EP-78240CW-R
Emulation probe for 64-pin plastic shrink DIP (CW type)
EP-78240GC-R
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EV-9200GC-64
Socket to be mounted on a target system board made for 64-pin plastic QFP (GC-AB8 type)
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF78014
Device file common to µPD78018F Subseries
(4) Real-time OS
RX78K/0
Real-time OS for 78K/0 Series
MX78K0
OS for 78K/0 Series
66
µPD78P018FY
(5) Cautions on using development tools
• The ID-78K0-NS, ID78K0, and SM78K0 are used in combination with the DF78014.
• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and the DF78014.
• NP-64CW and NP-64GC are products made by Naitou Densei Machidaseisakusho (TEL: +81-44-8223813).
Contact an NEC distributor regarding the purchase of these products.
• For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
• The host machine and OS suitable for each software are as follows:
Host Machine
[OS]
Software
PC
PC-9800 series [WindowsTM]
IBM PC/AT compatible
[Japanese/English Windows]
EWS
HP9000 series 700 TM [HP-UX TM]
SPARCstationTM [SunOSTM, SolarisTM]
NEWSTM (RISC) [NEWS-OSTM]
RA78K/0
√ Note
√
CC78K/0
√ Note
√
PG-1500 Controller
√
Note
—
ID78K0-NS
√
—
ID78K0
√
√
√
—
SM78K0
RX78K/0
√
Note
MX78K0
√
Note
Note
√
√
DOS-based software
67
µPD78P018FY
Drawing of Conversion Socket (EV-9200GC-64) and Recommended Footprint
Figure A-1. Drawing of EV-9200GC-64 (for reference only)
A
N
O
L
K
T
J
C
D
S
F
Q
M
R
B
E
EV-9200GC-64
1
P
No.1 pin index
G
H
I
EV-9200GC-64-G0E
ITEM
68
MILLIMETERS
INCHES
A
18.8
0.74
B
14.1
0.555
C
14.1
0.555
D
18.8
0.74
E
4-C 3.0
4-C 0.118
F
0.8
0.031
G
6.0
0.236
H
15.8
0.622
I
18.5
0.728
J
6.0
0.236
K
15.8
0.622
L
18.5
0.728
M
8.0
0.315
N
7.8
0.307
O
2.5
0.098
P
2.0
0.079
Q
1.35
0.053
R
0.35 ± 0.1
0.014+0.004
–0.005
S
φ 2.3
φ 0.091
T
φ 1.5
φ 0.059
µPD78P018FY
Figure A-2. Recommended Footprint of EV-9200GC-64 (for reference only)
G
J
H
D
E
F
K
I
L
C
B
A
EV-9200GC-64-P1E
ITEM
MILLIMETERS
A
19.5
B
14.8
INCHES
0.768
0.583
C
0.8±0.02 × 15=12.0±0.05
D
+0.003
0.8±0.02 × 15=12.0±0.05 0.031+0.002
–0.001 × 0.591=0.472 –0.002
0.031+0.002
–0.001 ×
0.591=0.472 +0.003
–0.002
E
14.8
0.583
F
19.5
0.768
G
6.00 ± 0.08
0.236+0.004
–0.003
H
6.00 ± 0.08
0.236+0.004
–0.003
I
0.5 ± 0.02
0.197+0.001
–0.002
J
φ 2.36 ± 0.03
φ 0.093+0.001
–0.002
K
φ 2.2 ± 0.1
φ 0.087+0.004
–0.005
L
φ 1.57 ± 0.03
φ 0.062+0.001
–0.002
Caution
Dimensions of mount pad for EV-9200 and that for
target device (QFP) may be different in some parts.
For the recommended mount pad dimensions for
QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).
69
µPD78P018FY
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name
Document No.
Japanese
English
µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Data Sheet
U10281J
U10281E
µPD78P018FY Data Sheet
U10989J
This document
µPD78018F, 78018FY Subseries User's Manual
U10659J
U10659E
78K/0 Series User's Manual - Instructions
U12326J
U12326E
78K/0 Series Instruction List
U10903J
—
78K/0 Series Instruction Set
U10904J
—
µPD78018FY Subseries Special Function Register List
U10287J
—
78K/0 Series Application Note
Basics (I)
U12704J
U12704E
Floating-Point Arithmetic Programs
U13482J
IEA-1289
Development Tool Documents (User's Manual) (1/2)
Document Name
Document No.
Japanese
English
Operation
U11802J
U11802E
Assembly Language
U11801J
U11801E
Structured Assembly Language
U11789J
U11789E
RA78K Series Structured Assembler Preprocessor
U12323J
EEU-1402
CC78K0 C Compiler
Operation
U11517J
U11517E
Language
U11518J
U11518E
Programming Know-How
U13034J
U13034E
PG-1500 PROM Programmer
U11940J
U11940E
PG-1500 Controller PC-9800 Series (MS-DOS TM) Based
EEU-704
EEU-1291
PG-1500 Controller IBM PC Series (PC DOS TM) Based
EEU-5008
U10540E
IE-78K0-NS
To be prepared
To be prepared
IE-78001-R-A
To be prepared
To be prepared
IE-78K0-R-EX1
To be prepared
To be prepared
IE-78018-NS-EM1
U13289J
To be prepared
EP-78240
EEU-986
U10332E
RA78K0 Assembler Package
CC78K/0 C Compiler Application Note
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
70
µPD78P018FY
Development Tool Documents (User's Manual) (2/2)
Document No.
Document Name
Japanese
English
SM78K0 System Simulator Windows Based
Reference
U10181J
U10181E
SM78K Series System Simulator
External Part User Open
U10092J
U10092E
Interface Specification
ID78K0-NS Integrated Debugger Windows Based
Reference
U12900J
U12900E
ID78K0 Integrated Debugger EWS based
Reference
U11151J
—
ID78K0 Integrated Debugger PC based
Reference
U11539J
U11539E
ID78K0 Integrated Debugger Windows based
Guide
U11649J
U11649E
Embedded Software Documents (User's Manual)
Document No.
Document Name
78K/0 Series Real-Time OS
78K/0 Series OS MX78K0
Japanese
English
Basic
U11537J
U11537E
Installation
U11536J
U11536E
Basic
U12257J
U12257E
Other Documents
Document Name
Document No.
Japanese
English
—
C13388E
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Guide to Prevent Damages for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892J
C11892E
Guide to Quality Assurance for Semiconductor Devices
—
MEI-1202
Microcomputer – Related Product Guide – Third Parties
U11416J
—
NEC IC Package Manual (CD-ROM)
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
71
µPD78P018FY
[MEMO]
72
µPD78P018FY
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
73
µPD78P018FY
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I 2C system, provided that the system conforms to the I2C Standard Specification as
defined by Philips.
FIP, IEBus, and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
74
µPD78P018FY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
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µPD78P018FY
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
The export of these products from Japan is regulated by the Japanese government. The export of some
or all of these products may be prohibited without governmental license. To export or re-export some or
all of these products from a country other than Japan may also be prohibited without a license from that
country. Please call an NEC sales representative.
License not needed:
µPD78P018FYDW, 78P018FYKK-S
The customer must judge the need for license: µPD78P018FYCW, 78P018FYGC-AB8
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consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5