DATA SHEET MOS INTEGRATED CIRCUIT µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, and 78018FY are the products in the µPD78018FY subseries within the 78K/0 series, and the products which is added the I2C bus control function to the µPD78018F subseries. A one-time PROM or EPROM product µPD78P018FY capable of operating in the same power supply voltage as of the mask ROM product and other development tools are also provided. Functions are described in detail in the following User's Manual, which should be read when carring out design work. µPD78018F, 78018FY Subseries User's Manual : U10659E 78K/0 Series Users Manual – Instruction : U12326E FEATURES • Serial interface : 2 channels (I2C bus mode : 1 channel) • Large on-chip ROM & RAM Item Product Name • • • • • • Program Memory (ROM) µPD78011FY 8K bytes µPD78012FY 16K bytes µPD78013FY 24K bytes µPD78014FY 32K bytes µPD78015FY 40K bytes µPD78016FY 48K bytes µPD78018FY 60K bytes Data Memory Internal HighSpeed RAM Internal Expanded RAM 512 bytes – Package Buffer RAM 32 bytes • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 14 mm) 1024 bytes 512 bytes 1024 bytes External memory expansion space : 64K bytes Minimum instruction execution time can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µs) I/O ports: 53 (N-ch open-drain : 4) 8-bit resolution A/D converter : 8 channels Timer : 5 channels Supply voltage : VDD = 1.8 to 5.5 V APPLICATION FIELDS Cellular phone, pager, VCR, audio, camera, home appliances, etc The information in this document is subject to change without notice. Document No. U10281EJ2V0DS00 (2nd edition) Date Published August 1997 N Printed in Japan The mark shows major revised points. © 1994 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY ORDERING INFORMATION Part Number µPD78011FYCW-××× µPD78011FYGC-×××-AB8 µPD78012FYCW-××× µPD78012FYGC-×××-AB8 µPD78013FYCW-××× µPD78013FYGC-×××-AB8 µPD78014FYCW-××× µPD78014FYGC-×××-AB8 µPD78015FYCW-××× µPD78015FYGC-×××-AB8 µPD78016FYCW-××× µPD78016FYGC-×××-AB8 µPD78018FYCW-××× µPD78018FYGC-×××-AB8 Package 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin Remark ××× indicates a ROM code suffix. 2 plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic shrink DIP QFP (14 × shrink DIP QFP (14 × shrink DIP QFP (14 × shrink DIP QFP (14 × shrink DIP QFP (14 × shrink DIP QFP (14 × shrink DIP QFP (14 × (750 mil) 14 mm) (750 mil) 14 mm) (750 mil) 14 mm) (750 mil) 14 mm) (750 mil) 14 mm) (750 mil) 14 mm) (750 mil) 14 mm) µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 78K/0 SERIES DEVELOPMENT The following shows the products organized according to usage. The names in the parallelograms are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin µ PD78075B µ PD78078 µ PD78070A 100-pin 80-pin µ PD780058 µ PD78058F µPD78075BY µPD78078Y µ PD78070AY µ PD780018AY µ PD780058YNote EMI-noise reduced version of µ PD78078 A timer was added to the µ PD78054 and external interface was enhanced ROM-less version of the µPD78078 Serial I/O of the µ PD78078Y was enhanced and the function is limited. Serial I/O of the µ PD78054 was enhanced and EMI-noise was reduced. µ PD78058FY EMI-noise reduced version of the µ PD78054 µPD78054 µPD780034 µ PD78054Y µPD780034Y UART and D/A converter were enhanced to the µ PD78014 and I/O was enhanced 64-pin 64-pin µ PD780024 µ PD78014H µ PD780024Y 64-pin µPD78018F µPD78014 µ PD780001 µPD78018FY Serial I/O of the µ PD78018F was added and EMI-noise was reduced. EMI-noise reduced version of µPD78018F Low-voltage (1.8 V) operation version of the µPD78014, with larger selection of ROM and RAM capacities µ PD78014Y An A/D converter and 16-bit timer were added to the µPD78002 An A/D converter was added to the µPD78002 64-pin µPD78002 µ PD78002Y Basic subseries for control 42/44-pin µ PD78083 80-pin 80-pin 64-pin 64-pin 64-pin A/D converter of the µ PD780024 was enhanced On-chip UART, capable of operating at low voltage (1.8 V) Inverter control 64-pin 64-pin A/D converter of the µ PD780924 was enhanced On-chip inverter control circuit and UART. EMI-noise was reduced. µPD780964 µPD780924 FIPTM drive The I/O and FIP C/D of the µ PD78044F were enhanced, Display output total: 53 100-pin µ PD780208 µ PD780228 80-pin µ PD78044H An N-ch open drain I/O was added to the µ PD78044F, Display output total: 34 80-pin µPD78044F Basic subseries for driving FIP, Display output total: 34 100-pin 78K/0 Series The I/O and FIP C/D of the µ PD78044H were enhanced, Display output total: 48 LCD drive 100-pin µ PD780308 µPD780308Y 100-pin µPD78064B µPD78064 The SIO of the µPD78064 was enhanced, and ROM, RAM capacity increased EMI-noise reduced version of the µ PD78064 µ PD78064Y Basic subseries for driving LCDs, On-chip UART 100-pin IEBusTM supported 80-pin µ PD78098B EMI-noise reduced version of the µPD78098 80-pin µ PD78098 An IEBus controller was added to the µPD78054 Meter control 80-pin µ PD780973 On-chip controller/driver for automobile meters LV 64-pin Note µ PD78P0914 On-chip PWM output, LV digital code decoder, and Hsync counter Under planning 3 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY The following lists the main functional differences between Y subseries products. Functions Subseries Name Control µPD78075BY µPD78078Y ROM Capacity 32 K to 40 K 48 K to 60 K 88 61 2.7 V I/O µPD78070AY – µPD780018AY 48 K to 60 K With automatic transmit/receive function, 3-wire : 1 ch Time division, 3-wire : 1 ch I2C bus (for multimaster) : 1 ch 88 µPD780058Y 24 K to 60 K 3-wire/2-wire/I2C : 1 ch With automatic transmit/receive function, 3-wire : 1 ch 3-wire/time division UART : 1 ch 68 1.8 V µPD78058FY 48 K to 60 K 69 2.7 V µPD78054Y 16 K to 60 K 3-wire/2-wire/I2C : 1 ch With automatic transmit/receive function, 3-wire : 1 ch 3-wire/UART : 1 ch µPD780034Y 8 K to 32 K UART 3-wire I2C bus (for multimaster) : 1 ch : 1 ch : 1 ch 51 µPD78018FY 8 K to 60 K 3-wire/2-wire/I2C : 1 ch With automatic transmit/receive function, 3-wire : 1 ch 53 µPD78014Y 8 K to 32 K 3-wire/2-wire/SBI/I2C : 1 ch With automatic transmit/receive function, 3-wire : 1 ch µPD78002Y 8 K to 16 K 3-wire/2-wire/SBI/I2C : 1 ch 48 K to 60 K 3-wire/2-wire/I2C 3-wire/time division UART 3-wire : 1 ch : 1 ch : 1 ch 3-wire/2-wire/I2C 3-wire/UART : 1 ch : 1 ch µPD780024Y LCD 3-wire/2-wire/I2C : 1 ch With automatic transmit/receive function, 3-wire : 1 ch 3-wire/UART : 1 ch VDD MIN. Value 1.8 V Serial Interface Configuration µPD780308Y drive µPD78064Y 16 K to 32 K 2.0 V 1.8 V 2.7 V 57 2.0 V Remark The functions other than the serial interface are the same as those of subseries products without the suffix Y. 4 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY OVERVIEW OF FUNCTION (1/2) Item Product Name µPD78011FY µPD78012FY µPD78013FY µPD78014FY µPD78015FY µPD78016FY µPD78018FY ROM High-speed RAM Expanded Internal memory 8K bytes 16K bytes 32K bytes 512 bytes 40K bytes 48K bytes 60 K bytes 1024 bytes — RAM Buffer RAM 24K bytes 512 bytes 1024 bytes 32 bytes Memory space 64K bytes General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time On-chip minimum instruction execution time cycle modification function When main system clock selected When subsystem clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 10.0 MHz operation) 122 µs (at 32.768 kHz operation) Instruction set • • • • 16-bit operation Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. I/O ports Total • CMOS input • CMOS I/O • N-channel open-drain I/O (15 V withstand voltage) : 53 : 02 : 47 : 04 A/D converter • 8-bit resolution × 8 channels • Operable over a wide power supply voltage range: VDD = 1.8 to 5.5 V Serial interface • 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable: 1 channel • 3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel Timer • • • • Timer output 3 (14-bit PWM output × 1) Clock output 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock: 10.0 MHz operation), 32.768 kHz (at subsystem clock: 32.768 kHz operation) Buzzer output 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: 10.0 MHz operation) Vectored Maskable Internal : 8 External : 4 Non-maskable Internal : 1 Software 1 interrupt sources 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer : : : : 1 2 1 1 channel channels channel channel 5 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY OVERVIEW OF FUNCTION (2/2) Item Product Name Test input Internal : 1 External : 1 Supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature Package 6 µPD78011FY µPD78012FY µPD78013FY µPD78014FY µPD78015FY µPD78016FY µPD78018FY TA = –40 to +85°C • 64-pin plastic shrink DIP (750 mil) • 64-pin plastic QFP (14 × 14 mm) µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY TABLE OF CONTENTS 1. PIN CONFIGURATION (TOP VIEW) ....................................................................................................... 8 2. BLOCK DIAGRAM ................................................................................................................................... 11 3. PIN FUNCTIONS ...................................................................................................................................... 12 3.1 PORT PINS ........................................................................................................................................................ 12 3.2 PINS OTHER THAN PORT PINS ...................................................................................................................... 13 3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ............................................. 15 4. MEMORY SPACE .................................................................................................................................... 17 5. PERIPHERAL HARDWARE FUNCTION FEATURES ............................................................................ 19 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6. PORTS ............................................................................................................................................................... CLOCK GENERATOR ....................................................................................................................................... TIMER/EVENT COUNTER ................................................................................................................................ CLOCK OUTPUT CONTROL CIRCUIT ............................................................................................................ BUZZER OUTPUT CONTROL CIRCUIT ........................................................................................................... A/D CONVERTER .............................................................................................................................................. SERIAL INTERFACES ...................................................................................................................................... 19 20 21 23 23 24 24 INTERRUPT FUNCTIONS AND TEST FUNCTIONS .............................................................................. 26 6.1 INTERRUPT FUNCTIONS ................................................................................................................................. 26 6.2 TEST FUNCTIONS ............................................................................................................................................ 29 7. EXTERNAL DEVICE EXPANSION FUNCTIONS .................................................................................... 30 8. STANDBY FUNCTIONS .......................................................................................................................... 30 9. RESET FUNCTIONS ................................................................................................................................ 30 10. INSTRUCTION SET ................................................................................................................................. 31 11. ELECTRICAL SPECIFICATIONS ............................................................................................................ 34 12. CHARACTERISTIC CURVE (REFERENCE VALUES) ........................................................................... 61 13. PACKAGE DRAWINGS ........................................................................................................................... 62 14. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 64 APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 65 APPENDIX B. RELATED DOCUMENTS ...................................................................................................... 67 7 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 1. PIN CONFIGURATION (TOP VIEW) • 64-Pin Plastic Shrink DIP (750 mil) µPD78011FYCW-×××, 78012FYCW-×××, 78013FYCW-×××, µPD78014FYCW-×××, 78015FYCW-×××, 78016FYCW-×××, µPD78018FYCW-××× P20/SI1 1 64 AV REF P21/SO1 2 63 AV DD P22/SCK1 3 62 P17/ANI7 P23/STB 4 61 P16/ANI6 P24/BUSY 5 60 P15/ANI5 P25/SI0/SB0/SDA0 6 59 P14/ANI4 P26/SO0/SB1/SDA1 7 58 P13/ANI3 P27/SCK0/SCL 8 57 P12/ANI2 9 56 P11/ANI1 P31/TO1 10 55 P10/ANI0 P32/TO2 11 54 AV SS P33/TI1 12 53 P04/XT1 P30/TO0 P34/TI2 13 52 XT2 P35/PCL 14 51 IC P36/BUZ 15 50 X1 P37 16 49 X2 V SS 17 48 V DD P40/AD0 18 47 P03/INTP3 P41/AD1 19 46 P02/INTP2 P42/AD2 20 45 P01/INTP1 P43/AD3 21 44 P00/INTP0/TI0 P44/AD4 22 43 RESET P45/AD5 23 42 P67/ASTB P46/AD6 24 41 P66/WAIT P47/AD7 25 40 P65/WR P50/A8 26 39 P64/RD P51/A9 27 38 P63 P52/A10 28 37 P62 P53/A11 29 36 P61 P54/A12 30 35 P60 P55/A13 31 34 P57/A15 V SS 32 33 P56/A14 Cautions 1. Always connect the IC (Internally Connected) pin to VSS directly. 2. Always connect the AVDD pin to VDD. 3. Always connect the AVSS pin to VSS. 8 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY • 64-Pin Plastic QFP (14 × 14 mm) µPD78011FYGC-×××-AB8, 78012FYGC-×××-AB8, 78013FYGC-×××-AB8, P27/SCK0/SCL P26/SO0/SB1/SDA1 P25/SI0/SB0/SDA0 P24/BUSY P23/STB P22/SCK1 P21/SO1 P20/SI1 AV REF AV DD P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 P12/ANI2 µPD78014FYGC-×××-AB8, 78015FYGC-×××-AB8, 78016FYGC-×××-AB8, µPD78018FYGC-×××-AB8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P34/TI2 5 44 XT2 P35/PCL 6 43 IC P36/BUZ 7 42 X1 P37 8 41 X2 V SS 9 40 V DD P40/AD0 10 39 P03/INTP3 P41/AD1 11 38 P02/INTP2 P42/AD2 12 37 P01/INTP1 P43/AD3 13 36 P00/INTP0/TI0 P44/AD4 14 35 RESET P45/AD5 15 34 P67/ASTB P46/AD6 16 17 P66/WAIT P50/A8 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 32 P65/WR P04/XT1 P64/RD 45 P63 4 P62 P33/TI1 P61 AV SS P60 46 P57/A15 3 P56/A14 P32/TO2 V SS P10/ANI0 P55/A13 47 P54/A12 2 P53/A11 P31/TO1 P51/A9 P11/ANI1 P52/A10 1 P47/AD7 P30/TO0 Cautions 1. Always connect the IC (Internally Connected) pin to VSS directly. 2. Always connect the AVDD pin to VDD. 3. Always connect the AVSS pin to VSS. 9 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 10 A8 to A15 AD0 to AD7 : Address Bus : Address/Data Bus PCL RD : Programmable Clock : Read Strobe ANI0 to ANI7 ASTB : Analog Input : Address Strobe RESET SB0, SB1 : Reset : Serial Bus AVDD AVREF : Analog Power Supply : Analog Reference Voltage SCK0, SCK1 SCL : Serial Clock : Serial Clock AVSS BUSY : Analog Ground : Busy SDA0, SDA1 SI0, SI1 : Serial Data : Serial Input BUZ IC : Buzzer Clock : Internally Connected SO0, SO1 STB : Serial Output : Strobe INTP0 to INTP3 : Interrupt from Peripherals P00 to P04 : Port0 TI0 to TI2 TO0 to TO2 : Timer Input : Timer Output P10 to P17 P20 to P27 : Port1 : Port2 VDD VSS : Power Supply : Ground P30 to P37 P40 to P47 : Port3 : Port4 WAIT WR : Wait : Write Strobe P50 to P57 P60 to P67 : Port5 : Port6 X1, X2 XT1, XT2 : Crystal (Main System Clock) : Crystal (Subsystem Clock) µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 2. BLOCK DIAGRAM TO0/P30 TI0/INTP0/P00 P00 16-bit TIMER/ EVENT COUNTER PORT0 P01 to P03 P04 TO1/P31 TI1/P33 TO2/P32 TI2/P34 8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2 WATCHDOG TIMER WATCH TIMER 78K/0 CPU CORE SI0/SB0/P25 SO0/SB1/P26 PORT1 P10 to P17 PORT2 P20 to P27 PORT3 P30 to P37 PORT4 P40 to P47 PORT5 P50 to P57 PORT6 P60 to P67 ROM SERIAL INTERFACE 0 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 AD0/P40 to AD7/P47 SERIAL INTERFACE 1 STB/P23 A8/P50 to A15/P57 BUSY/P24 EXTERNAL ACCESS RAM ANI0/P10 to ANI7/P17 AVDD RD/P64 WR/P65 WAIT/P66 A/D CONVERTER AVSS ASTB/P67 AVREF RESET INTP0/P00 to INTP3/P03 INTERRUPT CONTROL X1 SYSTEM CONTROL X2 XT1 BUZ/P36 BUZZER OUTPUT PCL/P35 CLOCK OUTPUT CONTROL XT2 VDD VSS IC (VPP) Remarks 1. Internal ROM & RAM capacity varies depending on the product. 2. ( ) : µPD78P018FY 11 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Name I/O Input P00 Input/ output P01 P02 Function Port 0 5-bit I/O port On Reset DualFunction Pin Input only Input INTP0/TI0 Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. Input INTP1 INTP2 P03 INTP3 P04Note 1 Input Input only P10 to P17 Input/ output Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software.Note 2 P20 Input/ output Port 2 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. P21 P22 P23 Input XT1 Input ANI0 to ANI7 Input SI1 SO1 SCK1 STB P24 BUSY P25 SI0/SB0/SDA0 P26 SO0/SB1/SDA1 P27 SCK0/SCL Input/ output P30 P31 P32 P33 Port 3 8-bit input/output port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistor can be used in software. Input TO0 TO1 TO2 TI1 P34 TI2 P35 PCL P36 BUZ P37 — P40 to P47 Input/ output Port 4 8-bit input/output port. Input/output can be specified in 8-bit unit. When used as an input port, on-chip pull-up resistor can be used in software. Test input flag (KRIF) is set to 1 by falling edge detection. Input AD0 to AD7 Notes 1. When using the P04/XT1 pins as an input port, set 1 to bit 6 (FRC) of the processor clock control register (PCC). Do not use the on-chip feedback register of the subsystem clock oscillator. 2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input, on-chip pull-up resistor is automatically unused. 12 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 3.1 PORT PINS (2/2) Pin Name I/O Function P50 to P57 Input/ output Port 5 8-bit input/output port. LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used in software. Input P60 Input/ output Port 6 8-bit input/output port. Input/output can be specified bit-wise. Input P61 P62 N-ch open-drain input/output port. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. P63 On Reset P64 P66 A8 to A15 RD When used as an input port, on-chip pull-up resistor can be used in software. P65 DualFunction Pin WR WAIT P67 ASTB 3.2 PINS OTHER THAN PORT PINS (1/2) Pin Name INTP0 I/O Input INTP1 INTP2 INTP3 SI0 Function External interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. On Reset DualFunction Pin Input P00/TI0 P01 P02 P03 Falling edge detection external interrupt request input. Input Serial interface serial data input. Input SI1 SO0 P20 Output Serial interface serial data output. Input SO1 SB0 SB1 P25/SB0/SDA0 P26/SB1/SDA1 P21 Input /output Serial interface serial data input/output. Input P25/SI0/SDA0 P26/SO0/SDA1 SDA0 P25/SI0/SB0 SDA1 P26/SO0/SB1 SCK0 SCL Input /output Serial interface serial clock input/output. Input P27/SCL P27/SCK0 SCK1 P22 STB Output Serial interface automatic transmit/receive strobe output. Input P23 BUSY Input Serial interface automatic transmit/receive busy input. Input P24 13 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 3.2 PINS OTHER THAN PORT PINS (2/2) Pin Name TI0 I/O Input Function External count clock input to 16-bit timer (TM0). TI1 External count clock input to 8-bit timer (TM1). TI2 External count clock input to 8-bit timer (TM2). TO0 Output 16-bit timer (TM0) output (shared as 14-bit PWM output). TO1 8-bit timer (TM1) output. TO2 8-bit timer (TM2) output. PCL BUZ Output Output On Reset Input DualFunction Pin P00/INTP0 P33 P34 Input P30 P31 P32 Clock output (for main system clock, subsystem clock trimming). Input P35 Buzzer output. Input P36 P40 to P47 AD0 to AD7 Input /output Low-order address/data bus at external memory expansion. Input A8 to A15 Output High-order address bus at external memory expansion. Input P50 to P57 RD Output External memory read operation strobe signal output. Input P64 WR External memory write operation strobe signal output. P65 Input Wait insertion at external memory access. Input P66 ASTB Output Strobe output which latches the address information output at port 4 and port 5 to access external memory. Input P67 ANI0 to ANI7 Input A/D converter analog input. Input P10 to P17 AVREF Input A/D converter reference voltage input. — — AVDD — A/D converter analog power supply. Connected to VDD. — — AVSS — A/D converter ground potential. Connected to VSS. — — RESET Input System reset input. — — X1 Input Main system clock oscillation crystal connection. — — X2 — — — XT1 Input Input P04 XT2 — — — VDD — Positive power supply. — — VSS — Ground potential. — — IC — Internal connection. Connected to VSS directly. — — WAIT 14 Subsystem clock oscillation crystal connection. µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, refer to Figure 3-1. Table 3-1. Input/Output Circuit Type of Each Pin Pin Name Input/output Circuit Type I/O Recommended Connection when Not Used P00/INTP0/TI0 2 Input Connected to VSS . P01/INTP1 8-A Input/output Individually connected to VSS via resistor. P04/XT1 16 Input Connected to VDD or VSS. P10/ANI0 to P17/ANI7 11 Input/output Individually connected to VDD or VSS via resisitor. P20/SI1 8-A P21/SO1 5-A P22/SCK1 8-A P23/STB 5-A P24/BUSY 8-A P25/SI0/SB0 10-A P02/INTP2 P03/INTP3 P26/SO0/SB1 P27/SCK0 P30/TO0 5-A P31/TO1 P32/TO2 P33/TI1 8-A P34/TI2 P35/PCL 5-A P36/BUZ P37 P40/AD0 to P47/AD7 5-E Individually connected to VDD via resistor. P50/A8 to P57/A15 5-A Individually connected to VDD or VSS via resistor. P60 to P63 13-B Individually connected to VDD via resistor. P64/RD 5-A Individually connected to VDD or VSS via resistor. P65/WR P66/WAIT P67/ASTB RESET 2 Input XT2 16 — AVREF — — Leave open. Connected to VSS . AVDD Connected to VDD . AVSS Connected to VSS . IC Connected to VSS directly. 15 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Figure 3-1. Pin Input/Output Circuits V DD Type 10-A Type 2 pull-up enable P-ch V DD IN data P-ch IN / OUT open drain output disable N-ch Schmitt-Triggered Input with Hysteresis Characteristic Type 5-A Type 11 V DD pull-up enable pull-up enable P-ch P-ch V DD P-ch data V DD IN / OUT data P-ch IN / OUT output disable V DD N-ch output disable Comparator N-ch P-ch + – N-ch VREF (Threshold Voltage) input enable input enable Type 5-E Type 13-B V DD pull-up enable data V DD Mask Option P-ch data output disable V DD IN / OUT N-ch P-ch V DD IN / OUT output disable N-ch P-ch RD Middle-High Voltage Input Buffer Type 8-A Type 16 V DD pull-up enable feedback cut-off P-ch P-ch V DD data P-ch IN / OUT output disable N-ch XT1 16 XT2 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 4. MEMORY SPACE The memory map of the µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY and 78016FY is shown in Figures 4-1 and 4-2. Figure 4-1. Memory Map (µPD78011FY, 78012FY, 78013FY, 78014FY) FFFFH FA7FH Special Function Registers (SFR) 256 × 8 Bits Use Prohibited F800H F7FFH FF00H FEFFH General-Purpose Registers 32 × 8 Bits FEE0H Internal Expanded RAM 512 × 8 Bits Note 1 F600H F5FFH FEDFH External Memory Internal High-Speed RAMNote 2 nnnnH + 1 mmmmH mmmmH – 1 nnnnH Use Prohibited FAE0H FADFH Data Memory Space FAC0H FABFH Program Area 1000H 0FFFH Buffer RAM 32 × 8 Bits CALLF Entry Area Use Prohibited 0800H 07FFH FA80H FA7FH Program Area Program Memory Space 0080H 007FH External Memory nnnnH + 1 nnnnH CALLT Table Area 0040H 003FH Internal ROMNote Vector Table Area 0000H 0000H Note Intermal ROM and internal high-speed RAM capacities vary depending on the product (refer to the table below). Product Name Intenal ROM End Address nnnnH µPD78011FY 1FFFH µPD78012FY 3FFFH µPD78013FY 5FFFH µPD78014FY 7FFFH Internal High-Speed RAM Start Address mmmmH FD00H FB00H 17 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Figure 4-2. Memory Map (µPD78015FY, 78016FY, 78018FY) FFFFH Special Function Registers (SFR) 256 × 8 Bits FF00H FEFFH General-Purpose Registers 32 × 8 Bits FEE0H FEDFH Internal High-Speed RAMNote mmmmH mmmmH – 1 Use Prohibited FAE0H FADFH Data Memory Space FAC0H FABFH Buffer RAM 32 × 8 Bits nnnnH Program Area Use Prohibited FA80H FA7FH 1000H 0FFFH Use Prohibited F800H F7FFH Program Memory Space kkkkH kkkkH – 1 CALLF Entry Area 0800H 07FFH Internal Expanded RAMNote Program Area 0080H 007FH External Memory nnnnH + 1 CALLT Table Area nnnnH 0040H 003FH Internal ROMNote Vector Table Area 0000H 0000H Note Intermal ROM, internal high-speed RAM, and internal expanded RAM capacities vary depending on the product (refer to the table below). Product Name Intenal ROM End Address nnnnH µPD78015FY 9FFFH µPD78016FY BFFFH µPD78018FY EFFFH 18 Internal High-Speed RAM Start Address Internal Expanded RAM Start Address mmmmH kkkkH FB00H F600H F400H µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 5. PERIPHERAL HARDWARE FUNCTION FEATURES 5.1 PORTS The I/O port has the following three types • CMOS input (P00, P04) : • CMOS input/output (P01 to P03, port 1 to port 5, P64 to P67) • N-ch open-drain input/output(15V withstand voltage) (P60 to P63) : 47 : 4 Total 2 : 53 Table 5-1. Functions of Ports Port Name Port 0 Pin Name Function P00, P04 Dedicated Input port P01 to P03 Input/output ports. Input/output can be specified bit-wise. Port 1 P10 to P17 Port 2 P20 to P27 Port 3 P30 to P37 Port 4 P40 to P47 Port 5 P50 to P57 Port 6 P60 to P63 P64 to P67 When used as an input port, pull-up resistor can be used in software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used in software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used in software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used in software. Input/output ports. Input/output can be specified in 8-bit units. When used as an input port, pull-up resistor can be used in software. Test input flag (KRIF) is set to 1 by falling edge detection. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used in software. LED can be driven directly. N-ch open-drain input/output port. Input/output can be specified bit-wise. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used in software. 19 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 5.2 CLOCK GENERATOR There are two types of clock generator: main system clock and subsystem clock. The minimum instruction exection time can be changed. • 0.4µs/0.8µs/1.6µs/3.2µs/6.4µs (Main system clock: at 10.0 MHz operation) • 122µs (Subsystem clock: at 32.768 KHz operation) Figure 5-1. Clock Generator Block Diagram XT1/P04 XT2 Subsystem Clock Osicillator Watch Timer Clock Output Function fXT Prescaler X1 X2 Main System Clock Osicillator fX Clock to Peripheral Hardware Prescaler fX fX fX fX 2 22 23 24 STOP Selector Standby Control Circuit Wait Control Circuit INTP0 Sampling Clock 20 CPU Clock (fCPU) µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 5.3 TIMER/EVENT COUNTER The following five channels are incorporated in the timer/event counter. • 16-bit timer/event counter : 1 channel • 8-bit timer/event counter • Watch timer : 2 channels : 1 channel • Watchdog timer : 1 channel Table 5-2. Operation of Timer/Event Counter 16-bit Timer/Event Counter Operation mode Functions 8-bit Timer/Event Counter Watch Timer Watchdog Timer Interval timer 1 channel 2 channels 1 channel 1 channel Externanal event counter 1 channel 2 channels – – Timer output 1 output 2 outputs – – PWM output 1 output – – – 1 input – – – 1 output 2 outputs – – Interrupt request 2 2 1 1 Test input – – 1 input – Pulse width mesurement Sqare wave output Figure 5-2. 16-bit Timer/Enent Counter Block Diagram Internal Bus 16-Bit Compare Register (CR00) PWM Pulse Output Control Circuit Match fX/2 fX/22 Selector INTTM0 Output Control Circuit TO0/P30 16-Bit Timer Register (TM0) fX/23 TI0/INTP0/P00 Edge Detector Clear Selector INTP0 16-Bit Capture Register (CR01) Internal Bus 21 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Figure 5-3. 8-bit Timer/Enent Counter Block Diagram Internal Bus INTIM1 8-Bit Compare Register (CR10) 8-Bit Compare Register (CR20) Selector Match Output Control Circuit TO2/P32 INTTM2 fX/22 to fX/210 Selector fX/212 8-Bit Timer Register 1 (TM1) TI1/P33 Clear Selector 8-Bit Timer Register 2 (TM2) Clear fX/22 to fX/210 Selector Selector fX/212 TI2/P34 Output Control Circuit TO1/P31 Internal Bus Figure 5-4. Watch Timer Block Diagram Selector fX/28 Selector fW Selector Prescaler fXT fW 24 fW 25 fW 26 fW 27 fW 28 INTWT fW 213 fW 29 Selector 22 5-Bit Counter fW 214 INTTM3 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Figure 5-5. Watchdog Timer Block Diagram fX 24 Prescaler fX 25 fX 26 fX 27 fX 28 fX 29 fX 210 fX 212 INTWDT Maskable Interrupt Request Selector Control Circuit 8-Bit Counter RESET INTWDT Non-Maskable Interrupt Request 5.4 CLOCK OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for clock output. • 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation) • 32.768 kHz (Subsystem clock: at 32.768 kHz operation) Figure 5-6. Clock Output Control Block Diagram fX/23 fX/24 fX/25 Selector fX/26 Synchronization Circuit Output Control Circuit PCL/P35 fX/27 fX/28 fXT 5.5 BUZZER OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for buzzer output. • 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation) Figure 5-7. Buzzer Output Control Block Diagram fX/210 fX/211 Selector Output Control Circuit BUZ/P36 fX/212 23 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 5.6 A/D CONVERTER The A/D converter has on-chip eight 8-bit resolution channels. There are the following two method to start A/D conversion. • Hardware starting • Software starting Figure 5-8. A/D Converter Block Diagram Series Resistor String AVDD Sample & Hold Circuit ANI0/P10 AVREF ANI1/P11 Voltage Comparator ANI2/P12 ANI3/P13 Tap Selector Selector ANI4/P14 ANI5/P15 ANI6/P16 Succesive Approxmation Register (SAR) ANI7/P17 Falling Edge Detector INTP3/P03 AVSS Control Circuit INTAD INTP3 A/D Conversion Result Register (ADCR) Internal Bus 5.7 SERIAL INTERFACES There are two on-chip clocked serial interfaces as follows. • Serial Interface channel 0 • Serial Interface channel 1 Table 5-3. Type and Function of Serial Interface Function Serial Interface Channel 0 Serial Interface Channel 1 3-wire serial I/O mode O (MSB/LSB-first switchable) O (MSB/LSB-first switchable) 3-wire serial I/O mode with automatic data transmit/ – O (MSB/LSB-first switchable) O (MSB-first) – O (MSB-first) – receive function 2-wire serial I/O mode 2 I C (Inter IC) bus mode 24 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Figure 5-9. Serial Interface Channel 0 Block Diagram Internal Bus SI0/SB0/SDA0/P25 Serial I/O Shift Register 0 (SIO0) Selector Output Latch SO0/SB1/SDA1/P26 Start Condition/ Stop Condition/ Acknowledge Detection Circuit Selector Serial Clock Counter SCK0/SCL/P27 Acknowlede Output Circuit Interrupt Request Signal Generator INTCSI0 fx/22 to fx/29 Serial Clock Control Circuit Selector TO2 Figure 5-10. Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Transmit/ Receive Address Pointer (ADTP) SI1/P20 Buffer RAM Serial I/O Shift Register 1 (SIO0) SO1/P21 STB/P23 BUSY/P24 SCK/P22 Handshake Control Circuit Serial Clock Counter Interrupt Request Signal Generator INTCSI1 fX/22 to fX/29 Serial Clock Control Circuit Selector TO2 25 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 INTERRUPT FUNCTIONS There are interrupt functions, 14 sources of three different kinds, as shown below. • Non-maskable : • Maskable • Software : 12 : 1 1 Table 6-1. Interrupt Source List Interrupt Type Default Priority Note 1 Interrupt Source Name Trigger Non-maskable ––– INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (with interval timer mode selected) 1 INTP0 2 Software Pin input edge detection Internal/ External Vector Table Address Basic Configuratin Type Note 2 Internal 0004H (A) (B) 0006H (C) INTP1 0008H (D) 3 INTP2 000AH 4 INTP3 000CH 5 INTCSI0 Serial interface channel 0 transfer end 6 INTCSI1 Serial interface channel 1 transfer end 0010H 7 INTTM3 Reference time interval signal from watch timer 0012H 8 INTTM0 16 bit timer/event counter match signal generation 0014H 9 INTTM1 8-bit timer/event counter 1 match signal generation 0016H 10 INTTM2 8-bit timer/event counter 2 match signal generation 0018H 11 INTAD A/D converter conversion end 001AH ––– BRK BRK instruction execution External Internal ––– 000EH 003EH (B) (E) Notes 1. The default pririty is the priority applicable when more than one maskable interrupt request is generated. 0 is the highest priority and 11, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) on the next page. 26 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Figure 6-1. Basic Interrupt Function Configuration (1/2) (A) Internal Non-Maskable Interrupt Internal Bus Interrupt Request Vector Table Address Generator Priority Control Circuit Standby Release Signal (B) Internal Maskable Interrupt Internal Bus MK Interrupt Request PR IE ISP Vector Table Address Generator Priority Control Circuit IF Standby Release Signal (C) External Maskable Interrupt (INTP0) Internal Bus Sampling Clock Select Register (SCS) Interrupt Request Sampling Clock External Interrupt Mode Register (INTM0) Edge Detector MK IF IE PR Priority Control Circuit ISP Vector Table Address Generator Standby Release Signal 27 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Figure 6-1. Basic Interrupt Function Configuration (2/2) (D) External Maskable Interrupt (Except INTP0) Internal Bus External Interrupt Mode Register (INTM0) Interrupt Request Edge Detector MK IE PR Priority Control Circuit IF ISP Vector Table Address Generator Standby Release Signal (E) Software Interrupt Internal Bus Interrupt Request IF IE ISP MK PR 28 : Interrupt request flag : Interrupt enable flag : In-service priority flag : Interrupt mask flag : Priority spcification flag Priority Control Circuit Vector Table Address Generator µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 6.2 TEST FUNCTIONS There are two test functions as shown in Table 6-2. Table 6-2. Test Source List Test Source Internal/External Name Trigger INTWT Watch timer overflow Internal INTPT4 Port 4 falling edge detection External Figure 6-2. Test Function Basic Configuration Internal Bus MK Test Input IF IF Standby Release Signal : Test input flag MK : Test mask flag 29 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 7. EXTERNAL DEVICE EXPANSION FUNCTIONS The external device expansion function is used to connect external devices to areas other than the internal ROM, RAM and SFR. Ports 4 to 6 are used for connection with external devices. 8. STANDBY FUNCTIONS There are the following two standby functions to reduce the current dissipation. • HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operat ing mode. • STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates withultra-low power consumption using only the subsystem clock. Figure 8-1. Standby Functions CSS=1 Main System Clock Operation Interrupt Request CSS=0 HALT Instruction STOP Instruction Interrupt Request STOP Mode (Main system clock oscillation stopped) HALT Mode (Clock supply to CPU is stopped, oscillation) Subsystem Clock OperationNote Interrupt Request HALT Instruction HALT ModeNote (Clock supply to CPU is stopped, oscillation) Note The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set the MCC to stop the main system clock. The STOP instruction cannot be used. Caution When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program. 9. RESET FUNCTIONS There are the following two reset methods. • External reset input by RESET pin. • Internal reset by watchdog timer runaway time detection. 30 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 10. INSTRUCTION SET (1) 8-Bit Instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ 2nd Operand #byte A r Note sfr saddr !addr16 MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP PSW [DE] [HL] MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV [HL+byte] [HL+B] $adder16 [HL+C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP 1 None ROR ROL RORC ROLC MOV INC DEC ADD ADDC SUB SUBC AND OR XOR CMP B, C DBNZ sfr MOV MOV sadder MOV MOV ADD ADDC SUB DBNZ INC DEC SUBC AND OR XOR CMP !adder16 PSW MOV MOV MOV [DE] MOV [HL] MOV [HL+byte] [HL+B] [HL+C] MOV PUSH POP ROR4 ROL4 X MULU C DIVUW Note Except r=A 31 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (2) 16-Bit Instruction MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand 1st Operand AX #byte AX rp Note ADDW MOVW SUBW XCHW saddrp MOVW !addr16 MOVW SP MOVW None MOVW CMPW rp MOVW MOVWNote sfrp MOVW MOVW sadderp MOVW MOVW MOVW MOVW !adder16 SP INCW, DECW PUSH, POP MOVW Note Only when rp=BC, DE, HL. (3) Bit Manipulation Instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd Operand A.bit sfr.bit saddr.bit PWS.bit [HL].bit CY $addr16 None 1st Operand A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 CY 32 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (4) Call Instruction/Branch Instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd Operand AX !addr16 !addr11 [addr5] $addr16 1st Operand Basic instruction Compound instruction BR CALL, BR CALLF CALLT BR, BC, BNC, BZ, BNZ BT,BF, BTCLR, DBNZ (5) Other Instruction ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 33 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Supply voltage Input voltage Rating Unit VDD –0.3 to +7.0 V AVDD –0.3 to VDD + 0.3 V AVREF –0.3 to VDD + 0.3 V AVSS –0.3 to +0.3 V –0.3 to VDD + 0.3 V –0.3 to +16 V –0.3 to VDD + 0.3 V AVSS – 0.3 to AVREF + 0.3 V 1 pin –10 mA P10 to P17, P20 to P27, P30 to P37 total –15 mA P01 to P03, P40 to P47, P50 to P57, P60 to P67 total –15 mA Peak value 30 mA rms 15 mA Peak value 100 mA rms 70 mA P01 to P03, P56, P57, Peak value 100 mA P60 to P67 total rms 70 mA P01 to P03, Peak value 50 mA P64 to P67 total rms 20 mA P10 to P17, P20 to P27, P30 to P37 Peak value 50 mA total 20 mA VI1 Test Conditions P00 to P04, P10 to P17, P20 to P27, P30 to P37 P40 toP47, P50 to P57, P64 to P67, X1, X2, XT2 VI2 Output voltage VO Analog input voltage VAN Output current high IOH Output current low P60 to P67 P10 to P17 1 pin P40 to P47, P50 to P55 total IOLNote Open-drain Analog input pin rms Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –65 to +150 °C Note rms should be calculated as follows: [rms] = [peak value] × √duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. 34 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Capacitance ( TA = 25 °C, VDD = VSS = 0 V ) Parameter Symbol Input capacitance CIN Test Conditions MIN. TYP. f = 1 MHz Unmeasured pins returned to 0 V I/O capacitance MAX. Unit 15 pF 15 pF 20 pF P01 to P03, P10 to P17, f = 1 MHz Unmeasured P20 to P27, P30 toP37, CIO pins returned to 0 V P40 toP47, P50 to P57, P64 to P67 P60 to P63 Remark The characteristics of a dual-function pin and a port pin are the same unless specified otherwise. Main System Clock Oscillation Circuit Characteristics ( TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator Ceramic resonator Recommended Circuit X1 X2 VSS Parameter Oscillator frequency (fX) Note 1 R1 C1 Crystal resonator X1 C2 X2 VSS C1 C2 Test Conditions MIN. TYP. MAX. 2.7 V ≤ VDD ≤ 5.5 V 1 10 1.8 V ≤ VDD < 2.7 V 1 5 Unit MHz Oscillation stabilization time Note 2 After VDD reaches oscillator voltage range MIN. Oscillator frequency (fX) Note 1 2.7 V ≤ VDD ≤ 5.5 V 1 10 1.8 V ≤ VDD < 2.7 V 1 5 Oscillation stabilization time Note 2 VDD = 4.5 to 5.5 V 4 ms MHz 10 ms 30 External clock X1 X2 X1 input frequency (fX) Note 1 1.0 10.0 MHz 45 500 ns X1 input µPD74HCU04 high/low level width (tXH , tXL) Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wiring the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ● Wiring should be as short as possible. ● Wiring should not cross other signal lines. ● Wiring should not be placed close to a varying high current. ● The potential of the oscillator capacitor ground should be the same as VSS. ● Do not ground wiring to a ground pattern in which a high current flows. ● Do not fetch a signal from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. 35 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator Crystal resonator Recommended Circuit XT1 XT2 VSS Test Conditions Oscillator frequency (fXT) Note 1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 R2 C3 External clock Parameter XT1 C4 XT2 Oscillation stabilization time Note 2 V DD = 4.5 to 5.5 V s 10 XT1 input frequency (fXT) Note 1 32 100 kHz XT1 input high/low level width (tXTH , tXTL) 5 15 µs Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ● Wiring should be as short as possible. ● Wiring should not cross other signal lines. ● Wiring should not be placed close to a varying high current. ● The potential of the oscillator capacitor ground should be the same as VSS. ● Do not ground wiring to a ground pattern in which a high current flows. ● Do not fetch a signal from the oscillator. 2. The subsystem clock oscillation circuit is a circuit with a low amplification level,more prone to misoperation due to noise than the main system clock. Particular care is therefore required with the wiring method when the subsystem clock is used. 36 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Recommended Oscillation Circuit Constant Recommended oscillation circuit constant differs depending on the model. (1) µPD78011FY, 78012FY, 78013FY, 78014FY (a) Main system clock: ceramic resonator (TA = –45 to +85 °C) Manufacturer TDK Corp. Product Name CCR4.19MC3 Murata Mfg. Co. Ltd. Frequency (MHz) 4.19 Recommended Oscillation Circuit Constant Oscillation Voltage Range C1 (pF) C2 (pF) MIN. (V) MAX. (V) Built-in Built-in 1.8 5.5 FCR4.19MC5 4.19 Built-in Built-in 1.8 5.5 CCR5.00MC3 5.00 Built-in Built-in 1.8 5.5 FCR5.00MC5 5.00 Built-in Built-in 1.8 5.5 CCR8.38MC 8.00 Built-in Built-in 2.7 5.5 FCR8.38MC5 8.00 Built-in Built-in 2.7 5.5 CCR10.00MC 10.00 Built-in Built-in 2.7 5.5 FCR10.00MC5 10.00 Built-in Built-in 2.7 5.5 CSA4.19MG 4.19 30 30 1.8 5.5 CST4.19MGW 4.19 Built-in Built-in 1.8 5.5 CSA5.00MG 5.00 30 30 1.8 5.5 CST5.00MGW 5.00 Built-in Built-in 1.8 5.5 CSA8.38MTZ 8.38 30 30 2.7 5.5 CST8.38MTW 8.38 Built-in Built-in 2.7 5.5 CSA10.00MTZ 10.00 30 30 2.7 5.5 CST10.00MTW 10.00 Built-in Built-in 2.7 5.5 (b) Main system clock: ceramic resonator (TA = –20 to +80 °C) Manufacturer Kyocera Corp. Caution Product Name Frequency (MHz) Recommended Oscillation Circuit Constant Oscillation Voltage Range C1 (pF) C2 (pF) MIN. (V) MAX. (V) PBRC5.00A 5.00 33 33 1.8 5.5 PBRC5.00B 5.00 Built-in Built-in 1.8 5.5 KBR-5.00MSA 5.00 33 33 1.8 5.5 KBR-5.00MKS 5.00 Built-in Built-in 1.8 5.5 KBR-8M 8.00 33 33 2.7 5.5 KBR-10M 10.00 33 33 2.7 5.5 The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact manufacturer of the resonator being used. 37 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (2) µPD78015FY, 78016FY (a) Main system clock: ceramic resonator (TA = –45 to +85 °C) Manufacturer Product Name Frequency (MHz) Recommended Oscillation Circuit Constant C1 (pF) Murata Mfg. Co. Ltd. Murata Mfg. Co. Ltd. (EMI noise reduced products) TDK Corp. CSB1000J 1.00 CSA2.00MG040 2.00 CST2.00MG040 2.00 CSA4.00MG040 4.00 CST4.00MGW040 CSA6.00MG CST6.00MGW 6.00 CSA10.0MTZ 10.0 CST10.0MTW 10.0 CSA6.00MG040 6.00 CST6.00MGW040 6.00 100 C2 (pF) Oscillation Voltage Range R1 (kΩ) MIN. (V) MAX. (V) 100 5.6 1.8 6.0 100 100 0 1.8 6.0 Built-in Built-in 0 1.8 6.0 100 100 0 1.8 6.0 4.00 Built-in Built-in 0 1.8 6.0 6.00 30 30 0 1.8 6.0 Built-in Built-in 0 1.8 6.0 30 30 0 1.8 6.0 Built-in Built-in 0 1.8 6.0 100 100 0 2.7 6.0 Built-in Built-in 0 2.7 6.0 CSA10.0MTZ040 10.0 100 100 0 2.7 6.0 CST10.0MTW040 10.0 Built-in Built-in 0 2.7 6.0 FCR4.0MC5 4.0 Built-in Built-in 2.2 1.8 6.0 FCR10.0MC 10.0 Built-in Built-in 1.0 1.8 6.0 (b) Main system clock: ceramic resonator (TA = –20 to +80 °C) Manufacturer Product Name Frequency (MHz) Recommended Oscillation Circuit Constant C1 (pF) Kyocera Corp. Caution Oscillation Voltage Range C2 (pF) MIN. (V) MAX. (V) PBRC5.00A 5.00 33 33 1.8 5.5 PBRC5.00B 5.00 Built-in Built-in 1.8 5.5 KBR-5.00MSA 5.00 33 33 1.8 5.5 KBR-5.00MKS 5.00 Built-in Built-in 1.8 5.5 KBR-8M 8.00 33 33 2.7 5.5 KBR-10M 10.00 33 33 2.7 5.5 The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact manufacturer of the resonator being used. 38 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (3) µPD78018FY (a) Main system clock: ceramic resonator (TA = –40 to +85 °C) Manufacturer TDK Corp. Murata Mfg. Co. Ltd. Product Name Frequency (MHz) Recommended Oscillation Circuit Constant Oscillation Voltage Range C1 (pF) C2 (pF) MIN. (V) MAX. (V) CCR4.0MC3 4.00 Built-in Built-in 1.8 5.5 FCR4.0MC5 4.00 Built-in Built-in 1.8 5.5 CCR8.0MC5 8.00 Built-in Built-in 2.7 5.5 FCR8.0MC 8.00 Built-in Built-in 2.7 5.5 CCR10.0MC5 10.0 Built-in Built-in 2.7 5.5 FCR10.0MC 10.0 Built-in Built-in 2.7 5.5 CSA4.0MG 4.00 30 30 1.8 5.5 CST4.0MGW 4.00 Built-in Built-in 1.8 5.5 CSA8.0MTZ 8.00 30 30 2.7 5.5 CST8.0MTW 8.00 Built-in Built-in 2.7 5.5 (b) Main system clock: ceramic resonator (TA = –20 to +80 °C) Manufacturer Kyocera Corp. Caution Product Name Frequency (MHz) Recommended Oscillation Circuit Constant Oscillation Voltage Range C1 (pF) C2 (pF) MIN. (V) MAX. (V) 1.8 5.5 FBRC4.00A 4.00 33 33 FBRC4.00B 4.00 Built-in Built-in 1.8 5.5 KBR-4.00MSB 4.00 33 33 1.8 5.5 KBR-4.00MKC 4.00 Built-in Built-in 1.8 5.5 KBR-8M 8.00 33 33 2.7 5.5 KBR-10M 10.00 33 33 2.7 5.5 The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact manufacturer of the resonator being used. 39 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Input voltage Symbol VIH1 high Test Conditions MAX. Unit 0.7 VDD VDD V 0.8 VDD VDD V P00 to P03, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V 0.8 VDD VDD V P33, P34, RESET 0.85 VDD VDD V VDD = 2.7 to 5.5 V 0.7 VDD 15 V 0.8 VDD 15 V VDD = 2.7 to 5.5 V VDD – 0.5 VDD V VDD – 0.2 VDD V 4.5 V ≤ VDD ≤ 5.5 V 0.8 VDD VDD V 2.7 V ≤ VDD < 4.5 V 0.9 VDD VDD V 1.8 V ≤ VDD < 2.7 V Note 0.9 VDD VDD V 0 0.3 VDD V P50 to P57, P64 to 67 0 0.2 VDD V P00 to P03, P20, P22, P24 to P27, VDD = 2.7 to 5.5 V 0 0.2 VDD V P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V MIN. TYP. P35 to P37, P40 to P47, P50 to P57, P64 to 67 VIH2 VIH3 P60 to P63 (N-ch open-drain) VIH4 VIH5 Input voltage VIL1 low X1, X2 XT1/P04, XT2 P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 5.5 V P35 to P37, P40 to P47, VIL2 P33, P34, RESET VIL3 VIL4 VIL5 Output VOH1 voltage high Output VOL1 P60 to P63 X1, X2 XT1/P04, XT2 0 0.15 VDD V 4.5 V ≤ VDD ≤ 5.5 V 0 0.3 VDD V 2.7 V ≤ VDD < 4.5 V 0 0.2 VDD V 0 0.1 VDD V VDD = 2.7 to 5.5 V 4.5 V ≤ VDD ≤ 5.5 V 0 0.4 V 0 0.2 V 0 0.2 VDD V 2.7 V ≤ VDD < 4.5 V 0 0.1 VDD V 1.8 V ≤ VDD < 2.7 V Note 0 0.1 VDD V VDD = 4.5 to 5.5 V, IOH = –1 mA VDD – 1.0 V IOH = –100 µA VDD – 0.5 V P50 to P57, P60 to P63 voltage low VDD = 4.5 to 5.5 V, 0.4 2.0 V 0.4 V 0.2 VDD V 0.5 V IOL = 15 mA VOL2 P01 to P03, P10 to P17, P20 to P27 VDD = 4.5 to 5.5 V, P30 to P37, P40 to P47, P64 to P67 IOL = 1.6 mA SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, open-drain pulled-up (R = 1 KΩ) VOL3 Note When using XT1/P04 as P04, input the inverse of P04 to XT2 using an inverter. Remark 40 IOL = 400 µA The characteristics of a dual-function pin and a port pin are the same unless specified otherwise. µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Symbol Input leakage ILIH1 Test Conditions MAX. Unit 3 µA X1, X2, XT1/P04, XT2 20 µA VIN = 15 V P60 to P63 80 µA VIN = 0 V P00 to P03, P10 to P17, –3 µA –20 µA –3 Note µA VOUT = VDD 3 µA VOUT = 0 V –3 µA VIN = VDD current high MIN. TYP. P00 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, RESET ILIH2 ILIH3 Input leakege ILIL1 current low P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, RESET ILIL2 X1, X2, XT1/P04, XT2 ILIL3 P60 to P63 Output leakage ILOH1 current high Output leakage ILOL current low Mask option R1 VIN = 0 V, P60 to P63 20 40 90 kΩ R2 VIN = 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37, 15 40 90 kΩ pull-up resister Software pull-up resister P40 to P47, P50 to P57, P60 to P67 Note For P60 to P63, if pull-up resistor is not provided (specifiable by mask option) a low-level input leak current of –200 µA (MAX.) flows only during the 3 clocks (no-wait time) after an instruction has been executed to read out port 6 (P6) or port mode register 6 (PM6). Outside the period of 3 clocks following execution a read-out instruction, the current is –3 µA (MAX.). Remark The characteristics of a dual-function pin and a port pin are the same unless specified otherwise. 41 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Supply current Symbol IDD1 Note 1 IDD2 IDD3 Test Conditions IDD6 MAX. Unit VDD = 5.0 V ± 10 % Note 2 9.0 18.0 mA oscillation operation mode VDD = 3.0 V ± 10 % Note 3 1.3 2.6 mA 10.00 MHz crystal VDD = 5.0 V ± 10 % Note 2 2.4 4.8 mA oscillation HALT mode VDD = 3.0 V ± 10 % Note 3 1.2 2.4 mA VDD = 5.0 V ± 10 % 60 120 µA VDD = 3.0 V ± 10 % 35 70 µA VDD = 2.0 V ± 10 % 24 48 µA VDD = 5.0 V ± 10 % 25 50 µA VDD = 3.0 V ± 10 % 5 15 µA 32.768 kHz crystal Note 4 32.768 kHz crystal oscillation HALT mode IDD5 TYP. 10.00 MHz crystal oscillation operation mode IDD4 MIN. Note 4 VDD = 2.0 V ± 10 % 2 10 µA XT1 = VDD VDD = 5.0 V ± 10 % 1 30 µA STOP mode when using feedback VDD = 3.0 V ± 10 % 0.5 10 µA resistor VDD = 2.0 V ± 10 % 0.3 10 µA XT1 = VDD VDD = 5.0 V ± 10 % 0.1 30 µA STOP mode when not using VDD = 3.0 V ± 10 % 0.05 10 µA feedback resistor VDD = 2.0 V ± 10 % 0.05 10 µA Notes 1. This current excludes the AVREF current, port current, and current which flows in the built-in pull-down resistor. 2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H) 3. When operating at low-speed mode (when the PCC is set to 04H) 4. When main system clock stopped. 42 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY AC Characteristics (1) Basic Operation (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 3.5 V ≤ VDD ≤ 5.5 V 0.4 64 µs (Min. instruction 2.7 V ≤ VDD < 3.5 V 0.8 64 µs execution time) 1.8 V ≤ VDD < 2.7 V 2.0 64 µs 125 µs Cycle time TCY Operating on main system clock Operating on subsystem clock TI0 input frequency TI1, TI2 input 40 2/fsam + 0.1 µs Note µs µs tTIH0 3.5 V ≤ VDD ≤ 5.5 V tTIL0 2.7 V ≤ VDD < 3.5 V 2/fsam + 0.2 1.8 V ≤ VDD < 2.7 V 2/fsam + 0.5 Note fTI1 VDD = 4.5 to 5.5 V frequency TI1, TI2 input 122 Note tTIH1 VDD = 4.5 to 5.5 V 0 4 MHz 0 275 kHz 100 ns 1.8 µs 3.5 V ≤ VDD ≤ 5.5 V 2/fsam + 0.1 Note µs 2.7 V ≤ VDD < 3.5 V 2/fsam + 0.2 Note µs 1.8 V ≤ VDD < 2.7 V Note µs high/low-level tTIL1 width Interrupt tINTH request input tINTL INTP0 high/low-level width INTP1 to INTP3, KR0 to KR7 RESET low tRSL VDD = 2.7 to 5.5 V level width VDD = 2.7 to 5.5 V 2/fsam + 0.5 10 µs 20 µs 10 µs 20 µs Note In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fX/2N+1, fX/64 and fX/128 (when N= 0 to 4). 43 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY TCY vs VDD (At main system clock operation) 60.0 Operation Guaranteed Range Cycle Time TCY [ µ S] 10.0 5.0 1.0 0.5 0.1 0 1.0 3.0 3.5 4.0 2.0 1.8 2.7 Supply voltage VDD [V] 44 5.0 5.5 6.0 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (2) Read/Write Operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.5tCY ns Address setup time tADS 0.5tCY – 30 ns Address hold time tADH 50 ns Data input time from address Data input time from RD↓ tADD1 (2.5 + 2n) tCY – 50 ns tADD2 (3 + 2n) tCY – 100 ns tRDD1 (1 + 2n) tCY – 25 ns tRDD2 (2.5 + 2n) tCY – 100 ns Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n) tCY – 20 ns tRDL2 (2.5 + 2n) tCY – 20 ns WAIT↓ input time from RD↓ tRDWT1 0.5tCY ns tRDWT2 1.5tCY ns WAIT↓ input time from WR↓ tWRWT 0.5tCY ns WAIT low-level width tWTL (0.5 + 2n) tCY + 10 (2 + 2n) tCY ns Write data setup time tWDS 100 ns Write data hold time tWDH 20 ns WR low-level width tWRL1 (2.5 + 2n) tCY – 20 ns RD↓ delay time from ASTB↓ tASTRD 0.5tCY – 30 ns WR↓ delay time from ASTB↓ tASTWR 1.5tCY – 30 ns ASTB↑ delay time from RD↑ in external fetch tRDAST tCY – 10 tCY + 40 ns Address hold time from RD↑ in external fetch tRDADH tCY tCY + 50 ns Write data output time from RD↑ tRDWD 0.5tCY + 5 0.5tCY + 30 ns 0.5tCY + 15 0.5tCY + 90 ns 30 ns Load resistor ≥ 5 kΩ VDD = 4.5 to 5.5 V Write data output time from WR↓ tWRWD VDD = 4.5 to 5.5 V 5 15 90 ns Address hold time from WR↑ tWRADH VDD = 4.5 to 5.5 V tCY tCY + 60 ns tCY tCY + 100 ns RD↑ delay time from WAIT↑ tWTRD 0.5tCY 2.5tCY + 80 ns WR↑ delay time from WAIT↑ tWTWR 0.5tCY 2.5tCY + 80 ns Remarks 1. tCY = TCY/4 2. n indicates number of waits. 45 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (3) Serial Interface (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V) (a) Serial Interface Channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output) Parameter SCK0 cycle time Symbol tKCY1 SCK0 high/low-level tKH1 width tKL1 SI0 setup time tSIK1 (to SCK0↑) SI0 hold time Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns tKCY1/2 – 50 ns VDD = 4.5 to 5.5 V tKCY1/2 – 100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.5 V 150 ns 2.0 V ≤ VDD < 2.7 V 300 ns 400 ns 400 ns tKSI1 (from SCK0↑) SO0 output delay time tKSO1 C = 100 pF Note 300 ns MAX. Unit from SCK0↓ Note C is the load capacitance of SCK0 and SO0 output line. (ii) 3-wire serial I/O mode (SCK0... External clock input) Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. TYP. 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns SCK0 high/low-level tKH2 4.5 V ≤ VDD ≤ 5.5 V 400 ns width tKL2 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V SI0 setup time tSIK2 VDD = 2.0 to 5.5 V (to SCK0↑) SI0 hold time tKSI2 1600 ns 2400 ns 100 ns 150 ns 400 ns (from SCK0↑) SO0 output delay time tKSO2 C = 100 pF Note VDD = 2.0 to 5.5 V tR2 When external device tF2 expansion function is used from SCK0↓ SCK0 rise, fall time When external When 16-bit timer 300 ns 500 ns 160 ns 700 ns 1000 ns device expansion output function is function is not used used When 16-bit timer output function is not used Note C is the load capacitance of SO0 output line. 46 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (iii) 2-wire serial I/O mode (SCK0... Internal clock output) Parameter SCK0 cycle time SCK0 high-level width Symbol tKCY3 tKH3 Test Conditions MIN. TYP. MAX. Unit R = 1 kΩ Note 2.7 V ≤ VDD ≤ 5.5 V 1600 ns C = 100 pF 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns VDD = 2.7 to 5.5 V tKCY3/2 – 160 ns tKCY3/2 – 190 ns tKCY3/2 – 50 ns SCK0 low-level width tKL3 VDD = 4.5 to 5.5 V tKCY3/2 – 100 ns SB0, SB1 setup time tSIK3 4.5 V ≤ VDD ≤ 5.5 V 300 ns 2.7 V ≤ VDD < 4.5 V 350 ns 2.0 V ≤ VDD < 2.7 V 400 ns (to SCK0↑) SB0, SB1 hold time 500 ns tKSI3 600 ns tKSO3 0 (from SCK0↑) SB0, SB1 output delay 300 ns time from SCK0↓ Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line. 47 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (iv) 2-wire serial I/O mode (SCK0... External clock input) Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time Symbol tKCY4 tKH4 tKL4 tSIK4 Test Conditions TYP. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns 2.7 V ≤ VDD ≤ 5.5 V 650 ns 2.0 V ≤ VDD < 2.7 V 1300 ns 2100 ns 2.7 V ≤ VDD ≤ 5.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns 100 ns 150 ns tKCY4/2 ns VDD = 2.0 to 5.5 V (to SCK0↑) SB0, SB1 hold time MIN. tKSI4 (from SCK0↑) SB0, SB1 output delay tKSO4 time from SCK0↓ SCK0 rise, fall time 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns C = 100 pF Note 2.0 V ≤ VDD < 4.5 V 0 500 ns 0 800 ns 160 ns 700 ns 1000 ns R = 1 kΩ, tR4 When external device tF4 expansion function is used When external When 16-bit timer device expansion output function is function is not used used When 16-bit timer output function is not used Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. 48 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (v) I2C bus mode (SCK0... Internal clock output) Parameter SCL cycle time SCL high-level width SCL low-level width Symbol tKCY5 tKH5 Test Conditions MIN. TYP. MAX. Unit R = 1 kΩ Note 2.7 V ≤ VDD ≤ 5.5 V 10 µs C = 100 pF 2.0 V ≤ VDD < 2.7 V 20 µs 30 µs VDD = 2.7 to 5.5 V tKCY5 – 160 ns tKCY5 – 190 ns tKCY5 – 50 ns tKL5 VDD = 4.5 to 5.5 V tKCY5 – 100 ns SDA0, SDA1 setup time tSIK5 2.7 V ≤ VDD ≤ 5.5 V 200 ns (to SCL↑) 2.0 V ≤ VDD ≤ 2.7 V 300 ns 400 ns 0 ns SDA0, SDA1 hold time tKSI5 (from SCL↓) SDA0, SDA1 output tKSO5 delay time from SCL↓ SDA0, SDA1↓ from 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns 2.0 V ≤ VDD < 4.5 V 0 500 ns 0 600 ns tKSB 200 ns 400 ns SDA1↓ 500 ns SDA0, SDA1 high-level tSBH 500 ns SCL↑ or SDA0, SDA1↑ from SCL↑ SCL↓ from SDA0, tSBK VDD = 2.0 to 5.5 V width Note R and C are the load resistance and load capacitance of the SCL, SDA0 and SDA1 output line. 49 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (vi) I2C bus mode (SCK0... External clock output) Parameter Symbol SCL cycle time tKCY6 SCL high/low-level tKH6 width tKL6 SDA0, SDA1 setup tSIK6 Test Conditions VDD = 2.0 to 5.5 V VDD = 2.0 to 5.5 V time (to SCL↑) SDA0, SDA1 hold time tKSI6 MIN. TYP. MAX. Unit 1000 ns 400 ns 600 ns 200 ns 300 ns 0 ns (from SCL↓) SDA0, SDA1 output tKSO6 delay time from SCL↓ SDA0, SDA1↓ from 4.5 V ≤ VDD ≤ 5.5 V 0 300 ns C = 100 pF Note 2.0 V ≤ VDD < 4.5 V 0 500 ns 0 600 ns R = 1 kΩ, 200 tKSB ns SCL↑ or SDA0, SDA1↑ from SCL↑ SCL↓ from SDA0, tSBK VDD = 2.0 to 5.5 V SDA1 SDA0, SDA1 high-level tSBH VDD = 2.0 to 5.5 V width SCL rise, fall time tR6 When external device expansion tF6 function is used When external 400 ns 500 ns 500 ns 800 ns When 16-bit timer 160 ns 700 ns 1000 ns device expansion output function function is not is used used When 16-bit timer output function is not used Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line. 50 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (b) Serial Interface Channel 1 (i) 3-wire serial I/O mode (SCK1... Internal clock output) Parameter SCK1 cycle time Symbol tKCY7 SCK1 high/low-level tKH7 width tKL7 SI1 setup time tSIK7 (to SCK1↑) SI1 hold time Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns VDD = 4.5 to 5.5 V tKCY7/2 – 50 ns tKCY7/2 – 100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.5 V 150 ns 2.0 V ≤ VDD < 2.7 V 300 ns 400 ns 400 ns tKSI7 (from SCK1↑) SO1 output delay time tKSO7 C = 100 pF Note 300 ns MAX. Unit from SCK1↓ Note C is the load capacitance of SCK1 and SO1 output line. (ii) 3-wire serial I/O mode (SCK1... External clock input) Parameter SCK1 cycle time Symbol tKCY8 Test Conditions MIN. TYP. 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns 400 ns SCK1 high/low-level tKH8 4.5 V ≤ VDD ≤ 5.5 V width tKL8 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V 1600 ns 2400 ns SI1 setup time tSIK8 VDD = 2.0 to 5.5 V (to SCK1↑) SI1 hold time tKSI8 100 ns 150 ns 400 ns (from SCK1↑) SO0 output delay time tKSO8 C = 100 pF Note VDD = 2.0 to 5.5 V from SCK1↓ SCK1 rise, fall time tR8 When external device tF8 expansion function is used When external When 16-bit timer 300 ns 500 ns 160 ns 700 ns 1000 ns device expansion output function is function is not used used When 16-bit timer output function is not used Note C is the load capacitance of SO1 output line. 51 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output) Parameter SCK1 cycle time Symbol tKCY9 SCK1 high/low-level tKH9 width tKL9 SI1 setup time tSIK9 (to SCK1↑) SI1 hold time Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns tKCY9/2 – 50 ns tKCY9/2 – 100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.5 V 150 ns 2.0 V ≤ VDD < 2.7 V 300 ns 400 ns 400 ns VDD = 4.5 to 5.5 V tKSI9 (from SCK1↑) SO1 output delay time tKSO9 C = 100 pF Note 300 ns tKCY9/2 – 100 tKCY9/2 + 100 ns 2.7 V ≤ VDD ≤ 5.5 V tKCY9 – 30 tKCY9 + 30 ns 2.0 V ≤ VDD < 2.7 V tKCY9 – 60 tKCY9 + 60 ns tKCY9 – 90 tKCY9 + 90 ns from SCK1↓ STB↑ from SCK1↑ tSBD Strobe signal tSBW high-level width Busy signal setup time tBYS 100 ns 4.5 V ≤ VDD ≤ 5.5 V 100 ns (from busy signal 2.7 V ≤ VDD < 4.5 V 150 ns detection timing) 2.0 V ≤ VDD < 2.7 V 200 ns 300 ns (to busy signal detection timing) Busy signal hold time SCK1↓ from busy tBYH tSPS inactive Note C is the load capacitance of SCK1 and SO1 output line. 52 2tKCY9 ns µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock input) Parameter SCK1 cycle time Symbol tKCY10 Test Conditions MIN. TYP. MAX. Unit 4.5 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.5 V 1600 ns 2.0 V ≤ VDD < 2.7 V 3200 ns 4800 ns SCK1 high/low-level tKH10, 4.5 V ≤ VDD ≤ 5.5 V 400 ns width tKL10 2.7 V ≤ VDD < 4.5 V 800 ns 2.0 V ≤ VDD < 2.7 V SI1 setup time tSIK10 VDD = 2.0 to 5.5 V (to SCK1↑) SI1 hold time tKSI10 1600 ns 2400 ns 100 ns 150 ns 400 ns (from SCK1↑) SO1 output delay time tKSO10 C = 100 pF Note VDD = 2.0 to 5.5 V tR10, tF10 When external device expansion from SCK1↓ SCK1 rise, fall time 300 ns 500 ns 160 ns 1000 ns function is used When external device expansion function is not used Note C is the load capacitance of the SO1 output line. 53 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY AC Timing Test Point (Excluding X1, XT1 Input) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) VIL4 (MAX.) X1 Input 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.) XT1 Input TI Timing tTIH0 tTIL0 TI0 1/fTI1 tTIL1 TI1,TI2 54 tTIH1 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Read/Write Operation External fetch (No wait): A8 to A15 Higher 8-Bit Address tADD1 Hi-Z Lower 8-Bit Address AD0 to AD7 tADS tADH Operation Code tRDD1 tRDADH tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH External fetch (Wait insertion): A8 to A15 Higher 8-Bit Address tADD1 Lower 8-Bit Address AD0 to AD7 tADS tADH Hi-Z Operation Code tRDADH tRDD1 tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 tWTL tWTRD 55 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY External data access (No wait): A8 to A15 Higher 8-Bit Address tADD2 Hi-Z Lower 8-Bit Address AD0 to AD7 tADS Read Data Hi-Z Hi-Z Write Data tRDD2 tADH tASTH tRDH ASTB RD tASTRD tRDWD tRDL2 tWDS tWDH tWRWD tWRADH WR tASTWR tWRL1 External data access (Wait insertion): A8 to A15 Higher 8-Bit Address tADD2 Lower 8-Bit Address AD0 to AD7 Hi-Z Read Data Hi-Z Hi-Z Write Data tADS tADH tASTH tRDD2 tRDH ASTB tASTRD RD tRDL2 tRDWD tWDH tWDS tWRWD WR tASTWR tWRL1 tWRADH WAIT tRDWT2 tWTL tWTRD tWTL tWRWT 56 tWTWR µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKLm tKHm tFn tRn SCK0,SCK1 tSIKm SI0,SI1 tKSIm Input Data tKSOm Output Data SO0,SO1 m = 1, 2, 7, 8 n = 2, 8 2-wire serial I/O mode: tKCY5,6 tKL5,6 tR6 tKH5,6 tF6 SCK0 tKSO5,6 tSIK5,6 tKSI5,6 SB0, SB1 I2C bus mode: tF6 tR6 tKCY5, 6 SCL tKL5, 6 tKH5, 6 tKSI5, 6 tSIK5, 6 tKSO5, 6 tKSB tKSB tSBK SDA0, SDA1 tSBH tSBK 57 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 3-wire serial I/O mode with automatic transmit/receive function: SO1 SI1 D2 D1 D2 D7 D0 D1 D7 D0 tSIK9,10 tKSI9,10 tKSO9,10 tKH9,10 tF10 SCK1 tKL9,10 tKCY9,10 tR10 tSBD tSBW STB 3-wire serial I/O mode with automatic transmit/receive function (busy processing): SCK1 8 7 9 Note 10 Note tBYS Note 1 10 + n tBYH tSPS BUSY (Active High) Note The signal is not actually driven low here; it is shown as such to indicate the timing. A/D converter characteristics (TA = –40 to +85 °C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 8 8 8 bit 2.7 V ≤ AVREF ≤ AVDD 0.6 % 1.8 V ≤ AVREF < 2.7 V 1.4 % Resolution Overall error Note Conversion time tCONV 2.0 V ≤ AVDD ≤ 5.5 V 19.1 200 µs 1.8 V ≤ AVDD < 2.0 V 38.2 200 µs µs Sampling time tSAMP 24/fX Analog input voltage VIAN AVSS AVREF V Reference voltage AVREF 1.8 AVDD V AVREF resistance RAIREF 4 14 Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value. 58 kΩ µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C) Parameter Symbol Data retention supply Test Conditions VDDDR MIN. TYP. 1.8 MAX. Unit 5.5 V 10 µA voltage Data retention supply IDDDR current VDDDR = 1.8 V 0.1 Subsystem clock stop and feedback resister disconnected Release signal set time Oscillation stabilization tSREL tWAIT wait time µs 0 18 Release by RESET 2 /fX ms Release by interrupt request Note ms Note In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS), selection of 213/fX and 215/fX to 218/fX is possible. Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retension Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby Release Signal : STOP Mode Release by Interrupt Request Signal) HALT Mode Operating Mode STOP Mode Data Retension Mode VDD VDDDR tSREL STOP Instruction Execition Standby Release Signal (Interrupt Request) tWAIT 59 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Interrupt Request Input Timing tINTL INTP0 to INTP2 tINTL INTP3 RESET Input Timing tRSL RESET 60 tINTH µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 12. CHARACTERISTIC CURVE (REFERENCE VALUES) IDD vs VDD (Main System Clock: 10.0 MHz) (TA = 25 °C) 10.0 PCC = 00H PCC = 01H 5.0 PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 Oscillation, XT1 Stop) 1.0 Supply Current IDD [mA] 0.5 0.1 0.05 PCC = B0H HALT (X1 Stop, XT1 Oscillation) 0.01 0.005 fX = 10.0 MHz fXT = 32.768 kHz 0.001 0 1 2 3 4 5 6 7 8 Supply Voltage VDD [V] 61 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 13. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K H G J I L F D N M NOTE B C M R ITEM MILLIMETERS INCHES 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. A 58.68 MAX. 2.311 MAX. B 1.78 MAX. 0.070 MAX. 2) Item "K" to center of leads when formed parallel. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.31 MAX. 0.170 MAX. J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0 0.669 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0~15° 0~15° P64C-70-750A,C-1 Remark 62 Dimensions and materials of ES products are the same as those of mass-production products. µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 64 PIN PLASTIC QFP ( 14) A B 48 49 33 32 F Q 5°±5° S D C detail of lead end 64 1 G 17 16 H I M J M P K N L P64GC-80-AB8-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. Remark ITEM MILLIMETERS INCHES A 17.6 ± 0.4 0.693 ± 0.016 B 14.0 ± 0.2 0.551 +0.009 –0.008 C 14.0 ± 0.2 0.551+0.009 –0.008 D 17.6 ± 0.4 0.693 ± 0.016 F 1.0 0.039 G 1.0 0.039 H 0.35 ± 0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 1.8 ± 0.2 0.071 ± 0.008 L 0.8 ± 0.2 0.031+0.009 –0.008 M 0.15+0.10 –0.05 0.006 +0.004 –0.003 N 0.10 0.004 P 2.55 0.100 Q 0.1 ± 0.1 0.004 ± 0.004 S 2.85 MAX. 0.112 MAX. Dimensions and materials of ES products are the same as those of mass-production products. 63 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY 14. RECOMMENDED SOLDERING CONDITIONS The µPD78011FY/78012FY/78013FY/78014FY/78015FY/78016FY/78018FY should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact our salespersonnel. Table 14-1. Surface Mounting Type Soldering Conditions (1) µPD78011FYGC-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm) µPD78012FYGC-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm) µPD78013FYGC-×××-AB8 µPD78014FYGC-×××-AB8 µPD78015FYGC-×××-AB8 µPD78016FYGC-×××-AB8 µPD78018FYGC-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm) : 64-Pin Plastic QFP (14 × 14 mm) : 64-Pin Plastic QFP (14 × 14 mm) : 64-Pin Plastic QFP (14 × 14 mm) : 64-Pin Plastic QFP (14 × 14 mm) Soldering Conditions Soldering Method Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Three times max. IR35-00-3 VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), Number of times: Three times max. VP15-00-3 Wave soldering Solder bath temperature: 260 °C max. Duration: 10 sec. max. Number of times: Once Preheating temperature: 120 °C max. (Package surface temperature) WS60-00-1 Partial heating Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side) — Caution Use more than one soldering method should be avoided (except in the case of partial heating). Table 14-2. Insertion Type Soldering Conditions µPD78011FYCW-××× µPD78012FYCW-××× µPD78013FYCW-××× µPD78014FYCW-××× µPD78015FYCW-××× µPD78016FYCW-××× µPD78018FYCW-××× Soldering Method Caution 64 : 64-Pin Plastic Shrink DIP (750 mil) : 64-Pin Plastic Shrink DIP (750 mil) : 64-Pin Plastic Shrink DIP (750 mil) : 64-Pin Plastic Shrink DIP (750 mil) : 64-Pin Plastic Shrink DIP (750 mil) : 64-Pin Plastic Shrink DIP (750 mil) : 64-Pin Plastic Shrink DIP (750 mil) Soldering Conditions Wave soldering (pin only) Solder bath temperature: 260°C max., Duration: 10 sec. max. Partial heating Pin temperature: 300°C max., Duration: 3 sec. max. (per pin) Wave soldering is only for the lead part in order that jet solder can not contact with the chip directly. µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD78018FY subseries. Language Processing Software RA78K/0 Notes 1, 2, 3, 4 78K/0 series common assembler package CC78K/0 Notes 1, 2, 3, 4 78K/0 series common C compiler package DF78014 Notes 1, 2, 3, 4 Device file common to µPD78014 subseries CC78K/0-L Notes 1, 2, 3, 4 78K/0 series common C compiler library source file PROM Writting Tools PG-1500 PROM programmer PA-78P018CW PA-78P018GC PA-78P018KK-S Programmer adapter connected to PG-1500 PG-1500 controller Notes 1, 2 PG-1500 control program Debugging Tool IE-78000-R 78K/0 series common in-circuit emulator IE-78000-R-A 78K/0 series common in-circuit emulator (for integrated debugger) IE-78000-R-BK 78K/0 series common break board IE-78014-R-EM-A µPD78018F and 78018FY subseries evaluation emulation board (VDD = 3.0 to 6.0 V) IE-78000-R-SV3 Interface adapter and cable when an EWS is used as the host machine (for IE-78000-R-A) IE-70000-98-IF-B Interface adapter when PC-9800 series (except notebook PC) is used as the host machine (for IE-78000-R-A) IE-70000-98N-IF Interface adapter and cable when PC-9800 series notebook PC is used as the host machine (for IE-78000-R-A) IE-70000-PC-IF-B Interface adapter when IBM PC/ATTM is used as the host machine (for IE-78000-R-A) EP-78240CW-R EP-78240GC-R Emulation probe common to µPD78244 subseries EV-9200GC-64 Socket to be mounted on target system board created for the 64-pin plastic QFP (GC-AB8 type) EV-9900 Tools for removing µPD78P018FYKK-S from EV-9200GC-64 SM78K0 Notes 5, 6, 7 78K/0 series common system simulator ID78K0 Notes 4, 5, 6, 7 IE-78000-R-A integrated dubugger SD78K0 Notes 1, 2 IE-78000-R screen debugger DF78014 Notes 1, 2, 4, 5, 6, 7 Device file common to µPD78014 subseries Real-Time OS RX78K/0 Notes 1, 2, 3, 4 MX78K0 Notes 1, 2, 3, 4 78K/0 series real-time OS 78K/0 series OS 65 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Fuzzy Inference Devleopment Support System FE9000 Note 1/FE9200 Note 6 Fuzzy knowledge data creation tool FT9080 Note 1/FT9085 Note 2 Translator FI78K0 Notes 1, 2 Fuzzy inference module FD78K0 Notes 1, 2 Fuzzy inference debugger Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/AT and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 series 300TM (HP-UXTM) based 4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS4800 series (EWS-UX/V) based 5. PC-9800 series (MS-DOS + WindowsTM) based 6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based Remarks 1. For development tools manufactured by a third party, refer to the 78K/0 Series Selection Guide (U11126E). 2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78014. 66 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY APPENDIX B. RELATED DOCUMENTS Device Related Documents Document No. Document Name Japanese English µPD78018F, 78018FY Subseries User's Manual U10659J U10659E 78K/0 Series User's Manual - Instruction U12326J IEU-1372 78K/0 Series Instruction Table U10903J — 78K/0 Series Instruction Set U10904J — µPD78018FY Subseries Special Function Register Table U10287J — 78K/0 Series Application Note Fundamental (I) IEA-715 IEA-1288 Floating-Point Arithmetic Program IEA-718 IEA-1289 Development Tools Documents (User’s Manual) (1/2) Document No. Document Name Japanese English Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 EEU-817 EEU-1402 Operation U11802J U11802E Assembly Language U11801J U11801E Structured Assembly Language U11789J U11789E Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Operation U11517J U11517E Language U11518J U11518E Programming Know-how EEA-618 EEA-1208 CC78K Series Library Source File U12322J — PG-1500 PROM Programmer U11940J EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Based EEU-704 EEU-1291 EEU-5008 U10540E IE-78000-R U11376J U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-78014-R-EM-A EEU-962 U10418E EP-78240 EEU-986 EEU-1513 U10181J U10181E RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package CC78K Series C Compiler CC78K0 C Compiler CC78K/0 C Compiler Application Note PG-1500 Controller IBM PC Series (PC DOS) Based SM78K0 System Simulator Caution Reference The contents of the above related documents are subject to change without notice. The latest documents should be used for desining, etc. 67 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Development Tools Documents (User's Manual) (2/2) Document No. Document Name Japanese English SM78K Series System Simulator External Part User Open Interface Specifications U10092J U10092E ID78K0 Integrated Debugger EWS Based Reference U11151J — ID78K0 Integrated Debugger PC Based Reference U11539J U11539E ID78K0 Integrated Debugger Windows Based Guide U11649J U11649E SD78K/0 Screen Debugger Introduction EEU-852 U10539E PC-9800 Series (MS-DOS) Based Reference U10952J — SD78K/0 Screen Debugger Introduction EEU-5024 EEU-1414 IBM PC/AT (PC DOS) Based Reference U11279J U11279E Embedded Software Documents (User's Manual) Document No. Document Name Japanese English Fundamental U11537J U11537E Installation U11536J U11536E Fundamental U12257J — Fuzzy Knowledge Data Creation Tool EEU-829 EEU-1438 78K/0, 78K/II, 87AD Series EEU-862 EEU-1444 EEU-858 EEU-1441 EEU-921 EEU-1458 78K/0 Series Real-Time OS 78K/0 Series OS MX78K0 Fuzzy Inference Development Support System - Translator 78K/0 Series Fuzzy Inference Development Suport System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger Other Documents Document Name Document No. Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance for Semiconductor Device C11893J MEI-1202 Guide for Products Related to Microcomputer: Other Companies U11416J — Caution The contents of the above related documents are subject to change without notice. The latest documents should be used for desining, etc. 68 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 69 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 70 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. FIP and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 71 µPD78011FY, 78012FY, 78013FY, 78014FY, 78015FY, 78016FY, 78018FY The related documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 72