DATA SHEET MOS INTEGRATED CIRCUIT µPD784044(A), 784046(A) 16-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD784046(A) is a model in the µPD784046 subseries within the 78K/IV series. A stricter quality assurance program applies µPD784046(A) compared to the µPD784046 (standard model). (In terms of NEC’s quality grading, this is a ”special” grade product.) The µPD784046(A) is provided with many peripheral hardware functions such as ROM, RAM, I/O port, 10-bit resolution A/D converter, timer, serial interface, and interrupt functions, in addition to a high-speed, high-performance CPU. The µPD784046(A) is under development. Moreover, a flash memory model, µPD78F4046Note, that can operate on the same supply voltage as the mask ROM model, and many development tools are under development. Note Use for functional evaluation only. The functions are described in detail in the following User’s Manuals. Be sure to read these manuals when designing your system. µPD784046 Subseries User’s Manual - Hardware : U11515E 78K/IV Series User’s Manual - Instruction : U10905E FEATURES • Higher reliability compared to the µPD784044 and 784046 • Minimum instruction execution time : 160 ns (with 12.5-MHz internal clock) ··· µPD784044(A), 784046(A) 200 ns (with 10-MHz internal clock) ··· µPD784044(A1), (A2), 784046(A1), (A2) • I/O port : 65 lines • Timer : 16-bit timer/counter × 2 units 16-bit timer × 3 units • A/D converter : 10-bit resolution × 16 channels • Serial interface UART/IOE (3-wire serial I/O) : 2 channels • Watchdog timer : 1 channel • Standby function HALT/STOP/IDLE mode • Supply voltage : VDD = 4.5 to 5.5 V APPLICATION FIELDS Automotive appliances, etc. In this document, in addition to the µPD784044(A) and µPD784046(A), the µPD784044(A1), 784044(A2) 784046(A1), and 784046(A2) are also explained. However, unless otherwise specified, the µPD784046(A) is treated as the representative model throughout this document. The information in this document is subject to change without notice. Document No. U13121EJ1V1DS00 (1st edition) Date Published March 2001 N CP(K) Printed in Japan © 1998 µPD784044(A), 784046(A) ORDERING INFORMATION Part Number Package µ PD784044GC(A)-×××-3B9 80-pin µ PD784044GC(A1)-×××-3B9 80-pin µ PD784044GC(A2)-×××-3B9 80-pin µ PD784046GC(A)-×××-3B9 Note 80-pin µ PD784046GC(A1)-×××-3B9 Note 80-pin µ PD784046GC(A2)-×××-3B9 Note 80-pin plastic plastic plastic plastic plastic plastic QFP QFP QFP QFP QFP QFP (14 (14 (14 (14 (14 (14 Internal ROM (bytes) Internal RAM (bytes) × × × × × × 14 14 14 14 14 14 mm) mm) mm) mm) mm) mm) 32 32 32 64 64 64 K K K K K K 1024 1024 1024 2048 2048 2048 Note Under development Remark ××× indicates ROM code suffix. QUALITY GRADE Special Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Differences between µPD784046 and µPD784046(A) Part Number Item µ PD784044, 784046, 78F4046 µ PD784044(A), 784046(A) Quality grade Standard Special Operating ambient temperature (TA ) –10 to +70 ˚C –40 to +85 ˚C Operating frequency 8 to 32 MHz 8 to 25 MHz Minimum instruction execution time 125 ns (with 16-MHz internal clock) 160 ns (with 12.5-MHz internal clock) DC characteristics V DD supply current differs. AC characteristics Bus timing and serial operation differ. A/D converter characteristics Conversion time and sampling time differ. Differences between µPD784046(A), 784046(A1) and 784046(A2) Part Number Item µ PD784046(A) µ PD784046(A1) µ PD784046(A2) Operating ambient temperature (T A ) –40 to +85 ˚C –40 to +110 ˚C Operating frequency 8 to 25 MHz 8 to 20 MHz –40 to +125 ˚C Minimum instruction execution time 160 ns (with 12.5-MHz internal clock) 200 ns (with 10-MHz internal clock) DC characteristics Analog pin input leakage current, V DD supply current and data retention current differ. AC characteristics Bus timing and serial operation differ. A/D converter characteristics AV REF current and A/D converter data retention current differ. Remark The differences between µ PD784044(A), 784044(A1) and 784044(A2) is the same as above table. 2 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) Product Development of 78K/IV Series : Under mass production : Under development Standard models For I2C bus µ PD784038Y µPD784038 µPD784026 A/D, 16-bit timer, improved power management Improved internal memory capacity, pin compatible with µPD784026 For multimaster I2C bus µPD784216Y µPD784216 100 pins, I/O, improved internal memory capacity For multimaster I2C bus µ PD784225Y µPD784225 80 pins, ROM correction added For multimaster I2C bus µPD784218Y µPD784218 Improved internal memory capacity, ROM correction added µPD784054 µPD784046 Internal 10-bit A/D ASSP models µPD784955 For DC converter control µPD784908 Internal IEBusTM controller For multimaster I2C bus µPD78F4943 For CD-ROM Flash memory: 56 KB µPD784928Y µPD784928 Improved functions of µPD784915 µPD784915 Software servo control, internal analog circuit for VCR, improved timer Data Sheet U13121EJ1V1DS 3 µPD784044(A), 784046(A) FUNCTION LIST µ PD784044(A) Product Item µ PD784046(A) Number of basic instructions (mnemonics) 113 General-purpose register 8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping) Minimum instruction execution time • 160 ns (with internal 12.5-MHz clock): µ PD784044(A), 784046(A) • 200 ns (with internal 10-MHz clock) : µ PD784044(A1), (A2), 784046(A1), (A2) Internal ROM 32K bytes 64 K bytes memory RAM 1024 bytes 2048 bytes Memory space I/O port 1M bytes with program/data combined Total 65 pins Input 17 pins I/O 48 pins Pins with Pins with 29 pins ancillary pull-up functions Note resistors Real-time output port 4 bits × 1 Timer/counter Timer 0 (16 bits) : Timer register × 1, capture/compare register × 4 Pulse output possible • Toggle output • Set/reset output Timer 1 (16 bits) : Timer register × 1, compare register × 2 Pulse output possible • Toggle output • Set/reset output Timer/counter 2 (16 bits) : Timer register × 1, compare register × 2 Pulse output possible • Toggle output • PWM/PPG output Timer/counter 3 (16 bits) : Timer register × 1, compare register × 2 Pulse output possible • Toggle output • PWM/PPG output Timer 4 (16 bits) : Timer register × 1, compare register × 2 Pulse output possible • Read-time output (4 bits × 1) A/D converter 10-bit resolution × 16 channels Serial interface UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator) Watchdog timer 1 channel Interrupt Hardware source 27 (internal: 23, external: 8 (internal/external: 4)) Software source BRK instruction, BRKCS instruction, operand error Non-maskable Internal: 1, external: 1 Maskable Internal: 22, external: 7 (internal/external: 4) • 4 levels of programmable priorities • 3 processing formats: vectored interrupt/macro service/context switching Bus sizing 8-bit/16-bit external data bus width selectable Standby HALT/STOP/IDLE mode Supply voltage V DD = 4.5 to 5.5 V Package 80-pin plastic QFP (14 × 14 mm) Note 4 The pins with ancillary functions are included in the I/O pins. Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) CONTENTS 1. DIFFERENCES BETWEEN µPD784044(A) AND 784046(A) ............................................................ 7 2. PIN CONFIGURATION (Top View) ..................................................................................................... 8 3. SYSTEM CONFIGURATION EXAMPLE ...........................................................................................10 4. BLOCK DIAGRAM ............................................................................................................................. 11 5. PIN FUNCTIONS ................................................................................................................................12 5.1 Port Pins .................................................................................................................................................... 12 5.2 Pins Other Than Port Pins ...................................................................................................................... 14 5.3 I/O Circuits of Pins and Processing of Unused Pins .......................................................................... 16 6. CPU ARCHITECTURE .......................................................................................................................18 6.1 6.2 Memory Space .......................................................................................................................................... 18 CPU Registers ........................................................................................................................................... 21 6.2.1 General-purpose registers ............................................................................................................. 21 6.2.2 Control registers ............................................................................................................................. 22 6.2.3 Special function registers (SFRs) .................................................................................................. 23 7. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................29 7.1 Ports ........................................................................................................................................................... 29 7.2 Clock Generation Circuit ......................................................................................................................... 30 7.3 Real-Time Output Port ............................................................................................................................. 32 7.4 Timer/Counter ........................................................................................................................................... 32 7.5 A/D Converter ........................................................................................................................................... 35 7.6 Serial Interface .......................................................................................................................................... 36 7.6.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................................... 37 7.7 Edge Detection Circuit ............................................................................................................................ 39 7.8 Watchdog Timer ........................................................................................................................................ 39 8. INTERRUPT FUNCTION....................................................................................................................40 8.1 Interrupt Source ....................................................................................................................................... 40 8.2 Vectored Interrupt .................................................................................................................................... 42 8.3 Context Switching .................................................................................................................................... 43 8.4 Macro Service ........................................................................................................................................... 44 9. LOCAL BUS INTERFACE .................................................................................................................47 9.1 Memory Expansion .................................................................................................................................. 48 9.2 Memory Space .......................................................................................................................................... 49 9.3 Programmable Wait .................................................................................................................................. 49 9.4 Bus Sizing Function ................................................................................................................................. 49 Data Sheet U13121EJ1V1DS 5 µPD784044(A), 784046(A) 10. STANDBY FUNCTION .......................................................................................................................50 11. RESET FUNCTION ............................................................................................................................51 12. INSTRUCTION SET ...........................................................................................................................52 13. ELECTRICAL SPECIFICATIONS ......................................................................................................57 14. PACKAGE DRAWING .......................................................................................................................80 15. RECOMMENDED SOLDERING CONDITIONS ................................................................................81 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................82 APPENDIX B. RELATED DOCUMENTS ...............................................................................................85 6 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 1. DIFFERENCES BETWEEN µPD784044(A) AND 784046(A) The only difference between the µ PD784044(A) and µ PD784046(A) is the internal memory capacity. The differences are shown in Table 1-1. Table 1-1. Differences between µPD784044(A) and 784046(A) Part Number Item µ PD784044(A) µ PD784046(A) Internal ROM 32K bytes (mask ROM) 64K bytes (mask ROM) Internal RAM 1024 bytes 2048 bytes Data Sheet U13121EJ1V1DS 7 µPD784044(A), 784046(A) 2. PIN CONFIGURATION (Top View) • 80-pin plastic QFP (14 × 14 mm) µPD784044GC(A)-×××-3B9, 784044GC(A1)-×××-3B9, 784044GC(A2)-×××-3B9 µPD784046GC(A)-×××-3B9Note, 784046GC(A1)-×××-3B9Note, 784046GC(A2)-×××-3B9Note P23/INTP2/TO02 RESET P24/INTP3/TO03 P25/INTP4 P26/INTP5/TI2 P27/INTP6/TI3 CLKOUT VSS X1 X2 VDD AVSS P80/ANI8 P81/ANI9 P82/ANI10 P83/ANI11 P84/ANI12 P85/ANI13 P86/ANI14 P87/ANI15 Note Under development 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P70/ANI0 1 60 P22/INTP1/TO01 P71/ANI1 2 59 BWD P72/ANI2 3 58 P21/INTP0/TO00 P73/ANI3 4 57 MODE P74/ANI4 5 56 P20/NMI P75/ANI5 6 55 VSS P76/ANI6 7 54 VDD P77/ANI7 8 53 P13/TO31 AVREF 9 52 P12/TO30 AVDD 10 51 P11/TO21 VSS 11 50 P10/TO20 VDD 12 49 P03/RTP3 P47/AD7 13 48 P02/RTP2 P46/AD6 14 47 P01/RTP1 P45/AD5 15 46 P00/RTP0 P44/AD4 16 45 P37/ASCK2/SCK2 P43/AD3 17 44 P36/TxD2/SO2 P42/AD2 18 43 P35/RxD2/SI2 P41/AD1 19 42 P34/ASCK/SCK1 P40/AD0 20 41 P33/TxD/SO1 Caution 8 P32/RxD/SI1 P31/TO11 P30/TO10 P94/WAIT P93/ASTB P91/LWR P92/HWR P90/RD P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Directly connect the MODE pin to VSS. Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) A16-A19 : Address Bus P50-P57 : Port5 AD0-AD15 : Address/Data Bus P60-P63 : Port6 ANI0-ANI15 : Analog Input P70-P77 : Port7 ASCK, ASCK2 : Asynchronous Serial Clock P80-P87 : Port8 ASTB : Address Strobe P90-P94 : Port9 AV DD : Analog Power Supply RD : Read Strobe AV REF : Analog Reference Voltage RESET : Reset AV SS : Analog Ground RTP0-RTP3 : Real-Time Port BWD : Bus Width Definition RxD, RxD2 : Receive Data CLKOUT : Clock Out SCK1,SCK2 : Serial Clock HWR : High Address Write Strobe SI1, SI2 : Serial Input INTP0-INTP6 : Interrupt from Peripherals SO1, SO2 : Serial Output LWR : Low Address Write Strobe TI2, TI3 : Timer Input MODE : Mode TO00-TO03, TO10, TO11, NMI : Non-maskable Interrupt TO20,TO21,TO30,TO31 P00-P03 : Port0 TxD, TxD2 : Transmit Data P10-P13 : Port1 V DD : Power Supply P20-P27 : Port2 V SS : Ground P30-P37 : Port3 WAIT : Wait P40-P47 : Port4 X1, X2 : Crystal Data Sheet U13121EJ1V1DS : Timer Output 9 µPD784044(A), 784046(A) 3. SYSTEM CONFIGURATION EXAMPLE (AC SERVO MOTOR CONTROL) Display lamp ABS control unit Output interface µ PD784046(A) Pulse • Right front wheel speed • Left front wheel speed • Right rear wheel speed • Left rear wheel speed Digital quantity • Brake sw • Parking sw • Neutral sw • TCS cut sw, etc. CPU Input interface Generalpurpose I/O • Timer unit • Interrupt controller Serial I/O Generalpurpose I/O ROM: 64 KB RAM : 2 KB Input interface UART External I/O interface 10 Power unit Data Sheet U13121EJ1V1DS Solenoid • Right front wheel • Left front wheel • Right rear wheel • Left rear wheel Monitor circuit 10-bit A/D converter Microcomputer for monitor Battery voltage (12 V) Solenoid drive circuit Subthrottle control Analog quantity • G sensor (front, rear) • G sensor (left, right) • Throttle divergence • Rupture detection, etc. External tester display system µPD784044(A), 784046(A) 4. BLOCK DIAGRAM NMI INTP0-INTP6 INTP0-INTP3 TO00-TO03 Programmable interrupt controller UART/IOE1 Baud-rate generator Timer 0 (16 bits) UART/IOE2 Baud-rate generator TO10, TO11 Timer 1 (16 bits) BUS I/F INTP5/TI2 TO20, TO21 INTP6/TI3 TO30, TO31 Timer/counter2 (16 BITS) 78K/IV CPU core ROM Timer/counter3 (16 BITS) Timer 4 (16 bits) RxD/SI1 TxD/SO1 ASCK/SCK1 RxD2/SI2 TxD2/SO2 ASCK2/SCK2 BWD AD0-AD15 A16-A19 RD LWR, HWR ASTB WAIT Port 0 P00-P03 Port 1 P10-P12 Port 2 P20 P21-P27 Port 3 P30-P37 Port 4 P40-P47 Port 5 P50-P57 Port 6 P60-P63 Port 7 P70-P77 Port 8 P80-P87 Port 9 P90-P94 RAM RTP0-RTP3 Real-time output port ANI0-ANI15 AVDD AVSS A/D converter AVREF INTP4 System control Watchdog timer CLKOUT RESET MODE X1 X2 VDD VSS Remark The internal ROM and RAM capacity differs depending on the products. Data Sheet U13121EJ1V1DS 11 µPD784044(A), 784046(A) 5. PIN FUNCTIONS 5.1 Port Pins (1/2) Pin Name I/O Shared by: Function P00-P03 I/O RTP0-RTP3 Port 0 (P0): • 4-bit I/O port • Can be set in input/output mode bit-wise. • Pins in input mode can all be connected to pull-up resistors at once via software. P10 I/O TO20 Port 1 (P1): P11 TO21 • 4-bit I/O port P12 TO30 • Can be set in input/output mode bit-wise. P13 TO31 P20 Input P21 I/O NMI Port 2 (P2): Input only INTP0/TO00 • 8-bit I/O port Can be set in input/output mode P22 INTP1/TO01 P23 INTP2/TO02 P24 INTP3/TO03 P25 INTP4 P26 INTP5/TI2 P27 INTP6/TI3 P30 I/O bit-wise. TO10 Port 3 (P3): TO11 • 8-bit I/O port P32 RxD/SI1 • Can be set in input/output mode bit-wise. P33 TxD/SO1 P34 ASCK/SCK1 P35 RxD2/SI2 P31 P36 TxD2/SO2 P37 ASCK2/SCK2 P40-P47 I/O AD0-AD7 Port 4 (P4): • 8-bit I/O port • Can be set in input/output mode bit-wise. • Pins in input mode can all be connected to pull-up resistors at once via software. P50-P57 I/O AD8-AD15 Port 5 (P5): • 8-bit I/O port • Can be set in input/output mode bit-wise. • Pins in input mode can all be connected to pull-up resistors at once via software. P60-P63 I/O A16-A19 Port 6 (P6): • 4-bit I/O port • Can be set in input/output mode bit-wise. • Pins in input mode can all be connected to pull-up resistors at once via software. 12 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 5.1 Port Pins (2/2) Pin Name I/O Shared by: Function P70-P77 Input ANI0-ANI7 Port 7 (P7): • 8-bit input port P80-P87 Input ANI8-ANI15 Port 8 (P8): • 8-bit input port RD Port 9 (P9): P91 LWR • 5-bit I/O port P92 HWR • Can be set in input/output mode bit-wise. P93 ASTB • Pins in input mode can all be connected to pull-up resistors at once P94 WAIT P90 I/O via software. Data Sheet U13121EJ1V1DS 13 µPD784044(A), 784046(A) 5.2 Pins Other Than Port Pins (1/2) Pin Name RTP0-RTP3 I/O Function P00-P03 Real-time output P20 Non-maskable interrupt request input INTP0 P21/TO00 External interrupt INTP1 P22/TO01 request input INTP2 P23/TO02 Capture trigger signal of CC02 INTP3 P24/TO03 Capture trigger signal of CC03 INTP4 P25 Conversion start trigger input of A/D converter INTP5 P26/TI2 NMI Output Shared by: Input INTP6 TO00 P21/INTP0 TO01 P22/INTP1 TO02 P23/INTP2 TO03 P24/INTP3 TO10 P30 TO11 P31 TO20 P10 TO21 P11 TO30 P12 TO31 P13 Timer output from timer/counter P26/INTP5 External count clock input to timer/counter 2 P27/INTP6 External count clock input to timer/counter 3 Input P32/SI1 Serial data input (UART0) P35/SI2 Serial data input (UART2) P33/SO1 Serial data output (UART0) RxD2 TxD – Input TI3 RxD Capture trigger signal of CC01 P27/TI3 Output TI2 Capture trigger signal of CC00 Output TxD2 P36/SO2 Serial data output (UART2) P34/SCK1 Baud rate clock input (UART0) P37/SCK2 Baud rate clock input (UART2) Input P32/RxD Serial data input (3-wire serial I/O1) P35/RxD2 Serial data input (3-wire serial I/O2) Output P33/TxD Serial data output (3-wire serial I/O1) P36/TxD2 Serial data output (3-wire serial I/O2) I/O P34/ASCK Serial clock input/output (3-wire serial I/O1) P37/ASCK2 Serial clock input/output (3-wire serial I/O2) AD0-AD7 I/O P40-P47 Lower multiplexed address/data bus when external memory is connected AD8-AD15 Note I/O P50-P57 • When 8-bit bus is specified Higher address bus when external memory is connected • When external 16-bit bus is specified Higher multiplexed address/data bus when external memory is connected A16-A19 Note Output P60-P63 Higher address bus when external memory is connected RD Output P90 Read strobe to external memory ASCK Input ASCK2 SI1 SI2 SO1 SO2 SCK1 SCK2 Note The number of pins used as address bus pins differs depending on the external address space (refer to 9. LOCAL BUS INTERFACE). 14 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 5.2 Pins Other Than Port Pins (2/2) Pin Name LWR I/O Output HWR ASTB Output Shared by: Function P91 • When external 8-bit bus is specified Write strobe to external memory • When external 16-bit bus is specified Write strobe to external memory located at lower position P92 Write strobe to external memory located at higher position when external 16-bit bus is specified P93 Timing signal output to externally latch address information output from AD0 through AD15 pins to access external memory WAIT Input P94 Inserts wait. BWD Input – Sets bus width. MODE Input – Directly connect this pin to VSS (this pin specifies test mode of IC). Output – Clock output. Outputs low level during IDLE mode and STOP mode. Otherwise, always outputs f XX (oscillation frequency). Input – Connect crystal for system clock oscillation (clock can be also input to X1). CLKOUT X1 X2 – – RESET Input – ANI0-ANI7 Input P70-P77 ANI8-ANI15 AV REF Chip reset Analog voltage input for A/D converter P80-P87 – Reference voltage for A/D converter AV DD – – Positive power supply for A/D converter AV SS – GND for A/D converter V DD – Positive power supply V SS – GND Data Sheet U13121EJ1V1DS 15 µPD784044(A), 784046(A) 5.3 I/O Circuits of Pins and Processing of Unused Pins Table 5-1 shows the I/O circuit type of each pin and recommended processing of the unused pins. For the I/O circuit type, refer to Figure 5-1. Table 5-1. I/O Circuit Type of Each Pin and Recommended Processing of Unused Pins Pin Name I/O Circuit Type I/O P00/RTP0-P03/RTP3 5-A I/O P10-P12 5 Recommended Connection of Unused Pins Input: Individually connect to V DD or V SS via resistor. Output: Leave unconnected. P11/TO21 P12/TO30 P13/TO31 P20/NMI 2 Input P21/INTP0/TO00 8 I/O P22/INTP1/TO01 Connect to V SS . Input: Individually connect to V DD or V SS via resistor. Output: Leave unconnected. P23/INTP2/TO02 P24/INTP3/TO03 P25/INTP4 P26/INTP5/TI2 P27/INTP6/TI3 P30/TO10 5 P31/TO11 P32/RxD/SI1 P33/TxD/SO1 P34/ASCK/SCK1 8 P35/RxD2/SI2 5 P36/TxD2/SO2 P37/ASCK2/SCK2 8 P40/AD0-P47/AD7 5-A P50/AD8-P57/AD15 P60/A16-P63/A19 P70/ANI0-P77/ANI7 9 Input Connect to V SS . P80/ANI8-P87/ANI15 P90/RD 5-A I/O P91/LWR Input: Individually connect to V DD or V SS via resistor. Output: Leave unconnected. P92/HWR P93/ASTB P94/WAIT MODE 1 RESET 2 CLKOUT 3 AV REF Input Directly connect to V SS . – Output – – Leave unconnected. Connect to V SS . AV SS AV DD Connect to V DD . Remark The circuit type numbers are serial in the 78K series but are not always so with some models (because some models are not provided with particular circuits). 16 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) Figure 5-1. I/O Circuits of Pins Type 1 Type 5-A VDD Pullup Enable VDD P-ch P-ch VDD Data P-ch IN IN/OUT N-ch Output disable N-ch Input enable Type 2 Type 8 VDD Data P-ch IN/OUT IN Output disable N-ch Schmitt trigger input with hysteresis characteristics Type 9 Type 3 VDD IN P-ch N-ch Comparator + – P-ch VREF (Threshold voltage) OUT N-ch Input enable Type 5 VDD Data P-ch IN/OUT Output disable N-ch Input enable Data Sheet U13121EJ1V1DS 17 µPD784044(A), 784046(A) 6. CPU ARCHITECTURE 6.1 Memory Space A 1M-byte memory space can be accessed. The mapping of the internal data area (special function registers and internal RAM) can be selected by using the LOCATION instruction. The LOCATION instruction must be always executed after the reset signal has been deasserted, and must not be used more than once. (1) When LOCATION 0 instruction is executed • Internal memory The internal data area and internal ROM area are as follows: Product Name Internal Data Area Internal ROM Area µ PD784044(A) 0FB00H-0FFFFH 00000H-07FFFH µ PD784046(A) 0F700H-0FFFFH 00000H-0F5FFH Caution 0F600H to 0FFFFH of the on-chip ROM (00000H to 0FFFFH) of the µPD784046(A) cannot be used as ROM in execution of the LOCATION 0 instruction (refer to Figure 6-2). • External memory The external memory is accessed in the external memory expansion mode. (2) When LOCATION 0FH instruction is executed • Internal memory The internal data area and internal ROM area are as follows: Internal Data Area Internal ROM Area µ PD784044(A) Product Name FFB00H-FFFFFH 00000H-07FFFH µ PD784046(A) FF700H-FFFFFH 00000H-0FFFFH • External memory The external memory is accessed in the external memory expansion mode. 18 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) Figure 6-1. µPD784044(A) Memory Map When LOCATION 0FH instruction is executed When LOCATION 0 instruction is executed F F F F F H Special function registers (SFRS) F F F D F H Note 1 F F FD 0H (256 bytes) FFF 0 0H F F F F FH F F E F FH 0 F E F FH External memory Note 1 (960K bytes) F F E 8 0H F F E 7 FH 0 FE 8 0H 0 F E 7 FH 1 0 0 0 0H 0 F F F F H Special function registers (SFRs) 0 F F D F H Note 1 0 F FD 0 H (256 bytes) 0 F F 0 0H 0 F E F FH Internal memory (1K bytes) 0 FB 0 0H 0 FA F FH Cannot be used (1280 bytes) 0 F 6 0 0H 0 F 5 F FH 0 FE 3 7H 0 FE 0 6H Main RAM Peripheral RAM Macro service control word area (50 bytes) Internal RAM (1K bytes) Cannot be used (1280 bytes) F F 6 0 0H F F 5 F FH F F E 3 7H F F E 0 6H Data area (512 bytes) F FD 0 0 H F F C F FH 0 FD 0 0 H 0 F C F FH Program/data area (512 bytes) External memoryNote 1 (1013248 bytes) F FB 0 0H 0 FB 0 0H 0 7 F F FH Note 2 External memory Note 1 (30208 bytes) Program/data area (32K bytes) 0 1 0 0 0H 0 0 F F FH CALLF entry area (2K bytes) 0 0 8 0 0H 0 0 7 F FH 0 8 0 0 0H 0 7 F F FH Internal ROM (32K bytes) 0 0 0 0 0H F F E F FH F FB 0 0H F FA F FH General-purpose registers (128 bytes) 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 1 0 0 0 0H 0 F F F FH Note 2 0 8 0 0 0H 0 7 F F FH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (32K bytes) 0 0 0 0 0H Notes 1. Accessed in the external memory expansion mode. 2. Base area or entry area by reset or interrupt. The internal RAM is not reset. Data Sheet U13121EJ1V1DS 19 µPD784044(A), 784046(A) Figure 6-2. µPD784046(A) Memory Map When LOCATION 0 instruction is executed F F F F FH F F E F FH 0 F E F FH General-purpose registers (128 bytes) External memoryNote 1 (960K bytes) 0 FE8 0H 0 F E 7 FH 1 0 0 0 0H 0 F F F F H Special function registers (SFRs) 0 F F D F H Note 1 0 F FD 0 H (256 bytes) 0 FF 0 0H 0 F E F FH Internal RAM (2K bytes) 0 F 7 0 0H 0 F 6 F FH 0 F 6 0 0H 0 F 5 F FH F F F F FH F F FDFH F F FD 0 H FFF 0 0H F F E F FH 0 F E 3 7 H Macro service control word area (50 bytes) 0 FE0 6H Main RAM Peripheral RAM 0 FD 0 0 H 0 FCF FH When LOCATION 0FH instruction is executed Special function registers (SFRs) Note 1 (256 bytes) Internal RAM (2K bytes) FFE8 0H F F E 7 FH FF 7 0 0H F F 6 F FH FFE3 7H FF 6 0 0H F F 5 F FH Cannot be used (256 bytes) FFE0 6H Data area (512 bytes) F FD 0 0 H F FCF FH Program/data area (1536 bytes) FF 7 0 0H 0 F 7 0 0H Cannot be used (256 bytes) Note 2 External memoryNote 1 (980480 bytes) 0 F F F FH 0 F 5 0 0H Program/data areaNote 3 Note 4 0 1 0 0 0H 0 0 F F FH CALLF entry area (2K bytes) Internal ROM (62976 bytes) 0 1 0 0 0H 0 0 7 F FH 0 0 0 8 0H 0 0 0 7 FH 0 0 0 4 0H 0 0 0 3 FH 0 0 0 0 0H 0 0 0 0 0H 1 0 0 0 0H 0 F F F FH CALLT table area (64 bytes) Vector table area (64 bytes) Internal ROM (64K bytes) Note 4 0 0 0 0 0H Notes 1. Accessed in the external memory expansion mode. 2. 2560 bytes in this area can be used as inernal ROM only when the LOCATION 0FH instruction is executed. 3. When the LOCATION 0 instruction is executed: 62976 bytes When the LOCATION 0FH instruction is executed: 65536 bytes 4. Base area or entry area by reset or interrupt. The internal RAM is not reset. 20 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 6.2 CPU Registers 6.2.1 General-purpose registers Sixteen 8-bit general-purpose registers are provided. Two 8-bit general-purpose registers can be used in pairs as a 16-bit general-purpose register. Of the 16-bit registers, four can be used with an 8-bit register for address expansion as 24-bit address specification registers. Eight banks of register sets are available which can be selected by software or context switching function. The general-purpose registers except the V, U, T, and W registers for address expansion are mapped to the internal RAM. Figure 6-3. General-Purpose Register Format A(R1) X(R0) AX(RP0) B(R3) C(R2) BC(RP1) R5 R4 RP2 R7 R6 RP3 R8 R9 V VP(RP4) VVP(RG4) UP(RP5) UUP(RG5) T E(R12) D(R13) DE(RP6) TDE(RG6) W R10 R11 U L(R14) H(R15) WHL(RG7) HL(RP7) 8 banks ( ): absolute name Caution R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of the PSW to 1. However, use this function only when using a 78K/III series program. Data Sheet U13121EJ1V1DS 21 µPD784044(A), 784046(A) 6.2.2 Control registers (1) Program counter (PC) This is a 20-bit program counter. Its contents are automatically updated as the program is executed. Figure 6-4. Program Counter (PC) Format 19 0 PC (2) Program status word (PSW) This register retains the status of the CPU and its contents are automatically updated as the program is executed. Figure 6-5. Program Status Word (PSW) Format PSWH 15 14 13 12 11 10 9 8 UF RBS2 RBS1 RBS0 — — — — 7 6 5 4 3 2 1 0 AC IE P/V 0 CY PSW PSWL Note S Z Note RSS This flag is provided so that the µPD784046(A) maintains compatibility with the 78K/III series. Be sure to clear this flag to 0 when using 78K/III series software. (3) Stack pointer (SP) This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the high-order 4 bits of this pointer. Figure 6-6. Stack Pointer (SP) Format 23 SP 22 0 20 0 0 0 0 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 6.2.3 Special function registers (SFRs) The special function registers are registers to which special functions are assigned, and include the mode registers and control registers of the internal peripheral hardware. These registers are mapped to a 256-byte space of addresses 0FF00H through 0FFFFH Note. Note When the LOCATION 0 instruction is executed. FFF00H through FFFFFH when the LOCATION 0FH instruction is executed. Caution Do not access an address in this area to which no SFR is allocated. If an address to which no SFR is allocated is accessed by mistake, the µPD784046(A) may be deadlocked. The deadlock status can be cleared only by inputting the reset signal. Table 6-1 lists the special function registers. The meanings of the symbols in this table are as follows: • Symbol ................................. Symbol indicating an SFR. These symbols are reserved for an NEC’s assembler (RA78K4). With a C compiler (CC78K4), they can be used as sfr variables by using the #pragma sfr directive. • R/W ...................................... Indicates whether the corresponding SFR can be read/written. R/W : Read/write R : Read only W : Write only • Bit units for manipulation .... Indicates bit units in which the corresponding SFR can be manipulated. SFRs that can be manipulated in 16-bit units can be written as operand sfrp. Specify the even addresses of these SFRs when specifying an address. SFRs that can be manipulated bit-wise can be written in bit manipulation instructions. • On reset ............................... Indicates the status of each register when the RESET signal is input. Data Sheet U13121EJ1V1DS 23 µPD784044(A), 784046(A) Table 6-1. Special Function Register List (1/5) Address Note 1 Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 0FF00H Port 0 P0 0FF01H Port 1 P1 8 bits R/W On reset 16 bits – Undefined – 0FF02H Port 2 P2 Note 2 0FF03H Port 3 P3 R/W 0FF04H Port 4 P4 – 0FF05H Port 5 P5 – 0FF06H Port 6 P6 – 0FF07H Port 7 P7 0FF08H Port 8 P8 0FF09H Port 9 P9 0FF0EH Port 0 buffer register P0L 0FF10H Timer register 0 TM0 Capture/compare register 00 CC00 Capture/compare register 01 R – – – – R/W – – R – – 0000H R/W – – Undefined CC01 – – Capture/compare register 02 CC02 – – Capture/compare register 03 CC03 – – Timer register 1 TM1 R – – 0000H Compare register 10 CM10 R/W – – Undefined Compare register 11 CM11 – – 0FF20H Port 0 mode register PM0 – 0FF21H Port 1 mode register PM1 – 0FF22H Port 2 mode register PM2 Note 3 – 0FF23H Port 3 mode register PM3 – 0FF24H Port 4 mode register PM4 – 0FF25H Port 5 mode register PM5 – 0FF26H Port 6 mode register PM6 – 0FF29H Port 9 mode register PM9 – 0FF2EH Real-time output port control register RTPC – 0FF2FH Port read control register PRDC – 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1BH 0FF1CH 0FF1DH 0FF1EH 0FF1FH FFH 00H Notes 1. When the LOCATION 0 instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. 2. Bit 0 of P2 can only be read. Bit 1 can be read/written. 3. Bit 0 of PM2 is fixed to “1” by hardware. 24 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) Table 6-1. Special Function Register List (2/5) Address Note 1 Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 8 bits R/W On reset 16 bits 0FF30H Timer unit mode register 0 TUM0 – 0FF31H Timer mode control register TMC – 0FF32H Timer output control register 0 TOC0 – 0FF33H Timer output control register 1 TOC1 – 0FF34H Timer unit mode register 2 TUM2 – 0FF35H Timer mode control register 2 TMC2 – 0FF36H Timer output control register 2 TOC2 – 0FF37H Timer mode control register 4 TMC4 0FF38H Prescaler mode register PRM – – 0FF39H Prescaler mode register 2 PRM2 – – 0FF3AH Prescaler mode register 4 PRM4 – – 0FF3BH Noise protection control register NPC – 0FF3CH External interrupt mode register 0 INTM0 – 0FF3DH External interrupt mode register 1 INTM1 – 0FF3EH Interrupt valid edge flag register 1 IEF1 – 0FF3FH Interrupt valid edge flag register 2 IEF2 – 0FF41H Port 1 mode control register PMC1 – 0FF42H Port 2 mode control register PMC2 Note 2 – 0FF43H Port 3 mode control register PMC3 – 0FF49H Port 9 mode control register PMC9 – 0FF4EH Pull-up resistor option register L PUOL – 0FF4FH Pull-up resistor option register H PUOH – 0FF50H Timer register 2 TM2 Compare register 20 CM20 Compare register 21 CM21 Timer register 3 TM3 Compare register 30 CM30 Compare register 31 CM31 Timer register 4 TM4 00H – Undefined 00H R – – 0000H R/W – – Undefined – – R – – 0000H R/W – – Undefined – – – – 0FF51H 0FF52H 0FF53H 0FF54H 0FF55H 0FF56H 0FF57H 0FF58H 0FF59H 0FF5AH 0FF5BH 0FF60H R 0000H 0FF61H Notes 1. When the LOCATION 0 instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. 2. Bits 0, and 5 through 7 of PMC2 are fixed to “0” by hardware. Data Sheet U13121EJ1V1DS 25 µPD784044(A), 784046(A) Table 6-1. Special Function Register List (3/5) Address Note 0FF62H Special Function Register (SFR) Name Symbol Compare register 40 CM40 Compare register 41 CM41 0FF6EH A/D converter mode register ADM 0FF70H A/D conversion result register 0 ADCR0 R/W R/W Bit units for manipulation 1 bit 8 bits – – – – On reset 16 bits Undefined 0FF63H 0FF64H 0FF65H – R – – 00H Undefined 0FF71H 0FF71H A/D conversion result register 0H ADCR0H – 0FF72H A/D conversion result register 1 ADCR1 – 0FF73H A/D conversion result register 1H ADCR1H – 0FF74H A/D conversion result register 2 ADCR2 – 0FF75H A/D conversion result register 2H ADCR2H – 0FF76H A/D conversion result register 3 ADCR3 – 0FF77H A/D conversion result register 3H ADCR3H – 0FF78H A/D conversion result register 4 ADCR4 – – – 0FF73H – – 0FF75H – – 0FF77H – – 0FF79H 0FF79H A/D conversion result register 4H ADCR4H – 0FF7AH A/D conversion result register 5 ADCR5 – – 0FF7BH A/D conversion result register 5H ADCR5H – 0FF7CH A/D conversion result register 6 ADCR6 – 0FF7DH A/D conversion result register 6H ADCR6H – 0FF7EH A/D conversion result register 7 ADCR7 – 0FF7FH A/D conversion result register 7H ADCR7H – 0FF84H Clocked serial interface mode register 1 CSIM1 0FF85H Clocked serial interface mode register 2 CSIM2 – 0FF88H Asynchronous serial interface mode register ASIM – 0FF89H Asynchronous serial interface mode register 2 ASIM2 – 0FF8AH Asynchronous serial interface status register ASIS 0FF8BH Asynchronous serial interface status register 2 ASIS2 – Undefined 0FF7BH – – 0FF7DH – – 0FF7FH Note R – 00H – – When the LOCATION 0 instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. 26 R/W – Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) Table 6-1. Special Function Register List (4/5) Address Note 1 Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit 0FF8CH 0FF8DH 0FF90H 8 bits On reset 16 bits Serial receive buffer: UART0 RXB R – – Serial transmit shift register: UART0 TXS W – – Serial shift register: IOE1 SIO1 R/W – – Serial receive buffer: UART2 RXB2 R – – Serial transmit shift register: UART2 TXS2 W – – Serial shift register: IOE2 SIO2 R/W – – Baud rate generator control register BRGC – – – – Undefined 00H 0FF91H Baud rate generator control register 2 BRGC2 0FFA8H In-service priority register ISPR R – 0FFAAH Interrupt mode control register IMC R/W – 80H 0FFACH Interrupt mask register 0L MK0L – FFH 0FFACH Interrupt mask register 0 MK0 0FFADH Interrupt mask register 0H MK0H – 0FFAEH Interrupt mask register 1L MK1L – 0FFAEH Interrupt mask register 1 MK1 Interrupt mask register 1H MK1H – – FFFFH 0FFADH – – FFH FFFFH 0FFAFH 0FFAFH 0FFC0H Standby control register Note 2 register Note 2 – FFH STBC – – 30H WDM – – 00H – 20H – AAH 0FFC2H Watchdog timer mode 0FFC4H Memory expansion mode register MM 0FFC7H Programmable wait control register 1 PWC1 – 0FFC8H Programmable wait control register 2 PWC2 – – AAAAH Bus width specification register BW – – Note 3 0FFC9H 0FFCAH 0FFCBH 0FFCFH Oscillation stabilization time specification register OSTS 0FFD0H0FFDFH External SFR area 0FFE0H – – 00H – – Undefined Interrupt control register (INTOV0) OVIC0 – 43H 0FFE1H Interrupt control register (INTOV1) OVIC1 – 0FFE2H Interrupt control register (INTOV4) OVIC4 – 0FFE3H Interrupt control register (INTP0) PIC0 – 0FFE4H Interrupt control register (INTP1) PIC1 – 0FFE5H Interrupt control register (INTP2) PIC2 – Notes 1. When the LOCATION 0 instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. 2. These registers can be written only by using dedicated instructions MOV STBC, #byte and MOV WDM, #byte, and cannot be written by any other instructions. 3. The value of this register on reset differs depending on the setting of the BWD pin. BWD = 0: 0000H BWD = 1: 00FFH Data Sheet U13121EJ1V1DS 27 µPD784044(A), 784046(A) Table 6-1. Special Function Register List (5/5) Address Note Special Function Register (SFR) Name Symbol R/W Bit units for manipulation 1 bit R/W 8 bits 16 bits 0FFE6H Interrupt control register (INTP3) PIC3 0FFE7H Interrupt control register (INTP4) PIC4 – 0FFE8H Interrupt control register (INTP5) PIC5 – 0FFE9H Interrupt control register (INTP6) PIC6 – 0FFEAH Interrupt control register (INTCM10) CMIC10 – 0FFEBH Interrupt control register (INTCM11) CMIC11 – 0FFECH Interrupt control register (INTCM20) CMIC20 – 0FFEDH Interrupt control register (INTCM21) CMIC21 – 0FFEEH Interrupt control register (INTCM30) CMIC30 – 0FFEFH Interrupt control register (INTCM31) CMIC31 – 0FFF0H Interrupt control register (INTCM40) CMIC40 – – 0FFF1H Interrupt control register (INTCM41) CMIC41 – 0FFF2H Interrupt control register (INTSER) SERIC – 0FFF3H Interrupt control register (INTSR) SRIC – Interrupt control register (INTCSI1) CSIIC1 – 0FFF4H Interrupt control register (INTST) STIC – 0FFF5H Interrupt control register (INTSER2) SERIC2 – 0FFF6H Interrupt control register (INTSR2) SRIC2 – Interrupt control register (INTCSI2) CSIIC2 – 0FFF7H Interrupt control register (INTST2) STIC2 – 0FFF8H Interrupt control register (INTAD) ADIC – Note 43H When the LOCATION 0 instruction is executed. Add “F0000H” to this value when the LOCATION 0FH instruction is executed. 28 On reset Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 7. PERIPHERAL HARDWARE FUNCTIONS 7.1 Ports The µ PD784046(A) has the ports shown in Figure 7-1. These ports can be used for various control operations. The function of each port is shown in Table 7-1. Ports 0, 4 through 6, and 9 can be connected to an internal pull-up resistor via software when they are set in the input mode. Figure 7-1. Port Configuration P00 P50 Port 0 P03 Port 5 P10 Port 1 P57 P13 P60 P20 Port 6 P63 Port 2 P27 P70-P77 8 Port 7 P80-P87 8 Port 8 P30 Port 3 P37 P40 Port 4 P90 Port 9 P47 P94 Data Sheet U13121EJ1V1DS 29 µPD784044(A), 784046(A) Table 7-1. Port Function Port Name Pin Name Port 0 P00-P03 Port 1 P10-P13 Port 2 P20-P27 Port 3 P30-P37 Port 4 P40-P47 Port 5 P50-P57 Port 6 P60-P63 Function Specification of Pull-Up Resistor by Software Can be set in input or output mode bit-wise. All pins in input mode – Can be set in input or output mode bit-wise (however, P20 is input-only). Port 7 P70-P77 Port 8 P80-P87 Port 9 P90-P94 Can be set in input or output mode bit-wise. All pins in input mode Input port – Can be set in input or output mode bit-wise. All pins in input mode 7.2 Clock Generation Circuit The clock generation circuit generates and controls the internal system clock (CLK) to be supplied to the CPU. Figure 7-2 shows the configuration of this circuit. Figure 7-2. Block Diagram of Clock Generation Circuit Divider X1 Clock generation circuit fXX or fX 1/2 fCLK X2 Remark fXX : crystal/ceramic oscillation frequency fX : external clock frequency fCLK : internal system clock frequency 30 Data Sheet U13121EJ1V1DS Internal system clock (CLK) µPD784044(A), 784046(A) Figure 7-3. Example of Using Oscillation Circuit (1) Crystal/ceramic oscillation µ PD784046(A) VSS X1 X2 (2) External clock input (a) EXTC bit of OSTS = 1 (b) EXTC bit of OSTS = 0 µ PD784046(A) µ PD784046(A) X1 X1 µPD74HC04, etc. X2 Caution Leave unconnected X2 When using the clock oscillation circuit, wire the portion enclosed by the dotted line in the above figure as follows to avoid adverse effects of wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with other signal lines. • Do not route the wiring in the vicinity of lines through which a high alternating current flows. • Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract signals from the oscillation circuit. Data Sheet U13121EJ1V1DS 31 µPD784044(A), 784046(A) 7.3 Real-Time Output Port The real-time output port outputs the data stored in the buffer in synchronization with a match interrupt of timer 4. This allows jitter-less pulse output to be obtained. Therefore, it is best suited to applications that output patterns at given intervals (such as stepping motor open loop control,etc.). As shown in Figure 7-4, port 0 and the port 0 buffer register form the core of configuration. Figure 7-4. Block Diagram of Real-Time Output Port Internal Bus 8 4 Real time output port control register (RTPC) Port 0 buffer register (P0L) 4 INTCM40 (from timer 4) Output trigger control circuit 4 Output latch (P0) RTP3 RTP2 RTP1 RTP0 7.4 Timer/Counter The µ PD784046(A) contains two 16-bit timer/counter units and three 16-bit timer units. These units support a total of 15 interrupt requests, which enable them to function as 15-channel timers. Table 7-2. Timer/Counter Function Name Timer 0 Timer 1 4ch 2ch Item Operating mode Interval timer Function Timer output External event counter – – 4ch 2ch Timer/ Timer/ Counter2 Counter 3 2ch 2ch 2ch 2ch 2ch – Toggle output – – Set/reset output PWM/PPG output Real-time output – – – – Overflow interrupt Number of interrupt requests 32 Timer 4 5 Data Sheet U13121EJ1V1DS 3 – – – – – – 2 2 – – 3 µPD784044(A), 784046(A) Figure 7-5. Block Diagram of Timer/Counter (1/2) Timer 0 fCLK Prescaler INTP0 Edge detection INTP1 Edge detection Timer register 0 (TM0) INTP0 Coinci- Capter/compare register 00 dence (CC00) INTP1 Coinci- Capter/compare register 01 dence (CC01) INTP2 INTP2 Edge detection CoinciCapter/compare register 02 dence (CC02) INTP3 INTP3 Edge detection INTOV0 Coinci- Capter/compare register 03 dence (CC03) INTCC00 Pulse INTCC01 output control TO00 TO01 INTCC02 TO02 Pulse INTCC03 output control TO03 Prescaler: f CLK /4, f CLK /8, f CLK/16, f CLK /32, fCLK /64 Timer 1 Clear control fCLK Prescaler Timer register 1 (TM1) INTOV1 Coinci- Compare register 10 dence (CM10) Coinci- Compare register 11 dence (CM11) INTCM10 TO10 Pulse output control TO11 INTCM11 Prescaler: f CLK /8, f CLK /16, fCLK /32, f CLK/64, f CLK /128 Data Sheet U13121EJ1V1DS 33 µPD784044(A), 784046(A) Figure 7-5. Block Diagram of Timer/Counter (2/2) Timer/counter 2 Clear control fCLK Prescaler Timer register 2 (TM2) Selector CoinciCompare register 20 dence (CM20) Coinci- Compare register 21 dence (CM21) TI2/INTP5 Edge detection INTCM20 TO20 Pulse output control TO21 INTCM21 INTP5 Prescaler: f CLK /4, f CLK /8, f CLK/16, f CLK /32, fCLK /64 Timer/counter 3 Clear control fCLK Prescaler Timer register 3 (TM3) Selector CoinciCompare register 30 dence (CM30) Coinci- Compare register 31 dence (CM31) TI3/INTP6 Edge detection INTCM30 TO30 Pulse output control TO31 INTCM31 INTP6 Prescaler: f CLK /4, f CLK /8, f CLK/16, f CLK /32, fCLK /64 Timer 4 Clear control fCLK Prescaler Timer register 4 (TM4) INTOV4 CoinciCompare register 40 dence (CM40) INTCM40 To real-time output port Coinci- Compare register 41 dence (CM41) Prescaler: f CLK /4, f CLK /8, f CLK/16, f CLK /32, fCLK /64 34 Data Sheet U13121EJ1V1DS INTCM41 µPD784044(A), 784046(A) 7.5 A/D Converter The µ PD784046(A) has an analog-to-digital (A/D) converter with 16 multiplexed analog input pins (ANI0 through ANI15). This converter is of successive approximation type. The result of conversion is stored to and retained in 10-bit A/D conversion result registers (ADCR0-ADCR7). Therefore, high-speed, high-accuracy conversion can be performed (conversion time: about 13.5 µ s: f CLK = 12.5 MHz). The A/D conversion operation can be started in the following modes: • Hardware start : Conversion is started by trigger input (INTP4). • Software start : Conversion is started by setting a bit of the A/D converter mode register (ADM). The A/D converter operates in the following modes: • Scan mode : Sequentially selects two or more analog input pins to obtain data to be converted from all • Select mode : Selects only one analog input pin to obtain successive conversion values. the pins. The above modes and stopping the conversion are specified by ADM. When the result of conversion is transferred to ADCRn (n = 0-7), interrupt request INTAD is generated. By using this interrupt request and by using macro service, the converted value can be successively transferred to memory. Figure 7-6. Block Diagram of A/D Converter ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 Input selector Series resistor string Sample & hold circuit AVREF R/2 Input selector INTP4 Edge detection circuit Voltage comparator Successive approximation register (SAR) Conversion trigger INTAD Control circuit R Tap selector ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 R/2 AVSS 10 Trigger enable ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 A/D converter mode register (ADM) 8 A/D conversion result register 10 Internal bus Data Sheet U13121EJ1V1DS 35 µPD784044(A), 784046(A) 7.6 Serial Interface The µ PD784046(A) is provided with two independent serial interface channels. • Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2 By using these serial interface channels, communication with an external device and local communication within a system can be performed at the same time (refer to Figure 7-7). Figure 7-7. Example of Serial Interface µ PD784046(A) master (UART) RS-232C driver/ receiver SO2 RxD SI2 TxD SCK2 Port slave (3-wire serial I/O) INTPn Port Note 36 Handshake line Data Sheet U13121EJ1V1DS SI SO Note SCK Port INT µPD784044(A), 784046(A) 7.6.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) Two serial interface channels from which asynchronous serial interface mode and three-wire serial I/O mode can be selected are provided. (1) Asynchronous serial interface mode In this mode, 1-byte data following a start bit is transferred or received. The internal baud rate generator allows communication in a wide range of baud rates. The clock input to the ASCK pin can also be divided to define a baud rate. The baud rate generator can also set a baud rate conforming to the MIDI standard (31.25 kbps). Figure 7-8. Block Diagram in Asynchronous Serial Interface Mode Internal bus Receive buffer RXB, RXB2 Receive shift register RxD, RxD2 Transmit shift register TXS, TXS2 TxD, TxD2 Receive control Parity check INTSR, INTSR2 INTSER, INTSER2 Transmit control Parity append INTST, INTST2 Baud rate generator ASCK, ASCK2 Selector 1/2m fCLK 1/2n+1 1/2m Remark fCLK: internal system clock n = 0 to 11 m = 16 to 30 Data Sheet U13121EJ1V1DS 37 µPD784044(A), 784046(A) (2) 3-wire serial I/O mode This mode is to start transmission when the master device makes a serial clock active and to communicate 1-byte data in synchronization with this clock. The interface in this mode communicates with devices that have conventional clocked serial interface. Basically, communication is performed by using three lines: serial clock (SCK) and two serial data (SI and SO) lines. To connect two or more devices, a handshake line is necessary. Figure 7-9. Block Diagram in 3-Wire Serial I/O Mode Internal bus Direction control circuit SIO1, SIO2 Shift register SI1, SI2 Output latch SO1, SO2 Serial clock control circuit Remark fCLK: internal system clock n = 0 to 11 m = 1, 16 to 30 38 Data Sheet U13121EJ1V1DS Interrupt generation circuit Selector Serial clock counter SCK1, SCK2 1/2m INTCSI1, INTCSI2 1/2n+1 fCLK µPD784044(A), 784046(A) 7.7 Edge Detection Circuit The interrupt input pins (NMI and INTP0 through INTP6) input not only interrupt requests but also trigger signals of the internal hardware. Because all the interrupts and internal hardware operate by detecting specific edges of the input signals, a function to detect edges is provided. In addition, a noise rejection function is also provided to prevent detection of a wrong edge due to noise. Pin Detectable Edge Noise Rejected by: NMI Either rising or falling edge Analog delay INTP0-INTP6 Either rising or falling edge, or both edges Clock sampling Note Note A sampling clock can be selected. 7.8 Watchdog Timer A watchdog timer is provided to detect a hang-up of the CPU. This watchdog timer generates a non-maskable interrupt unless it is cleared by software within a specified interval time. Once the watchdog timer has been enable to operate, its operation cannot be stopped by software. Moreover, it can be specified whether the interrupt by the watchdog timer or the interrupt from the NMI pin takes precedence. Figure 7-10. Block Diagram of Watchdog Timer fCLK/211 fCLK Divider fCLK/212 Selector fCLK/29 Watchdog timer (8 bits) Overflow INTWDT fCLK/213 WDT CLR Data Sheet U13121EJ1V1DS 39 µPD784044(A), 784046(A) 8. INTERRUPT FUNCTION The three types of interrupt processing shown in Table 8-1 can be selected. Table 8-1. Interrupt Request Processing Processing Mode Processed by: Vectored interrupt Software Context switching Macro service Firmware Processing Contents of PC and PSW Branches to and executes processing routine (any processing contents). Saves and restores to/from stack. Automatically selects register bank, and branches to and executes processing routine (any processing contents). Saves or restores to/from fixed area in register bank. Executes data transfer between memory and I/O (any processing contents). Retained 8.1 Interrupt Source As interrupt sources, twenty-seven sources listed in Table 8-2, BRK instruction execution, and operand error are available. Four priority levels of interrupt processing can be selected, so that nesting during interrupt processing and the levels of interrupt requests that are generated at the same time can be controlled. However, nesting always advances with macro service (i.e., nesting is not kept pending). The default priority is the priority (fixed) of the processing for the interrupt requests that have occurred at the same time and have the same priority level (refer to Table 8-2). 40 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) Table 8-2. Interrupt Sources Type Default Source Priority Software – Name BRK instruction Trigger Execution of instruction Internal/ Macro External Service – – BRKCS instruction Non- – maskable Maskable Operand error If result of exclusive OR of operands byte and byte is not FFH when MOV STBC, #byte, MOV WDM, #byte, or LOCATION instruction is executed NMI Detection of pin input edge External Internal INTWDT Overflow of watchdog timer 0 (highest) INTOV0 Overflow of timer 0 1 INTOV1 Overflow of timer 1 2 INTOV4 Overflow of timer 4 3 INTP0 Detection of pin input edge (CC00 capture trigger) External INTCC00 Generation of TM0-CC00 coincidence signal Internal INTP1 Detection of pin input edge (CC01 capture trigger) External INTCC01 Generation of TM0-CC01 coincidence signal Internal INTP2 Detection of pin input edge (CC02 capture trigger) External INTCC02 Generation of TM0-CC02 coincidence signal Internal INTP3 Detection of pin input edge (CC03 capture trigger) External INTCC03 Generation of TM0-CC03 coincidence signal Internal 7 INTP4 Detection of pin input edge (A/D converter conversion start trigger) External 8 INTP5 Detection of pin input edge (TM2 event counter input) 9 INTP6 Detection of pin input edge (TM3 event counter input) 10 INTCM10 Generation of TM1-CM10 coincidence signal 11 INTCM11 Generation of TM1-CM11 coincidence signal 12 INTCM20 Generation of TM2-CM20 coincidence signal 13 INTCM21 Generation of TM2-CM21 coincidence signal 14 INTCM30 Generation of TM3-CM30 coincidence signal 15 INTCM31 Generation of TM3-CM31 coincidence signal 16 INTCM40 Generation of TM4-CM40 coincidence signal 17 INTCM41 Generation of TM4-CM41 coincidence signal 18 INTSER Occurrence of UART0 reception error 4 5 6 19 INTSR End of UART0 reception INTCSI1 End of 3-wire serial I/O1 transfer 20 INTST End of UART0 transfer 21 INTSER2 Occurrence of UART2 reception error 22 INTSR2 End of UART2 reception INTCSI2 End of 3-wire serial I/O2 transfer 23 INTST2 End of UART2 transfer 24 (lowest) INTAD End of A/D converter conversion (transfer to ADCR) Data Sheet U13121EJ1V1DS Internal 41 µPD784044(A), 784046(A) 8.2 Vectored Interrupt Execution branches to a processing routine by using the memory contents of the vector table address corresponding to an interrupt source as the branch destination address. The following operations are performed so that the CPU processes the interrupt: • On branch : Saves status of CPU (contents of PC and PSW) to stack • On returning : Restores status of CPU from stack Execution is returned from the processing routine to the main routine by the RETI instruction. The branch destination address must be in a range of 0 to FFFFH. Table 8-3. Vector Table Address Interrupt Source Vector Table Address Vector Table Address BRK instruction 003EH INTCM10 001AH Operand error 003CH INTCM11 001CH NMI 0002H INTCM20 001EH INTWDT 0004H INTCM21 0020H INTOV0 0006H INTCM30 0022H INTOV1 0008H INTCM31 0024H INTOV4 000AH INTCM40 0026H INTP0 000CH INTCM41 0028H INTSER 002AH 000EH INTSR 002CH INTCC00 INTP1 INTCC01 INTP2 INTCSI1 0010H INTST INTSER2 0030H 0012H INTSR2 0032H INTCC02 INTP3 INTCC03 42 Interrupt Source 002EH INTCSI2 INTP4 0014H INTST2 0034H INTP5 0016H INTAD 0036H INTP6 0018H Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 8.3 Context Switching A specific register bank is selected by hardware when an interrupt request is generated or when the BRKCS instruction is executed. Execution branches to the vector address stored in advance to the selected register bank, and the current contents of the program counter (PC) and program status word (PSW) are stacked to the register bank. The branch destination address must be in a range of 0 to FFFFH. Figure 8-1. Context Switching Operation When Interrupt Request Is Generated Register bank 0000B < 7 > Transfer (0 to 7) Register bank n (n = 0 to 7) PC15_0 PC19-16 < 6 > Exchange < 2 > Save (bits 8 through 11 of temporary register) < 5 > Save A X B C R5 R4 R7 R6 V VP U UP < 3 > Select register bank (RBS0 to RBS2←n) Temporary register < 1 > Save T D E W H L < 4 > RSS←0 IE ←0 PSW Data Sheet U13121EJ1V1DS 43 µPD784044(A), 784046(A) 8.4 Macro Service The µ PD784046(A) has a total of seven types of macro service. Each macro service is outlined below. (1) Counter mode: EVTCNT • Operation (a) Increments or decrements an 8-bit macro service counter (MSC). (b) A vectored interrupt request is generated when the value of MSC reaches 0. +1 / _1 MSC • Application example: Event counter, measurement of number of times of capture (2) Block transfer mode: BLKTRS • Operation (a) Transfers block data between the buffer and an SFR specified by the SFR pointer (SFR.PTR). (b) The transfer source and destination can be an SFR or buffer. The length of the data to be transferred can be byte or word. (c) The number of times data is to be transferred (block size) is specified by MSC. (d) MSC is auto-decremented (–1) each time the macro service has been executed. (e) When the value of MSC has reached 0, a vectored interrupt request is generated. SFR.PTR _1 Buffer N MSC Buffer 1 SFR Internal bus • Application example: Data transfer/reception of serial interface 44 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (3) Block transfer mode (with memory pointer): BLKTRS-P • Operation This is the block transfer mode in (2) with a memory pointer (MEM.PTR) appended. The appended buffer area of MEMP can be freely set on the memory space. Remark MEM.PTR is auto-incremented (+1: byte data transfer/+2: word data transfer) each time the macro service has been executed. SFRP _1 MSC +1 / +2 MEM.PTR Buffer N Buffer 1 SFR Internal bus • Application example: Same as (2) (4) Data differential mode: DTADIF • Operation (a) Calculates the difference between the contents of the SFR specified by SFR pointer (SFR.PTR) (current value) and the contents of the SFR loaded to the last data buffer (LDB). (b) Stores the result of the calculation to a predetermined buffer area. (c) Stores the contents of the current value of SFR to LDB. (d) The number of times the data is to be transferred (block size) is specified by MSC. The value of MSC is auto-decremented (–1) each time the macro service has been executed. (e) When the value of MSC has reached 0, a vectored interrupt request is generated. Remark The differential calculation can be performed only an SFR of 16-bit configuration. SFR.PTR _1 MSC SFR LDB Buffer N Buffer 1 Differential calculation Internal bus • Application example: Measurement of period and pulse width by capture register of timer 0 Data Sheet U13121EJ1V1DS 45 µPD784044(A), 784046(A) (5) Data differential mode (with memory pointer): DTADIF-P • Operation This is the data differential mode in (4) with a memory pointer (MEM.PTR) appended. The appended MEM.PTR can set a buffer area to which the differential data is to be stored on the memory space freely. Remarks 1. The differential calculation can be performed only an SFR of 16-bit configuration. 2. The buffer is specified by the result of an operation between MEM.PTR and MSCNote. The value of MEM.PTR is not updated after the data has been transferred. Note MEM.PTR – (MSC × 2) + 2 SFR.PTR Buffer N _1 MSC SFR LDB MEM.PTR Differential calculation Buffer 1 Internal bus • Application example: Same as (4) (6) CPU monitoring mode0: SFLF0 • Operation (a) Checks the internal operation of the CPU. (b) When the blocks are operating normally, the value given by subtracting 10 from the initial value is transferred to the SFR specified by the SFR pointer (SFR.PTR). • Application example: Used for self checking of the CPU during normal operation. (7) CPU monitoring mode1: SELF1 • Operation (a) Checks the internal operation of the CPU. (b) When the blocks are operating normally, the value given by subtracting 8 from the initial value is transferred to the SFR specified by the SFR pointer (SFR.PTR). • Application example: Used for self checking of the CPU during normal operation. 46 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 9. LOCAL BUS INTERFACE The µ PD784046(A) can be connected to an external memory or I/O (memory mapped I/O), supporting a 1Mbyte memory space (refer to Figure 9-1). Figure 9-1. Example of Local Bus Interface (with external 8-bit bus specified) Address bus A16-A19 Decoder µ PD784046(A) RD LWR SRAM AD0-AD7 ASTB PROM Character generator Data bus Latch Address bus AD8-AD15 Gate array I/O expansion Centronics I/F, etc. Data Sheet U13121EJ1V1DS 47 µPD784044(A), 784046(A) 9.1 Memory Expansion The external program memory or data memory can be expanded from 256 bytes up to 1M bytes in seven steps. When an external device is connected, the address/data bus and read/write strobe signals are controlled by using ports 4 through 6 and P90 through P93 pins. The functions of these ports and pins are set by the memory expansion mode register (MM). Table 9-1. Setting of Pin Function Memory Expansion Pin Function Mode Register Port 4 Port 5 Port 6 MM0-MM3 P40-P47 P50-P57 P60-P63 Port mode General-purpose port External memory expansion mode AD0-AD7 AD8 to AD15 are set stepwise. Rest of pins can be used as general-purpose port pins. P90-P93 A16 through A19 are set stepwise. Rest of pins can be used as general-purpose port pins. P90 P91 P92 P93 : : : : RD LWR HWR ASTB Remark AD8 through AD15 are used as address bus. The number of pins of ports 5 and 6 that are used as address bus pins can be changed according to the size of the external memory connected (external address space), so that the external memory can be expanded stepwise. The pins not used as address bus pins can be used as general-purpose I/O port pins (refer to Table 9-2). The external address space can be set in seven steps by MM. Table 9-2. Operations of Ports 5 and 6 (in external memory expansion mode) Port 5 P50 P51 P52 P53 P54 Port 6 P55 P56 P57 P60 P61 P62 External address space P63 General-purpose port 256 bytes or less Note AD8 1K bytes or less Note AD9 AD10 4K bytes or less Note AD11 AD12 16K bytes or less Note AD13 AD14 AD15 64K bytes or less A16 A17 256K bytes or less A18 Note 1M bytes or less When the external 16-bit bus is specified, do not set MM such that the external address space is of this size. Caution When the external 16-bit bus is specified, set MM such that all the pins of port 5 (P50 through P57) are used as AD pins (AD8 through AD15). 48 A19 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 9.2 Memory Space The 1M-byte memory space is divided into the following eight spaces of logical addresses. Each space can be controlled by using the programmable wait function and bus sizing function. Figure 9-2. Memory Space F F F F FH 512K bytes 8 0 0 0 0H 7 F F F FH 256K bytes 4 0 0 0 0H 3 F F F FH 128K bytes 2 0 0 0 0H 1 F F F FH 64K bytes 1 0 0 0 0H 0 F F F FH 16K bytes 0C0 0 0H 0 B F F FH 16K bytes 0 8 0 0 0H 0 7 F F FH 16K bytes 0 4 0 0 0H 0 3 F F FH 16K bytes 0 0 0 0 0H 9.3 Programmable Wait A wait state can be inserted to each of the eight memory spaces while the RD, LWR, and HWR signals are active. Even if memories with different access times are connected, therefore, the overall efficiency of the system is not degraded. In addition, an address wait function that extends the active period of the ASTB signal is also available to extend the address decode time (this function can be set to all the spaces). 9.4 Bus Sizing Function The µ PD784046(A) can change the external data bus width between 8 and 16 bits when an external device is connected. Even if the memory space is divided by eight, the bus width of each memory space can be specified independently. Data Sheet U13121EJ1V1DS 49 µPD784044(A), 784046(A) 10. STANDBY FUNCTION The µ PD784046(A) has the following standby function modes that reduce the power consumption of the chip. • HALT mode : This mode stops the operating clock of the CPU. It can reduce the average power consumption through intermittent operation by combination of a normal operation and this mode. • IDLE mode : This mode stops the entire system with the operation of the oscillation circuit continuing. Normal program operation can be restored from this mode with the power consumption close to that in the STOP mode and time equivalent to that in the HALT mode. • STOP mode : This mode stops the oscillator and stops all the internal operations of the chip to minimize the power consumption to the level of only leakage current. These modes are programmable. Macro service can be started from the HALT mode. Figure 10-1. Standby Status Transition Waits for stabilization of oscillation Macro service request End of first processing End of macro service Program operation I NM ID RE LE SE set T tin NM inp g ut I Interrupt request of masked interrupt te No Note IDLE (standby) t es qu ut re pt inp g rru ET ttin te S se RE LT HA In STOP (standby) g ttin se t P pu O ST ET in S RE Macro service Ma En cro d o se f fi rvic e rst pr req u oc es est sin g on ilizati on stab Oscillati expires time HALT (standby) Only unmasked interrupt request Remark Only external input of NMI is valid. The watchdog timer cannot be used to release the standby mode (STOP/HALT/IDLE). 50 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 11. RESET FUNCTION When a low level is input to the RESET pin, the internal hardware is initialized (reset status). When the RESET signal goes high, the following data is set to the program counter (PC). • Lower 8 bits of PC : contents of address 0000H • Middle 8 bits of PC : contents of address 0001H • Higher 4 bits of PC : 0 The contents of the PC are assumed as a branch destination address and program execution is started from this address. Therefore, the program can be reset and started from any address. Set the contents of each register by program as necessary. To prevent malfunctioning due to noise, a noise rejection circuit is provided to the RESET input circuit. This noise rejection circuit is a sampling circuit with analog delay. Figure 11-1. Accepting Reset Delay Delay Delay PC initialization Instruction execution at reset start address RESET (input) Internal reset signal Reset starts Reset ends Keep the RESET signal active until the oscillation stabilization time (about 40 ms) elapses when executing a reset operation on power application or when releasing the STOP mode by reset. Figure 11-2. Reset Operation on Power Application Oscillation stabilization time Delay Initializes PC Instruction execution at reset start address VDD RESET (input) Internal reset signal Reset ends Data Sheet U13121EJ1V1DS 51 µPD784044(A), 784046(A) 12. INSTRUCTION SET (1) 8-bit instructions (( ): combination realized by writing A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 12-1. Instructions for 8-Bit Addressing 2nd Operand #byte A r saddr r’ saddr’ sfr !addr16 mem r3 [WHL+] !!addr24 [saddrp] PSWL [WHL–] 1st Operand A [%saddrg] PSWH (MOV) MOV (MOV)Note 6 MOV (MOV) MOV MOV ADDNote 1 (XCH) XCH (XCH)Note 6 (XCH) (XCH) XCH (XCH) ADDNote 1 (ADD)Note 1 (MOV) (ADD)Note 1 (ADD)Note 1 (ADD)Note 1, 6 (ADD)Note 1 ADDNote 1 r (MOV) MOV MOV MOV MOV ADDNote 1 (XCH) MOV XCH XCH XCH XCH (ADD)Note 1 ADDNote 1 ADDNote 1 ADDNote 1 (MOV)Note 6 MOV MOV n NoneNote 2 (MOV) RORNote 3 MULU DIVUW INC DEC saddr MOV ADDNote 1 (ADD)Note 1 ADDNote 1 sfr MOV MOV INC XCH DEC ADDNote 1 DBNZ MOV PUSH ADDNote 1 (ADD)Note 1 ADDNote 1 POP CHKL CHKLA !addr16 MOV (MOV) !!addr24 ADDNote 1 mem MOV [saddrp] ADDNote 1 MOV [%saddrg] mem3 ROR4 ROL4 r3 MOV MOV PSWL PSWH B, C DBNZ STBC, WDM MOV [TDE+] (MOV) [TDE–] (ADD)Note 1 MOVBKNote 5 MOVMNote 4 Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. Either the second operand is not used, or the second operand is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. If saddr is saddr2 in this combination, some instructions have a short code length. 52 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (2) 16-bit instructions (( ): combination realized by writing AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 12-2. Instructions for 16-Bit Addressing 2nd Operand #word AX rp saddrp rp’ saddrp’ sfrp !addr16 !!addr24 1st Operand AX mem [WHL+] byte n NoneNote 2 SHRW MULWNote 4 [saddrp] [%saddrg] (MOVW) ADDW Note 1 (MOVW) (MOVW) (MOVW)Note 3 MOVW (MOVW) MOVW (MOVW) (XCHW) (XCHW) (XCHW)Note 3 (XCHW) XCHW XCHW (XCHW) (ADDW)Note 1 (ADDW)Note 1 (ADDW)Note 1, 3 (ADDW)Note 1 rp MOVW ADDW saddrp Note 1 MOVW ADDW Note 1 (MOVW) MOVW (XCHW) XCHW MOVW MOVW MOVW XCHW XCHW (ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 SHLW INCW (MOVW)Note 3 MOVW MOVW INCW (ADDW)Note 1 ADDWNote 1 XCHW DECW DECW ADDWNote 1 sfrp MOVW MOVW MOVW PUSH ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 MOVW (MOVW) POP MOVW MOVTBLW !!addr24 mem MOVW [saddrp] [%saddrg] PSW PUSH POP SP ADDWG SUBWG post PUSH POP PUSHU POPU [TDE+] (MOVW) SACW byte MACW MACSW Notes 1. SUBW and CMPW are the same as ADDW. 2. Either the second operand is not used, or the second operand is not an operand address. 3. If saddrp is saddrp2 in this combination, some instructions have a short code length. 4. MULUW and DIVUX are the same as MULW. Data Sheet U13121EJ1V1DS 53 µPD784044(A), 784046(A) (3) 24-bit instructions (( ): combination realized by writing WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 12-3. Instructions for 24-Bit Addressing 2nd Operand #imm24 WHL 1st Operand WHL rg saddrg !!addr24 mem1 [%saddrg] NoneNote SP rg’ (MOVG) (MOVG) (MOVG) (MOVG) (ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG MOVG (MOVG) MOVG MOVG ADDG (ADDG) ADDG DECG SUBG (SUBG) SUBG PUSH saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG rg (MOVG) MOVG MOVG MOVG MOVG INCG POP [%saddrg] SP MOVG MOVG MOVG INCG DECG Note 54 Either the second operand is not used, or the second operand is not an operand address. Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BCLR, BFSET Table 12-4. Addressing of Bit Manipulation Instructions 2nd Operand CY saddr.bit /saddr.bit sfr.bit /sfr.bit A.bit /A.bit X.bit /X.bit PSWL.bit /PSWL.bit PSWH.bit /PSWH.bit mem2.bit /mem2.bit !addr16.bit /!addr16.bit NoneNote 1st Operand !!addr24.bit /!!addr24.bit CY MOV1 AND1 NOT1 AND1 OR1 SET1 OR1 CLR1 XOR1 saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit Note Either the second operand is not used, or the second operand is not an operand address. Data Sheet U13121EJ1V1DS 55 µPD784044(A), 784046(A) (5) Call/return/branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 12-5. Addressing for Call/Return/Branch Instructions Operand of $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None instruction address Basic BCNote CALL CALL CALL CALL CALL CALL CALL instruction BR BR BR BR BR BR BR BR Compound instruction CALLF CALLT BRKCS BRK RET RETCS RETI RETCSB RETB BF BT BTCLR BFSET DBNZ Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC. (6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS 56 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 13. ELECTRICAL SPECIFICATIONS Caution The followings are the specifications for the µPD784044(A), (A1), and (A2). For the µPD784046(A), (A1), and (A2), these are target specifications. (1) Electrical specifications of µPD784044(A), 784046(A) (1/6) Absolute Maximum Ratings (TA = 25 ˚C) Parameter Symbol Ratings Unit V DD –0.5 to +7.0 V AV DD –0.5 to V DD + 0.5 V Supply voltage Conditions AV SS Input voltage VI Output voltage VO Low-level output current I OL High-level output current I OH Analog input voltage A/D converter reference V IAN –0.5 to +0.5 V –0.5 to V DD + 0.5 ≤ 7.0 V –0.5 to V DD + 0.5 V 15 mA Total of all output pins 150 mA All output pins –10 mA Total of all output pins –100 mA AV DD > V DD –0.5 to V DD + 0.5 V Note 1 All output pins Note 2 AV REF input voltage V DD ≥ AV DD –0.5 to AV DD + 0.5 AV DD > V DD –0.5 to V DD + 0.5 V DD ≥ AV DD –0.5 to AV DD + 0.5 V Operating temperature TA –40 to +85 ˚C Storage temperature T stg –65 to +150 ˚C Notes 1. Pins other than the pins in Note 2. 2. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions Oscillation Frequency TA V DD 8 MHz ≤ f XX ≤ 25 MHz –40 to +85 ˚C 4.5 to 5.5 V Capacitance (TA = 25 ˚C, VSS = VDD = 0 V) Parameter Input capacitance Symbol Conditions MIN. TYP. MAX. Unit CI f = 1 MHz 10 pF Output capacitance CO 0 V except measured pins 10 pF I/O capacitance C IO 10 pF Data Sheet U13121EJ1V1DS 57 µPD784044(A), 784046(A) (1) Electrical specifications of µPD784044(A), 784046(A) (2/6) Oscillation Circuit Characteristics (TA = –40 to +85 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Resonator Recommended Circuit Ceramic resonator or crystal resonator X1 VSS C1 MIN. MAX. Unit Oscillation frequency (f XX ) 8 25 MHz X1 input frequency (f X) 8 25 MHz X1 input rise, fall time 0 5 ns X1 input high-, low-level width 20 105 ns X2 C2 External clock X1 Item X2 OpenNote HCMOS inverter Note When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse phase clock of the pin X1 to the pin X2 when the EXTC bit = 1. Caution When using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. • Always keep the ground potential for the capacitor in the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract any signal from the oscillation circuit. 58 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (1) Electrical specifications of µPD784044(A), 784046(A) (3/6) DC Characteristics (TA = –40 to +85 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol MAX. Unit 0 0.8 V Note 1 2.2 V DD V V IH2 Note 2 0.8 V DD V DD Low-level output voltage V OL I OL = 2.0 mA High-level output voltage V OH I OH = –400 µ A Low-level input voltage V IL High-level input voltage V IH1 Input leakage current Analog pin input leakage current Conditions MIN. TYP. 0.45 V DD – 1.0 V V I LI Note 3 0 V ≤ V I ≤ V DD ±10 µA I LIAN Note 4 0 V ≤ V I ≤ AV DD ±1 µA Output leakage current I LO 0 V ≤ V O ≤ V DD ±10 µA V DD supply current I DD1 Operating mode (f XX = 25 MHz) 40 70 mA I DD2 HALT mode (f XX = 25 MHz) 25 50 mA I DD3 IDLE mode (f XX = 25 MHz) 10 20 mA 2 15 µA 15 50 µA 40 80 kΩ Data retention voltage V DDDR STOP mode Data retention current I DDDR STOP mode VDDDR = 2.5 V 2.5 VDDDR = 5 V ± 10 % Pull-up resistor RL 15 V Notes 1. Pins other than pins in Note 2. 2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET 3. Input and I/O pins (except X1 and X2, and P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used as analog inputs) 4. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used as analog input, only during the nonsampling operation) Data Sheet U13121EJ1V1DS 59 µPD784044(A), 784046(A) (1) Electrical specifications of µPD784044(A), 784046(A) (4/6) AC Characteristics (TA = –40 to +85 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Read/write operation Parameter Symbol Expression MIN. MAX. Unit 80 250 ns System clock cycle time t CYK Address setup time (vs. ASTB↓) t SAST (0.5 + a) T – 20 20 ns Address hold time (vs. ASTB↓) t HSTA 0.5T – 20 20 ns ASTB high-level width t WSTH (0.5 + a) T – 17 23 ns Address→RD↓ delay time t DAR (1 + a) T – 15 65 ns RD↓→address float time t FRA 0 ns Address→data input time t DAID (2.5 + a + n) T – 56 144 ns RD↓→data input time t DRID (1.5 + n) T – 48 72 ns ASTB↓→RD↓ delay time t DSTR 0.5T – 16 24 Data hold time (vs. RD↑) t HRID 0 ns RD↑→address active time t DRA 0.5T – 14 26 ns RD low-level width t WRL (1.5 + n) T – 30 90 ns Address→LWR, HWR↓ delay time t DAW (1 + a) T – 15 65 ns ns LWR, HWR↓→data output time t DWOD ASTB↓→LWR, HWR↓ delay time t DSTW 0.5T – 16 24 15 ns Data setup time (vs. LWR, HWR↑) t SODW (1.5 + n) T – 25 95 ns Data hold time (vs. LWR, HWR↑) t HWOD 0.5T – 14 26 ns LWR, HWR↑→ ASTB↑ delay time t DWST 1.5T – 15 105 ns LWR, HWR low-level width t WWL (1.5 + n) T – 36 84 ns Address→WAIT↓ input time t DAWT (2 + a) T – 50 110 ns ASTB↓→WAIT↓ input time t DSTWT 1.5T – 40 80 ns ASTB↓→WAIT hold time t HSTWT (1.5 + n) T + 5 ASTB↓→WAIT↑ delay time t DSTWTH (1.5 + n) T – 40 RD↓→WAIT↓ input time t DRWT T – 40 RD↓→WAIT hold time t HRWT (1 + n) T + 5 RD↓→WAIT↑ delay time t DRWTH (1 + n) T – 40 LWR, HWR↓→WAIT↓ input time t DWWT T – 40 LWR, HWR↓→WAIT hold time t HWWT (1 + n) T + 5 LWR, HWR↓→WAIT↑ delay time Note t DWWTH (1 + n) T – 40 125 ns ns 160 Note ns 40 ns 85 ns 120 Note ns 40 ns 85 ns 120 Note ns Specification when an external wait is inserted Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or programmable wait control registers 1, 2 (PWC1, PWC2). (n ≥ 0. n ≥ 1 for tDSTWTH, tDRWTH, tDWWTH). 4. Calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (tCYK = T). The values in the above expression column are calculated based on T = 80 ns. 60 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (1) Electrical specifications of µPD784044(A), 784046(A) (5/6) Serial Operation (TA = –40 to +85 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Serial clock cycle time t CYSK Serial clock low-level width t WSKL Serial clock high-level width t WSKH Conditions MIN. MAX. Unit SCK1, SCK2 output BRG T SFT ns SCK1, SCK2 input 640 ns 0.5T SFT–40 ns External clock SCK1, SCK2 output BRG SCK1, SCK2 input External clock SCK1, SCK2 output BRG SCK1, SCK2 input External clock 280 ns 0.5T SFT–40 ns 280 ns SI1, SI2 setup time (vs. SCK1, SCK2↑) t SSSK 80 ns SI1, SI2 hold time (vs. SCK1, SCK2↑) t HSSK 80 ns SCK1, SCK2↓→SO1, SO2 output delay time t DSBSK R = 1 kΩ, C = 100 pF 0 150 ns MIN. MAX. Unit Remarks 1. TSFT is a value set in software. The minimum value is tCYK × 8. 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) Other Operations (TA = –40 to +85 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Conditions NMI high, low-level width t WNIH , t WNIL 10 µs INTP0-INTP6 high, low-level width t WITH, t WITL 4 t CYSMP TI2, TI3 high, low-level width t WTIH , t WTIL 4 t CYSMP RESET high, low-level width t WRSH , t WRSL 10 µs Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software. When NIn = 0, tCYSMP = tCYK When NIn = 1, tCYSMP = tCYK × 4 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) 3. NIn: Bit n of NPC (n = 0-6) AC Timing Test Point VDD 0.8 VDD or 2.2 V Test point 0.8 V 0.8 VDD or 2.2 V 0.8 V 0V Data Sheet U13121EJ1V1DS 61 µPD784044(A), 784046(A) (1) Electrical specifications of µPD784044(A), 784046(A) (6/6) AD Converter Characteristics (TA = –40 to +85 ˚C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V, VDD – 0.5 V ≤ AVDD ≤ VDD) Parameter Symbol Conditions Resolution Total MIN. TYP. MAX. 10 error Note Unit bit 4.5 V ≤ AV REF ≤ AV DD ±0.5 %FSR 3.4 V ≤ AV REF < 4.5 V ±0.7 %FSR ±1/2 LSB Quantization error Conversion time t CONV 80 ns ≤ t CYK ≤ 250 ns 169 t CYK Sampling time t SAMP 80 ns ≤ t CYK ≤ 250 ns 20 t CYK Zero-scale Full-scale error Note error Note Nonlinearity error Note 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±3.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±3.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±2.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB –0.3 AV REF +0.3 V 3.4 AV DD V Analog input voltage V IAN A/D converter reference input voltage AV REF AV REF current AI REF 1.0 3.0 mA AV DD supply current AI DD 2.0 6.0 mA A/D converter data retention current AI DDDR AV DDDR = 2.5 V 2 10 µA AV DDDR = 5 V ± 10% 10 50 µA Note STOP mode The quantization error is excluded. Remark tCYK = 1/fCLK (fCLK is internal system clock frequency). 62 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (2) Electrical specifications of µPD784044(A1), 784046(A1) (1/6) Absolute Maximum Ratings (TA = 25 ˚C) Parameter Symbol Ratings Unit V DD –0.5 to +7.0 V AV DD –0.5 to V DD + 0.5 V AV SS –0.5 to +0.5 V –0.5 to V DD + 0.5 ≤ 7.0 V –0.5 to V DD + 0.5 V All output pins 15 mA Total of all output pins 150 mA Supply voltage Input voltage VI Output voltage VO Low-level output current I OL High-level output current I OH Analog input voltage A/D converter reference V IAN Conditions Note 1 All output pins –10 mA Total of all output pins –100 mA AV DD > V DD –0.5 to V DD + 0.5 V V DD ≥ AV DD –0.5 to AV DD + 0.5 Note 2 AV REF input voltage AV DD > V DD –0.5 to V DD + 0.5 V DD ≥ AV DD –0.5 to AV DD + 0.5 V Operating temperature TA –40 to +110 ˚C Storage temperature T stg –65 to +150 ˚C Notes 1. Pins other than the pins in Note 2. 2. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions Oscillation Frequency TA V DD 8 MHz ≤ f XX ≤ 20 MHz –40 to +110 ˚C 4.5 to 5.5 V Capacitance (TA = 25 ˚C, VSS = VDD = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CI f = 1 MHz 10 pF Output capacitance CO 0 V except measured pins 10 pF I/O capacitance C IO 10 pF Data Sheet U13121EJ1V1DS 63 µPD784044(A), 784046(A) (2) Electrical specifications of µPD784044(A1), 784046(A1) (2/6) Oscillation Circuit Characteristics (TA = –40 to +110 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Resonator Recommended Circuit Ceramic resonator or crystal resonator X1 VSS C1 MIN. MAX. Unit 8 20 MHz X1 input frequency (f X) 8 20 MHz X1 input rise, fall time 0 5 ns X1 input high-, low-level width 20 105 ns X2 C2 External clock X1 Item Oscillation frequency (f XX ) X2 OpenNote HCMOS inverter Note When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse phase clock of the pin X1 to the pin X2 when the EXTC bit = 1. Caution When using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. • Always keep the ground potential for the capacitor in the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract any signal from the oscillation circuit. 64 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (2) Electrical specifications of µPD784044(A1), 784046(A1) (3/6) DC Characteristics (TA = –40 to +110 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol MAX. Unit 0 0.8 V Note 1 2.2 V DD V V IH2 Note 2 0.8 V DD V DD Low-level output voltage V OL I OL = 2.0 mA High-level output voltage V OH I OH = –400 µ A Low-level input voltage V IL High-level input voltage V IH1 Input leakage current Analog pin input leakage current Conditions MIN. TYP. 0.45 V DD – 1.0 V V I LI Note 3 0 V ≤ V I ≤ V DD ±10 µA I LIAN Note 4 0 V ≤ V I ≤ AV DD ±2 µA Output leakage current I LO 0 V ≤ V O ≤ V DD ±10 µA V DD supply current I DD1 Operating mode (f XX = 20 MHz) 30 60 mA I DD2 HALT mode (f XX = 20 MHz) 15 30 mA I DD3 IDLE mode (f XX = 20 MHz) 10 20 mA 2 100 µA 15 1000 µA 40 80 kΩ Data retention voltage V DDDR STOP mode Data retention current I DDDR STOP mode VDDDR = 2.5 V 2.5 VDDDR = 5 V ± 10 % Pull-up resistor RL 15 V Notes 1. Pins other than pins in Note 2. 2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET 3. Input and I/O pins (except X1 and X2, and P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used as analog inputs) 4. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used as analog input, only during the nonsampling operation) Data Sheet U13121EJ1V1DS 65 µPD784044(A), 784046(A) (2) Electrical specifications of µPD784044(A1), 784046(A1) (4/6) AC Characteristics (TA = –40 to +110 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Read/write operation Parameter Symbol Expression MIN. MAX. Unit 100 250 ns System clock cycle time t CYK Address setup time (vs. ASTB↓) t SAST (0.5 + a) T – 20 30 ns Address hold time (vs. ASTB↓) t HSTA 0.5T – 20 30 ns ASTB high-level width t WSTH (0.5 + a) T – 17 33 ns Address→RD↓ delay time t DAR (1 + a) T – 15 85 ns RD↓→address float time t FRA 0 ns Address→data input time t DAID (2.5 + a + n) T – 56 194 ns RD↓→data input time t DRID (1.5 + n) T – 53 97 ns ASTB↓→RD↓ delay time t DSTR 0.5T – 16 34 Data hold time (vs. RD↑) t HRID 0 ns RD↑→address active time t DRA 0.5T – 14 36 ns RD low-level width t WRL (1.5 + n) T – 30 120 ns Address→LWR, HWR↓ delay time t DAW (1 + a) T – 15 85 ns ns LWR, HWR↓→data output time t DWOD ASTB↓→LWR, HWR↓ delay time t DSTW 0.5T – 16 34 15 ns Data setup time (vs. LWR, HWR↑) t SODW (1.5 + n) T – 25 125 ns Data hold time (vs. LWR, HWR↑) t HWOD 0.5T – 14 36 ns LWR, HWR↑→ ASTB↑ delay time t DWST 1.5T – 15 135 ns LWR, HWR low-level width t WWL (1.5 + n) T – 36 114 ns Address→WAIT↓ input time t DAWT (2 + a) T – 50 150 ns ASTB↓→WAIT↓ input time t DSTWT 1.5T – 40 110 ns ASTB↓→WAIT hold time t HSTWT (1.5 + n) T + 5 ASTB↓→WAIT↑ delay time t DSTWTH (1.5 + n) T – 40 RD↓→WAIT↓ input time t DRWT T – 40 RD↓→WAIT hold time t HRWT (1 + n) T + 5 RD↓→WAIT↑ delay time t DRWTH (1 + n) T – 40 LWR, HWR↓→WAIT↓ input time t DWWT T – 40 LWR, HWR↓→WAIT hold time t HWWT (1 + n) T + 5 LWR, HWR↓→WAIT↑ delay time Note t DWWTH (1 + n) T – 40 155 ns ns 210 Note ns 60 ns 105 ns 160 Note ns 60 ns 105 ns 160 Note ns Specification when an external wait is inserted Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or programmable wait control registers 1, 2 (PWC1, PWC2). (n ≥ 0. n ≥ 1 for tDSTWTH, tDRWTH, tDWWTH). 4. Calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (tCYK = T). The values in the above expression column are calculated based on T = 100 ns. 66 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (2) Electrical specifications of µPD784044(A1), 784046(A1) (5/6) Serial Operation (TA = –40 to +110 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Serial clock cycle time t CYSK Serial clock low-level width t WSKL Serial clock high-level width t WSKH Conditions MIN. MAX. Unit SCK1, SCK2 output BRG T SFT ns SCK1, SCK2 input 800 ns 0.5T SFT–40 ns External clock SCK1, SCK2 output BRG SCK1, SCK2 input External clock SCK1, SCK2 output BRG SCK1, SCK2 input External clock 360 ns 0.5T SFT–40 ns 360 ns SI1, SI2 setup time (vs. SCK1, SCK2↑) t SSSK 80 ns SI1, SI2 hold time (vs. SCK1, SCK2↑) t HSSK 80 ns SCK1, SCK2↓→SO1, SO2 output delay time t DSBSK R = 1 kΩ, C = 100 pF 0 150 ns MIN. MAX. Unit Remarks 1. TSFT is a value set in software. The minimum value is tCYK × 8. 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) Other Operations (TA = –40 to +110 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Conditions NMI high, low-level width t WNIH , t WNIL 10 µs INTP0-INTP6 high, low-level width t WITH, t WITL 4 t CYSMP TI2, TI3 high, low-level width t WTIH , t WTIL 4 t CYSMP RESET high, low-level width t WRSH , t WRSL 10 µs Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software. When NIn = 0, tCYSMP = tCYK When NIn = 1, tCYSMP = tCYK × 4 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) 3. NIn: Bit n of NPC (n = 0-6) AC Timing Test Point VDD 0.8 VDD or 2.2 V Test point 0.8 V 0.8 VDD or 2.2 V 0.8 V 0V Data Sheet U13121EJ1V1DS 67 µPD784044(A), 784046(A) (2) Electrical specifications of µPD784044(A1), 784046(A1) (6/6) AD Converter Characteristics (TA = –40 to +110 ˚C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V, VDD – 0.5 V ≤ AVDD ≤ VDD) Parameter Symbol Conditions Resolution Total MIN. TYP. MAX. 10 error Note Unit bit 4.5 V ≤ AV REF ≤ AV DD ±0.5 %FSR 3.4 V ≤ AV REF < 4.5 V ±0.7 %FSR ±1/2 LSB Quantization error Conversion time t CONV 169 t CYK Sampling time t SAMP 20 t CYK Zero-scale Full-scale error Note error Note Nonlinearity error Note 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±3.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±3.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±2.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB –0.3 AV REF +0.3 V 3.4 AV DD V Analog input voltage V IAN A/D converter reference input voltage AV REF AV REF current AI REF 3.0 4.0 mA AV DD supply current AI DD 2.0 6.0 mA A/D converter data retention current AI DDDR AV DDDR = 2.5 V 2 100 µA AV DDDR = 5 V ± 10% 10 1000 µA Note STOP mode The quantization error is excluded. Remark tCYK = 1/fCLK (fCLK is internal system clock frequency). 68 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (3) Electrical specifications of µPD784044(A2), 784046(A2) (1/6) Absolute Maximum Ratings (TA = 25 ˚C) Parameter Symbol Ratings Unit V DD –0.5 to +7.0 V AV DD –0.5 to V DD + 0.5 V AV SS –0.5 to +0.5 V –0.5 to V DD + 0.5 ≤ 7.0 V –0.5 to V DD + 0.5 V All output pins 15 mA Total of all output pins 150 mA Supply voltage Input voltage VI Output voltage VO Low-level output current I OL High-level output current I OH Analog input voltage A/D converter reference V IAN Conditions Note 1 All output pins –10 mA Total of all output pins –100 mA AV DD > V DD –0.5 to V DD + 0.5 V V DD ≥ AV DD –0.5 to AV DD + 0.5 Note 2 AV REF input voltage AV DD > V DD –0.5 to V DD + 0.5 V DD ≥ AV DD –0.5 to AV DD + 0.5 V Operating temperature TA –40 to +125 ˚C Storage temperature T stg –65 to +150 ˚C Notes 1. Pins other than the pins in Note 2. 2. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions Oscillation Frequency TA V DD 8 MHz ≤ f XX ≤ 20 MHz –40 to +125 ˚C 4.5 to 5.5 V Capacitance (TA = 25 ˚C, VSS = VDD = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CI f = 1 MHz 10 pF Output capacitance CO 0 V except measured pins 10 pF I/O capacitance C IO 10 pF Data Sheet U13121EJ1V1DS 69 µPD784044(A), 784046(A) (3) Electrical specifications of µPD784044(A2), 784046(A2) (2/6) Oscillation Circuit Characteristics (TA = –40 to +125 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Resonator Recommended Circuit Ceramic resonator or crystal resonator X1 VSS C1 MIN. MAX. Unit 8 20 MHz X1 input frequency (f X) 8 20 MHz X1 input rise, fall time 0 5 ns X1 input high-, low-level width 20 105 ns X2 C2 External clock X1 Item Oscillation frequency (f XX ) X2 OpenNote HCMOS inverter Note When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse phase clock of the pin X1 to the pin X2 when the EXTC bit = 1. Caution When using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: • Keep the wiring length as short as possible. • Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of a line through which a high alternating current flows. • Always keep the ground potential for the capacitor in the oscillation circuit at the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. • Do not extract any signal from the oscillation circuit. 70 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (3) Electrical specifications of µPD784044(A2), 784046(A2) (3/6) DC Characteristics (TA = –40 to +125 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol MAX. Unit 0 0.8 V Note 1 2.2 V DD V V IH2 Note 2 0.8 V DD V DD Low-level output voltage V OL I OL = 2.0 mA High-level output voltage V OH I OH = –400 µ A Low-level input voltage V IL High-level input voltage V IH1 Input leakage current Analog pin input leakage current Conditions MIN. TYP. 0.45 V DD – 1.0 V V I LI Note 3 0 V ≤ V I ≤ V DD ±10 µA I LIAN Note 4 0 V ≤ V I ≤ AV DD ±2 µA Output leakage current I LO 0 V ≤ V O ≤ V DD ±10 µA V DD supply current I DD1 Operating mode (f XX = 20 MHz) 30 60 mA I DD2 HALT mode (f XX = 20 MHz) 15 30 mA I DD3 IDLE mode (f XX = 20 MHz) 10 20 mA 2 100 µA 15 1000 µA 40 80 kΩ Data retention voltage V DDDR STOP mode Data retention current I DDDR STOP mode VDDDR = 2.5 V 2.5 VDDDR = 5 V ± 10 % Pull-up resistor RL 15 V Notes 1. Pins other than pins in Note 2. 2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/ INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET 3. Input and I/O pins (except X1 and X2, and P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 used as analog inputs) 4. Pins P70/ANI0-P77/ANI7, P80/ANI8-P87/ANI15 (pins used as analog input, only during the nonsampling operation) Data Sheet U13121EJ1V1DS 71 µPD784044(A), 784046(A) (3) Electrical specifications of µPD784044(A2), 784046(A2) (4/6) AC Characteristics (TA = –40 to +125 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Read/write operation Parameter Symbol Expression MIN. MAX. Unit 100 250 ns System clock cycle time t CYK Address setup time (vs. ASTB↓) t SAST (0.5 + a) T – 20 30 ns Address hold time (vs. ASTB↓) t HSTA 0.5T – 20 30 ns ASTB high-level width t WSTH (0.5 + a) T – 17 33 ns Address→RD↓ delay time t DAR (1 + a) T – 15 85 ns RD↓→address float time t FRA 0 ns Address→data input time t DAID (2.5 + a + n) T – 56 194 ns RD↓→data input time t DRID (1.5 + n) T – 53 97 ns ASTB↓→RD↓ delay time t DSTR 0.5T – 16 34 Data hold time (vs. RD↑) t HRID 0 ns RD↑→address active time t DRA 0.5T – 14 36 ns RD low-level width t WRL (1.5 + n) T – 30 120 ns Address→LWR, HWR↓ delay time t DAW (1 + a) T – 15 85 ns ns LWR, HWR↓→data output time t DWOD ASTB↓→LWR, HWR↓ delay time t DSTW 0.5T – 16 34 15 ns Data setup time (vs. LWR, HWR↑) t SODW (1.5 + n) T – 25 125 ns Data hold time (vs. LWR, HWR↑) t HWOD 0.5T – 14 36 ns LWR, HWR↑→ ASTB↑ delay time t DWST 1.5T – 15 135 ns LWR, HWR low-level width t WWL (1.5 + n) T – 36 114 ns Address→WAIT↓ input time t DAWT (2 + a) T – 50 150 ns ASTB↓→WAIT↓ input time t DSTWT 1.5T – 40 110 ns ASTB↓→WAIT hold time t HSTWT (1.5 + n) T + 5 ASTB↓→WAIT↑ delay time t DSTWTH (1.5 + n) T – 40 RD↓→WAIT↓ input time t DRWT T – 40 RD↓→WAIT hold time t HRWT (1 + n) T + 5 RD↓→WAIT↑ delay time t DRWTH (1 + n) T – 40 LWR, HWR↓→WAIT↓ input time t DWWT T – 40 LWR, HWR↓→WAIT hold time t HWWT (1 + n) T + 5 LWR, HWR↓→WAIT↑ delay time Note t DWWTH (1 + n) T – 40 155 ns ns 210 Note ns 60 ns 105 ns 160 Note ns 60 ns 105 ns 160 Note ns Specification when an external wait is inserted Remarks 1. T = tCYK = 1/fCLK (fCLK is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (WAIT) or programmable wait control registers 1, 2 (PWC1, PWC2). (n ≥ 0. n ≥ 1 for tDSTWTH, tDRWTH, tDWWTH). 4. Calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (tCYK = T). The values in the above expression column are calculated based on T = 100 ns. 72 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) (3) Electrical specifications of µPD784044(A2), 784046(A2) (5/6) Serial Operation (TA = –40 to +125 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Serial clock cycle time t CYSK Serial clock low-level width t WSKL Serial clock high-level width t WSKH Conditions MIN. MAX. Unit SCK1, SCK2 output BRG T SFT ns SCK1, SCK2 input 800 ns 0.5T SFT–40 ns External clock SCK1, SCK2 output BRG SCK1, SCK2 input External clock SCK1, SCK2 output BRG SCK1, SCK2 input External clock 360 ns 0.5T SFT–40 ns 360 ns SI1, SI2 setup time (vs. SCK1, SCK2↑) t SSSK 80 ns SI1, SI2 hold time (vs. SCK1, SCK2↑) t HSSK 80 ns SCK1, SCK2↓→SO1, SO2 output delay time t DSBSK R = 1 kΩ, C = 100 pF 0 150 ns MIN. MAX. Unit Remarks 1. TSFT is a value set in software. The minimum value is tCYK × 8. 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) Other Operations (TA = –40 to +125 ˚C, VDD = 4.5 to 5.5 V, VSS = 0 V) Parameter Symbol Conditions NMI high, low-level width t WNIH , t WNIL 10 µs INTP0-INTP6 high, low-level width t WITH, t WITL 4 t CYSMP TI2, TI3 high, low-level width t WTIH , t WTIL 4 t CYSMP RESET high, low-level width t WRSH , t WRSL 10 µs Remarks 1. tCYSMP is a sampling clock set in the noise protection control register (NPC) in software. When NIn = 0, tCYSMP = tCYK When NIn = 1, tCYSMP = tCYK × 4 2. tCYK = 1/fCLK (fCLK is internal system clock frequency) 3. NIn: Bit n of NPC (n = 0-6) AC Timing Test Point VDD 0.8 VDD or 2.2 V Test point 0.8 V 0.8 VDD or 2.2 V 0.8 V 0V Data Sheet U13121EJ1V1DS 73 µPD784044(A), 784046(A) (3) Electrical specifications of µPD784044(A2), 784046(A2) (6/6) AD Converter Characteristics (TA = –40 to +125 ˚C, VDD = 4.5 to 5.5 V, VSS = AVSS = 0 V, VDD – 0.5 V ≤ AVDD ≤ VDD) Parameter Symbol Conditions Resolution Total MIN. TYP. MAX. 10 error Note Unit bit 4.5 V ≤ AV REF ≤ AV DD ±0.5 %FSR 3.4 V ≤ AV REF < 4.5 V ±0.7 %FSR ±1/2 LSB Quantization error Conversion time t CONV 169 t CYK Sampling time t SAMP 20 t CYK Zero-scale Full-scale error Note error Note Nonlinearity error Note 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±3.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±3.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB 4.5 V ≤ AV REF ≤ AV DD ±1.5 ±2.5 LSB 3.4 V ≤ AV REF < 4.5 V ±1.5 ±4.5 LSB –0.3 AV REF +0.3 V 3.4 AV DD V Analog input voltage V IAN A/D converter reference input voltage AV REF AV REF current AI REF 3.0 4.0 mA AV DD supply current AI DD 2.0 6.0 mA A/D converter data retention current AI DDDR AV DDDR = 2.5 V 2 100 µA AV DDDR = 5 V ± 10% 10 1000 µA Note STOP mode The quantization error is excluded. Remark tCYK = 1/fCLK (fCLK is internal system clock frequency). 74 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) Read Operation (8 bits) tCYK (CLK) AD8-AD15 (Output) High-order address tDAID tSAST AD0-AD7 (Input/output) Hi-Z High-order address Hi-Z Low-order address (output) Data (input) tWSTH Hi-Z Low-order address (output) Hi-Z tHRID ASTB (Output) tHSTA tFRA RD (Output) tDSTR tDRID tDRA tDAR tWRL tDSTWTH tHSTWT tDSTWT tDRWT tHRWT tDRWTH tDAWT WAIT (Input) Data Sheet U13121EJ1V1DS 75 µPD784044(A), 784046(A) Write Operation (8 bits) tCYK (CLK) AD8-AD15 (Output) AD0-AD7 (Output) High-order address tSAST Low-order address (Output) High-order address Undefined Data (Output) tHWOD tWSTH ASTB (Output) tDWST tHSTA LWR (Output) tDSTW tDWOD tDAW tSODW tWWL tDSTWTH tHSTWT tDSTWT tDAWT tHWWT tDWWTH tDWWT WAIT (Input) 76 Data Sheet U13121EJ1V1DS Low-order address (Output) µPD784044(A), 784046(A) Read Operation (16 bits) tCYK (CLK) tDAID tSAST AD8-AD15 AD0-AD7 (Input/output) Hi-Z Hi-Z Address (Output) Data (Input) tWSTH Hi-Z Address (Output) Hi-Z tHRID ASTB (Output) tHSTA tFRA RD (Output) tDSTR tDRA tDRID tDAR tWRL tDSTWTH tHSTWT tDSTWT tDRWT tHRWT tDRWTH tDAWT WAIT (Input) Data Sheet U13121EJ1V1DS 77 µPD784044(A), 784046(A) Write Operation (16 bits) tCYK (CLK) AD8-AD15 AD0-AD7 (Output) tSAST Address (Output) Undefined Data (Output) tHWOD tWSTH ASTB (Output) tDWST tHSTA HWR, LWR (Output) tDSTW tDWOD tDAW tSODW tWWL tDSTWTH tHSTWT tDSTWT tDAWT tHWWT tDWWTH tDWWT WAIT (Input) 78 Data Sheet U13121EJ1V1DS Address (Output) µPD784044(A), 784046(A) Serial Operation tCYSK tWSKH tWSKL SCK1, SCK2 tDSBSK SO1, SO2 SI1, SI2 tSSSK tHSSK Interrupt Input Timing tWNIH tWNIL 0.8 VDD NMI 0.8 V tWITH tWITL 0.8 VDD INTP0-INTP6 0.8 V Reset Input Timing tWRSH tWRSL 0.8 VDD RESET 0.8 V Timer Input Timing tWTIH tWTIL 0.8 VDD TI2, TI3 0.8 V Data Sheet U13121EJ1V1DS 79 µPD784044(A), 784046(A) 14. PACKAGE DRAWING 80 PIN PLASTIC QFP (14x14) A B 41 40 60 61 detail of lead end C D S R Q 21 20 80 1 F J G I H M K P M N L NOTE ITEM Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 17.2±0.4 0.677±0.016 B 14.0±0.2 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.2±0.4 0.677±0.016 F 0.825 0.032 G 0.825 0.032 H 0.30±0.10 0.012 +0.004 –0.005 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6±0.2 L 0.8±0.2 M 0.15 +0.10 –0.05 0.063±0.008 0.031 +0.009 –0.008 0.006 +0.004 –0.003 N 0.10 0.004 P 2.7±0.1 0.106 +0.005 –0.004 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. S80GC-65-3B9-5 Remark The package dimensions and materials of ES versions are the same as those of mass-production versions. 80 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) 15. RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the conditions recommended below. For details of soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, please contact your NEC representative. Table 15-1. Surface-Mount Type Soldering Conditions µ PD784044GC(A)-×××-3B9 : 80-pin plastic QFP (14 × 14 mm) µ PD784044GC(A1)-×××-3B9 : 80-pin plastic QFP (14 × 14 mm) µ PD784044GC(A2)-×××-3B9 : 80-pin plastic QFP (14 × 14 mm) Soldering Method Soldering Conditions Infrared reflow Package peak temperature: 235 ˚C, Time: 30 sec. max. (210 ˚C min.), Number of times: 3 max. Partial heating Pin temterature: 300 ˚C max., 3 sec. max. (per side of device) Caution Recommended Condition Symbol IR35-00-3 – The µPD784046(A), (A1), and (A2) are under development. Therefore, the soldering conditions for the µPD784046(A), (A1), and (A2) are undefined. Data Sheet U13121EJ1V1DS 81 µPD784044(A), 784046(A) APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for developing systems using the µ PD784046(A). Refer to (5) Cautions when the development tools are used. (1) Language processing software RA78K4 78K/IV series common assembler package CC78K4 78K/IV series common C compiler package DF784046 Device file for the µ PD784046 subseries CC78K4-L 78K/IV series common C compiler library source file (2) Flash memory writing tools Flashpro II (Part number: FL-PR2) Dedicated flash programmer for microcomputers incorporating flash memory FA-80GC Adapter for flash memory writing (3) Debugging tools • When using the IE-78K4-NS in-circuit emulator IE-78K4-NS Note 78K/IV series common in-circuit emulator IE-70000-MC-PS-B Power supply unit for IE-78K4-NS IE-70000-98-IF-C Note Interface adapter necessary when a PC-9800 series computer (except notebook-type personal computer) is used as host machine IE-70000-CD-IF Note PC card and interface cable necessary when a PC-9800 series notebook-type personal computer is used as host machine IE-70000-PC-IF-C Note Interface adapter necessary when an IBM PC/ATTM or a compatible machine is used as host machine IE-784046-NS-EM1 Note Emulation board for emulating the µ PD784046 subseries NP-80GC Emulation probe for 80-pin plastic QFP (GC-3B9 type) EV-9200GC-80 Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-3B9 type) ID78K4-NS Note Integrated debugger for IE-78K4-NS SM78K4 78K/IV series common system simulator DF784046 Device file for the µ PD784046 subseries Note 82 Under development Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) • When using the IE-784000-R in-circuit emulator IE-784000-R 78K/IV series common in-circuit emulator IE-70000-98-IF-B IE-70000-98-IF-C Note Interface adapter necessary when a PC-9800 series computer (except notebook-type personal computer) is used as host machine IE-70000-98N-IF Interface adapter and cable necessary when a PC-9800 series notebook-type personal computer is used as host machine IE-70000-PC-IF-B Interface adapter necessary when an IBM PC/AT or a compatible machine is used IE-70000-PC-IF-C Note as host machine IE-78000-R-SV3 Interface adapter and cable necessary when an EWS is used as host machine IE-784000-R-EM 78K/IV series common emulation board IE-784046-NS-EM1 Note IE-784046-R-EM1 Emulation board for emulating the µ PD784046 subseries IE78K4-R-EX2 Note Emulation probe conversion board necessary when the IE-784046-NS-EM1 is used in the IE-784000-R. Not necessary when the IE-784046-R-EM1 is used. EP-78230GC-R Emulation probe for 80-pin plastic QFP (GC-3B9 type) EV-9200GC-80 Socket to be mounted on the board of the target system made for the 80-pin plastic QFP (GC-3B9 type) ID78K4 Integrated debugger for IE-784000-R SM78K4 78K/IV series common system simulator DF784046 Device file for the µ PD784046 subseries Note Under development (4) Real-time OS RX78K/IV Real-time OS for 78K/IV series MX78K4 OS for 78K/IV series Data Sheet U13121EJ1V1DS 83 µPD784044(A), 784046(A) (5) Cautions when the development tools are used • The ID-78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784046. • The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784046. • Flashpro II, FA-80GC, and NP-80GC are product of Naito Densei Machida Mfg. Co., Ltd. (TEL: (044)8223813). Contact an NEC distributor when purchasing these products. • Host machines and OSs compatible with the software are as follows: Host Machine [OS] PC PC-9800 Series [Windows TM ] IBM PC/AT and compatible machines [Japanese/English Windows] Software RA78K4 Note CC78K4 Note ID78K4-NS EWS HP9000 series 700 TM [HP-UX TM] SPARCstation TM [SunOS TM] NEWS TM (RISC) [NEWS-OS TM ] – ID78K4 SM78K4 – RX78K/IV Note MX78K4 Note Note 84 DOS based software Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) APPENDIX B. RELATED DOCUMENTS Device-related documents Document Name Document No. µPD784044(A), 784046(A) Data Sheet This document µPD78F4046 Preliminary Product Information U11447E µPD784046 Subseries User’s Manual - Hardware U11515E 78K/IV Series User’s Manual - Instruction U10905E 78K/IV Series Application Note - Software Basics U10095E Development tool-related documents (User’s Manuals) Document Name RA78K4 Assembler Package CC78K4 C Compiler Document No. Operation U11334E Language U11162E Structured Assembler Preprocessor U11743E Operation U11572E Language U11571E IE-78K4-NS U13356E IE-784000-R U12903E IE-784046-NS-EM1 U13744E IE-784046-R-EM1 U11677E EP-78230 EEU-1515 SM78K4 System Simulator Windows Based Reference U10093E SM78K Series System Simulator External Part User Open Interface Specifications U10092E ID78K4-NS Integrated Debugger Reference U12796E ID78K4 Integrated Debugger Windows Based Reference U10440E Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system. Data Sheet U13121EJ1V1DS 85 µPD784044(A), 784046(A) Embedded software-related documents (User’s Manual) Document Name 78K/IV Series Real-Time OS 78K/IV Series OS, MX78K4 Document No. Fundamental U10603E Installation U10604E Fundamental U11779E Other documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability and Quality Control C10983E Guide to Prevent Damages for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system. 86 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) [MEMO] Data Sheet U13121EJ1V1DS 87 µPD784044(A), 784046(A) [MEMO] 88 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet U13121EJ1V1DS 89 µPD784044(A), 784046(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 90 Data Sheet U13121EJ1V1DS µPD784044(A), 784046(A) IEBus is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. Some of related document may be preliminary, but is not marked as such. Please keep this in mind as you refer to this information The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. Data Sheet U13121EJ1V1DS 91 µPD784044(A), 784046(A) • The information in this document is current as of March, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. 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(Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4