NEC UPD78368A

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78363A,78365A,78366A,78368A
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
µPD78366A is provided with a high-speed, high-performance CPU and powerful operation functions. Unlike the
existing µPD78328, µPD78366A is also provided with a high-resolution PWM signal output function which
substantially contributes to improving the performance of the inverter control.
A PROM model, µPD78P368A, is also available.
Detailed functions, etc. are described in the following user’s manual. Be sure to read the manual to design systems.
µPD78366A User’s Manual Hardware: U10205E
µPD78356 User’s Manual
: U12117E
FEATURES
• Internal 16-bit architecture, external 8-bit data bus
• High-speed processing by pipeline control method and high- speed operating clock
• Minimum instruction execution time: 125 ns (internal clock: at 16 MHz, external clock: 8 MHz)
•
•
•
•
•
Real-time pulse unit for inverter control
10-bit resolution A/D converter: 8 channels
8-/9-/10-/12-bit resolution variable PWM signal output function: 2 channels
Powerful serial interface: 2 channels
Internal memory:
ROM: none (µPD78365A)
24K bytes (µPD78363A)
32K bytes (µPD78366A)
48K bytes (µPD78368A)
RAM: 768 bytes (µPD78363A)
2K bytes (µPD78365A, 78366A, 78368A)
APPLICATION EXAMPLES
• Inverter air conditioner
• Factory automation fields, such as industrial robots and machine tools.
ORDERING INFORMATION
Part Number
µPD78363AGF-×××-3B9
Package
Internal ROM
80-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD78365AGF-3B9
80-pin plastic QFP (14 × 20 mm)
None
µPD78366AGF-×××-3B9
80-pin plastic QFP (14 × 20 mm)
Mask ROM
µPD78368AGF-×××-3B9
80-pin plastic QFP (14 × 20 mm)
Mask ROM
Remark
××× indicates a ROM code suffix.
Unless otherwise specified, the functions and performances of the µPD78366 are described throughout this document.
The information in this document is subject to change without notice.
Document No. U11109EJ2V0DS00 (2nd edition)
Date Published September 1997 N
Printed in Japan
The mark
shows major revised points.
©
©
1995
1995
µPD78363A, 78365A, 78366A, 78368A
78K/III Series Product Development
µPD78372 subseries
Reinforced timer,
A/D added
µPD78366A subseries
(for control application
in automotive appliance)
Pulse output function
for inverter control,
expanded ROM, RAM
µPD78363A
µPD78365A
µPD78366A
µPD78368A
µPD78P368A
µPD78361A
µPD78362A
µPD78P364A
(for inverter)
µPD78356 subseries
(for camera, HDD)
µPD78352A subseries
A/D, D/A relative instruction
added, expanded ROM, RAM
(for HDD)
High-performance CPU,
sum-of-products instruction added
Reinforced timer and
A/D, expanded ROM
and RAM
µ PD78334 subseries
(for control application in OA and FA fields)
µPD78322 subseries
High-speed, multi-function,
reinforced interrupt,
10-bit A/D
(for control application in OA and FA fields)
µ PD78312A subseries
(for control application in OA and FA fields)
2
Pulse output function
for inverter control
µPD78328 subseries
(for inverter)
µPD78363A, 78365A, 78366A, 78368A
PIN CONFIGURATION (TOP VIEW)
• 80-pin plastic QFP (14 × 20 mm)
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P90/RD
P91/WR
P92
P93
ASTB
P80/TO00
P81/TO01
P82/TO02
P83/TO03
P84/TO04
P85/TO05
µPD78363AGF-×××-3B9, 78365AGF-3B9, 78366AGF-×××-3B9, 78368AGF-×××-3B9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VSS
1
64
P52/A10
P00/RTP0
2
63
P51/A9
P01/RTP1
3
62
P50/A8
P02/RTP2
4
61
P47/AD7
P03/RTP3
5
60
P46/AD6
P04/PWM0
6
59
P45/AD5
P05/TCUD/PWM1
7
58
P44/AD4
P06/TIUD/TO40
8
57
P43/AD3
P07/TCLRUD
WDTO
9
56
P42/AD2
10
55
P41/AD1
IC
11
54
P40/AD0
VDD
12
53
VSS
VSS
13
52
VDD
X1
14
51
AV DD
X2
15
50
AV REF
MODE1
16
49
P77/ANI7
RESET
17
48
P76/ANI6
P30/TXD0
18
47
P75/ANI5
P31/RXD0
19
46
P74/ANI4
P32/SO/SB0
20
45
P73/ANI3
P33/SI/SB1
21
44
P72/ANI2
P34/SCK
22
43
P71/ANI1
P35/TX D1
23
42
P70/ANI0
P36/RX D1
24
41
AV SS
P25/INTP4
P24/INTP3/TI
P23/INTP2
P22/INTP1
P21/INTP0
MODE0
P20/NMI
VSS
P17
P16
P15
P14
P13
P12
P11
P10
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Caution Connect the IC pin directly to VSS.
Remark ××× indicates a ROM code suffix
3
µPD78363A, 78365A, 78366A, 78368A
P00-P07
: Port0
P10-P17
: Port1
P20-P25
: Port2
P30-P36
: Port3
P40-P47
: Port4
P50-P57
: Port5
P70-P77
: Port7
P80-P85
: Port8
P90-P93
: Port9
RTP0-RTP3
: Real-time Port
NMI
: Nonmaskable Interrupt
INTP0-INTP4
: Interrupt From Peripherals
TO00-TO05, TO04 : Timer Output
4
TI
: Timer Input
TIUD
: Timer Input Up Down Counter
TCUD
: Timer Control Up Down Counter
TCLRUD
: Timer Clear Up Down Counter
ANI0-ANI7
: Analog Input
TXD0, TXD1
: Transmit Data
RXD0, RXD1
: Receive Data
SI
: Serial Input
SO
: Serial Output
SB0, SB1
: Serial Bus
SCK
: Serial Clock
PWM0, PWM1
: Pulse Width Modulation Output
WDTO
: Watchdog Timer Ouput
MODE0, MODE1
: Mode
AD0-AD7
: Address/Data Bus
A8-A15
: Address Bus
ASTB
: Address Strobe
RD
: Read Strobe
WR
: Write Strobe
RESET
: Reset
X1, X2
: Crystal
AV DD
: Analog VDD
AV SS
: Analog VSS
AV REF
: Analog Reference Voltage
VDD
: Power Supply
VSS
: Ground
IC
: Internally Connected
µPD78363A, 78365A, 78366A, 78368A
FUNCTIONAL OUTLINE
Item
Product name
µPD78365A
ROM
24K bytes
None
RAM
768 bytes
2K bytes
Memory space
64K bytes (externally expandable)
General-purpose registers
8 bits × 16 × 8 banks
Number of basic instructions
115
Instruction set
•
•
•
•
•
•
I/O lines
µPD78368A
µPD78366A
125 ns (internal clock: 16 MHz, external clock: 8 MHz)
Minimum instruction
execution time
Internal memory
µPD78363A
32K bytes
48K bytes
16-bit transfer/operation
Multiplication/division (16 bits × 16 bits, 32 bits ÷ 16 bits)
Bit manipulation
String
Sum-of-products operation (16 bits × 16 bits + 32 bits)
Relative operation
Input
14 (of which 8 are shared with analog input)
I/O
49
31
49
Real-time pulse unit
• 16-bit timer × 1
10-bit dead time timer × 3
16-bit compare register × 4
2 kinds of output mode can be selected
Mode 0, set-reset output: 6 channels
Mode 1, buffer output: 6 channels
• 16-bit timer × 1
16-bit compare register × 1
• 16-bit timer × 1
16-bit capture register × 1
16-bit capture/compare register × 1
• 16-bit timer × 1
16-bit capture register × 2
16-bit capture/compare register × 1
• 16-bit timer × 1
16-bit compare register × 2
16-bit resolution PWM output: 1 channel
Real-time output port
Pulse outputs associated with real-time pulse unit: 4 lines
PWM unit
8-/9-/10-/12-bit resolution variable PWM output: 2 channels
A/D converter
10-bit resolution, 8 channels
Serial interface
Dedicated baud rate generator
UART (w/pin selection function):
Clocked serial interface/SBI:
1 channel
1 channel
Interrupt function
• External: 6, internal: 14 (of which 2 are multiplexed with external)
• 4 priority levels can be specified through software
• 3 types of interrupt processing modes selectable
(vectored interrupt, macro service, and context switching)
Package
80-pin plastic QFP (14 × 20 mm)
Others
• Watchdog timer
• Standby function (HALT and STOP modes)
5
µPD78363A, 78365A, 78366A, 78368A
DIFFERENCES BETWEEN µPD78363A, 78365A, 78366A, AND 78368A
Item
Product name
µPD78363A
µPD78366A
µPD78368A
48K bytes
µPD78365A
ROM
24K bytes
32K bytes
None
RAM
786 bytes
2K bytes
Input
14 (of which 8 are multiplexed with analog input)
I/O
49
31
Can be set in input or output mode in units
of 8 bits. In external memory expansion
mode, this port functions as multiplexed
address/data bus (AD0-AD7).
Always functions as multiplexed address/
data bus (AD0-AD7).
Can be set in input or output mode in
1-bit units. In external memory expansion
mode, this port functions as address bus
(A8-A15).
Always functions as address bus (A8-A15)
Can be set in input or output mode in
1-bit units. In external memory expansion
mode, P90 outputs RD strobe signal, and
P91 outputs WR strobe signal.
P90 always functions as RD strobe signal
output pin, and P91 always functions as WR
strobe signal output pin. P92 and P93
function as I/O port lines.
Memory expansion
mode register (MM)
Sets port 4 in input or output mode in units
of 8 bits. In external memory expansion
mode, sets memory expansion width of ports
4 and 5.
Always fixed to external memory expansion
mode.
Port 5 mode
register (PM5)
Sets port 5 in input or output mode in
1-bit units.
None
Setting of
MODE0, MODE1
• In ordinary operation mode:
MODE0, 1 = LL
• Always set as follows:
MODE0, 1 = HH
Internal ROM
I/O lines
Port 4 (P40-P47)
Port 5 (P50-P57)
Port 9 (P90-P93)
• In ROM-less mode:
MODE0, 1 = HH
6
NMI
5
INTP
5
PROGRAMMABLE
INTERRUPT
CONTROLLER
4
BCU
X1
MAIN RAM
X2
RESET
GENERAL
REGISTERS
128 × 8
&
DATA
MEMORY
128 × 8
ASTB
SYSTEM
CONTROL
ROM
24K × 8
32K × 8
48K × 8
ALU
7
TIMER/COUNTER
UNIT
(REAL-TIME
PULSE UNIT)
TCUD
MICRO ROM
PERIPHERAL
RAM
512 × 8
1792 × 8
MODE1
MODE0
BUS
CONTROL
8
A8-A15
&
8
AD0-AD7
PREFETCH
CONTROL
TCLRUD
SCK
SO/SB0
SI/B1
TX D
RX D
2
SERIAL
INTERFACE
(SBI)
(UART)
A/D
CONVERTER
WATCHDOG
TIMER
PORT
2
6
8
8
8
7
6
8
8
P7
P6
P5
P4
P3
P2
P1
P0
P8
VDD
VSS
Remark The internal ROM and RAM capacities differ depending on the product.
2
4
WDTO
PWM
AV DD
AV SS
AV REF
INTP2
REAL-TIME
OUTPUT PORT
ANI
4
4
2
8
RTP
RWM
7
µPD78363A, 78365A, 78366A, 78368A
TIUD
MICRO
SEQUENCE
CONTROL
TI
RD
WR
&
&
TO
BLOCK DIAGRAM
ROM/RAM
EXU
µPD78363A, 78365A, 78366A, 78368A
CONTENTS
1.
2.
3.
PIN FUNCTIONS ................................................................................................................................... 10
1.1
PORT PINS ..................................................................................................................................... 10
1.2
PINS OTHER THAN PORT PINS .................................................................................................. 11
1.3
PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ....................................................... 13
CPU ARCHITECTURE ............................................................................................................ 15
2.1
MEMORY SPACE ........................................................................................................................... 15
2.2
DATA MEMORY ADDRESSING .................................................................................................... 18
2.3
PROCESSOR REGISTERS ........................................................................................................... 20
2.3.1
Control Registers ................................................................................................................. 21
2.3.2
General-Purpose Registers ..................................................................................................22
2.3.3
Special Function Registers (SFR) ........................................................................................23
FUNCTIONAL BLOCKS........................................................................................................... 29
3.1
EXECUTION UNIT (EXU) ............................................................................................................... 29
3.2
BUS CONTROL UNIT (BCU) ......................................................................................................... 29
3.3
ROM/RAM ....................................................................................................................................... 29
3.4
PORT FUNCTIONS ........................................................................................................................ 30
3.5
CLOCK GENERATOR CIRCUIT ................................................................................................... 32
3.6
REAL-TIME PULSE UNIT (RPU) .................................................................................................. 34
3.7
REAL-TIME OUTPUT PORT (RTP) .............................................................................................. 42
3.8
A/D CONVERTER .......................................................................................................................... 43
3.9
SERIAL INTERFACE ..................................................................................................................... 44
3.10 PWM UNIT ...................................................................................................................................... 46
3.11 WATCHDOG TIMER (WDT) .......................................................................................................... 47
4.
INTERRUPT FUNCTIONS ................................................................................................................... 48
4.1
OUTLINE ......................................................................................................................................... 48
4.2
MACRO SERVICE .......................................................................................................................... 49
4.3
CONTEXT SWITCHING ................................................................................................................. 52
4.3.1
Context Switching Function by Interrupt Request ................................................................ 52
4.3.2
Context Switching Function by BRKCS Instruction ..............................................................53
4.3.3
Restoration from Context Switching .....................................................................................53
5.
EXTERNAL DEVICE EXPANSION FUNCTION ............................................................................. 54
6.
STANDBY FUNCTIONS ...................................................................................................................... 55
7.
RESET FUNCTION ............................................................................................................................... 56
8.
INSTRUCTION SET .............................................................................................................................. 57
9.
EXAMPLE OF SYSTEM CONFIGURATION ........................................................................... 71
10. ELECTRICAL SPECIFICATIONS ............................................................................................ 72
8
µPD78363A, 78365A, 78366A, 78368A
11. PACKAGE DRAWING .............................................................................................................. 83
12. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 84
APPENDIX A. DIFFERENCES BETWEEN µPD78366A AND µPD78328 ................................... 85
APPENDIX B. TOOLS ..................................................................................................................... 86
B.1
DEVELOPMENT TOOLS ............................................................................................................... 86
B.2
EMBEDDED SOFTWARE .............................................................................................................. 91
9
µPD78363A, 78365A, 78366A, 78368A
1.
PIN FUNCTIONS
1.1
PORT PINS
Pin name
I/O
P00-P03
P04
P05
I/O
Function
Port 0.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P06
I/O
Port 1.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 2.
6-bit input port.
P21
P22
–
NMI
INTP0
INTP1
Input
INTP2
P24
INTP3/TI
P25
INTP4
Port 3.
7-bit I/O port.
Can be set in input or output mode in 1-bit units.
P30
P31
P32
P33
I/O
TXD0
RXD0
SO/SB0
SI/SB1
P34
SCK
P35
TXD1
P36
RXD1
P40-P47
I/O
Port 4.
8-bit I/O Port.
Can be set in input or output mode in 8-bit units.
AD0-AD7
P50-P57
I/O
Port 5.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
A8-A15
P70-P77
Input
P80-P85
Port 7.
8-bit input port
ANI0-ANI7
I/O
Port 8.
6-bit I/O port.
Can be set in input or output mode in 1-bit units.
TO00-TO05
I/O
Port 9.
4-bit I/O port.
Can be set in input or output mode in 1-bit units.
P90
P91
P92
P93
10
PWM0
TCUD/PWM1
TCLRUD
P20
P23
RTP0-RTP3
TIUD/TO40
P07
P10-P17
Shared by:
RD
WR
–
–
µPD78363A, 78365A, 78366A, 78368A
1.2
PINS OTHER THAN PORT PINS (1/2)
Pin name
I/O
Function
Shared by:
RTP0-RTP3
Output
Real-time output port that outputs pulses in synchronization with trigger
signal from real-time pulse unit.
P00-P03
NMI
INTP0
INTP1
Non-maskable interrupt request input.
P20
External interrupt request input.
P21
P22
Input
INTP2
P23
INTP3
P24/TI
INTP4
P25
External count clock input to timer 1.
TI
TCUD
Input
External count clock input to up/down counter (timer 4).
TCLRUD
TO00-TO05
Count operation selection control signal input to up/down counter (timer
4).
TIUD
Clear signal input to up/down counter (timer 4).
Output
Pulse output from real-time pulse unit.
TXD0
Input
Output
Analog input to A/D converter.
Serial data output of asynchronous serial interface.
Input
Serial data input of asynchronous serial interface.
P07
P80-P85
P70-P77
P30
P31
P36
RXD1
SCK
P06/TO40
P35
TXD1
RXD0
P05/PWM1
P06/TIUD
TO40
ANI0-ANI7
P24/INTP3
I/O
Serial clock input/output of clocked serial interface.
P34
SI
Input
Serial data input of clocked serial interface in 3-line mode.
P33/SB1
SO
Ouput
Serial data output of clocked serial interface in 3-line mode.
P32/SB0
P32/SO
SB0
I/O
SB1
Serial data input/output of clocked serial interface in SBI mode.
P04
PWM0
Output
PWM signal output.
Output
Signal output indicating overflow of watchdog timer (generates nonmaskable interrupt).
–
Multiplexed address/data bus when memory is externally expanded.
P40-P47
Address bus when memory is externally expanded.
P50-P57
PWM1
WDTO
AD0-AD7
I/O
A8-A15
Outputs timing signal at which address information output from AD0-AD7
and A8-A15 pins to access external memory is to be latched.
ASTB
RD
WR
P33/SI
Output
P05/TCUD
–
Read strobe signal output to external memory.
P90
Write strobe signal output to external memory.
P91
11
µPD78363A, 78365A, 78366A, 78368A
1.2
PINS OTHER THAN PORT PINS (2/2)
Pin name
I/O
Shared by:
Input
Control signal input to set operation mode. With µPD78363A, 78366A, and
78368A MODE0 and MODE1 are usually connected to VSS. With µPD78365A,
MODE0 and MODE1 are always connected to V DD.
–
RESET
Input
System reset input
–
X1
Input
–
X2
–
Crystal oscillator connecting pins for system clock. If a clock is externally
supplied, input it to pin X1. Leave pin X2 open.
AVREF
Input
A/D converter reference voltage input.
–
AVDD
–
A/D converter analog power supply.
–
AVSS
–
A/D converter GND.
–
VDD
–
Positive power supply
–
VSS
–
GND
–
IC
–
Internally connected. Connect this pin to VSS.
–
MODE0
MODE1
12
Function
µPD78363A, 78365A, 78366A, 78368A
1.3
PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS
Table 1-1 shows the I/O circuit types of the respective pins, and recommended connections of the unused
pins. Figure 1-1 shows the circuits of the respective pins.
Table 1-1. Pin I/O Circuit Type and Recommended Connections of Unused Pins
Pin
I/O circuit type
Recommended connections
5-A
Input : Independently connect to VDD or VSS through resistor
Output : Leave unconnected
P00/RTP0-P03/RTP3
P04/PWM0
P05/TCUD/PWM1
P06/TIUD/TO40
P07/TCLRUD
P10-P17
P20/NMI
2
P21/INTP0
P22/INTP1
Connect to VSS
P23/INTP2
2-A
P24/INTP3/TI
P25/INTP4
P30/TXD0
5-A
P31/RXD0
P32/SO/SB0
P33/SI/SB1
8-A
P34/SCK
Input : Independently connect to VDD or VSS through resistor
Output : Leave unconnected
P35/TXD1
P36/RXD1
5-A
P40/AD0-P47/AD7
P50/A8-P57/A15
P70/ANI0-P77/ANI7
9
Connect to VSS
P80/TO00-P85/TO05
P90/RD
5-A
P91/WR
Input : Independently connect to VDD or VSS through resistor
Output : Leave unconnected
P92, P93
ASTB
5
WDTO
19
MODE0, MODE1
1
RESET
2
IC
–
Connect to VSS
AVREF, AVSS
AVDD
Connect to VSS
–
Connect to VDD
Connect to VSS
13
µPD78363A, 78365A, 78366A, 78368A
Figure 1-1. Pin I/O Circuits
Type 1
VDD
Type 5-A
VDD
Pull-up
enable
P-ch
P-ch
IN
N-ch
Data
VDD
P-ch
Output
disable
N-ch
IN/OUT
Input
enable
Type 2
Type 8-A
VDD
Pull-up
enable
IN
Schmitt trigger input with hysteresis characteristics
Type 2-A
P-ch
Data
VDD
P-ch
Output
disable
N-ch
IN/OUT
Type 9
Comparator
VDD
IN
Pull-up
enable
P-ch
P-ch
N-ch
+
–
Vref
(Threshold voltage)
IN
Input
enable
Schmitt trigger input with hysteresis characteristics
Type 5
Type 19
VDD
Data
Output
disable
Intput
enable
14
P-ch
IN/OUT
OUT
N-ch
N-ch
µPD78363A, 78365A, 78366A, 78368A
2.
CPU ARCHITECTURE
2.1
MEMORY SPACE
The µPD78366A can access a memory space of 64K bytes. Figures 2-1 through 2-3 show the memory map.
Figure 2-1. Memory Map (µPD78368A)
MODE0, 1 = LL
FFFFH
FF00H
Special function register
(SFR)
(256 × 8)
FEFFH
Main RAM
(256 × 8)
MODE0, 1 = HH
⋅ ROM-less mode
FEFFH
FE80H
General-purpose
register (128 × 8)
FE25H
FE06H
Macro service
control (32 × 8)
FF00H
Data memory
FDFFH
Peripheral RAM
(1792 × 8)
F700H
F700H
Data area
(768 × 8)
F6FFH
Memory space
(64 K × 8)
BFFFH
Program memory
Data memory
External memory Note
(14080 × 8)
Program area
1000H
0FFFH
0800H
07FFH
C000H
Program area
BFFFH
0080H
007FH
CALLT instruction table area
(64 × 8)
Program memory
Data memory
External memory
(63232 × 8)
CALLF instruction entry area
(2048 × 8)
Internal ROM
(49152 × 8)
0FFFH
0040H
003FH
Vector table area
(64 × 8)
0000H
0000H
0000H
Note Accessed in external memory expansion mode.
Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the
address that specifies the operand must be an even value.
15
µPD78363A, 78365A, 78366A, 78368A
Figure 2-2. Memory Map (µPD78365A, 78366A)
MODE0, 1 = HH
⋅ µ PD78365A
⋅ µ PD78366A in ORM-less mode
MODE0, 1 = LL
( µ PD78366A)
FFFFH
FF00H
Special function register
(SFR)
(256 × 8)
FEFFH
Main RAM
(256 × 8)
FEFFH
FE80H
General-purpose
register (128 × 8)
FE25H
FE06H
Macro service
control (32 × 8)
FF00H
Data memory
FDFFH
Peripheral RAM
(1792 × 8)
F700H
F700H
Data area
(2048 × 8)
F6FFH
Memory space
(64 K × 8)
7FFFH
Program memory
Data memory
External memory Note
(30464 × 8)
Program area
1000H
0FFFH
0800H
07FFH
8000H
Program area
7FFFH
0080H
007FH
CALLT instruction table area
(64 × 8)
Program memory
Data memory
External memory
(63232 × 8)
CALLF instruction entry area
(2048 × 8)
Internal ROM
(32768 × 8)
0FFFH
0040H
003FH
Vector table area
(64 × 8)
0000H
0000H
0000H
Note Accessed in external memory expansion mode.
Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the
address that specifies the operand must be an even value.
16
µPD78363A, 78365A, 78366A, 78368A
Figure 2-3. Memory Map (µPD78363A)
MODE0, 1 = LL
FFFFH
FF00H
Special function register
(SFR)
(256 × 8)
FEFFH
Main RAM
(256 × 8)
MODE0, 1 = HH
⋅ ROM-less mode
FEFFH
FE80H
General-purpose
register (128 × 8)
FE25H
FE06H
Macro service
control (32 × 8)
FF00H
Data memory
FDFFH
Peripheral RAM
(512 × 8)
FC00H
FC00H
Data area
(768 × 8)
FBFFH
Memory space
(64 K × 8)
5FFFH
Program memory
Data memory
External memory Note
(39936 × 8)
Program area
1000H
0FFFH
0800H
07FFH
6000H
Program area
5FFFH
0080H
007FH
CALLT instruction table area
(64 × 8)
Program memory
Data memory
External memory
(64512 × 8)
CALLF instruction entry area
(2048 × 8)
Internal ROM
(24576 × 8)
0FFFH
0040H
003FH
Vector table area
(64 × 8)
0000H
0000H
0000H
Note Accessed in external memory expansion mode.
Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the
address that specifies the operand must be an even value.
17
µPD78363A, 78365A, 78366A, 78368A
2.2
DATA MEMORY ADDRESSING
The µPD78366A is provided with many addressing modes that improve the operability of the memory and
can be used with high-level languages. Especially, an area of addresses F700H-FFFFH (In the µPD78363A,
FC00H-FFFFH) to which the data memory is mapped can be addressed in a mode peculiar to the functions
provided in this area, including special function registers (SFR) and general-purpose registers.
Figure 2-4. Data Memory Addressing (µPD78368A)
FFFFH
FF20H
FF1FH
Special function
register
(SFR)
SFR addressing
FF00H
FEFFH
General-purpose
register
Register addressing
Short direct addressing
FE80H
FE7FH
FE20H
FE1FH
Main RAM
FE00H
FDFFH
Peripheral RAM
F700H
F6FFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Based indexed addressing
(with displacement)
External memory
6C00H
BFFFH
Internal ROM Note
0000H
Note Is external memory in the ROMless mode.
Caution For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the address
that specifies the operand must be an even value.
18
µPD78363A, 78365A, 78366A, 78368A
Figure 2-5. Data Memory Addressing (µPD78365A, 78366A)
FFFFH
FF20H
FF1FH
Special function
register
(SFR)
SFR addressing
FF00H
FEFFH
General-purpose
register
Register addressing
Short direct addressing
FE80H
FE7FH
FE20H
FE1FH
Main RAM
FE00H
FDFFH
Peripheral RAM
F700H
F6FFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Based indexed addressing
(with displacement)
External memory
8000H
7FFFH
Internal ROM Note
0000H
Note Is external memory in the ROMless mode of the µPD78365A or µPD78366A.
Caution For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the address
that specifies the operand must be an even value.
19
µPD78363A, 78365A, 78366A, 78368A
Figure 2-6. Data Memory Addressing (µPD78363A)
FFFFH
FF20H
FF1FH
Special function
register
(SFR)
SFR addressing
FF00H
FEFFH
General-purpose
register
Register addressing
Short direct addressing
FE80H
FE7FH
FE20H
FE1FH
Main RAM
FE00H
FDFFH
Peripheral RAM
FC00H
FBFFH
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Based indexed addressing
(with displacement)
External memory
6000H
5FFFH
Internal ROM Note
0000H
Note Is external memory in the ROMless mode.
Caution For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the address
that specifies the operand must be an even value.
2.3
PROCESSOR REGISTERS
The µPD78366A is provided with the following three types of processor registers:
• Control registers
• General-purpose registers
• Special function registers (SFRs)
20
µPD78363A, 78365A, 78366A, 78368A
2.3.1
Control Registers
(1) Program counter (PC)
This is a 16-bit register that holds an address of the instruction to be executed next.
(2) Program status word (PSW)
This 16-bit register indicates the status of the CPU as a result of instruction execution.
(3) Stack pointer (SP)
This 16-bit register indicates the first address of the stack area (LIFO) of the memory.
(4) CPU control word (CCW)
This 8-bit register is used to control the CPU.
Figure 2-7. Configuration of Control Registers
15
0
PC
PSW
SP
0
7
CCW
Figure 2-8. Configuration of PSW
8
15
UF
PSW
RBS2
RBS1
RBS0
0
0
0
0
0
7
S
Z
UF
RSS
AC
IE
P/V
0
CY
: User flag
RBS0-RBS2: Register bank select flag
S
: Sign flag (MSB of execution result)
Z
: Zero flag
RSS
: Register set select flag
AC
: Auxiliary carry flag
IE
: Interrupt request enable flag
P/V
: Parity/overflow flag
CY
: Carry flag
Figure 2-9. Configuration of CCW
0
7
CCW
0
0
TPF
0
0
0
0
TPF
0
: Table position flag
21
µPD78363A, 78365A, 78366A, 78368A
2.3.2
General-Purpose Registers
The µPD78366A is provided with eight banks of general-purpose registers with one bank consisting of 8
words × 16 bits. Figure 2-10 shows the configuration of the general-purpose register banks. The generalpurpose registers are mapped to an area of addresses FE80H-FEFFH. Each of these registers can be used
as an 8-bit register. In addition, two registers can be used as one 16-bit register pair (refer to Figure 2-11 ).
These general-purpose registers facilitate complicated multitask processing.
Figure 2-10. Configuration of General-Purpose Register Banks
Bank 7
Bank 1
Bank 0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
15
0
Figure 2-11. Processing Bits of General-Purpose Registers
8-bit processing
FEFFH
FE80H
RBNK0
R15
R14
(FH)
RP7
(EH)
RBNK1
R13
R12
(DH)
RP6
(CH)
RBNK2
R11
R10
(BH)
RP5
(AH)
RBNK3
R9
R8
(9H)
RP4
(8H)
RBNK4
R7
R6
(7H)
RP3
(6H)
RBNK5
R5
R4
(5H)
RP2
(4H)
RBNK6
R3
R2
(3H)
RP1
(2H)
(1H)
RP0
(0H)
RBNK7
R1
7
22
16-bit processing
R0
07
0
15
0
µPD78363A, 78365A, 78366A, 78368A
2.3.3
Special Function Registers (SFR)
Special function registers (SFRs) are registers assigned special functions such as mode registers and control
registers for internal peripheral hardware, and are mapped to a 256-byte address space at FF00H through
FFFFH.
Table 2-1 lists the SFRs. The meanings of the symbols in this table are as follows:
• Symbol ................................... Indicates the mnemonic symbol for an SFR.
This mnemonic can be coded in the operand field of an instruction.
• R/W ........................................ Indicates whether the SFR can be read or written.
R/W : Read/write
R
: Read only
W
: Write only
• Bit units for manipulation ...... Indicates bit units in which the SFR can be manipulated. The SFRs that
can be manipulated in 16-bit units can be coded as an sfrp operand.
Specify an even address for these SFRs.
The SFRs that can be manipulated in 1-bit units can be coded as the
operand of bit manipulation instructions.
• On reset ................................. Indicates the status of the register at RESET input.
Cautions 1. Do not access the addresses in the range FF00H through FFFFH to which no special
function register is allocated. If these addresses are accessed, malfunctioning may
occur.
2. Do not write data to the read-only registers. Otherwise, the internal circuit may not
operate normally.
3. When using read data as byte data, process undefined bit(s) first.
4. TOUT and TXS are write-only registers. Do no read these registers.
5. Bits 0, 1, and 4 of SBIC are write-only bits. When these bits are read, they are always
"0".
23
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List of Special Function Registers (1/5)
Address
FF00H
Special function register (SFR)
Port 0
Symbol
Bit units for
manipulation
R/W
P0
R/W
On reset
1 bit
8 bits
16 bits
●
●
–
●
●
–
●
●
–
●
●
–
●
●
–
●
●
–
●
●
–
FF01H
Port 1
P1
FF02H
Port 2
P2
FF03H
Port 3
P3
FF04H
Port 4
P4Note
FF05H
Port 5
P5Note
FF07H
Port 7
P7
FF08H
Port 8
P8
●
●
–
FF09H
Port 9
P9
●
●
–
Compare register 00
CM00
–
–
●
Compare register 01
CM01
–
–
●
Compare register 02
CM02
–
–
●
R
R/W
R
FF10H
FF11H
FF12H
Undefined
FF13H
FF14H
FF15H
R/W
FF16H
Compare register 03
CM03
–
–
●
Buffer register CM00
BFCM00
–
–
●
Buffer register CM01
BFCM01
–
–
●
Buffer register CM02
BFCM02
–
–
●
–
–
●
FF17H
FF18H
FF19H
FF1AH
FF1BH
FF1CH
FF1DH
FF1EH
Timer register 0
TM0
FF20H
Port 0 mode register
PM0
●
●
–
FF21H
Port 1 mode register
PM1
●
●
–
FF23H
Port 3 mode register
PM3
●
●
–
×111 1111B
FF25H
Port 5 mode register
PM5Note
●
●
–
FFH
FF28H
Port 8 mode register
PM8
●
●
–
××11 1111B
FF29H
Port 9 mode register
PM9
●
●
–
×××× 1111B
Reload register
DTIME
–
–
●
Undefined
Timer unit mode register 0
TUM0
●
●
–
R
0000H
FF1FH
R/W
FF2CH
FFH
FF2DH
FF2EH
R/W
FF2FH
00H
Timer unit mode register 1
TUM1
●
●
–
Compare register 10
CM10
–
–
●
Undefined
–
–
●
0000H
FF30H
FF31H
FF32H
Timer register 1
FF33H
Note Not provided for the µPD78365A.
24
TM1
R
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List of Special Function Registers (2/5)
Address
Special function register (SFR)
Symbol
Bit units for
manipulation
R/W
8 bits
16 bits
–
–
●
FF34H
Capture/compare register 20
CC20
R/W
On reset
1 bit
FF35H
Undefined
FF36H
–
–
●
TM2
–
–
●
0000H
BFCM03
–
–
●
Underfined
Capture register 20
CT20
Timer register 2
FF37H
R
FF38H
FF39H
FF3AH
Buffer register CM03
FF3BH
FF3CH
External interrupt mode register 0
INTM0
●
●
–
FF3DH
External interrupt mode register 1
INTM1
●
●
–
FF40H
Port 0 mode control register
PMC0
●
●
–
FF43H
Port 3 mode control register
PMC3
FF44H
Pull-up resistor option register L
PUOL
FF45H
Pull-up resistor option register H
FF48H
●
●
–
●
●
–
PUOH
●
●
–
Port 8 mode control register
PMC8
●
●
–
FF4EH
Sampling control register 0
SMPC0
●
●
–
FF4FH
Sampling control register 1
SMPC1
●
●
–
Capture/compare register 30
CC30
–
–
●
Capture register 30
CT30
–
–
●
Capture register 31
CT31
–
–
●
Timer register 3
TM3
–
–
●
CM40
–
–
●
R/W
FF50H
00H
×000 0000B
00H
××00 0000B
00H
FF51H
FF52H
Undefined
FF53H
FF54H
R
FF55H
FF56H
0000H
FF57H
FF58H
Compare register 40
FF59H
R/W
Undefined
FF5AH
Compare register 41
CM41
–
–
●
FF5BH
FF5CH
Timer register 4
TM4
R
–
–
●
0000H
FF5DH
FF5EH
Timer control register 4
TMC4
R/W
–
●
–
00H
FF5FH
Timer out register
TOUT
W
–
●
–
××01 0101B
FF60H
Real-time output port register
●
●
–
Undefined
FF61H
Real-time output port mode register
●
●
–
RTP
RTPM
R/W
FF62H
Port read control register
FF68H
A/D converter mode register
PRDC
●
●
–
ADM
●
●
–
00H
25
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List of Special Function Registers (3/5)
Address
Special function register (SFR)
Symbol
Bit units for
manipulation
R/W
8 bits
16 bits
FF70H
Slave buffer register 0
SBUF0
●
●
–
FF71H
Slave buffer register 1
SBUF1
●
●
–
FF72H
Slave buffer register 2
SBUF2
●
●
–
FF73H
Slave buffer register 3
SBUF3
●
●
–
FF74H
Slave buffer register 4
SBUF4
●
●
–
FF75H
Slave buffer register 5
SBUF5
●
●
–
FF76H
Master buffer register 0
MBUF0
●
●
–
FF77H
Master buffer register 1
MBUF1
●
●
–
FF78H
Master buffer register 2
MBUF2
●
●
–
FF79H
Master buffer register 3
MBUF3
●
●
–
FF7AH
Master buffer register 4
MBUF4
●
●
–
R/W
Undefined
FF7BH
Master buffer register 5
MBUF5
●
●
–
FF7CH
Timer control register 0
TMC0
●
●
–
FF7DH
Timer control register 1
TMC1
●
●
–
FF7EH
Timer control register 2
TMC2
●
●
–
FF7FH
Timer control register 3
TMC3
●
●
–
FF80H
Clocked serial interface mode register
CSIM
●
●
–
FF82H
Serial bus interface control register
SBIC
●
●
–
FF84H
Baud rate generator control register
BRGC
●
●
–
FF85H
Baud rate generator compare register
BRG
FF86H
Serial I/O shift register
SIO
FF88H
Asynchronous serial interface mode register
ASIM
FF8AH
Asynchronous serial interface status register
ASIS
R/WNote
R/W
R
–
●
–
●
–
●
●
–
80H
●
●
–
00H
–
●
–
–
●
–
Undefined
FF8CH
Serial receive buffer: UART
RXB
FF8EH
Serial transfer shift register: UART
TXS
FFA0H
PWM control register 0
PWMC0
●
●
–
FFA1H
PWM control register 1
PWMC1
●
●
–
FFA2H
PWM register 0L
PWM0L
●
●
–
PWM register 0
PWM0
–
–
●
W
R/W
FFA3H
Note Bits 7 and 5
: read/write
Bits 6, 3, and 2 : read-only
Bits 4, 1, and 0 : write-only
00H
●
FFA2H
26
On reset
1 bit
Undefined
00H
Undefined
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List of Special Function Registers (4/5)
Address
FFA4H
Special function register (SFR)
PWM register 1L
Symbol
R/W
PWM1L
FFA4H
Bit units for
manipulation
8 bits
16 bits
●
●
–
–
–
●
●
●
–
R/W
PWM register 1
PWM1
On reset
1 bit
Undefined
FFA5H
FFA8H
In-service priority register
FFAAH
Interrupt mode control register
IMC
●
●
–
80H
FFACH
Interrupt mask register 0L
MK0L
●
●
–
FFH
Interrupt mask register 0
MK0
–
–
●
FFFFH
Interrupt mask register 0H
MK0H
●
●
–
FFH
A/D conversion result register 0
ADCR0
–
–
●
ADCR0H
–
●
–
ADCR1
–
–
●
ADCR1H
–
●
–
ADCR2
–
–
●
ADCR2H
–
●
–
ADCR3
–
–
●
ADCR3H
–
●
–
ADCR4
–
–
●
ADCR4H
–
●
–
ADCR5
–
–
●
ADCR5H
–
●
–
ADCR6
–
–
●
ADCR6H
–
●
–
ADCR7
–
–
●
ISPR
FFACH
R
R/W
00H
FFADH
FFADH
FFB0H
FFB1H
FFB1H
A/D conversion result register 0H
FFB2H
A/D conversion result register 1
FFB3H
FFB3H
A/D conversion result register 1H
FFB4H
A/D conversion result register 2
FFB5H
FFB5H
A/D conversion result register 2H
FFB6H
A/D conversion result register 3
FFB7H
R
FFB7H
A/D conversion result register 3H
FFB8H
A/D conversion result register 4
Undefined
FFB9H
FFB9H
A/D conversion result register 4H
FFBAH
A/D conversion result register 5
FFBBH
FFBBH
A/D conversion result register 5H
FFBCH
A/D conversion result register 6
FFBDH
FFBDH
A/D conversion result register 6H
FFBEH
A/D conversion result register 7
FFBFH
FFBFH
A/D conversion result register 7H
ADCR7H
–
●
–
FFC0H
Standby control register
STBCNote
–
●
–
FFC1H
CPU control word
●
●
–
–
●
–
FFC2H
Watchdog timer mode register
CCW
WDMNote
R/W
0000 ×000B
00H
Note Can be written when a special instruction is executed.
27
µPD78363A, 78365A, 78366A, 78368A
Table 2-1. List of Special Function Registers (5/5)
Address
FFC4H
Special function register (SFR)
Memory expansion mode register
Symbol
Bit units for
manipulation
R/W
8 bits
16 bits
MM
●
●
–
Note
PWC
–
–
●
C0AAH
–
●
●
–
Undefined
OVIC3
●
●
–
FFC6H
Programmable wait control register
On reset
1 bit
FFC7H
FFD0H
|
External SFR area
FFDFH
FFE0H
Interrupt control register (INTOV3)
FFE1H
Interrupt control register (INTP0/INTCC30)
PIC0
●
●
–
FFE2H
Interrupt control register (INTP1)
PIC1
●
●
–
FFE3H
Interrupt control register (INTP2)
PIC2
●
●
–
FFE4H
Interrupt control register (INTP3/INTCC20)
PIC3
FFE5H
Interrupt control register (INTP4)
PIC4
FFE6H
Interrupt control register (INTTM0)
FFE7H
●
●
–
●
●
–
TMIC0
●
●
–
Interrupt control register (INTCM03)
CMIC03
●
●
–
FFE8H
Interrupt control register (INTCM10)
CMIC10
●
●
–
FFE9H
Interrupt control register (INTCM40)
CMIC40
●
●
–
FFEAH
Interrupt control register (INTCM41)
CMIC41
●
●
–
FFEBH
Interrupt control register (INTSER)
SERIC
●
●
–
FFECH
Interrupt control register (INTSR)
SRIC
●
●
–
FFEDH
Interrupt control register (INTST)
STIC
●
●
–
FFEEH
Interrupt control register (INTCSI)
CSIIC
●
●
–
FFEFH
Interrupt control register (INTAD)
ADIC
●
●
–
R/W
Note The value of the MW register at reset time differs depending on the product.
µPD78363A
: 60H
µPD78365A, 78366A : 20H
µPD78368A
28
: 00H
43H
µPD78363A, 78365A, 78366A, 78368A
3.
FUNCTIONAL BLOCKS
3.1
EXECUTION UNIT (EXU)
EXU controls address computation, arithmetic and logical operations, and data transfer through microprogram.
EXU has an internal main RAM. This RAM can be accessed by instructions faster than the peripheral RAM.
3.2
BUS CONTROL UNIT (BCU)
BCU starts necessary bus cycles according to the physical address obtained by the execution unit (EXU).If
EXU does not request start of the bus cycle, an address is generated to prefetch an instruction. The prefetched
op code is stored in an instruction queue.
3.3
ROM/RAM
The internal ROM and RAM capacities differ depending on the product.
The µPD78363A has a 24-KB ROM and a 512-B peripheral RAM. The µPD78366A has a 32-KB ROM and
a 1792-B peripheral RAM. The µPD78368A has a 48-KB ROM and a 1792-B peripheral RAM. The µPD78365A
does not have a ROM and only has a 1792-B peripheral RAM.
Access to the ROM can be disabled by using the MODE0 and MODE1 pins, in which case an external memory
of 64 KB can be accessed.
29
µPD78363A, 78365A, 78366A, 78368A
3.4
PORT FUNCTIONS
The µPD78366A is provided with the ports shown in Figure 3-1 for various control operations.
The functions of each port are listed in Table 3-1. These ports function not only as digital ports but also as
input/output lines of the internal hardware.
Figure 3-1. Port Configuration
P00
P50
Port 0
Port 5
P07
P57
P10
P70-P77
Port 1
8
Port 7
P17
P80
P20
Port 8
Port 2
P85
P25
P90
P30
Port 9
P93
Port 3
P36
Port 4
30
8
P40-P47
µPD78363A, 78365A, 78366A, 78368A
Table 3-1. Functions of Each Port
Port
Port 0
Port 1
Port function
8-bit I/O port. Can be set in input or
output mode in 1-bit units.
8-bit I/O port. Can be set in input or
output mode in 1-bit units.
Multiplexed function
In control mode, serves as real-time output port (RTP), or
input operation control signal of real-time pulse unit (RPU)
and output PWM signal.
—
6-bit input port.
Inputs external interrupt and count pulse of real-time pulse
unit (RPU) (fixed to the control mode).
Port 3
7-bit I/O port. Can be set in input or
output in 1-bit units.
In control mode, inputs/outputs signals of serial interfaces
(UART, CSI).
Port 4
8-bit I/O port. Can be set in input or
output mode in 8-bit units.
Address data bus (AD0-AD7) when memory is externally
expanded.
Port 5
8-bit I/O port. Can be set in input or
output mode in 1-bit units.
Address bus (A8-A15) when memory is externally expanded.
Port 7
8-bit input port.
Input analog signals to A/D converter (fixed to the control
mode).
Port 8
6-bit I/O port. Can be set in input or
output mode in 1-bit units.
In control mode, outputs timer of real-time pulse unit (RPU).
Port 9
4-bit I/O port. Can be set in input or
output mode in 1-bit units.
Outputs control signal when memory is externally expanded.
Port 2
31
µPD78363A, 78365A, 78366A, 78368A
3.5
CLOCK GENERATOR CIRCUIT
The clock generator circuit generates and controls the internal system clock (CLK) that is supplied to the CPU.
Figure 3-2. Block Diagram of Clock Generator Circuit
X1
X2
System
cloock
oscillator
circuit
Frequency
divider
Frequency
divider
f XX
or
fX
1/2
PLL
control
circuit
1/2
f CLK
Internal system
clock (CLK)
STOP mode
Remarks 1.
fXX : crystal oscillation frequency
2.
fX : external clock frequency
3.
fCLK : internal system clock frequency
By connecting an 8-MHz crystal resonator across the X1 and X2 pins, an internal system clock of up to 16
MHz (fCLK) can be generated.
The system clock oscillation circuit oscillates by using the crystal resonator connected across the X1 and
X2 pins. It stops oscillation in standby mode.
An external clock can also be input. To do so, input the clock signal to the X1 pin and leave the X2 pin open.
Caution
32
Do not set STOP mode when the external clock is used.
µPD78363A, 78365A, 78366A, 78368A
Figure 3-3. External Circuit of System Clock Oscillator Circuit
(a) crystal oscillator
(b) external clock
µ PD78366A
µ PD78366A
VSS
X1
X1
X2
Open X2
Cautions 1. Wire the portion enclosed by dotted line in Figure 3-3 as follows to avoid adverse
influences due to wiring capacity when using the system clock oscillation circuit.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal line. Make sure that the wiring is not close
to lines through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillation circuit at the same
potential as VSS. Do not ground the circuit to a ground pattern through which a high
current flows.
• Do not extract signals from the oscillator circuit.
2. To input an external clock, do not connect a load such as wiring capacitance to the X2
pin.
33
µPD78363A, 78365A, 78366A, 78368A
3.6
REAL-TIME PULSE UNIT (RPU)
The real-time pulse unit (RPU) can measure pulse intervals and frequencies, and output programmable
pulses (six channels of PWM control signals).
The RPU consists of five 16-bit timers (timers 0 through 4), of which one is provided with a 10-bit dead time
timer, which is ideal for inverter control. In addition, a function to turn off the output by the software or an external
interrupt is also provided.
Each timer has the following features:
• Timer 0 : Controls the PWM period of the TO00 through TO05 pins. In addition, operates as a
general-purpose interval timer. Timer 0 has the following five operation modes:
• General-purpose interval timer mode
• PWM mode 0 (symmetrical triangular wave)
• PWM mode 0 (asymmetrical triangular wave)
• PWM mode 0 (saw-tooth wave)
• PWM mode 1
• Timer 1 : Operates as a general-purpose interval timer.
• Timers 2, 3 : Has a programmable input sampling circuit that rejects the noise of an input signal,
and a capture function.
• Timer 4 : Operates as a general-purpose timer or an up-down counter. When operating as a generalpurpose timer, controls the PWM cycle of the TO40 output pin. Timer 4 has the following
two operation modes:
• General-purpose timer mode
• Up/down counter mode (UDC mode)
34
µPD78363A, 78365A, 78366A, 78368A
The RPU consists of the hardware shown in Table 3-2. Figures 3-4 through 3-12 show the block diagrams
of the respective timers.
Table 3-2. Configuration of Real-Time Pulse Unit (RPU)
Timer register
Timer 0 16-bit timer (TM0)
Timer 1 16-bit timer (TM1)
Timer 2 16-bit timer (TM2)
16-bit compare register (CM00)
Compare
register
coincidence
interrupt
–
16-bit compare register (CM01)
–
16-bit compare register (CM02)
–
16-bit compare register (CM03)
INTCM03
16-bit compare register (CM10)
INTCM10
16-bit capture/compare register (CC20)
INTCC20
Register
16-bit capture register (CT20)
16-bit capture/compare register (CC30)
Timer 3 16-bit timer (TM3)
16-bit capture register (CT30)
16-bit capture register (CT31)
Timer 4 16-bit timer (TM4)
–
Capture
trigger
Timer
output
Timer
clear
–
6
INTCM03
–
–
INTCM10
INTP3
–
INTCC20
–
INTCC30
INTCC30
INTP0
–
INTP1
–
INTP4
16-bit compare register (CM40)
INTCM40
16-bit compare register (CM41)
INTCM41
–
1
TCLRUD
INTCM40
35
µPD78363A, 78365A, 78366A, 78368A
Figure 3-4. Block Diagram of Timer 0 (PWM mode 0 ... symmetrical triangular wave,
asymmetrical triangular wave)
BFCM03
CM03
fCLK
fCLK/2
fCLK/4
fCLK/8
fCLK/16
INTCM03
16
TM0
INTTM0
U/D
16
UP = 0
DOWN = 1
fCLK
DTIME
ALVTO
Output off function
by external interrupt
and software
10
BFCM00
CM00
R
DTM0
Underflow
R
S
S
R
S
BFCM01
CM01
R
DTM1
R
S
R
S
BFCM02
R
DTM2
S
R
R
S
TM0
: Timer register
ALVTO: Bit 2 of TUM0 register
CM00-CM03
: Compare registers
U/D
DTIME
: Reload register
DTM0-DTM2
: Dead time timers
Remark f CLK : internal system clock
36
TO02
(V phase)
TO03
(V phase)
Underflow
S
BFCM00-BFCM03 : Buffer registers
TO01
(U phase)
Underflow
S
CM02
TO00
(U phase)
: Bit 3 of TMC0 register
TO04
(W phase)
TO05
(W phase)
µPD78363A, 78365A, 78366A, 78368A
Figure 3-5. Block Diagram of Timer 0 (PWM mode 0 ... saw-tooth wave)
BFCM03
CM03
fCLK
fCLK/2
fCLK/4
fCLK/8
fCLK/16
16
INTCM03
Clear
TM0
fCLK
DTIME
ALVTO
16
Output off function
by external interrupt
and software
10
BFCM00
CM00
R
DTM0
Underflow
R
S
S
R
S
BFCM01
CM01
R
DTM1
R
S
R
S
BFCM02
R
DTM2
S
R
R
S
: Timer register
CM00-CM03
: Compare registers
TO02
(V phase)
TO03
(V phase)
Underflow
S
TM0
TO01
(U phase)
Underflow
S
CM02
TO00
(U phase)
TO04
(W phase)
TO05
(W phase)
BFCM00-BFCM03 : Buffer registers
DTIME
: Reload register
DTM0-DTM2
: Dead time timers
ALVTO
: Bit 2 of TUM0 register
Remark f CLK : internal system clock
37
µPD78363A, 78365A, 78366A, 78368A
Figure 3-6. Block Diagram of Timer 0 (PWM mode 1)
BFCM03
CM03
16
fCLK
fCLK/2
fCLK/4
fCLK/8
fCLK/16
INTCM03
Clear
TM0
fCLK
DTIME
16
10
6-bit buffer
register
BFCM00
CM00
DTM0
T
Underflow
6-bit buffer
register
MBUF1
SBUF1
MBUF0
SBUF0
MBUF3
SBUF3
MBUF2
BFCM01
CM01
DTM1
T
Underflow
SBUF2
MBUF5
SBUF5
MBUF4
SBUF4
BFCM02
CM02
DTM2
T
Underflow
TOUT
6-bit write-only
register
Output off function
by external interrupt
and software
TO00 TO02 TO04
(U phase) (V phase) (W phase)
TO01 TO03 TO05
(U phase) (V phase) (W phase)
TM0
: Timer register
CM00-CM03
: Compare registers
BFCM00-BFCM03 : Buffer registers
DTIME
: Reload register
DTM0-DTM2
: Dead time timers
Remark f CLK : internal system clock
38
MBUF0-MBUF5 : Master buffer registers
SBUF0-SBUF5 : Slave buffer registers
TOUT
: Timer out register
µPD78363A, 78365A, 78366A, 78368A
Figure 3-7. Block Diagram of Timer 0 (general-purpose interval timer mode)
Master buffer register
(MBUF0)
Compare register
CM03
INTCM03
16
6
Slave buffer register
(SBUF0)
Timer register
TM0
6
Clear
Timer out register
(TOUT)
Output off function by external
interrupt and software
TO00 TO02 TO04
TO01 TO03 TO05
Figure 3-8. Block Diagram of Timer 1
Clear
fCLK/4
fCLK/8
fCLK/16
TI
Timer register
TM1
16
Compare register
CM10
INTCM10
Remark fCLK: internal system clock
39
µPD78363A, 78365A, 78366A, 78368A
Figure 3-9. Block Diagram of Timer 2
Clear
fCLK/22
fCLK/23
fCLK/24
fCLK/25
fCLK/26
fCLK/28
fCLK/29
fCLK/210
4-point sampling
noise rejection
circuit
INTP3
fCLK
fCLK/22
fCLK/23
fCLK/24
fCLK/26
fCLK/27
fCLK/28
CLR2
Timer register TM2
16
Capture/compare
register CC20
INTP3/INTCC20
Capture register CT20
Remark fCLK: internal system clock
Figure 3-10. Block Diagram of Timer 3
Clear
fCLK/22
fCLK/23
fCLK/24
fCLK/25
fCLK/26
fCLK/28
Timer register TM3
CLR3
INTOV3
16
INTP0
4-point sampling
noise rejection
circuit
Capture/compare
register CC30
4-point sampling
noise rejection
circuit
Capture register CT30
INTP1
4-point sampling
noise rejection
circuit
Capture register CT31
INTP4
INTP0/INTCC30
fCLK
fCLK/22
fCLK/23
fCLK/24
INTP1
fCLK
fCLK/22
fCLK/23
fCLK/24
INTP4
fCLK
fCLK/22
fCLK/23
fCLK/24
Remark fCLK: internal system clock
40
µPD78363A, 78365A, 78366A, 78368A
Figure 3-11. Block Diagram of Timer 4 (General-Purpose Timer Mode)
Clear
fCLK
fCLK/2
fCLK/4
fCLK/8
fCLK/16
fCLK/32
Timer register
TM4
INTCM40
16
Compare register
CM40
ALV40
S
Q
TO40
R
Compare register
CM41
INTCM41
Remark fCLK: internal system clock
Figure 3-12. Block Diagram of Timer 4 (UDC Mode)
TCLRUD
Clear
fCLK/4
fCLK/8
fCLK/16
16
TIUD
TCUD
Up/down
detector
OVF
UDF
Timer register
TM4
Pre-set
Compare register
CM40
INTCM40
Compare register
CM41
INTCM41
Remark fCLK: internal system clock
41
µPD78363A, 78365A, 78366A, 78368A
3.7
REAL-TIME OUTPUT PORT (RTP)
The real-time output port is a 4-bit port that can output the contents of the real-time output port register (RTP)
in synchronization with the trigger signal from the real-time pulse unit (RPU). It can output synchronization
pulses of multiple channels.
Also, PWM modulation can be applied to P00-P03.
Figure 3-13. Block Diagram of Real-Time Output Port
Internal bus
4
RTP
INTCM03 (from RPU)
INTCM10 (from RPU)
INTP0/INTCC30 (from RPU)
Software trigger
Output trigger
control circuit
4
RTPM
PWM0
PWM1
PWM signal
control circuit
Output latch
(P03-P00)
P03P02 P01P00
42
µPD78363A, 78365A, 78366A, 78368A
3.8
A/D CONVERTER
The µPD78366A contains a high-speed, high-resolution 10-bit analog-to-digital (A/D) converter (conversion
time 12.6 µs at an internal clock frequency of 16 MHz). Successive approximation type is adopted. This
converter is provided with eight analog input lines (ANI0-ANI7) and can perform various operations as the
application requires, in select, scan, and mixed modes.
When A/D conversion ends, an internal interrupt (INTAD) occurs. This interrupt can start a macro service
that executes automatic data transfer through hardware.
Figure 3-14. Block Diagram of A/D Converter
AV DD
Sample & hold
ANI0
AV REF
ANI1
ANI4
Input curcuit
ANI2
ANI3
Resistor
string
AV SS
Comparator
0
ANI5
9
ANI6
10
SAR (10)
ANI7
10
9
0
ADCR0
ADCR1
INTCM03
INTP2
ADCR2
Controller
ADCR3
(Start trigger)
ADCR4
ADCR5
ADM (8)
ADCR6
ADCR7
8
10
Internal bus
43
µPD78363A, 78365A, 78366A, 78368A
3.9
SERIAL INTERFACE
The µPD78366A is provided with the following two independent serial interfaces:
• Asynchronous serial interface (UART) (with pin selection function)
• Clocked serial interface
• 3-line serial I/O mode
• Serial bus interface mode (SBI mode)
Since the µPD78366A contains a baud rate generator (BRG), any serial transfer rate can be set regardless
of the operating clock frequency. The baud rate generator is a block to generate the shift clock for the transmit/
receive serial interface, and is used commonly with the two channels of the serial interfaces.
The serial transfer rate can be selected in a range of 110 bps to 38.4 Kbps by the mode register.
Figure 3-15. Block Diagram of Asynchronous Serial Interface
Internal bus
ASIM
Receive
RXB
buffer
RXE PS1 PS0 CL SL SPS SCK
SPS
TXD1
SPS
Receive
control
parity
check
1
—
16
44
PE FE OVE
TXS
Transfer
shift
register
INTSER
INTSR
Transfer
control
parity
append
1
—
16
INTST
Selector
TXD0
Receive
shift
register
Selector
RXD1
Selector
ASIS
RXD0
Transfer/
receive
baud rate
generator
output
fCLK/8
µPD78363A, 78365A, 78366A, 78368A
Figure 3-16. Block Diagram of Clocked Serial Interface
Internal bus
8
8
8
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
CSIM CTXE CRXE WUP MOD2 MOD1 MOD0 CLS1 CLS0
RELT
CMDT
MOD1
MOD2
0
7
Selector
SI/SB1
Shift register (SIO)
SO latch
D Q
SO/SB0
Selector
Busy/
acknowledge
detector
circuit
MOD1
MOD2
MOD1
Serial
clock
counter
SCK
WUP
Interrupt
signal
generation
control
circuit
INTCSI
Selector
Bus release/
command/
acknowledge
detector
circuit
Serial clock
control circuit
1/2
Baud rate
generator (BRG)
f CLK/8
f CLK/32
CLS0
CLS1
Figure 3-17. Block Diagram of Baud Rate Generator
Internal bus
7
1
—
2
0
7
0
BRG
BRGC
TMBRG
Prescaler
Coincidence
Clear
f CLK/2
Serial interface
45
µPD78363A, 78365A, 78366A, 78368A
3.10
PWM UNIT
The µPD78366A is provided with two lines that output 8-/9-/10-/12-bit resolution variable PWM signals. The
PWM output can be used as a digital-to-analog conversion output by connecting an external lowpass filter, and
ideal for controlling actuators such as motors.
An output of between 244 Hz and 62.5 kHz can be obtaind, depending on the combination of the count clock
(62.5 ns to 1 µs) and counter bit length (8, 9, 10, or 12) (at an internal clock frequency of 16 MHz).
Figure 3-18. Block Diagram of PWM Unit
7
8
9 Overflow
f CLK
f CLK/2
f CLK/4
Counter (12)
ALVn
11
f CLK/8
S
0-7
0-8
0-9 Coinci-
f CLK/16
dence
Comparator (12)
Compare register CMPn (12)
PWM buffer register n (12)
Remark n = 0, 1
46
0-11
Q
PWMn
R
µPD78363A, 78365A, 78366A, 78368A
3.11
WATCHDOG TIMER (WDT)
The watchdog timer is a free running timer equipped with a non-maskable interrupt function to prevent
program hang-up or deadlock. When an error of the program is detected, the overflow interrupt (INTWDT) of
the watchdog timer occurs and the watchdog timer output pin (WDTO) goes low. By connecting this output pin
to the RESET pin, any malfunctioning of the application system due to program error can be prevented.
Figure 3-19. Block Diagram of Watchdog Timer
f CLK/29
f CLK/211
Watchdog timer
(8 bits)
Overflow
S
Q
Clear
f CLK/213
f CLK
Clear
WDTO
R
Timer
(5 bits)
Overflow
WDT CLR
WDT STOP
INTWDT
Oscillation
stabilization
time control circuit
47
µPD78363A, 78365A, 78366A, 78368A
4.
INTERRUPT FUNCTIONS
4.1
OUTLINE
The µPD78366A is provided with powerful interrupt functions that can process interrupt requests from the
internal hardware peripherals and external sources. In addition, the following three interrupt processing modes
are available. In addition, four levels of interrupt priority can be specified.
• Vectored interrupt processing
• Macro service
• Context switching
Table 4-1. Interrupt Sources
Interrupt source
Type
Note
Name
Nonmaskable
Source unit
Vector
table
address
External
0002H
Trigger
–
NMI
NMI pin input
–
INTWDT
Watchdog timer
WDT
0004H
0
INTOV3
Overflow of timer 3
RPU
0006H
External/RPU
0008H
1 INTP0/INTCC30 INTP0 pin input/CC30 coincidence signal
2
INTP1
INTP1 pin input
Macro
service
Context
switching
None
None
Provided
Provided
000AH
External
3
4
Maskable
INTP2
INTP2 pin input
INTP3/INTCC20 INTP3 pin input/CC20 coincidence signal
5
INTP4
INTP4 pin input
6
INTTM0
7
000CH
External/RPU
000EH
External
0010H
Underflow of timer 0
0012H
INTCM03
CM03 coincidence signal
0014H
8
INTCM10
CM10 coincidence signal
9
INTCM40
CM40 coincidence signal
0018H
10
INTCM41
CM41 coincidence signal
001AH
11
INTSER
Receive error of UART
001CH
12
INTSR
End of UART reception
13
INTST
End of UART transfer
14
INTCSI
End of CSI transfer/reception
CSI
0022H
15
INTAD
End of A/D conversion
A/D
0024H
–
BRK
BRK instruction
–
003EH
–
BRKCS
BRKCS instruction
–
–
RPU
UART
0016H
001EH
0020H
None
Software
Provided
None
Exception
–
TRAP
Reset
–
RESET
Illegal op code trap
–
003CH
Reset input
–
0000H
None
Note Default priority : Priority that takes precedence when two or more maskable interrupts occur at the
same time. 0 is the highest priority, and 15 is the lowest.
48
µPD78363A, 78365A, 78366A, 78368A
4.2
MACRO SERVICE
The µPD78366A has a total of five macro services. Each macro service is described below.
(1) Counter mode: EVTCNT
• Operation
(a) Increments or decrements an 8-bit macro service counter (MSC).
(b) A vector interrupt request is generated when MSC reaches 0.
MSC
+1/–1
• Application example: As event counter, or to measure number of times a value is captured
(2) Block transfer mode: BLKTRS
• Operation
(a) Transfers data block between a buffer and a SFR specified by SFR pointer (SFRP).
(b) The transfer source and destination can be in SFR or buffer area. The length of the transfer data
can be specified to be byte or word.
(c) The number of times the data is to be transferred (block size) is specified by MSC.
(d) MSC is auto decremented by one each time the macro service has been executed.
(e) When MSC reaches 0, a vector interrupt request is generated.
SFRP
–1
Buffer N
MSC
SFR
Buffer 1
Internal bus
• Application example: To transfer/receive data through serial interface
49
µPD78363A, 78365A, 78366A, 78368A
(3) Block transfer mode (with memory pointer): BLKTRS-P
• Operation
This is the block transfer mode in (2) above with a memory pointer (MEMP). The appended buffer
area of MEMP can be freely set on the memory space.
Remark Each time the macro service is executed, MEMP is auto incremented (by one for byte
data transfer and by two for word data transfer).
Buffer N
SFRP
–1
MSC
MEMP
+1/+2
SFR
Buffer 1
Internal bus
• Application example: Same as (2)
(4) Data differential mode: DTADIF
• Operation
(a) Calculates the difference between the contents of SFR (current value) specified by SFRP and the
contents of SFR saved to the last data buffer (LDB).
(b) Stores the result of the calculation in a predetermined buffer area.
(c) Stores the contents of the current value of the SFR in LDB.
(d) The number of times the data is to be transferred (block size) is specified by MSC. Each time the
macro service is executed, MSC is auto decremented by one.
(e) When MSC reaches 0, a vector interrupt request is generated.
Remark The differential calculation can be carried out only with 16-bit SFRs.
SFRP
–1
MSC
LDB
SFR
Buffer N
Differential calculation
Buffer 1
Internal bus
• Application example : To measure cycle and pulse width by the capture register of the real-time
pulse unit (RPU)
50
µPD78363A, 78365A, 78366A, 78368A
(5) Data differential mode (with memory pointer): DTADIF-P
• Operation
This is the data differential mode in (4) above with memory pointer (MEMP). By appending MEMP,
the buffer area in which the differential data is to be stored can be set freely on the memory space.
Remarks 1.
2.
The differential calculation can be carried out only with 16-bit SFRs.
The buffer is specified by the result of operation by MEMP and MSCNote. MEMP is
not updated after the data has been transferred.
Note MEMP – (MSC × 2) + 2
SFRP
Buffer N
–1
MSC
LDB
SFR
MEMP
Buffer 1
Differential calculation
Internal bus
• Application example: Same as (4)
51
µPD78363A, 78365A, 78366A, 78368A
4.3
CONTEXT SWITCHING
This function is to select a specific register bank through the hardware, and to branch execution to a vector
address predetermined in the register bank. At the same time, it saves the present contents of the PC and PSW
to the register bank when an interrupt occurs, or when the BRKCS instruction is executed.
4.3.1
Context Switching Function by Interrupt Request
When a context switching enable flag corresponding to each maskable interrupt request is set to 1 in the EI
(interrupt enable) status, the context switching function can be started.
The context switching operation by an interrupt request is performed as follows:
(1) When an interrupt request is generated, a register bank to which the context is to be switched is specified
by the contents of the low-order 3 bits of the row address (even address) of the corresponding vector table.
(2) A predetermined vector address is transferred to the PC in the register bank to which the context is to
be switched, and the contents of the PC and PSW immediately before the switching takes place are saved
to the register bank.
(3) Execution branches to an address indicated by the contents of the PC newly set.
Figure 4-1. Operation of Context Switching
Register Bank
RP0
PC
RP1
Exchange
RP2
Save
RP3
RP4
PSW
RP5
RP6
RP7
52
Register Bank
(0-7)
µPD78363A, 78365A, 78366A, 78368A
4.3.2
Context Switching Function by BRKCS Instruction
The context switching function can be started by the BRKCS instruction.
The operation of context switching by an interrupt request is as follows:
(1) An 8-bit register is specified by the operand of the BRKCS instruction, and the register bank to which
the context is to be switched is specified by the contents of this register (only the low-order 3 bits of 8 bits
are valid).
(2) The vector address predetermined in the register bank to which the context is to be switched is transferred
to the PC, and at the same time, the contents of the PC and PSW immediately before the switching takes
place are saved to the register bank.
(3) Execution branches to the contents of the PC newly set.
4.3.3
Restoration from Context Switching
To restore from the switched context, one of the following two instructions are used. Which instruction is
to be executed is determined by the source that has started the context switching.
Table 4-2. Instructions to Restore from Context Switching
Restore instruction
Context switching starting source
RETCS
Occurrence of interrupt
RETCSB
Execution of BRKCS instruction
53
µPD78363A, 78365A, 78366A, 78368A
5.
EXTERNAL DEVICE EXPANSION FUNCTION
The µPD78366A can connect external devices (data memory, program memory, and peripheral devices) in
addition to the internal ROM and RAM areas. To connect an external device, the address/data bus and read/
write strobe signals are controlled by using ports 4, 5, and 9.
Table 5-1. Pin Function with External Device Connected
Pin function with external device connected
Pin
Function
Name
P40-P47
Multiplexed address/data bus
AD0-AD7
P50-P57
Address bus
A8-A15
P90
Read strobe
RD
P91
Write strobe
WR
ASTB
54
Address strobe
ASTB
µPD78363A, 78365A, 78366A, 78368A
6.
STANDBY FUNCTIONS
The µPD78366A is provided with standby functions to reduce the power consumption of the system. The
standby functions can be effected in the following two modes:
• HALT mode ..... In this mode, the operating clock of the CPU is stopped. By using this mode in
combination with an ordinary operation mode, the µPD78366A operates
intermittently to reduce the total power consumption of the system.
• STOP mode .... In this mode, the oscillator is stopped, and therefore the entire system is stopped.
Therefore, power consumption can be minimized with only a leakage current
flowing.
Each mode is set through software. Figure 6-1 shows the transition of the status in the standby modes (STOP
and HALT modes).
Figure 6-1. Transition of Standby Status
Ordinary
se
t
T
OP
I
t
pt
rru
nte
di s
ske cur
ma oc
NM
d
se
ST
SE
se
LT
RE
lea
re
re
T
lea
SE
se
d
RE
HA
Un
STOP
HALT
55
µPD78363A, 78365A, 78366A, 78368A
7.
RESET FUNCTION
When a low level is input to the RESET pin, the system is reset, and each hardware enters the initial status
(reset status). When the RESET pin goes high, the reset status is released, and program execution is started.
Initialize the contents of each register through program as necessary.
Especially, change the number of cycles of the programmable wait control register as necessary.
The RESET pin is equipped with a noise rejecter circuit of analog delay to prevent malfunctioning due to noise.
Cautions 1. While the RESET pin is active (low level), all the pins go into a high-impedance state
(except WDTO, AVREF, AVDD, AVSS, VDD, VSS, X1, and X2 pins).
2. When an external RAM is connected, do not connect a pull-up resistor to the P90/RD and
P91/WR pins, because the P90/RD and P91/WR pins may go into a high-impedance state,
resulting in destruction of the contents of the external RAM. In addition, signal contention
occurs on the address/data bus, resulting in damage to the input/output circuit.
Figure 7-1. Accepting Reset Signal
RESET input
Analog
delay
Rejected
as noise
Analog
delay
Analog
delay
Reset
accepted
Reset
released
To effect reset on when power is applied, make sure that sufficient time elapses to stabilize the oscillation
after the power is applied until the reset signal is accepted, as shown in Figure 7-2.
Figure 7-2. Reset on Power Application
VDD
RESET
Oscillation
stabilization
time
Analog
delay
Reset
released
56
µPD78363A, 78365A, 78366A, 78368A
8.
INSTRUCTION SET
Write an operand in the operand field of each instruction according to the description of the instruction
(for details, refer to the Assembler Specifications). Some instructions have two or more operands. Select
one of them. Uppercase characters, +, –, #, $, !, [, and ] are keywords and must be written as is.
Write an appropriate numeric value or label as immediate data. To write a label, be sure to write #, $,
!, [, or ].
Table 8-1. Operand Representation and Description
Representation
Description
r
r1
r2
R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15
R0, R1, R2, R3, R4, R5, R6, R7
C, B
rp
rp1
rp2
RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7
RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7
DE, HL, VP, UP
sfr
sfrp
Special function register symbol (Refer to Table 2-1.)
Special function register symbol (register that can be manipulated in 16-bit units. Refer to Table
2-1.)
post
RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7
(More than one symbol can be written. However, RP5 can be written only for PUSH and POP
instructions, and PSW can be written only for PUSHU and POPU instructions.)
mem
[DE], [HL], [DE+], [HL+], [DE–], [HL–], [VP], [UP]
[DE + A], [HL + A], [DE + B], [HL + B], [VP + DE], [VP + HL]
[DE + byte], [HL + byte], [VP + byte], [UP + byte], [SP + byte]
word[A], word[B], word[DE], word[HL]
saddr
saddrp
FE20H-FF1FH immediate data or label
FE20H-FF1EH immediate data (however, bit0 = 0) or label (manipulated in 16-bit units)
$ addr16
! addr16
0000H-FDFFH immediate data or label; relative addressing
0000H-FDFFH immediate data or label; immediate addressing
(However, up to FFFFH can be written for MOV instruction. Only FE00H-FEFFH can be written
for MOVTBLW instruction.)
800H-FFFH immediate data or label
addr11
addr5
;
;
;
;
register indirect mode
based indexed mode
based mode
indexed mode
40H-7EH immediate data (however, bit0 = 0)Note or label
word
byte
bit
n
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
3-bit immediate data (0-7)
Note Do not access bit0 = 1 (odd address) in word units.
Remarks
1.
rp and rp1 are the same in terms of register name that can be written but are different in code
to be generated.
2.
r, r1, rp, rp1, and post can be written in absolute name (R0-R15, RP0-RP7) and function name
(X, A, C, B, E, D, L, H, AX, BC, DE, HL, VP, and UP).
3.
Immediate addressing can address the entire space. Relative addressing can address only a
range of –128 to +127 from the first address of the next instruction.
57
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
8-bit data transfer
MOV
XCH
Operand
Byte
Operation
r1, #byte
2
r1 ← byte
saddr, #byte
3
(saddr) ← byte
sfrNote ,
3
sfr ← byte
r, r1
2
r ← r1
A, r1
1
A ← r1
A, saddr
2
A ← (saddr)
saddr, A
2
(saddr) ← A
saddr, saddr
3
(saddr) ← (saddr)
A, sfr
2
A ← sfr
sfr, A
2
sfr ← A
#byte
A, mem
1-4
A ← (mem)
mem, A
1-4
(mem) ← A
A, [saddrp]
2
A ← ((saddrp))
[saddrp], A
2
((saddrp)) ← A
A, !addr16
4
A ← (addr16)
!addri16, A
4
(addr16) ← A
PSWL, #byte
3
PSWL ← byte
PSWH, #byte
3
PSWH ← byte
PSWL, A
2
PSWL ← A
PSWH, A
2
PSWH ← A
A, PSWL
2
A ← PSW L
A, PSWH
2
A ← PSW H
A, r1
1
A ↔ r1
r, r1
2
r ↔ r1
A, mem
2-4
A ↔ (mem)
A, saddr
2
A ↔ (saddr)
A, sfr
3
A ↔ sfr
A, [saddrp]
2
A ↔ ((saddrp))
saddr, saddr
3
(saddr) ↔ (saddr)
S
Z
AC P/V CY
×
×
×
×
×
×
×
×
×
×
Note When STBC or WDM is written as sfr, this instruction is treated as a dedicated instruction whose number
of bytes is different from that of this instruction.
Remark For symbols in flag, refer to the table below.
Symbol
(Blank)
58
Remarks
No change
0
Cleared to 0
1
Set to 1
×
Set/cleared according to result
P
P/V flag functions as parity flag
V
P/V flag operates as overflow flag
R
Value previously saved is restored
16-bit data transfer
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
MOVW
XCHW
8-bit operation
ADD
ADDC
Operand
Byte
Operation
rp1, #word
3
rp1 ← word
saddrp, #word
4
(saddrp) ← word
sfrp, #word
4
sfrp ← word
rp, rp1
2
rp ← rp1
AX, saddrp
2
AX ← (saddrp)
saddrp, AX
2
(saddrp) ← AX
saddrp, saddrp
3
(saddrp) ← (saddrp)
AX, sfrp
2
AX ← sfrp
sfrp, AX
2
sfrp ← AX
rp1, !addr16
4
rp1 ← (addr16)
!addr16, rp1
4
(addr16) ← rp1
AX, mem
2-4
AX ← (mem)
mem, AX
2-4
(mem) ← AX
AX, saddrp
2
AX ↔ (saddrp)
AX, sfrp
3
AX ↔ sfrp
saddrp, saddrp
3
(saddrp) ↔ (saddrp)
rp, rp1
2
rp ↔ rp1
S
Z
AC P/V CY
AX ↔ (mem)
AX, mem
2-4
A, #byte
2
A, CY ← A + byte
×
×
×
V
×
saddr, #byte
3
(saddr), CY ← (saddr) + byte
×
×
×
V
×
sfr, #byte
4
sfr, CY ← sfr + byte
×
×
×
V
×
r, r1
2
r, CY ← r + r1
×
×
×
V
×
A, saddr
2
A, CY ← A + (saddr)
×
×
×
V
×
A, sfr
3
A, CY ← A + sfr
×
×
×
V
×
saddr, saddr
3
(saddr), CY ← (saddr) + (saddr)
×
×
×
V
×
A, mem
2-4
A, CY ← A + (mem)
×
×
×
V
×
mem, A
2-4
(mem), CY ← (mem) + A
×
×
×
V
×
A, #byte
2
A, CY ← A + byte + CY
×
×
×
V
×
saddr, #byte
3
(saddr), CY ← (saddr) + byte + CY
×
×
×
V
×
sfr, #byte
4
sfr, CY ← sfr + byte + CY
×
×
×
V
×
r, r1
2
r, CY ← r + r1 + CY
×
×
×
V
×
A, saddr
2
A, CY ← A + (saddr) + CY
×
×
×
V
×
A, sfr
3
A, CY ← A + sfr + CY
×
×
×
V
×
saddr, saddr
3
(saddr), CY ← (saddr) + (saddr) + CY
×
×
×
V
×
A, mem
2-4
A, CY ← A + (mem) + CY
×
×
×
V
×
mem, A
2-4
(mem), CY ← (mem) + A + CY
×
×
×
V
×
59
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
8-bit operation
SUB
SUBC
AND
60
Operand
Byte
Operation
S
Z
AC P/V CY
A, #byte
2
A, CY ← A – byte
×
×
×
V
×
saddr, #byte
3
(saddr), CY ← (saddr) – byte
×
×
×
V
×
sfr, #byte
4
sfr, CY ← sfr – byte
×
×
×
V
×
r, r1
2
r, CY ← r – r1
×
×
×
V
×
A, saddr
2
A, CY ← A – (saddr)
×
×
×
V
×
A, sfr
3
A, CY ← A – sfr
×
×
×
V
×
saddr, saddr
3
(saddr), CY ← (saddr) – (saddr)
×
×
×
V
×
A, mem
2-4
A, CY ← A – (mem)
×
×
×
V
×
mem, A
2-4
(mem), CY ← (mem) – A
×
×
×
V
×
A, #byte
2
A, CY ← A – byte – CY
×
×
×
V
×
saddr, #byte
3
(saddr), CY ← (saddr) – byte – CY
×
×
×
V
×
sfr, #byte
4
sfr, CY ← sfr – byte – CY
×
×
×
V
×
r, r1
2
r, CY ← r – r1 – CY
×
×
×
V
×
A, saddr
2
A, CY ← A – (saddr) – CY
×
×
×
V
×
A, sfr
3
A, CY ← A – sfr – CY
×
×
×
V
×
saddr, saddr
3
(saddr), CY ← (saddr) – (saddr) – CY
×
×
×
V
×
A, mem
2-4
A, CY ← A – (mem) – CY
×
×
×
V
×
mem, A
2-4
(mem), CY ← (mem) – A – CY
×
×
×
V
×
A, #byte
2
A ← A ∧ byte
×
×
P
saddr, #byte
3
(saddr) ← (saddr) ∧ byte
×
×
P
sfr, #byte
4
sfr ← sfr ∧ byte
×
×
P
r, r1
2
r ← r ∧ r1
×
×
P
A, saddr
2
A ← A ∧ (saddr)
×
×
P
A, sfr
3
A ← A ∧ sfr
×
×
P
saddr, saddr
3
(saddr) ← (saddr) ∧ (saddr)
×
×
P
A, mem
2-4
A ← A ∧ (mem)
×
×
P
mem, A
2-4
(mem) ← (mem) ∧ A
×
×
P
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
8-bit operation
OR
XOR
CMP
Operand
Byte
Operation
S
Z
AC P/V CY
A, #byte
2
A ← A ∨ byte
×
×
P
saddr, #byte
3
(saddr) ← (saddr) ∨ byte
×
×
P
sfr, #byte
4
sfr ← sfr ∨ byte
×
×
P
r, r1
2
r, ← r ∨ r1
×
×
P
A, saddr
2
A ← A ∨ (saddr)
×
×
P
A, sfr
3
A ← A ∨ sfr
×
×
P
saddr, saddr
3
(saddr) ← (saddr) ∨ (saddr)
×
×
P
A, mem
2-4
A ← A ∨ (mem)
×
×
P
mem, A
2-4
(mem) ← (mem) ⁄ A
×
×
P
A, #byte
2
A ← A ∨ byte
×
×
P
saddr, #byte
3
(saddr) ← (saddr) ∨ byte
×
×
P
sfr, #byte
4
sfr ← sfr ∨ byte
×
×
P
r, r1
2
r ← r ∨ r1
×
×
P
A, saddr
2
A ← A ∨ (saddr)
×
×
P
A, sfr
3
A ← A ∨ sfr
×
×
P
saddr, saddr
3
(saddr) ← (saddr) ∨ (saddr)
×
×
P
A, mem
2-4
A ← A ∨ (mem)
×
×
P
mem, A
2-4
(mem) ← (mem) ∨ A
×
×
P
A, #byte
2
A – byte
×
×
×
V
×
saddr, #byte
3
(saddr) – byte
×
×
×
V
×
sfr, #byte
4
sfr – byte
×
×
×
V
×
r, r1
2
r – r1
×
×
×
V
×
A, saddr
2
A – (saddr)
×
×
×
V
×
A, sfr
3
A – sfr
×
×
×
V
×
saddr, saddr
3
(saddr) – (saddr)
×
×
×
V
×
A, mem
2-4
A – (mem)
×
×
×
V
×
mem, A
2-4
(mem) – A
×
×
×
V
×
61
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
16-bit operation
Multiplication
/division
Operation
S
Z
AC P/V CY
3
AX, CY ← AX + word
×
×
×
V
×
saddrp, #word
4
(saddrp), CY ← (saddrp) + word
×
×
×
V
×
sfrp, #word
5
sfrp, CY ← sfrp + word
×
×
×
V
×
rp, rp1
2
rp, CY ← rp + rp1
×
×
×
V
×
AX, saddrp
2
AX, CY ← AX + (saddrp)
×
×
×
V
×
AX, sfrp
3
AX, CY ← AX + sfrp
×
×
×
V
×
saddrp, saddrp
3
(saddrp), CY ← (saddrp) + (saddrp)
×
×
×
V
×
AX, #word
3
AX, CY ← AX – word
×
×
×
V
×
saddrp, #word
4
(saddrp), CY ← (saddrp) – word
×
×
×
V
×
sfrp, #word
5
sfrp, CY ← sfrp – word
×
×
×
V
×
rp, rp1
2
rp, CY ← rp – rp1
×
×
×
V
×
AX, saddrp
2
AX, CY ← AX – (saddrp)
×
×
×
V
×
AX, sfrp
3
AX, CY ← AX – sfrp
×
×
×
V
×
saddrp, saddrp
3
(saddrp), CY ← (saddrp) – (saddrp)
×
×
×
V
×
AX, #word
3
AX – word
×
×
×
V
×
saddrp, #word
4
(saddrp) – word
×
×
×
V
×
sfrp, #word
5
sfrp – word
×
×
×
V
×
rp, rp1
2
rp – rp1
×
×
×
V
×
AX, saddrp
2
AX – (saddrp)
×
×
×
V
×
AX, sfrp
3
AX – sfrp
×
×
×
V
×
saddrp, saddrp
3
(saddrp) – (saddrp)
×
×
×
V
×
MULU
r1
2
AX ← AX × r1
DIVUW
r1
2
AX (quotient), r1 (remainder) ← AX ÷ r1
MULUW
rp1
2
AX (high-order 16 bits), rp1 (low-order 16 bits) ← AX × rp1
DIVUX
rp1
2
AXDE (quotient), rp1 (remainder) ← AXDE ÷ rp1
MULW
rp1
2
AX (high-order 16 bits), rp1 (low-order 16 bits) ← AX × rp1
MACW
n
3
AXDE ← (B) × (C) + AXDE
B ← B + 2, C ← C + 2, n ← n – 1
End if n = 0 or P/V = 1
×
×
×
V
×
n
3
AXDE ← (B) × (C) + AXDE
B ← B + 2, C ← C + 2, n ← n – 1
if overflow (P/V = 1) then
AXDE ← 7FFFFFFFH
if underflow (P/V = 1) then
AXDE ← 80000000H
end if n = 0 or P/V = 1
×
×
×
V
×
[DE + ], [HL + ]
4
AX ← AX + | (DE) – (HL) |
DE ← DE + 2 HL ← HL + 2 C ← C – 1
end if C = 0 or cy = 1
×
×
×
V
×
SUBW
CMPW
Sum-of-products
operation with
saturation
MACSW
Relative
operation
Sum-of- Signed
products multiplioperation cation
Byte
AX, #word
ADDW
62
Operand
SACW
Table
shift
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
MOVTBLW !addr16, n
Increment/decrement
INC
DEC
INCW
BCD
adjustment
Shift rotate
DECW
Data
conversion
Operand
Byte
4
Operation
S
Z
AC P/V CY
(addr16 + 2) ← (addr16), n ← n – 1
addr16 ←addr16 – 2, End if n = 0
r1
1
r1 ← r1 + 1
×
×
×
V
saddr
2
(saddr) ← (saddr) + 1
×
×
×
V
r1
1
r1 ← r1 – 1
×
×
×
V
saddr
2
(saddr) ← (saddr) – 1
×
×
×
V
rp2
1
rp2 ← rp2 + 1
saddrp
3
(saddrp) ← (saddrp) + 1
rp2
1
rp2 ← rp2 – 1
saddrp
3
(saddrp) ← (saddrp) – 1
ROR
r1, n
2
(CY, r17 ← r1 0, r1m–1 ← r1m ) × n times
P
×
ROL
r1, n
2
(CY, r10 ← r1 7, r1m+1 ← r1m) × n times
P
×
RORC
r1, n
2
(CY ← r10, r17 ← CY, r1m–1 ← r1m) × n times
P
×
ROLC
r1, n
2
(CY ← r17, r10 ← CY, r1m+1 ← r1m ) × n times
P
×
SHR
r1, n
2
(CY ← r10, r17 ← 0, r1m–1 ← r1m) × n times
×
×
0
P
×
SHL
r1, n
2
(CY ← r17, r10 ← 0, r1m+1 ← r1m ) × n times
×
×
0
P
×
SHRW
rp1, n
2
(CY ← rp10, rp115 ← 0, rp1m–1 ← rp1m)
× n times
×
×
0
P
×
SHLW
rp1, n
2
(CY ← rp115 , rp10 ← 0, rp1m+1 ← rp1m )
× n times
×
×
0
P
×
ROR4
[rp1]
2
A3–0 ← (rp1)3–0,
(rp1)7–4 ← A3–0,
(rp1)3–0 ← (rp1)7–4
ROL4
[rp1]
2
A3–0 ← (rp1)7–4,
(rp1)3–0 ← A3–0,
(rp1)7–4 ← (rp1)3–0
2
Decimal Adjust Accumelator
×
×
0
P
×
1
When A7 = 0, X ← A, A ← 00H
When A7 = 1, X ← A, A ← FFH
ADJBA
ADJBS
CVTBW
Remarks 1.
n of the shift rotate instruction indicates the number of times the shift rotate instruction is
executed.
2.
The address of the table shift instruction ranges from FE00H to FEFFH.
63
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
Operand
Byte
S
Bit manipulation
Z
AC P/V CY
CY, saddr.bit
3
CY ← (saddr.bit)
×
CY, sfr.bit
3
CY ← sfr.bit
×
CY, A.bit
2
CY ← A.bit
×
CY, X.bit
2
CY ← X.bit
×
CY, PSWH.bit
2
CY ← PSWH.bit
×
CY, PSWL.bit
2
CY ← PSW L.bit
×
saddr.bit, CY
3
(saddr.bit) ← CY
sfr.bit, CY
3
sfr.bit ← CY
A.bit, CY
2
A.bit ← CY
X.bit, CY
2
X.bit ← CY
PSWH.bit, CY
2
PSWH.bit ← CY
PSWL.bit, CY
2
PSWL.bit ← CY
CY, saddr.bit
3
CY ← CY ∧ (saddr.bit)
×
CY, /saddr.bit
3
CY ← CY ∧ (saddr.bit)
×
CY, sfr.bit
3
CY ← CY ∧ sfr.bit
×
CY, /sfr.bit
3
CY ← CY ∧ sfr.bit
×
CY, A.bit
2
CY ← CY ∧ A.bit
×
CY, /A.bit
2
CY ← CY ∧ A.bit
×
CY, X.bit
2
CY ← CY ∧ X.bit
×
CY, /X.bit
2
CY ← CY ∧ X.bit
×
CY, PSWH.bit
2
CY ← CY ∧ PSWH.bit
×
CY, /PSWH.bit
2
CY ← CY ∧ PSWH.bit
×
CY, PSWL.bit
2
CY ← CY ∧ PSWL.bit
×
CY, /PSWL.bit
2
CY ← CY ∧ PSWL.bit
×
CY, saddr.bit
3
CY ← CY ∨ (saddr.bit)
×
CY, /saddr.bit
3
CY ← CY ∨ (saddr.bit)
×
CY, sfr.bit
3
CY ← CY ∨ sfr.bit
×
CY, /sfr.bit
3
CY ← CY ∨ sfr.bit
×
CY, A.bit
2
CY ← CY ∨ A.bit
×
CY, /A.bit
2
CY ← CY ∨ A.bit
×
CY, X.bit
2
CY ← CY ∨ X.bit
×
CY, /X.bit
2
CY ← CY ∨ X.bit
×
CY, PSWH.bit
2
CY ← CY ∨ PSWH.bit
×
CY, /PSWH.bit
2
CY ← CY ∨ PSWH.bit
×
CY, PSWL.bit
2
CY ← CY ∨ PSWL.bit
×
CY, /PSWL.bit
2
CY ← CY ∨ PSWL.bit
×
MOV1
AND1
OR1
64
Operation
×
×
×
×
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
Operand
Byte
S
Z
AC P/V CY
CY, saddr.bit
3
CY ← CY ∨ (saddr.bit)
×
CY, sfr.bit
3
CY ← CY ∨ sfr.bit
×
CY, A.bit
2
CY ← CY ∨ A.bit
×
CY, X.bit
2
CY ← CY ∨ X.bit
×
CY, PSWH.bit
2
CY ← CY ∨ PSWH.bit
×
CY, PSWL.bit
2
CY ← CY ∨ PSWL.bit
×
saddr.bit
2
(saddr.bit) ← 1
sfr.bit
3
sfr.bit ← 1
A.bit
2
A.bit ← 1
X.bit
2
X.bit ← 1
PSWH.bit
2
PSWH.bit ← 1
PSWL.bit
2
PSWL.bit ← 1
saddr.bit
2
(saddr.bit) ← 0
sfr.bit
3
sfr.bit ← 0
A.bit
2
A.bit ← 0
X.bit
2
X.bit ← 0
PSWH.bit
2
PSWH.bit ← 0
PSWL.bit
2
PSWL.bit ← 0
saddr.bit
3
(saddr.bit) ← (saddr.bit)
sfr.bit
3
sfr.bit ← sfr.bit
A.bit
2
A.bit ← A.bit
X.bit
2
X.bit ← X.bit
PSWH.bit
2
PSWH.bit ← PSWH.bit
PSWL.bit
2
PSWL.bit ← PSWL.bit
SET1
CY
1
CY ← 1
1
CLR1
CY
1
CY ← 0
0
NOT1
CY
1
CY ← CY
×
XOR1
SET1
Bit manipulation
Operation
CLR1
NOT1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
65
Call/return
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
Operand
Byte
S
Z
!addr16
3
(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALLF
!addr11
2
(SP – 1) ← (PC + 2)H , (SP – 2) ← (PC + 2)L,
PC15 – 11 ← 00001, PC10 – 0 ← addr11, SP ← SP – 2
CALLT
[addr5]
1
(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (TPF, 00000000, addr5 + 1),
PCL ← (TPF, 00000000, addr5 ), SP ← SP – 2
rp1
2
(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L,
PCH ← rp1 H, PCL ← rp1 L, SP ← SP – 2
[rp1]
2
(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L,
PCH ← (rp1 + 1), PCL ← (rp1), SP ← SP – 2
BRK
1
(SP – 1) ← PSWH, (SP – 2) ← PSW L
(SP – 3) ← (PC + 1)H, (SP – 4) ← (PC + 1)L,
PCL ← (003EH), PCH ← (003FH),
SP ← SP – 4, IE ← 0
RET
1
PCL ← (SP), PCH ← (SP + 1), SP ← SP + 2
RETB
1
PCL ← (SP), PCH ← (SP +1)
PSWL ← (SP + 2), PSWH ← (SP + 3)
SP ← SP + 4
R
R
R
R
R
RETI
1
PCL ← (SP), PCH ← (SP + 1)
PSWL ← (SP + 2), PSWH ← (SP + 3)
SP ← SP + 4
R
R
R
R
R
sfrp
3
(SP – 1) ← sfrH
(SP – 2) ← sfrL
SP ← SP – 2
post
2
{(SP – 1) ← postH, (SP – 2) ← post L, SP ← SP
– 2} × n times
PSW
1
(SP – 1) ← PSWH, (SP – 2) ← PSWL, SP ← SP – 2
post
2
{(UP – 1) ← postH, (UP – 2) ← post L, UP ← UP
– 2} × n times
sfrp
3
sfrL ← (SP)
sfrH ← (SP + 1)
SP ← SP + 2
post
2
{postL ← (SP), postH ← (SP + 1), SP ← SP + 2}
× n times
PSW
1
PSWL ← (SP), PSWH ← (SP + 1), SP ← SP + 2
R
R
R
R
R
post
2
{postL ← (UP),postH ← (UP + 1), UP ← UP + 2}
× n times
SP, #word
4
SP ← word
SP, AX
2
SP ← AX
AX, SP
2
AX ← SP
INCW
SP
2
SP ← SP + 1
DECW
SP
2
SP ← SP – 1
CALL
PUSHU
POP
POPU
MOVW
Remark n of the stack manipulation instruction is the number of registers written as post.
66
AC P/V CY
CALL
PUSH
Stack manipulation
Operation
Unconditional Special
Instructions
branch
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
Operand
Byte
S
Z
AC P/V CY
CHKL
sfr
3
(pin level) ∨ (signal level before output buffer)
×
×
P
CHKLA
sfr
3
A ← (pin level) ∨ (signal level before output buffer)
×
×
P
!addr16
3
PC ← addr16
rp1
2
PCH ← rp1H, PCL← rp1L
[rp1]
2
PCH ← (rp1 + 1), PCL ← (rp1)
$addr16
2
PC ← PC + 2 + jdisp8
$addr16
2
PC ← PC + 2 + jdisp8 if CY = 1
$addr16
2
PC ← PC + 2 + jdisp8 if CY = 0
$addr16
2
PC ← PC + 2 + jdisp8 if Z = 1
$addr16
2
PC ← PC + 2 + jdisp8 if Z = 0
$addr16
2
PC ← PC + 2 + jdisp8 if P/V = 1
$addr16
2
PC ← PC + 2 + jdisp8 if P/V = 0
BN
$addr16
2
PC ← PC + 2 + jdisp8 if S = 1
BP
$addr16
2
PC ← PC + 2 + jdisp8 if S = 0
BGT
$addr16
3
PC ← PC + 3 + jdisp8 if (P/V ∨ S) ⁄ Z = 0
BGE
$addr16
3
PC ← PC + 3 + jdisp8 if P/V ∨ S= 0
BLT
$addr16
3
PC ← PC + 3 + jdisp8 if P/V ∨ S = 1
BLE
$addr16
3
PC ← PC + 3 + jdisp8 if (P/V ∨ S) ⁄ Z = 1
BH
$addr16
3
PC ← PC + 3 + jdisp8 if Z ∨ CY = 0
BNH
$addr16
3
PC ← PC + 3 + jdisp8 if Z ∨ CY = 1
saddr.bit, $addr16
3
PC ← PC + 3 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16
4
PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16
3
PC ← PC + 3 + jdisp8 if A.bit = 1
X.bit, $addr16
3
PC ← PC + 3 + jdisp8 if X.bit = 1
PSWH.bit, $addr16
3
PC ← PC + 3 + jdisp8 if PSWH.bit = 1
PSWL.bit, $addr16
3
PC ← PC + 3 + jdisp8 if PSWL.bit = 1
saddr.bit, $addr16
4
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16
4
PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16
3
PC ← PC + 3 + jdisp8 if A.bit = 0
X.bit, $addr16
3
PC ← PC + 3 + jdisp8 if X.bit = 0
PSWH.bit, $addr16
3
PC ← PC + 3 + jdisp8 if PSWH.bit = 0
PSWL.bit, $addr16
3
PC ← PC + 3 + jdisp8 if PSWL.bit = 0
BR
BC
BL
BNC
BNL
BZ
BE
BNZ
BNE
BV
BPE
BNV
BPO
Conditional branch
Operation
BT
BF
67
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
Operand
Byte
Z
AC P/V CY
×
×
×
×
×
×
×
×
×
×
4
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
then reset (saddr.bit)
sfr.bit, $addr16
4
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16
3
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
X.bit, $addr16
3
PC ← PC + 3 + jdisp8 if X.bit = 1
then reset X.bit
PSWH.bit, $addr16
3
PC ← PC + 3 + jdisp8 if PSWH.bit = 1
then reset PSWH.bit
PSWL.bit, $addr16
3
PC ← PC + 3 + jdisp8 if PSWL.bit = 1
then reset PSWL.bit
saddr.bit, $addr16
4
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
then set (saddr.bit)
sfr.bit, $addr16
4
PC ← PC + 4 + jdisp8 if sfr.bit = 0
then set sfr.bit
A.bit, $addr16
3
PC ← PC + 3 + jdisp8 if A.bit = 0
then set A.bit
X.bit, $addr16
3
PC ← PC + 3 + jdisp8 if X.bit = 0
then set X.bit
PSWH.bit, $addr16
3
PC ← PC + 3 + jdisp8 if PSWH.bit = 0
then set PSW H.bit
PSWL.bit, $addr16
3
PC ← PC + 3 + jdisp8 if PSWL.bit = 0
then set PSWL.bit
r2, $addr16
2
r2 ← r2 – 1,
then PC ← PC + 2 + jdisp8 if 2 ≠ 0
saddr, $addr16
3
(saddr) ← (saddr) – 1,
then PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
BRKCS
RBn
2
PCH ↔ R5, PCL ↔ R4, R7 ← PSWH,
R6 ← PSWL, ← RBS2 – 0 ← n, RSS ← 0, IE ← 0
RETCS
!addr16
3
PCH ← R5, PCL ← R4, R5, R4 ← addr16
PSWH ← R7, PSWL ← R6
R
R
R
R
R
RETCSB
!addr16
4
PCH ← R5, PCL ← R4, R5, R4 ← addr16
PSWH ← R7, PSWL ← R6
R
R
R
R
R
Conditional branch
BFSET
DBNZ
Context switching
S
saddr.bit, $addr16
BTCLR
68
Operation
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
Operand
Byte
S
Z
AC P/V CY
[DE+], A
2
(DE+) ← A, C ← C – 1
End if C = 0
[DE–], A
2
(DE–) ← A, C ← C – 1
End if C = 0
[DE+], [HL+]
2
(DE+) ← (HL+), C ← C – 1
End if C = 0
[DE–], [HL–]
2
(DE–) ← (HL–), C ← C – 1
End if C = 0
[DE+], A
2
(DE+) ↔ A, C ← C – 1
End if C = 0
[DE–], A
2
(DE–) ↔ A, C ← C – 1
End if C = 0
[DE+], [HL+]
2
(DE+) ↔ (HL+), C ← C – 1
End if C = 0
[DE–], [HL–]
2
(DE–) ↔ (HL–), C ← C – 1
End if C = 0
[DE+], A
2
(DE+) – A, C ← C – 1
End if C = 0 or Z = 0
×
×
×
V
×
[DE–], A
2
(DE–) – A, C ← C – 1
End if C = 0 or Z = 0
×
×
×
V
×
[DE+], [HL+]
2
(DE+) – (HL+), C ← C – 1
End if C = 0 or Z = 0
×
×
×
V
×
[DE–], [HL–]
2
(DE–) – (HL–), C ← C – 1
End if C = 0 or Z = 0
×
×
×
V
×
[DE+], A
2
(DE+) – A, C ← C – 1
End if C = 0 or Z = 1
×
×
×
V
×
[DE–], A
2
(DE–) – A, C ← C – 1
End if C = 0 or Z = 1
×
×
×
V
×
[DE+], [HL+]
2
(DE+) – (HL+), C ← C – 1
End if C = 0 or Z = 1
×
×
×
V
×
[DE–], [HL–]
2
(DE–) – (HL–), C ← C – 1
End if C = 0 or Z = 1
×
×
×
V
×
[DE+], A
2
(DE+) – A, C ← C – 1
End if C = 0 or CY = 0
×
×
×
V
×
[DE–], A
2
(DE–) – A, C ← C – 1
End if C = 0 or CY = 0
×
×
×
V
×
[DE+], [HL+]
2
(DE+) – (HL+), C ← C – 1
End if C = 0 or CY = 0
×
×
×
V
×
[DE–], [HL–]
2
(DE–) – (HL–), C ← C – 1
End if C = 0 or CY = 0
×
×
×
V
×
MOVM
MOVBK
XCHM
XCHBK
CMPME
String
Operation
CMPBKE
CMPMNE
CMPBKNE
CMPMC
CMPBKC
69
Instructions
µPD78363A, 78365A, 78366A, 78368A
Flag
Mnemonic
Operand
Byte
S
Z
AC P/V CY
[DE+], A
2
(DE+) – A, C ← C – 1
End if C = 0 or CY = 1
×
×
×
V
×
[DE–], A
2
(DE–) – A, C ← C – 1
End if C = 0 or CY = 1
×
×
×
V
×
[DE+], [HL+]
2
(DE+) – (HL+), C ← C – 1
End if C = 0 or CY = 1
×
×
×
V
×
[DE–], [HL–]
2
(DE–) – (HL–), C ← C – 1
End if C = 0 or CY = 1
×
×
×
V
×
STBC, #byte
4
STBC ← byteNote
WDM, #byte
4
WDM ← byteNote
1
RSS ← RSS
RBn
2
RBS2 – 0 ← n, RSS ← 0
RBn, ALT
2
RBS2 – 0 ← n, RSS ← 1
NOP
1
No Operation
EI
1
IE ← 1 (Enable Interruptt)
DI
1
IE ← 0 (Disable Interrupt)
String
CMPMNC
CMPBKNC
MOV
CPU control
Operation
SWRS
SEL
Note If the op code of the STBC register and WDM register manipulation instructions is wrong, an op code
trap interrupt occurs.
Operation on trap:
(SP – 1) ← PSWH, (SP – 2) ← PSWL,
(SP – 3) ← (PC – 4)H, (SP – 4) ← (PC – 4)L,
PCL ← (003CH), PCH ← (003DH),
SP ← SP – 4, IE ← 0
70
µPD78363A, 78365A, 78366A, 78368A
9.
EXAMPLE OF SYSTEM CONFIGURATION
Controlling outdoor apparatus of inverter air conditioner
µ PD78366A
Real-time pulse unit
CM03
Dead time setting register
U/D
16-bit timer
CM00
Pulse generation
circuit
CM01
CM02
(Analog signal)
U
TO00
U
TO01
V
TO02
V
TO03
W
TO04
W
TO05
Inverter
AC power
supply monitor
External temperature
Thermal exchange
temperature
Outlet temperature
ANI0
ANI1
ANI2
ANI3
ANI4
ROM 32K bytes
10-bit A/D
converter
RAM 2K bytes
Generalpurpose port
P40
P41
P42
P43
Inlet temperature
DC monitor
Compressor motor
temperature monitor
NMI
INTP1
Programmable
interrupt
controller
Real-time
output port
P00
P01
P02
P03
4-way valve
2-way valve
Outdoor fan
motor
Stepping
motor
(electronic
expansion
valve)
RX D
Indoor apparatus
controller
TX D
Serial
interface
71
µPD78363A, 78365A, 78366A, 78368A
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T A = 25 ˚C)
Parameter
Symbol
Rating
Unit
V DD
–0.5 to +7.0
V
AV DD
–0.5 to V DD + 0.5
V
AV SS
–0.5 to +0.5
V
–0.5 to V DD + 0.5
V
–0.5 to V DD + 0.5
V
Note
20
mA
Output pins other than
those in the note
4.0
mA
Total of all output pins
200
mA
All output pins
–3.0
mA
Total of all output pins
–25
mA
AV SS – 0.5 to AV DD + 0.5
V
AV REF
AV SS – 0.5 to AV DD + 0.5
V
Operating ambient temperature
TA
–40 to +85
˚C
Storage temperature
T stg
–60 to +150
˚C
Power supply voltage
Input voltage
VI
Output voltage
VO
Low-level output current
I OL
High-level output current
I OH
Analog input voltage
V IAN
A/D converter reference input voltage
Test conditions
Pins other than
P70/ANI0-P77/ANI7
P70/ANI0-P77/ANI7 pins
Note P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40, P07/TCLRUD, P10-P17, and
P80/TO00-P85/TO05 pins.
Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even
momentarily. In other words, an absolute maxumum rating is a value at which the
possibility of psysical damage to the product cannnot be ruled out. Care must therefore
be taken to ensure that the these ratings are not exceeded during use of the product.
Recommended Operating Conditions
Oscillation frequency
TA
V DD
3 MHz ≤ f XX ≤ 8 MHz
–40 to +85 ˚C
+5.0 V ± 10 %
Capacitance (T A = 25 ˚C, V SS = VDD = 0 V)
Parameter
72
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CI
f = 1 MHz
20
pF
Output capacitance
CO
0 V except measured pins
20
pF
I/O capacitance
C IO
20
pF
µPD78363A, 78365A, 78366A, 78368A
Oscillator Characteristics (T A = –40 to +85 ˚C, V DD = +5 V ± 10 %, V SS = 0 V)
Resonator
Ceramic resonator or
crystal resonator
Recommended circuit
VSS
X1
C1
Parameter
MIN.
MAX.
Unit
Oscillation frequency (f XX)
3
8
MHz
X1 input frequency (f X)
3
8
MHz
X1 rise/fall time (t XR, t XF)
0
30
ns
X1 input high-/low-level
width (t WXH , t WXL )
40
170
ns
X2
C2
External clock
X1
X2
Leave unconnected
HCMOS
inverter
Caution When using system clock oscillation circuits, to reduce the effect of the wiring
capacitouce, etc, wire the area indicated by dotted-line as follows:
• Make the wiring as short as possible.
• Do not allow the wiring to intersect other signal lines. Keep it away from other lines in which
varying high currents flow.
• Make sure that the ground point of the oscillation circuit capacitor is always at the same
electric potential as VSS. Do not allow the wiring to be grounded to a ground pattern in which
very high currents are flowing.
• Do not extract signals from the oscillation circuit.
73
µPD78363A, 78365A, 78366A, 78368A
DC Characteristics (T A = –40 to +85 ˚C, V DD = +5 V ± 10 %, V SS = 0 V)
Parameter
Symbol
Low-level input voltage
V IL1
Note 1
V IL2
High-level input voltage
Low-level output voltage
High-level output voltage
Test conditions
MIN.
TYP.
MAX.
Unit
0
0.8
V
Note 2
0
0.2V DD
V
V IH1
Note 1
2.2
V
V IH2
Note 2
0.8V DD
V
V OL1
Note 3
I OL = 2.0 mA
0.45
V
V OL2
Note 4
I OL = 15 mA
1.5
V
V OL3
Note 5
I OL = 10 mA
1.5
V
V OH
I OH = –400 µ A
V DD – 1.0
V
Input leakage current
I LI
0 V ≤ V I ≤ V DD, AV DD = V DD
±10
µA
Output leakage current
I LO
0 V ≤ V O ≤ V DD , AV DD = V DD
±10
µA
V DD supply current
I DD1
Operating mode
70
120
mA
I DD2
HALT mode
45
70
mA
Data retention voltage
V DDDR
STOP mode
Data retention current
I DDDR
STOP mode
Pull-up resistance
RL
2.5
V
V DDDR = 2.5 V
2
10
µA
V DDDR = 5.0 V ± 10 %
10
50
µA
60
150
kΩ
VI = 0 V
15
Notes 1. Pins other than those specified in Note 2.
2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3/TI, P25/INTP4, P32/
SO/SB0, P33/SI/SB1 and P34/SCK pins.
3. Pins other than those specified in Notes 4 and 5.
4. P80/TO00-P85/TO05 pins (When I OL = 15 mA is in operation, up to three pins can be ON
simultaneously.)
5. P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40 and P07/TCLRUD pins
(When I OL = 10 mA is in operation, up to four pins can be ON simultaneously.) as well as P10-P17
pins (When I OL = 10 mA is in operation, up to four pins can be ON simultaneously.).
Caution When the P80-P85, P00-P07, and P10-P17 pins are not used under the conditions specified
in Notes 4 and 5, they have the same characteristics as in Note 3.
74
µPD78363A, 78365A, 78366A, 78368A
AC Characteristics (T A = –40 to +85 ˚C, V DD = +5 V ± 10 %, V SS = 0 V, C L = 100 pF, f XX = 8 MHz)
Read/Write Operation (when general-purpose memory is connected)
Parameter
Symbol
Test conditions
MIN.
MAX.
Unit
166.7
ns
System clock cycle time
t CYK
62.5
Address setup time (vs. ASTB ↓)
t SAST
7
ns
Address hold time (vs. ASTB ↓)
t HSTA
11
ns
RD ↓ → address float time
t FRA
24
ns
Address → data input time
t DAID
100
ns
RD ↓ → data input time
t DRID
49
ns
ASTB ↓ → RD ↓ delay time
t DSTR
15
ns
Data hold time (vs. RD ↑)
t HRID
0
ns
RD ↑ → address active time
t DRA
17
ns
RD low-level width
tWRL
63
ns
ASTB high-level width
t WSTH
14
ns
WR ↓ → data output time
t DWOD
ASTB ↓ → WR ↓ delay time
t DSTW
15
ns
WR ↑ → ASTB ↑ delay time
t DWST
78
ns
Data setup time (vs. WR ↑)
t SODW
57
ns
Data hold time (vs. WR ↑)
t HWOD
8
ns
WR low-level width
t WWL
63
ns
21
ns
t CYK-dependent Bus Timing Definition
Parameter
Arithmetic expression
MIN./MAX.
Unit
t SAST
(0.5 + a) T – 24
MIN.
ns
t HSTA
0.5T – 20
MIN.
ns
t WSTH
(0.5 + a) T – 17
MIN.
ns
t DSTR
0.5T – 16
MIN.
ns
t WRL
(1.5 + n) T – 30
MIN.
ns
t DAID
(2.5 + a + n) T – 56
MAX.
ns
t DRID
(1.5 + n) T – 44
MAX.
ns
t DRA
0.5T – 14
MIN.
ns
t DSTW
0.5T – 16
MIN.
ns
t DWST
1.5T – 15
MIN.
ns
t WWL
(1.5 + n) T – 30
MIN.
ns
t DWOD
0.5T – 10
MAX.
ns
t SODW
(1 + n) T – 5
MIN.
ns
Remarks 1. T = t CYK = 1/f CLK (f CLK refers to the internal system clock frequency.)
2. a becomes 1 when the address wait is inserted. Otherwise, it becomes 0.
3. n refers to the number of wait cycles that is inserted by specifying the PWC register.
4. Only the bus timings indicated in this table depend on t CYK.
75
µPD78363A, 78365A, 78366A, 78368A
Serial Operation (T A = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V)
Parameter
Symbol
Serial clock cycle time
t CYSK
Serial clock low-level
t WSKL
width
Serial clock high-level
t WSKH
width
Test conditions
MIN.
MAX.
Unit
SCK output
Internal 8 dividing
500
ns
SCK input
External clock
500
ns
SCK output
Internal 8 dividing
210
ns
SCK input
External clock
210
ns
SCK output
Internal 8 dividing
210
ns
SCK input
External clock
210
ns
SI setup time (vs. SCK ↑)
t SRXSK
80
ns
SI hold time (vs. SCK ↑)
t HSKRX
80
ns
SCK ↓ → SO delay time
t DSKTX
R = 1 kΩ, C = 100 pF
210
ns
Up/Down Counter Operation (T A = –40 to +85 ˚C, V DD = +5 V ± 10 %, V SS = 0 V)
Parameter
TIUD high-/low-level
Symbol
tWTIUH, t WTIUL
MAX.
Unit
2T
ns
Mode 4
4T
ns
t WTCUH, t WTCUL Other than mode 4
2T
ns
Mode 4
4T
ns
2T
ns
width
TCLRUD high-/low-level width t WCLUH, tWCLUL
TCUD setup time (vs. TIUD ↑)
t STCU
Mode 3
T
ns
TCUD hold time (vs. TIUD ↑)
t HTCU
Mode 3
T
ns
TIUD setup time (vs. TCUD)
t S4TIU
Mode 4
2T
ns
TIUD hold time (vs. TCUD)
t H4TIU
Mode 4
2T
ns
TIUD & TCUD cycle time
t CYC
Other than mode 4
4
MHz
t CYC4
Mode 4
2
MHz
Remark T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.)
76
MIN.
Other than mode 4
width
TCUD high-/low-level
Test conditions
µPD78363A, 78365A, 78366A, 78368A
Other Operations (T A = –40 to +85 ˚C, V DD = +5 V ± 10 %, VSS = 0 V)
Parameter
Symbol
Test conditions
MIN.
MAX.
Unit
NMI high-/low-level width t WNIH, t WNIL
2
µs
RESET high-/low-level width t WRSH, t WRSL
1.5
µs
Ts = T
250
ns
Ts = 4T
1.0
µs
Ts = 8T
2.0
µs
Ts = 16T
4.0
µs
Ts = T
250
ns
Ts = 4T
1.0
µs
Ts = 8T
2.0
µs
Ts = 16T
4.0
µs
Ts = T
250
ns
Ts = 4T
1.0
µs
Ts = T
250
ns
Ts = 4T
1.0
µs
Ts = 8T
2.0
µs
Ts = 16T
4.0
µs
Ts = 64T
16.0
µs
Ts = 128T
32.0
µs
Ts = 256T
64.0
µs
Ts = T
250
ns
Ts = 4T
1.0
µs
Ts = 8T
2.0
µs
Ts = 16T
4.0
µs
INTP0 high-/low-level
t WI0H, t WI0L
width
INTP1 high-/low-level
t WI1H, t WI1L
width
INTP2 high-/low-level
t WI2H, t WI2L
width
INTP3(TI) high-/low-
t WI3H, t WI3L
level width
INTP4 high-/low-level
width
t WI4H, t WI4L
Remarks 1. T = t CYK = 1/f CLK (f CLK refers to the internal system clock frequency.)
2. Ts refers to the input sampling frequency. INTP0-INTP4 can be selected to programmable.
77
µPD78363A, 78365A, 78366A, 78368A
A/D Converter Characteristics (T A = –40 to +85 ˚C, V DD = +5 V ± 10 %, VSS = AV SS = 0 V,
V DD – 0.5 V ≤ AV DD ≤ V DD)
Parameter
Symbol
Test conditions
MIN.
Resolution
Total
TYP.
10
error Note 1
Conversion time
Sampling time
t CONV
t SAMP
Zero-scale error Note 1
error Note 1
Nonlinearity
error Note 1
Analog input
voltage Note 2
V IAN
Analog input impedance
R AN
4.5 V ≤ AV REF ≤ AV DD
±0.4
%FSR
3.4 V ≤ AV REF ≤ AV DD
±0.7
%FSR
±1/2
LSB
62.5 ns ≤ t CYK < 80 ns
208
t CYK
80 ns ≤ t CYK ≤ 166.6 ns
169
t CYK
62.5 ns ≤ t CYK < 80 ns
24
t CYK
80 ns ≤ t CYK ≤ 166.6 ns
20
t CYK
4.5 V ≤ AV REF ≤ AV DD
±1.5
±2.5
LSB
3.4 V ≤ AV REF ≤ AV DD
±1.5
±4.5
LSB
4.5 V ≤ AV REF ≤ AV DD
±1.5
±2.5
LSB
3.4 V ≤ AV REF ≤ AV DD
±1.5
±4.5
LSB
4.5 V ≤ AV REF ≤ AV DD
±1.5
±2.5
LSB
3.4 V ≤ AV REF ≤ AV DD
±1.5
±4.5
LSB
AVREF + 0.3
V
–0.3
When not sampling
10
When sampling
Reference voltage
AV REF
AV REF1 current
AI REF
AV DD supply current
AI DD
A/D converter data
retention current
AI DDDR
Unit
bit
Quantization error
Full-scale
MAX.
Note 3
3.4
Operating mode
STOP mode
MΩ
AV DDDR = 2.5 V
AV DDDR = 5 V ± 10 %
AV DD
V
1.0
3.0
mA
2.0
6.0
mA
2
10
µA
10
50
µA
Notes 1. The quantization error is excluded.
2. When –0.3 V ≤ V IAN ≤ 0 V, the conversion result becomes 000H.
When 0 V < V IAN < AV REF , the conversion is performed with the 10-bit resolution.
When AV REF ≤ V IAN ≤ +0.3 V, the conversion result becomes 3FFH.
3. The analog input impedance at the time of sampling is the same as the equivalent circuit shown
below. (The values in the diagram are TYP. values; they are not guaranteed values)
1 kΩ
Analog input pin
25 pF
(Input
capacitance
included)
78
4 pF
µPD78363A, 78365A, 78366A, 78368A
Cautions 1. When using the P70/ANI0-P77/ANI7 pins for both digital and analog inputs, the previously described characteristics are not guaranteed. Therefore, ensure that all of the
eight P70/ANI0-P77/ANI7 pins are used either for analog input or digital input.
2. When using the P70/ANI0-P77/ANI7 pins as digital input, make sure to set that AVDD = V DD ,
and AV SS = V SS.
AC Timing Test Point
VDD
0.8 VDD or 2.2 V
0.8 VDD or 2.2 V
Test point
0.2 VDD or 0.8 V
0.2 VDD or 0.8 V
0V
79
µPD78363A, 78365A, 78366A, 78368A
Read Operation
tCYK
(CLK)
A8-A15
(Output)
High-order address
tDAID
tSAST
AD0-AD7
(Input/output)
Hi-Z
High-order address
Hi-Z
Low-order address (Output)
Hi-Z
Data (Input)
tWSTH
Low-order address (Output)
tHRID
ASTB
(Output)
tHSTA
tFRA
RD
(Output)
tDSTR
tDRID
tDRA
tWRL
Write Operation
(CLK)
A8-A15
(Output)
High-order address
High-order address
tSAST
AD0-AD7
(Output)
Low-order address (Output)
Undefined
Data (Output)
tWSTH
tHWOD
ASTB
(Output)
tHSTA
tDWST
WR
(Output)
tDSTW
tDWOD
tSODW
tWWL
80
Low-order address (Output)
Hi-Z
µPD78363A, 78365A, 78366A, 78368A
Serial Operation
tCYSK
tWSKH
tWSKL
SCK
tDSKTX
SO
SI
tSRXSK
tHSKRX
Up/Down Counter (Timer 4) Input Timing
tWTIUH
TIUD
tWTIUL
tSTCU
tHTCU
tWTCUL
TCUD
tWTCUH
tWCLUH
TCLRUD
tWCLUL
TIUD
tS4TIU
tH4TIU
tS4TIU
tH4TIU
TCUD
81
µPD78363A, 78365A, 78366A, 78368A
Interrupt Input Timing
tWNIH
tWNIL
0.8 VDD
NMI
0.2 VDD
tWInH
tWInL
0.8 VDD
INTPn
0.2 VDD
Remark n = 0 to 4
Reset Input Timing
tWRSH
tWRSL
0.8 VDD
RESET
0.2 VDD
82
µPD78363A, 78365A, 78366A, 78368A
11. PACKAGE DRAWING
80 PIN PLASTIC QFP (14×20)
A
B
41
40
64
65
F
Q
5°±5°
S
D
C
detail of lead end
25
24
80
1
G
H
I M
J
M
P
K
N
L
P80GF-80-3B9-2
NOTE
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
ITEM
MILLIMETERS
INCHES
A
23.6 ± 0.4
0.929 ± 0.016
B
20.0 ± 0.2
0.795 +0.009
–0.008
C
14.0 ± 0.2
0.551+0.009
–0.008
D
17.6 ± 0.4
0.693 ± 0.016
F
1.0
0.039
G
0.8
0.031
H
0.35 ± 0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8 ± 0.2
0.071 –0.009
L
0.8 ± 0.2
0.031+0.009
–0.008
M
0.15+0.10
–0.05
0.006+0.004
–0.003
N
0.15
0.006
P
2.7
0.106
Q
0.1 ± 0.1
0.004 ± 0.004
S
3.0 MAX.
0.119 MAX.
+0.008
83
µPD78363A, 78365A, 78366A, 78368A
12. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the conditions recommended below.
For details of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, please contact your NEC sales
representative.
Table 12-1. Surface Mount Type Soldering Conditions
µ PD78363AGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)
µ PD78365AGF-3B9
: 80-Pin Plastic QFP (14 × 20 mm)
µ PD78366AGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)
µ PD78368AGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)
Soldering method
Soldering conditions
Recommended
condition symbol
Infrared reflow
Package peak temperature: 235 ˚C, Duration: 30 sec. max. (210 ˚C or
above) Number of times: 3 max.
IR35-00-3
VPS
Package peak temperature: 215 ˚C, Duration: 40 sec. max. (200 ˚C or
above) Number of times: 3 max.
VP15-00-3
Wave soldering
Solder bath temperature: 260 ˚C or less, Time: 10 sec. max.,
Number of times: 1, Pre-heating temperature: 120 ˚C max. (Package
surface temperature)
WS60-00-1
Partial heating
Pin temperature: 300 ˚C or less
Duration: 3 sec. max. (per side of device)
–
Caution Use of more than one soldering method should be avoided (except in the case of partial
heating).
84
µPD78363A, 78365A, 78366A, 78368A
APPENDIX A. DIFFERENCES BETWEEN µPD78366A AND µPD78328
Product name
µPD78366A
Item
Minimum instruction
execution time
Internal
memory
125 ns
µPD78328
internal clock : 16 MHz
external clock : 8 MHz
250 ns
ROM
32K bytes
16K bytes
RAM
2K bytes
512 bytes
Memory space
64K bytes (can be externally expanded)
General-purpose
registers
8 bits × 16 × 8 banks
Number of basic
instructions
115
Instruction set
•
•
•
•
111
16-bit transfer/operation
Multiplication/division (16 bits × 16 bits, 32 bits ÷ 16 bits)
Bit manipulation
String
• Sum-of-products operation
(16 bits × 16 bits + 32 bits)
• Relative operation
I/O lines
internal clock : 8 MHz,
external clock : 16 MHz
—
Input
14 (of which 8 are multiplexed with analog
input)
11 (of which 8 are multiplexed with analog
input)
I/O
49
41
Real-time pulse unit
•
•
•
•
•
16-bit timer × 5
16-bit compare register × 7
16-bit capture register × 3
16-bit capture/compare register × 2
Two output modes selectable
Mode 0, set-reset output : 6 channels
Mode 1, buffer output
: 6 channels
•
•
•
•
16-bit timer × 3
16-bit compare register × 14
16-bit capture/compare register × 1
Two output modes selectable
Mode 0, set-reset output : 6 channels
toggle output
: 1 channel
Mode 1, buffer output
: 8 channels
• 16-bit resolution PWM output: 1 channel
Real-time output port
4 (buffer output in 4-bit units)
4/8 (buffer output in 4-/8-bit units)
PWM unit
8-/9-/10-/12-bit resolution variable PWM
output: 2 channels
8-bit resolution PWM output: 1 channel
A/D converter
10-bit resolution, 8 channels
Serial interface
Dedicated baud rate generator
UART (with pin selection function)
: 1 channel
Clocked serial interface/SBI : 1 channel
Dedicated baud rate generator
UART
: 1 channel
Clocked serial interface/SBI : 1 channel
Interrupt function
• External: 6, internal: 14 (2 multiplexed
with external)
• 4 programmable priority levels
• External: 4, internal: 17
• 3 programmable priority levels
• Three processing selectable
(vectored interrupt/macro service/context switching)
Test source
None
Internal: 1
PLL control circuit
Provided (external 8 MHz → internal: 16 MHz)
None
Package
• 80-pin plastic QFP (14 × 20 mm)
• 64-pin plastic shrink DIP
• 64-pin plastic QFP (14 × 20 mm)
Others
• Watchdog timer
• Standby functions (HALT mode, STOP mode)
85
µPD78363A, 78365A, 78366A, 78368A
APPENDIX B. TOOLS
B.1 DEVELOPMENT TOOLS
The following development tools are available to support the system development using µPD78366A :
Language Processor
78K/III series
relocatable assembler
(RA78K3)
A relocatable assembler, that can be used commonly for the 78K/III series products. Since this
assembler is provided with macro functions, it enhances the developmnt efficency. A structured
assembler, that can explicitly describe the program control structure, is also supplied, so that
the program productivity and maintainability can be improved.
Host machine
PC-9800 series
IBM PC/ATTM and its
OS
Order code (product name)
3.5" 2HD
µS5A13RA78K3
5" 2HD
µS5A10RA78K3
3.5" 2HC
µS7B13RA78K3
5" 2HC
µS7B10RA78K3
MS-DOSTM
PC DOSTM
compatible model
78K/III series
C compiler
(CC78K3)
Supply media
HP9000 series 700TM
HP-UXTM
DAT
µS3P16RA78K3
SPARC stationTM
SunOSTM
Cartridge tape
µS3K15RA78K3
NEWSTM
NEWS-OSTM
(QIC-24)
µS3R15RA78K3
This is a C compiler that can be commonly used for 78K/III series.
This program converts the program written in C language to object codes microcomputer can
execute. When using this compiler, the 78K/III series relocatable assembler (RA78K3) is
necessary.
Host machine
PC-9800 series
IBM PC/AT and its
OS
Supply media
Order code (product name)
3.5" 2HD
µS5A13CC78K3
5" 2HD
µS5A10CC78K3
3.5" 2HC
µS7B13CC78K3
5" 2HC
µS7B10CC78K3
MS-DOS
PC DOS
compatible model
HP9000 series 700
HP-UX
DAT
µS3P16CC78K3
SPARC station
SunOS
Cartridge tape
µS3K15CC78K3
NEWS
NEWS-OS
(QIC-24)
µS3R15CC78K3
Remark The operations of the relocatable assembler and C compiler are guaranteed only on the specified
host machine and OS described above.
86
µPD78363A, 78365A, 78366A, 78368A
Hardware
PROM Writing Tools
PG-1500
This is a PROM programmer that can program PROM-contained single-chip microcontrollers
in standalone mode or under control of a host machine when the accessory board and an
optional programmer adapter are connected. It can also program representative PROMs from
256K-bit to 4M-bit models.
PA-78P368GF
PA-78P368KL
PROM programmer adapters that writes a program to the µPD78P368A on a general-purpose
PROM programmer such as the PG-1500.
PA-78P368GF : for µPD78P368AGF
PA-78P368KL : for µPD78P368AKL
PG-1500
controller
Connects the PG-1500 and a host machine with a serial intrface and a parallel interface to control
the PG-1500 from the host machine.
Software
Host machine
PC-9800 series
IBM PC/AT and
OS
Supply media
Order code (part number)
3.5" 2HD
µS5A13PG1500
5" 2HD
µS5A10PG1500
3.5" 2HC
µS7B13PG1500
3.5" 2HC
µS7B10PG1500
MS-DOS
PC DOS
compatible machines
Remark The operation of the PG-1500 controller is guaranteed only on the above host machine and OS.
Hardware
Debugging Tools (When IE Controller Is Used)
IE-78350-R
In-circuit emulator that can be used to develop and debug application systems. Connected to
a host machine for debugging.
IE-78365-R-EM1
I/O emulation board that emulates the peripheral functions of the target device such as I/O ports.
Emulation probe that connects the IE-78350-R to the target system. One conversion socket,
EV-9200G-80 EV-9200G-80, used to connect the target system is supplied as an accessory.
EP-78365GF-R
IE-78350-R
control program
(IE controller)
Program that controls the IE-78350-R on the host machine. It can automatically execute
commands, enhancing debugging efficiency.
Software
Host machine
PC-9800 series
IBM PC/AT and
compatible machines
OS
Supply media
Order code (part number)
3.5" 2HD
µS5A13IE78365A
5" 2HD
µS5A10IE78365A
3.5" 2HC
µS7B13IE78365A
3.5" 2HC
µS7B10IE78365A
MS-DOS
PC DOS
Remark The operation of the IE controller is guaranteed only on the above host machine and OS.
87
µPD78363A, 78365A, 78366A, 78368A
Development Tool Configuration (When Using IE Controller)
Host machine
PC-9800 series
IBM PC series
EWS
RS-232-C
IE-78350-R
in-circuit emulator
+
IE-78365-R-EM1
I/O emulation board
(optional)
Software
Emulation probe
RS-232C
PROM
programmer
Relocatable
assembler
C compiler
PG-1500
controller
EP-78365GF-R
+
Conversion socket for connecting
the emulation probe and the target systemNote
PG-1500
IE controller
EV-9200G-80
Built-in PROM models
µ PD78P368AGF µ PD78P368AKL
+
+
Programmer adapter
PA-78P368GF
PA-78P368KL
Note A socket is provided with the emulation probe.
Remarks 1. Host machine and PG-1500 can be directly connected by RS-232-C.
2. 3.5-inch FD represents the supply media of software in this figure.
88
Target system
µPD78363A, 78365A, 78366A, 78368A
Hardware
Debugging Tools (When Integrated Debugger Is Used)
IE-784000-R
In-circuit emulation that can be used to develop and debug the application system. Connected
to a host machine for debugging.
IE-78350-R-EM-A
Emulation board that emulates the peripheral functions of the target device such as I/O ports.
IE-78365-R-EM1
I/O emulation board that emulates the peripheral functions of the target device such as I/O ports.
EP-78365GF-R
Emulation probe connecting the IE-784000-R to the target system. One conversion socket, EV9200G-80, used to connect the target system is supplied as an accessory.
EV-9200G-80
IE-70000-98-IF-B
Interface adapter to connect PC-9800 series (except notebook type personal computer) as the
host machine.
Interface adapter and cable to connect PC-9800 series notebook type personal computer as the
host machine.
IE-70000-PC-IF-B Interface adapter and cable to connect IBM PC as the host machine.
IE-78000-R-SV3 Interface board to connect EWS as the host machine.
IE-70000-98N-IF
Integrated debugger Program controlling the in-circuit emulator for the 78K/III series. Used in combination with a
device file (DF78365). Can debug a program coded in the C language, structured assembly
(ID78K3)
language, or assembly language at source program level. Can also split the screen of the host
machine into windows on each of which information is displayed, enhancing debugging
efficiency.
Host machine
Order code (part number)
OS
µSAA13ID78K3
µSAA10ID78K3
IBM PC/AT and compatible
PC DOS
3.5" 2HC
µSAB13ID78K3
+
Windows
5" 2HC
µSAB10ID78K3
machines (Japanese Windows)
IBM PC/AT and compatible
3.5" 2HC
µSBB13ID78K3
machines (English Windows)
5" 2HC
µSBB10ID78K3
File containing information peculiar to device. Use in combination with an assembler (RA78
K3), C compiler (CC78K3), and integrated debugger (ID78K3).
Host machine
Order code (part number)
OS
Supply media
PC-9800 series
MS-DOS
3.5" 2HD
µS5A13DF78365
5" 2HD
µS5A10DF78365
IBM PC/AT and compatible
PC DOS
3.5" 2HC
µS7B13DF78365
machines
5" 2HC
µS7B10DF78365
Software
PC-9800 series
Device File
(DF78365)
Supply media
MS-DOS
+
WindowsTM
3.5" 2HD
5" 2HD
Remark The operation of the integrated debugger and device file is guaranteed only on the above host
machine and OS.
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µPD78363A, 78365A, 78366A, 78368A
Development Tool Configuration (When Using Integrated Debugger)
Host machine
PC-9800 series
IBM PC/AT
EWS
IE-70000-98-IF-B
IE-70000-98N-IF
IE-70000-PC-IF-B
IE-784000-R
in-circuit emulator
+
IE-78350-R-EM-A
emulation board
(optional)
Emulation probe
+
IE-78365-R-EM1
I/O emulation board
(optional)
Software
RS-232C
EP-78365GF-R
Relocatable
assembler
C compiler
PG-1500
controller
+
Conversion socket for connecting
the emulation probe and the target systemNote
PROM programmer
PG-1500
Integrated
Device file
debugger
Built-in PROM models
EV-9200G-80
µ PD78P368AGF µ PD78P368AKL
+
+
Programmer adapter
PA-78P368GF
PA-78P368KL
Note A socket is provided with the emulation probe.
Remarks 1. Desk top-type PC represents host machine in this figure.
2. 3.5-inch FD represents the supply media of software in this figure.
90
Target system
µPD78363A, 78365A, 78366A, 78368A
B.2 EMBEDDED SOFTWARE
The following embedded software is available for enhancing the efficiency of program development and
maintenance.
REAL-TIME OS
Real-time OS
(RX78K/III)Note
RX78K/III is intended to implement a multi-tasking environment for use in the control field where
real-time capability is a must. It can allocate the idle time of the CPU to other processing to
improve the overall performance of the system.
RX78K/III provides system calls conforming to the µITRON specification.
The RX78K/III package supplies a tool (configurator) to create the nucleus of RX78K/III and
multiple information tables.
Host machine
PC-9800 series
IBM PC/AT and compatible
machines
Order code (part number)
OS
Supply media
MS-DOS
3.5" 2HD
Pending
PC DOS
5" 2HD
3.5" 2HC
Pending
Pending
5" 2HC
Pending
Note Under development
Caution Before purchasing this product, you are requested to conclude a contract licensing use by
filling out a specified form.
Remark When using the RX78K/III real-time OS, the RA78K3 assembler package (optional) is necessary.
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Fuzzy Inference Development Support System
Fuzzy knowledge data Program that supports input/editing and evaluation (simulation) of fuzzy knowledge (fuzzy rules
and membership functions).
creation tool
Host machine
Order code (part number)
(FE9000, FE9200)
OS
Supply media
µS5A13FE9000
µS5A10FE9000
IBM PC/AT and compatible
PC DOS
µS7B13FE9200
+
machines
Windows
5" 2HC
µS7B10FE9200
Program that converts the fuzzy knowledge data obtained by using the fuzzy knowledge data
Translator
creation tool into assembler source program for the RA78K/III.
(FT78K3)Note
Host machine
Order code (part number)
OS
Supply media
PC-9800 series
MS-DOS
3.5" 2HD
µS5A13FT78K3
5" 2HD
µS5A10FT78K3
IBM PC/AT and compatible
PC DOS
3.5" 2HC
µS7B13FT78K3
machines
5" 2HC
µS7B10FT78K3
Fuzzy inference module Program that executes fuzzy inference when linked with the fuzzy knowledge data converted
by the translator.
(FI78K/III)Note
Host machine
Order code (part number)
OS
Supply media
µS5A13FI78K3
PC-9800 series
MS-DOS
3.5" 2HD
5" 2HD
µS5A10FI78K3
IBM PC/AT and compatible
PC DOS
3.5" 2HC
µS7B13FI78K3
machines
5" 2HC
µS7B10FI78K3
Fuzzy inference debugger Support software that evaluates and adjusts the fuzzy knowledge data at the hardware level by
using an in-circuit emulator.
(FD78K/III)
Host machine
Order code (part number)
OS
Supply media
PC-9800 series
MS-DOS
3.5" 2HD
µS5A13FD78K3
µS5A10FD78K3
5" 2HD
IBM PC/AT and compatible
PC DOS
3.5" 2HC
µS7B13FD78K3
µS7B10FD78K3
machines
5" 2HC
PC-9800 series
MS-DOS
3.5" 2HD
5" 2HD
3.5" 2HC
Note Under development
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µPD78363A, 78365A, 78366A, 78368A
[MEMO]
93
µPD78363A, 78365A, 78366A, 78368A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to V DD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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µPD78363A, 78365A, 78366A, 78368A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics (France) S.A.
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd.
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
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µPD78363A, 78365A, 78366A, 78368A
MS-DOS and windows are either registered trademarks or trademarks of Microsoft
Corporation in the United states and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products
may be prohibited without governmental license. To export or re-export some or all of these products from a country other than
Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Lisence not needed
: µPD78365A
The customer must judge the need for license : µPD78363A, 78366A, 78368A
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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