DATA SHEET MOS INTEGRATED CIRCUIT µPD78F0034AY 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µ PD78F0034AY is a product of the µPD780034AY Subseries in the 78K/0 Series, and is equivalent to the µPD780034AY but with flash memory in place of internal ROM. The µPD78F0034AY incorporates flash memory, which can be programmed and erased while mounted on the board. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual: U14046E 78K/0 Series User’s Manual Instruction: U12326E FEATURES • On-chip I2C bus serial interface supported multimaster • Pin-compatible with mask ROM versions (except VPP pin) • Flash memory: 32 KbytesNote • Internal high-speed RAM: 1024 bytesNote • Supply voltage: VDD = 1.8 to 5.5 V Note The flash memory and internal high-speed RAM capacities can be changed with the memory size switching register (IMS). Remark For the differences between the flash memory and the mask ROM versions, refer to 1. DIFFERENCES BETWEEN µ PD78F0034AY AND MASK ROM VERSIONS. ORDERING INFORMATION Part Number Package Internal ROM µPD78F0034AYCW 64-pin plastic shrink DIP (750 mils) Flash memory µPD78F0034AYGC-AB8 64-pin plastic QFP (14 × 14 mm) Flash memory µPD78F0034AYGK-8A8 64-pin plastic LQFP (12 × 12 mm) Flash memory The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14041EJ1V0DS00 (1st edition) Date Published September 1999 N CP(K) Printed in Japan © 1999 µ PD78F0034AY 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. Products in mass-production Products under development Y subseries products are compatible with I2C bus. Control 100-pin µ PD78075B 100-pin µ PD78078 µPD78078Y 100-pin µ PD78070A µ PD78070AY ROM-less version of the µ PD78078 µPD78078 with reduced EMI noise µPD78054 with timer and enhanced external interface function µ PD780018AY µPD78078Y with enhanced serial I/O and select functions µ PD780058 µ PD78058F µPD780058Y µ PD78058FY µPD78054 with enhanced serial I/O and reduced EMI noise µPD78054 with reduced EMI noise 80-pin µ PD78054 µ PD78054Y 80-pin µPD78018F with UART and D/A, and enhanced I/O µPD780024A with expanded RAM 64-pin µ PD780065 µ PD780078 µPD780078Y µPD780034A with timer and enhanced serial I/O 64-pin µ PD780034A µ PD780034AY µPD780024A with enhanced A/D 64-pin µ PD780024A µ PD780024AY µPD78018F with enhanced serial I/O 64-pin 64-pin µ PD78014H 100-pin 80-pin 80-pin 42/44-pin µPD78018F µPD78018F with reduced EMI noise µ PD78018FY µPD78083 Basic subseries for control On-chip UART and capable of low-voltage (1.8 V) operation Inverter control 64-pin µPD780988 100-pin µ PD780208 100-pin µ PD780228 µPD78044H with enhanced I/O, FIP, C/D. Total display outputs: 48 80-pin µ PD780232 Panel control. On-chip FIP C/D. Total display outputs: 53 80-pin µ PD78044H µPD78044F with N-ch open drain I/O. Total display outputs: 34 80-pin µ PD78044F Basic subseries for FIP drive. Total display outputs: 34 On-chip inverter control circuit and UART. EMI noise reduced products FIP drive 78K/0 Series µPD78044F with enhanced I/O, FIP, C/D. Total display outputs: 53 LCD drive 100-pin µ PD780308 100-pin µ PD78064B 100-pin µ PD78064 80-pin µ PD780841 µ PD780308Y µPD78064 with enhanced SIO and expanded ROM and RAM µPD78064 with reduced EMI noise µ PD78064Y Basic subseries for LCD drive. On-chip UART Call ID supported On-chip Call ID function and simple DTMF. EMI noise reduced products Bus interface supported 100-pin µ PD780948 On-chip DCAN controller 80-pin µ PD78098B µPD78054 with IEBusTM controller. EMI noise reduced products 80-pin µPD780701Y On-chip DCAN/IEBus controller 80-pin µPD780833Y On-chip J1850 (CLASS2) controller Meter control 2 100-pin µ PD780958 For industrial meter control 80-pin µ PD780955 Ultra low-power consumption and on-chip UART 80-pin µ PD780973 On-chip controller/driver for automobile meter driving 80-pin µ PD780824 For automobile meter driving. On-chip DCAN controller Data Sheet U14041EJ1V0DS00 µ PD78F0034AY The major functional differences among the Y subseries are shown below. Function ROM Capacity Configuration of Serial Interface I/O V DD MIN. Value Subseries Name Control µPD78078Y 48 K to 60 K 1 ch 88 1.8 V 61 2.7 V µPD78070AY –– 3-wire with automatic transmit/receive function: 1 ch 3-wire/UART: 1 ch µPD780018AY 48 K to 60 K 3-wire with automatic transmit/receive function: 1 ch Time-division 3-wire: 1 ch I 2C bus (multimaster supported): 1 ch 88 µPD780058Y 24 K to 60 K 3-wire/2-wire/I2C: 1 ch 3-wire with automatic transmit/receive function: 1 ch 3-wire/time-division UART: 1 ch 68 1.8 V µPD78058FY 48 K to 60 K 3-wire/2-wire/I2C: 69 2.7 V µPD78054Y 16 K to 60 K 3-wire with automatic transmit/receive function: 1 ch 3-wire/UART: 1 ch µPD780078Y 48 K to 60 K 3-wire UART: 3-wire/UART: I 2C bus (multimaster supported): 1 1 1 1 ch ch ch ch 52 1.8 V µPD780034AY 8 K to 32 K UART: 3-wire: I 2C bus (multimaster supported): 1 ch 1 ch 1 ch 51 1.8 V µPD78018FY 8 K to 60 K 3-wire/2-wire/I2C: 1 ch 3-wire with automatic transmit/receive function: 1 ch 53 µPD780308Y 48 K to 60 K 3-wire/2-wire/I2C: 3-wire/time-division UART: 3-wire: 1 ch 1 ch 1 ch 57 µPD78064Y 16 K to 32 K 3-wire/2-wire/I2C: 3-wire/UART: 1 ch 1 ch µPD780024AY LCD 3-wire/2-wire/I2C: drive 1 ch 2.0 V 2.0 V Remark Functions other than the serial interface are common to the non-Y subseries Data Sheet U14041EJ1V0DS00 3 µ PD78F0034AY OVERVIEW OF FUNCTIONS Item Function Kbytes Note Internal Flash memory 32 memory High-speed RAM 1024 bytesNote Memory space 64 Kbytes General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time On-chip minimum instruction execution time cycle modification function When main system clock selected 0.24 µ s/0.48 µs/0.95 µs/1.91 µs/3.81 µ s (@ 8.38-MHz operation) When subsystem clock selected 122 µ s (@ 32.768-kHz operation) Instruction set • 16-bit operation, multiply/divide (8 bits × 8 bits,16 bits ÷ 8 bits) • Bit manipulation (set, reset, test, Boolean operation) • BCD adjust, etc. I/O ports Total: 51 • CMOS input: 8 • CMOS I/O: 39 • N-ch open drain I/O (5-V resistance): 4 A/D converter • 10-bit resolution × 8 channels • Operable over a wide power supply voltage range: AVDD = 1.8 to 5.5 V Serial interface • • • 3-wire serial I/O mode: 1 channel UART mode: 1 channel I 2C bus mode (multimaster supported): 1 channel Timer • • • • 16-bit timer/event counter: 8-bit timer/event counter: Watch timer: Watchdog timer: Timer outputs 3 (8-bit PWM output capable 2) Clock output 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz (@ 8.38-MHz operation with main system clock) 32.768 kHz (@ 32.768-kHz operation with subsystem clock) Buzzer output 1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38-MHz operation with main system clock) Vectored interrupt sources Maskable Internal: 13 External: 5 Non-maskable Internal: 1 Software 1 1 2 1 1 channel channels channel channel Test inputs Internal: 1 External: 1 Supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = –40 to +85°C Package • 64-pin plastic shrink DIP (750 mils) • 64-pin plastic QFP (14 × 14 mm) • 64-pin plastic LQFP (12 × 12 mm) Note The capacities of the flash memory and the internal high-speed RAM can be changed with the memory size switching register (IMS). 4 Data Sheet U14041EJ1V0DS00 µ PD78F0034AY PIN CONFIGURATION (TOP VIEW) • 64-pin plastic shrink DIP (750 mils) µ PD78F0034AYCW P40/AD0 1 64 P67/ASTB P41/AD1 2 63 P66/WAIT P42/AD2 3 62 P65/WR P43/AD3 4 61 P64/RD P44/AD4 5 60 P75/BUZ P45/AD5 6 59 P74/PCL P46/AD6 7 58 P73/TI51/TO51 P47/AD7 8 57 P72/TI50/TO50 P50/A8 9 56 P71/TI01 P51/A9 10 55 P70/TI00/TO0 P52/A10 11 54 P03/INTP3/ADTRG P53/A11 12 53 P02/INTP2 P54/A12 13 52 P01/INTP1 P55/A13 14 51 P00/INTP0 P56/A14 15 50 VSS1 P57/A15 16 49 X1 VSS0 17 48 X2 VDD0 18 47 VPP P30 19 46 XT1 P31 P32/SDA0 20 21 45 44 XT2 RESET P33/SCL0 22 43 AVDD P34 23 42 AVREF P35 24 41 P10/ANI0 P36 25 40 P11/ANI1 P20/SI30 26 39 P12/ANI2 P21/SO30 27 38 P13/ANI3 P22/SCK30 28 37 P14/ANI4 P23/RxD0 29 36 P15/ANI5 P24/TxD0 30 35 P16/ANI6 P25/ASCK0 31 34 P17/ANI7 VDD1 32 33 AVSS Cautions 1. Connect the VPP pin directly to VSS0 or V SS1 in normal operation mode. 2. Connect the AV SS pin to VSS0. Remark When the µ PD78F0034AY is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. Data Sheet U14041EJ1V0DS00 5 µ PD78F0034AY • 64-pin plastic QFP (14 × 14 mm) µ PD78F0034AYGC-AB8 • 64-pin plastic LQFP (12 × 12 mm) P72/TI50/TO50 P73/TI51/TO51 P74/PCL P75/BUZ P64/RD P65/WR P66/WAIT P67/ASTB P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 µ PD78F0034AYGK-8A8 P50/A8 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 P71/TI01 43 P00/INTP0 P56/A14 7 42 VSS1 P57/A15 8 41 X1 VSS0 9 40 X2 VDD0 10 39 VPP P30 11 38 XT1 P31 12 37 XT2 P32/SDA0 13 36 RESET P33/SCL0 14 35 AVDD P34 15 34 AVREF P35 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P10/ANI0 P11/ANI1 P12/ANI2 6 P13/ANI3 P55/A13 P14/ANI4 P01/INTP1 P15/ANI5 44 P16/ANI6 5 P17/ANI7 P54/A12 AVSS P02/INTP2 VDD1 45 P25/ASCK0 4 P24/TxD0 P53/A11 P23/RxD0 P03/INTP3/ADTRG P22/SCK30 P70/TI00/TO0 46 P21/SO30 47 3 P36 2 P20/SI30 P51/A9 P52/A10 Cautions 1. Connect the VPP pin directly to VSS0 or V SS1 in normal operation mode. 2. Connect the AV SS pin to VSS0. Remark When the µ PD78F0034AY is used in application fields that require reduction of the noise generated from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and VSS1 to different ground lines, is recommended. 6 Data Sheet U14041EJ1V0DS00 µ PD78F0034AY A8 to A15: Address Bus PCL: Programmable Clock AD0 to AD7: Address/Data Bus RD: Read Strobe ADTRG: AD Trigger Input RESET: Reset ANI0 to ANI7: Analog Input RxD0: Receive Data ASCK0: Asynchronous Serial Clock SCK30, SCL0: Serial Clock ASTB: Address Strobe SDA0: Serial Data AVDD: Analog Power Supply SI30: Serial Input Serial Output AV REF: Analog Reference Voltage SO30: AVSS : Analog Ground TI00, TI01, TI50, TI51: Timer Input BUZ: Buzzer Clock TO0, TO50, TO51: Timer Output INTP0 to INTP3: External Interrupt Input TxD0: Transmit Data P00 to P03: Port 0 VDD0 , VDD1 : Power Supply P10 to P17: Port 1 VPP : Programming Power Supply P20 to P25: Port 2 VSS0, V SS1: Ground P30 to P36: Port 3 WAIT: Wait P40 to P47: Port 4 WR: Write Strobe P50 to P57: Port 5 X1, X2: Crystal (Main System Clock) P64 to P67: Port XT1, XT2: Crystal (Subsystem Clock) P70 to P75: Port 7 Data Sheet U14041EJ1V0DS00 7 µ PD78F0034AY BLOCK DIAGRAM TI00/TO0/P70 16-BIT TIMER/ EVENT COUNTER PORT0 P00 to P03 TI50/TO50/P72 8-BIT TIMER/ EVENT COUNTER50 PORT1 P10 to P17 TI51/TO51/P73 8-BIT TIMER/ EVENT COUNTER51 PORT2 P20 to P25 WATCHDOG TIMER PORT3 P30 to P36 PORT4 P40 to P47 PORT5 P50 to P57 PORT6 P64 to P67 PORT7 P70 to P75 TI01/P71 WATCH TIMER SI30/P20 SO30/P21 SCK30/P22 RxD0/P23 TxD0/P24 ASCK0/P25 SDA0/P32 SCL0/P33 ANI0/P10 to ANI7/P17 AVDD AVSS AVREF INTP0/P00 to INTP3/P03 8 78K/0 CPU CORE FLASH MEMORY (32 Kbytes) SERIAL INTERFACE30 UART0 RAM (1024 Bytes) AD0/P40 to AD7/P47 A8/P50 to A15/P57 I2C BUS EXTERNAL ACCESS A/D CONVERTER RD/P64 WR/P65 WAIT/P66 ASTB/P67 INTERRUPT CONTROL BUZ/P75 BUZZER OUTPUT PCL/P74 CLOCK OUTPUT CONTROL SYSTEM CONTROL VDD0 VDD1 VSS0 VSS1 VPP Data Sheet U14041EJ1V0DS00 RESET X1 X2 XT1 XT2 µ PD78F0034AY CONTENTS 1. DIFFERENCES BETWEEN µPD78F0034AY AND MASK ROM VERSIONS .............................. 10 2. PIN FUNCTIONS ............................................................................................................................. 11 2.1 Port Pins ................................................................................................................................................. 11 2.2 Non-Port Pins ......................................................................................................................................... 12 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins .................................................. 14 3. MEMORY SIZE SWITCHING REGISTER (IMS) ............................................................................ 16 4. FLASH MEMORY PROGRAMMING .............................................................................................. 17 4.1 Selection of Communication Mode ..................................................................................................... 17 4.2 Flash Memory Programming Functions ............................................................................................. 18 4.3 Connection of Flashpro II and Flashpro III ........................................................................................ 18 5. ELECTRICAL SPECIFICATIONS ................................................................................................... 20 6. PACKAGE DRAWINGS .................................................................................................................. 43 7. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 46 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 48 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 54 Data Sheet U14041EJ1V0DS00 9 µ PD78F0034AY 1. DIFFERENCES BETWEEN µPD78F0034AY AND MASK ROM VERSIONS The µ PD78F0034AY is a product provided with a flash memory which enables writing, erasing, and rewriting of programs with device mounted on the target system. The functions of the µ PD78F0034AY (except the functions specified for flash memory) can be made the same as those of the mask ROM versions by setting the memory size switching register (IMS). Table 1-1 shows the differences between the flash memory (µ PD78F0034AY) and the mask ROM versions. Table 1-1. Differences Between µ PD78F0034AY and Mask ROM Versions Item µPD78F0034AY Mask ROM Versions µPD780034AY Subseries µPD780024AY Subseries Note Internal ROM structure Flash memory Mask ROM Internal ROM capacity 32 Kbytes µPD780031AY: µPD780032AY: µPD780033AY: µPD780034AY: 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes µPD780021AY: µPD780022AY: µPD780023AY: µPD780024AY: 8 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes Internal high-speed RAM capacity 1024 bytes µPD780031AY: µPD780032AY: µPD780033AY: µPD780034AY: 512 bytes 512 bytes 1024 bytes 1024 bytes µPD780021AY: µPD780022AY: µPD780023AY: µPD780024AY: 512 bytes 512 bytes 1024 bytes 1024 bytes A/D converter resolution 10 bits Mask option specification of on-chip pull-up resistor for pins P30 to P31 Not available Available IC pin Not provided Provided VPP pin Provided Not provided Electrical specifications, recommended soldering conditions Refer to the data sheet of individual products. Note 8 bits The µ PD78F0034AY can be used as the flash memory version of the µPD780024AY Subseries. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions. 10 Data Sheet U14041EJ1V0DS00 µPD78F0034AY 2. PIN FUNCTIONS 2.1 Port Pins (1/2) Pin Name P00 I/O I/O Function Port 0 After Reset Input 4-bit input/output port. P01 INTP2 An on-chip pull-up resistor can be specified by means of software. P03 P10 to P17 P20 INTP0 INTP1 Input/output can be specified in 1-bit units. P02 Alternate Function INTP3/ADTRG Input I/O Port 1 8-bit input only port. Input ANI0 to ANI7 Port 2 Input SI30 6-bit input/output port. P21 SO30 Input/output can be specified in 1-bit units. P22 SCK30 An on-chip pull-up resistor can be specified by means of software. P23 RxD0 P24 TxD0 P25 ASCK0 P30 I/O P31 Port 3 N-ch open drain input/output port. 7-bit input/output port. LEDs can be driven directly. Input Input/output can be specified P32 — SDA0 in 1-bit units P33 SCL0 P34 An on-chip pull-up resistor can be P35 specified by means of software. — P36 P40 to P47 I/O Port 4 8-bit input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Interrupt request flag KRIF is set to 1 by falling edge detection. Input AD0 to AD7 P50 to P57 I/O Port 5 8-bit input/output port. LEDs can be driven directly. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Input A8 to A15 P64 I/O Port 6 Input RD P65 P66 4-bit input/output port. WR Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. P67 WAIT ASTB Data Sheet U14041EJ1V0DS00 11 µ PD78F0034AY 2.1 Port Pins (2/2) Pin Name P70 I/O I/O Function Port 7 After Reset Input 6-bit input/output port. P71 TI00/TO0 TI01 Input/output can be specified in 1-bit units. P72 Alternate Function TI50/TO50 An on-chip pull-up resistor can be specified by means of software. P73 TI51/TO51 P74 PCL P75 BUZ 2.2 Non-Port Pins (1/2) Pin Name I/O INTP0 to INTP2 Input Function External interrupt request input by which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. After Reset Input INTP3 Alternate Function P00 to P02 P03/ADTRG SI30 Input Serial interface serial data input. Input P20 SO30 Output Serial interface serial data output. Input P21 SDA0 I/O Serial interface serial data input/output. Input P32 SCK30 I/O Serial interface serial clock input/output. Input P22 SCL0 P33 RxD0 Input Serial data input for asynchronous serial interface. Input P23 TxD0 Output Serial data output for asynchronous serial interface. Input P24 ASCK0 Input Serial clock input for asynchronous serial interface. Input P25 TI00 Input External count clock input to 16-bit timer (TM0). Capture trigger signal input to TM0 capture register (CR01). Input P70/TO0 TI01 Capture trigger signal input to TM0 capture register (CR00). P71 TI50 External count clock input to 8-bit timer (TM50). P72/TO50 TI51 External count clock input to 8-bit timer (TM51). P73/TO51 TO0 Output 16-bit timer (TM0) output. Input P70/TI00 TO50 8-bit timer (TM50) output (shared with 8-bit PWM output). Input P72/TI50 TO51 8-bit timer (TM51) output (shared with 8-bit PWM output). P73/TI51 PCL Output Clock output (for trimming of main system clock and subsystem clock). Input P74 BUZ Output Buzzer output. Input P75 Lower address/data bus for extending memory externally. Input P40 to P47 AD0 to AD7 I/O A8 to A15 Output Higher address bus for extending memory externally. Input P50 to P57 RD Output Strobe signal output for read operation of external memory. Input P64 WR Strobe signal output for write operation of external memory. WAIT Input ASTB Output 12 P65 Inserting wait for accessing external memory. Input P66 Strobe output which externally latches address information output to ports 4 and 5 to access external memory. Input P67 Data Sheet U14041EJ1V0DS00 µPD78F0034AY 2.2 Non-Port Pins (2/2) Pin Name I/O Function After Reset Alternate Function ANI0 to ANI7 Input A/D converter analog input. Input P10 to P17 ADTRG Input A/D converter trigger signal input. Input P03/INTP3 AVREF Input A/D converter reference voltage input. — — AVDD — A/D converter analog power supply. Set the voltage equal to VDD0 or VDD1 . — — AVSS — A/D converter ground potential. Set the voltage equal to VSS0 or VSS1 . — — RESET Input System reset input. — — X1 Input Connecting crystal resonator for main system clock oscillation. — — X2 — — — — — — — XT1 Input Connecting crystal resonator for subsystem clock oscillation. XT2 — VDD0 — Positive power supply voltage for ports. — — VSS0 — Ground potential of ports. — — VDD1 — Positive power supply (except ports). — — VSS1 — Ground potential (except ports). — — VPP — Applying high-voltage for program write/verify. Connect directly to VSS0 or V SS1 in normal operation mode. — — Data Sheet U14041EJ1V0DS00 13 µ PD78F0034AY 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output configuration of each type, refer to Figure 2-1 . Table 2-1. Types of Pin Input/Output Circuits Pin Name Input/Output Circuit Type I/O 8-C Input Independently connect to VSS0 via a resistor. P10/ANI0 to P17/ANI7 25 Input Independently connect to VDD0 or VSS0 via a resistor. P20/SI30 8-C Input/output P21/SO30 5-H P22/SCK30 8-C P00/INTP0 to P02/INTP2 Recommended Connection of Unused Pins P03/INTP3/ADTRG P23/RxD0 P24/TxD0 5-H P25/ASCK0 8-C P30, P31 13-P P32/SDA0 13-R Input/output Independently connect to VDD0 via a resistor. P33/SCL0 P34 8-C P35 5-H P36 8-C P40/AD0 to P47/AD7 5-H Input/output Independently connect to VDD0 via a resistor. P50/A8 to P57/A15 5-H Input/output Independently connect to VDD0 or VSS0 via a resistor. P64/RD Independently connect to VDD0 or VSS0 via a resistor. Input/output P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 8-C P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL 5-H P75/BUZ RESET 2 XT1 16 XT2 AVDD AVREF Input Connect to VDD0 . — — — Leave open. Connect to VDD0 . Connect to VSS0. AVSS VPP 14 Connect directly to V SS0 or V SS1. Data Sheet U14041EJ1V0DS00 µPD78F0034AY Figure 2-1. Pin Input/Output Circuits Type 2 Type 13-R IN/OUT Data Output disable N-ch IN VSS0 Schmitt-triggered input with hysteresis characteristics Type 5-H Pullup enable Data Type 16 VDD0 Feedback cut-off P-ch P-ch VDD0 P-ch IN/OUT Output disable N-ch VSS0 XT1 XT2 Input enable Type 25 Type 8-C VDD0 Pullup enable Data P-ch Comparator P-ch + – VDD0 N-ch VSS0 VREF (threshold voltage) P-ch IN IN/OUT Output disable VSS0 Type 13-P Data Output disable Input enable N-ch IN/OUT N-ch VSS0 Input enable Data Sheet U14041EJ1V0DS00 15 µ PD78F0034AY 3. MEMORY SIZE SWITCHING REGISTER (IMS) IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used. By setting IMS, the internal memory of the µ PD78F0034AY can be mapped identically to that of a mask ROM version. IMS is set with an 8-bit memory manipulation instruction. RESET input sets the IMS to CFH. Caution The initial value of IMS is setting disabled (CFH). Be sure to set C8H or the value of the target mask ROM version at the moment of initial setting. Figure 3-1. Format of Memory Size Switching Register 7 IMS 6 5 RAM2 RAM1 RAM0 4 0 3 2 1 0 ROM3 ROM2 ROM1 ROM0 Address After reset R/W FFF0H CFH R/W ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity 0 0 1 0 8 Kbytes 0 1 0 0 16 Kbytes 0 1 1 0 24 Kbytes 1 0 0 0 32 Kbytes Other than above Setting prohibited RAM2 RAM1 RAM0 Selection of Internal High-Speed RAM Capacity 0 1 0 512 bytes 1 1 0 1024 bytes Other than above Setting prohibited Table 3-1 shows the IMS set value to make the memory mapping the same as those of mask ROM versions. Table 3-1. Set Value of Memory Size Switching Register Target Mask ROM Versions 16 IMS Set Value µPD780031AY 42H µPD780032AY 44H µPD780033AY C6H µPD780034AY C8H Data Sheet U14041EJ1V0DS00 µPD78F0034AY 4. FLASH MEMORY PROGRAMMING Writing to flash memory can be performed without removing the memory from the target system (on board programming). Writing is performed with the dedicated flash programmer (Flashpro II (model No.: FL-PR2) or Flashpro III (model No.: FL-PR3 and PG-FP3)) connected to the host machine and the target system. Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro II or Flashpro III. Remark FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd. 4.1 Selection of Communication Mode Writing to a flash memory is performed using Flashpro II or Flashpro III in a serial communication. Select one of the communication modes in Table 4-1. The selection of the communication mode is made by using the format shown in Figure 4-1. Each communication mode is selected by the number of VPP pulses shown in Table 4-1. Table 4-1. List of Communication Mode Communication Mode Channels Used Pin VPP Pulses 3-wire serial I/O 1 SI30/P20 SO30/P21 SCK30/P22 0 I 2C bus 1 SDA0/P32 SCL0/P33 4 UART 1 RxD0/P23 TxD0/P24 8 Pseudo 3-wire serial I/O 1 P72/TI50/TO50 (serial clock input) P71/TI01 (serial data output) P70/TI00/TO0 (serial data input) 12 Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 4-1. Figure 4-1. Format of Communication Mode Selection VPP pulses 10 V VPP VDD VSS VDD RESET VSS Flash write mode Data Sheet U14041EJ1V0DS00 17 µ PD78F0034AY 4.2 Flash Memory Programming Functions Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 4-2 shows major functions of flash memory programming. Table 4-2. Major Functions of Flash Memory Programming Function Description Reset Used to stop write operation and detect transmission cycle. Batch verify Compares the entire memory contents with the input data. Batch erase Erases the entire memory contents. Batch blank check Checks the deletion status of the entire memory. High-speed write Performs write to the flash memory based on the write start address and the number of data to be written (number of bytes). Continuous write Performs continuous write based on the information input with high-speed write operation. Status Used to confirm the current operating mode and operation end. Oscillation frequency setting Sets the frequency of the resonator. Erase time setting Sets the memory erase time. Silicon signature read Outputs the device name and memory capacity, and device block information. 4.3 Connection of Flashpro II and Flashpro III The connection of Flashpro II or Flashpro III and the µ PD78F0034AY differs according to the communication mode (3-wire serial I/O, UART, and pseudo 3-wire serial I/O). The connection for each communication mode is shown in Figures 4-2 through 4-5, respectively. Figure 4-2. Connection of Flashpro II or Flashpro III for 3-Wire Serial I/O Mode µ PD78F0034AY Flashpro II, Flashpro III VPP VPP VDD VDD RESET RESET SCK SCK30 SO SI30 SI SO30 VSS GND 18 Data Sheet U14041EJ1V0DS00 µPD78F0034AY Figure 4-3. Connection of Flashpro II or Flashpro III for I2C Bus Mode µ PD78F0034AY Flashpro II, Flashpro III VPP VPP VDD VDD RESET RESET SCK ASCK0 SO SCL0 SI SDA0 VSS GND Figure 4-4. Connection of Flashpro II or Flashpro III for UART Mode µPD78F0034AY Flashpro II, Flashpro III VPP VPP VDD VDD RESET RESET SO RxD0 SI TxD0 GND VSS Figure 4-5. Connection of Flashpro II or Flashpro III for Pseudo 3-Wire Serial I/O Mode µ PD78F0034AY Flashpro II, Flashpro III VPP VPP VDD VDD RESET RESET SCK P72 SO P70 SI P71 (serial clock input) (serial data input) (serial data output) GND VSS Data Sheet U14041EJ1V0DS00 19 µPD78F0034AY 5. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Test Conditions Ratings Unit VDD –0.3 to +6.5 V VPP –0.3 to +10.5 V AVDD AVREF –0.3 to VDD + 0.3 Note V –0.3 to VDD + 0.3 Note V AVSS Input voltage Output voltage –0.3 to +0.3 VI1 P00 to P03, P10 to P17,P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, X1, X2, XT1, XT2, RESET VI2 P30 to P33 –0.3 to VDD + N-ch open drain VO –0.3 to +6.5 –0.3 to VDD + V V 0.3 Note 0.3Note VAN P10 to P17 Output current, high I OH Per pin –10 mA Total for P00 to P03, P40 to P47, P50 to P57, P64 to P67, P70 to P75 –15 mA Total for P20 to P25, P30 to P36 –15 mA Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 20 mA Per pin for P30 to P33, P50 to P57 30 mA Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 50 mA Total for P20 to P25 20 mA Total for P30 to P36 100 mA Total for P50 to P57 100 mA –40 to +85 °C –40 to +125 °C Operating ambient temperature Storage temperature Note I OL AVSS –0.3 to AVREF + and –0.3 to V DD + 0.3Note V Analog input voltage Output current, low Analog input pin V 0.3 Note TA Tstg V The rating should be 6.5 V or less. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. 20 Data Sheet U14041EJ1V0DS00 µPD78F0034AY Capacitance (TA = 25°C, V DD = V SS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz Pins other than measured pins returned to 0 V. 15 pF I/O capacitance CIO f = 1 MHz Pins other than measured pins returned to 0 V. P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, 15 pF P30 to P33 20 pF Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. Main System Clock Oscillation Circuit Characteristics (TA = –40 to 85 °C, V DD = 1.8 to 5.5 V) Resonator Ceramic resonator Recommended Circuit VPP X2 C2 Crystal resonator X1 C1 VPP X2 C2 External clock X1 C1 X2 µ PD74HCU04 X1 Parameter Test Conditions Oscillation frequency (f X) Note 1 VDD = 4.0 to 5.5 V Oscillation stabilization time Note 2 After VDD reaches oscillation voltage range MIN. Oscillation frequency (f X) Note 1 VDD = 4.0 to 5.5 V Oscillation stabilization time Note 2 VDD = 4.0 to 5.5 V X1 input frequency (f X) Note 1 VDD = 4.0 to 5.5 V X1 input high-/low-level width (tXH, t XL) VDD = 4.0 to 5.5 V MIN. TYP. MAX. Unit 1.0 8.38 MHz 1.0 5.0 4 ms 1.0 8.38 MHz 1.0 5.0 10 ms 30 1.0 8.38 1.0 5.0 50 500 85 500 MHz ns Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always keep the ground point of the oscillator capacitor the same potential as VSS1. • Do not ground the capacitor to a ground pattern through which a high current flows. • Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. Data Sheet U14041EJ1V0DS00 21 µPD78F0034AY Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Crystal resonator Recommended Circuit XT2 XT1VPP R C4 External clock C3 XT2 Parameter Oscillation frequency (f XT)Note 1 Oscillation stabilization time Note 2 XT1 µPD74HCU04 Test Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s VDD = 4.0 to 5.5 V X1 input frequency (f XT)Note 1 X1 input high-/low-level width (tXTH, t XTL) 10 32 38.5 kHz 5 15 µs Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after V DD reaches oscillator voltage MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken line in the above figures to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. • Do not route the wiring near a signal line through which a high fluctuating current flows. • Always keep the ground point of the oscillator to the same potential as VSS1 . • Do not ground the capacitor to a ground pattern in which a high current flows. • Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. 22 Data Sheet U14041EJ1V0DS00 µPD78F0034AY Recommended Oscillator Constant Main System Clock: Ceramic Resonator (TA = –40 to +85 °C) Manufacturer Part Number Frequency Recommended Circuit Constant Oscillation Voltage Range (MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V) Murata Mfg. CSB1000J 1.00 100 100 1.9 5.5 Co., Ltd. CSA2.00MG040 2.00 100 100 2.0 5.5 CST2.00MG040 2.00 On-chip On-chip 2.0 5.5 CSA3.58MG 3.58 30 30 2.0 5.5 CST3.58MGW 3.58 On-chip On-chip 2.0 5.5 CSA3.58MG093 3.58 30 30 1.8 5.5 CST3.58MGW093 3.58 On-chip On-chip 1.8 5.5 CSA4.19MG 4.19 30 30 2.0 5.5 CST4.19MGW 4.19 On-chip On-chip 2.0 5.5 CSA4.19MG093 4.19 30 30 1.8 5.5 CST4.19MGW093 4.19 On-chip On-chip 1.8 5.5 CSA5.00MG 5.00 30 30 2.0 5.5 CST5.00MGW 5.00 On-chip On-chip 2.0 5.5 CSA5.00MG093 5.00 30 30 1.8 5.5 CST5.00MGW093 5.00 On-chip On-chip 1.8 5.5 CSA8.00MTZ 8.00 30 30 4.0 5.5 CST8.00MTW 8.00 On-chip On-chip 4.0 5.5 CSA8.00MTZ093 8.00 30 30 4.0 5.5 CST8.00MTW093 8.00 On-chip On-chip 4.0 5.5 CSA8.38MTZ 8.38 30 30 4.0 5.5 CST8.38MTW 8.38 On-chip On-chip 4.0 5.5 CSA8.38MTZ093 8.38 30 30 4.0 5.5 CST8.38MTW093 8.38 On-chip On-chip 4.0 5.5 CCR3.58MC3 3.58 On-chip On-chip 1.8 5.5 CCR4.19MC3 4.19 On-chip On-chip 1.8 5.5 CCR5.0MC3 5.00 On-chip On-chip 1.8 5.5 CCR8.0MC5 8.00 On-chip On-chip 4.0 5.5 CCR8.38MC5 8.38 On-chip On-chip 4.0 5.5 TDK Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details please contact directly the manufacturer of the resonator you will use. Data Sheet U14041EJ1V0DS00 23 µPD78F0034AY DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Output current, high I OH Output current, low I OL Input voltage, high VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage, low VIL1 VIL2 VIL3 VIL4 Conditions MIN. TYP. MAX. Unit Per pin –1 mA All pins –15 mA Per pin for P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 10 mA Per pin for P30 to P33, P50 to P57 15 mA Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75 20 mA Total for P20 to P25 10 mA Total for P30 to P36 70 mA Total for P50 to P57 70 mA 0.7 VDD VDD V 0.8 VDD VDD V 0.8 VDD VDD V 0.85 VDD VDD V 0.7 VDD 5.5 V 0.8 VDD 5.5 V VDD–0.5 VDD V VDD–0.2 VDD V 0.8 VDD VDD V 0.9 VDD VDD V 0 0.3 VDD V 0 0.2 VDD V 0 0.2 VDD V 0 0.15 VDD V P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75 VDD = 2.7 to 5.5 V P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET VDD = 2.7 to 5.5 V P30 to P33 (N-ch open-drain) VDD = 2.7 to 5.5 V X1, X2 VDD = 2.7 to 5.5 V XT1, XT2 VDD = 4.0 to 5.5 V P10 to P17, P21, P24, P35, P40 to P47, P50 to P57, P64 to P67, P74, P75 VDD = 2.7 to 5.5 V P00 to P03, P20, P22, P23, P25, P34, P36, P70 to P73, RESET VDD = 2.7 to 5.5 V P30 to P33 4.0 V ≤ VDD ≤ 5.5 V 0 0.3 VDD V 2.7 V ≤ VDD < 4.0 V 0 0.2 VDD V 1.8 V ≤ VDD < 2.7 0 0.1 VDD V VDD = 2.7 to 5.5 V 0 0.4 V 0 0.2 V 0 0.2 VDD V X1, X2 VIL5 XT1, XT2 VDD = 4.0 to 5.5 V 0 0.1 VDD V Output voltage, high VOH1 VDD = 4.0 to 5.5 V, IOH = –1 mA VDD–1.0 VDD V I OH = –100 µ A VDD–0.5 VDD V Output voltage, low VOL1 2.0 V P30 to P33 VDD = 4.0 to 5.5 V, IOL = 15 mA P50 to P57 0.4 P00 to P03, P20 to P25, P34 to P36, P40 to P47, P64 to P67, P70 to P75 VOL2 VDD = 4.0 to 5.5 V, IOL = 1.6 mA I OL = 400 µA 2.0 V 0.4 V 0.5 V Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 24 Data Sheet U14041EJ1V0DS00 µPD78F0034AY DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Input leakage current, high Symbol I LIH1 Conditions VIN = VDD I LIH2 Input leakage current, low MIN. TYP. P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET X1, X2, XT1, XT2 I LIH3 VIN = 5.5 V P30 to P33 I LIL1 VIN = 0 V P00 to P03, P10 to P17, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, RESET I LIL2 X1, X2, XT1, XT2 I LIL3 P30 to P33 MAX. Unit 3 µA 20 µA 3 µA –3 µA –20 µA –3 µA Output leakage current, low I LOH VOUT = VDD 3 µA Output leakage current, low I LOL VOUT = 0 V –3 µA Software pullup resistor R VIN = 0 V, P00 to P03, P20 to P25, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75 90 kΩ 15 30 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins . Data Sheet U14041EJ1V0DS00 25 µPD78F0034AY DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Supply Symbol IDD1 currentNote 1 Conditions 8.38-MHz crystal VDD = 5.0 V ± 10 %Note 2 VDD = 3.0 V ± 10 %Note 2 oscillation operating mode 5.00-MHz crystal oscillation operation mode VDD = 2.0 V IDD2 8.38-MHz crystal 10% Note 3 VDD = 5.0 V ± 10 %Note 2 VDD = 3.0 V ± 10 %Note 2 VDD = 2.0 V ± 10 %Note 3 oscillation HALT mode 5.00-MHz crystal MIN. TYP. MAX. Unit A/D converter stopped 10.5 21 mA A/D converter operating 11.5 23 mA A/D converter stopped 4.5 9 mA A/D converter operating 5.5 11 mA A/D converter stopped 1 2 mA A/D converter operating 2 6 mA 1.2 2.4 mA 5 mA 0.8 mA 1.7 mA 0.4 mA 1.1 mA Peripheral functions stopped Peripheral functions operating oscillation HALT mode Peripheral functions stopped 0.4 Peripheral functions operating Peripheral functions stopped 0.2 Peripheral functions operating IDD3 IDD4 IDD5 VDD = 5.0 V ± 10%Note 2 115 230 µA VDD = 3.0 V ± 10%Note 2 95 190 µA VDD = 2.0 V ± 10%Note 3 75 150 µA VDD = 5.0 V ± 10%Note 2 30 60 µA VDD = 3.0 V ± 10%Note 2 6 18 µA VDD = 2.0 V ± 10%Note 3 2 10 µA XT1 = 0 V, STOP mode VDD = 5.0 V ± 10%Note 2 0.1 30 µA When feed-back resistor not used VDD = 3.0 V ± 10%Note 2 0.05 10 µA VDD = 2.0 V ± 10%Note 3 0.05 10 µA 32.768-kHz crystal oscillation operating 32.768-kHz crystal oscillation HALT modeNote 4 modeNote 4 Notes 1. Refers to the total current flowing through the internal power supply (VDD0 and V DD1). Includes peripheral operating current (however, current flowing through the pull-up resistors of ports and the AVREF pin is not included). 2. When the processor clock control register (PCC) is set to 00H. 3. When PCC is set to 02H. 4. When the main system clock is stopped. 26 Data Sheet U14041EJ1V0DS00 µPD78F0034AY AC Characteristics (1) Basic operation (TA = –40 to +85 °C, V DD = 1.8 to 5.5 V) Parameter Symbol Cycle time TCY (Min. instruction Test Conditions Operating on main 4.0 ≤ VDD ≤ 5.5 V system clock 2.7 V ≤ VDD < 4.0 V execution time) TI00, TI01 input t TIH0, tTIL0 high-/low-level width TI50, TI51 input f TI5 t TIH5, tTIL5 Interrupt request input high-/low -level width t INTH, tINTL RESET low-level width t RSL TYP. MAX. Unit 0.24 16 µs 0.4 16 µs 1.6 16 µs 125 µs Operating on subsystem clock 103.9Note 1 4.0 V ≤ VDD ≤ 5.5 V 2/fsam + 0.1Note2 µs 2.7 V ≤ VDD < 4.0 V 2/fsam + 0.2Note2 µs 2/fsam + 0.5Note2 µs VDD = 2.7 to 5.5 V frequency TI50, TI51 input high-/low-level width MIN. VDD = 2.7 to 5.5 V INTP0 to INTP3, P40 to P47 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 122 0 4 MHz 0 275 kHz 100 ns 1.8 µs 1 µs 2 µs 10 µs 20 µs Notes 1. Value when using an external clock. When using a crystal resonator, the value becomes 114 µ s (MIN.). 2. Selection of f sam = fX , fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8. Data Sheet U14041EJ1V0DS00 27 µPD78F0034AY TCY vs V DD (main system clock) 16.0 Cycle time TCY [ µ s] 10.0 Operation Guaranteed Range 5.0 2.0 1.6 1.0 0.8 0.4 0.24 0.1 0 1.0 2.0 1.8 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] 28 Data Sheet U14041EJ1V0DS00 µPD78F0034AY (2) Read/write operation (T A = –40 to +85 °C, V DD = 4.0 to 5.5 V) (1/3) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width t ASTH 0.3t CY ns Address setup time t ADS 20 ns Address hold time tADH 6 ns Data input time from address t ADD1 (2 + 2n)tCY – 54 ns t ADD2 (3 + 2n)tCY – 60 ns 100 ns Address output time from RD↓ t RDAD 0 Data input time from RD↓ tRDD1 (2 + 2n)tCY – 87 ns tRDD2 (3 + 2n)tCY – 93 ns Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY – 33 ns tRDL2 (2.5 + 2n)tCY – 33 ns WAIT↓ input time from RD↓ WAIT↓ input time from WR↓ t RDWT1 t CY – 43 ns t RDWT2 t CY – 43 ns t WRWT t CY – 25 ns (2 + 2n)tCY ns WAIT low-level width tWTL (0.5 + n)t CY + 10 Write data setup time tWDS 60 ns Write data hold time t WDH 6 ns WR low-level width t WRL1 (1.5 + 2n)tCY – 15 ns RD↓ delay time from ASTB↓ t ASTRD 6 ns WR↓ delay time from ASTB↓ t ASTWR 2tCY – 15 ns ASTB↑ delay time from RD↑ in external fetch t RDAST 0.8tCY – 15 1.2t CY ns Address hold time from RD↑ in external fetch t RDADH 0.8t CY – 15 1.2t CY + 30 ns Write data output time from RD↑ tRDWD 40 Write data output time from WR↓ tWRWD 10 60 ns Address hold time from WR↑ t WRADH 0.8tCY – 15 1.2t CY + 30 ns RD↑ delay time from WAIT↑ t WTRD 0.8t CY 2.5t CY + 25 ns WR↑ delay time from WAIT↑ t WTWR 0.8t CY 2.5t CY + 25 ns ns Remarks 1. tCY = T CY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) Data Sheet U14041EJ1V0DS00 29 µPD78F0034AY (2) Read/write operation (T A = –40 to +85°C, V DD = 2.7 to 4.0 V) (2/3) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width t ASTH 0.3t CY ns Address setup time t ADS 30 ns Address hold time t ADH 10 ns Data input time from address t ADD1 (2 + 2n)tCY – 108 ns t ADD2 (3 + 2n)tCY – 120 ns 200 ns Address output time from RD↓ t RDAD 0 Data input time from RD↓ tRDD1 (2 + 2n)tCY – 148 ns tRDD2 (3 + 2n)tCY – 162 ns Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY – 40 ns tRDL2 (2.5 + 2n)tCY – 40 ns WAIT↓ input time from RD↓ WAIT↓ input time from WR↓ tRDWT1 t CY – 75 ns tRDWT2 t CY – 60 ns t WRWT t CY – 50 ns (2 + 2n)tCY ns WAIT low-level width t WTL (0.5 + 2n)tCY + 10 Write data setup time tWDS 60 ns Write data hold time tWDH 10 ns WR low-level width tWRL1 (1.5 + 2n)tCY – 30 ns RD↓ delay time from ASTB↓ t ASTRD 10 ns WR↓ delay time from ASTB↓ t ASTWR 2tCY – 30 ns ASTB↑ delay time from RD↑ in external fetch t RDAST 0.8t CY – 30 1.2t CY ns Address hold time from RD↑ in external fetch tRDADH 0.8t CY – 30 1.2t CY + 60 ns Write data output time from RD↑ tRDWD 40 Write data output time from WR↓ tWRWD 20 120 ns Address hold time from WR↑ t WRADH 0.8t CY – 30 1.2t CY + 60 ns RD↑ delay time from WAIT↑ t WTRD 0.5t CY 2.5t CY + 50 ns WR↑ delay time from WAIT↑ t WTWR 0.5t CY 2.5t CY + 50 ns ns Remarks 1. tCY = T CY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) 30 Data Sheet U14041EJ1V0DS00 µPD78F0034AY (2) Read/write operation (T A = –40 to +85°C, V DD = 1.8 to 2.7 V) (3/3) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width t ASTH 0.3t CY ns Address setup time t ADS 120 ns Address hold time t ADH 20 ns Data input time from address t ADD1 (2 + 2n)tCY – 233 ns t ADD2 (3 + 2n)tCY – 240 ns 400 ns Address output time from RD↓ t RDAD 0 Data input time from RD↓ tRDD1 (2 + 2n)tCY – 325 ns tRDD2 (3 + 2n)tCY – 332 ns Read data hold time tRDH 0 ns RD low-level width tRDL1 (1.5 + 2n)tCY – 92 ns tRDL2 (2.5 + 2n)tCY – 92 ns WAIT↓ input time from RD↓ WAIT↓ input time from WR↓ tRDWT1 t CY – 350 ns tRDWT2 t CY – 132 ns t WRWT t CY – 100 ns (2 + 2n)tCY ns WAIT low-level width t WTL (0.5 + 2n)tCY + 10 Write data setup time tWDS 60 ns Write data hold time tWDH 20 ns WR low-level width tWRL1 (1.5 + 2n)tCY – 60 ns RD↓ delay time from ASTB↓ t ASTRD 20 ns WR↓ delay time from ASTB↓ t ASTWR 2tCY – 60 ns ASTB↑ delay time from RD↑ at external fetch t RDAST 0.8t CY – 60 1.2t CY ns Address hold time from RD↑ at external fetch tRDADH 0.8t CY – 60 1.2tCY + 120 ns Write data output time from RD↑ tRDWD 40 Write data output time from WR↓ tWRWD 40 240 ns Address hold time from WR↑ t WRADH 0.8t CY – 60 1.2tCY + 120 ns RD↑ delay time from WAIT↑ t WTRD 0.5t CY 2.5tCY + 100 ns WR↑ delay time from WAIT↑ t WTWR 0.5t CY 2.5tCY + 100 ns ns Remarks 1. tCY = T CY/4 2. n indicates the number of waits. 3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB pins.) Data Sheet U14041EJ1V0DS00 31 µPD78F0034AY (3) Serial interface (TA = –40 to +85°C, V DD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (SCK30... internal clock output) Parameter SCK30 cycle time SCK30 high-/low-level width Symbol t KCY1 t KH1 Conditions SI30, SI31 hold time (from SCK30) S030 output delay time from SCK30 Note t SIK1 TYP. MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V 954 ns 2.7 V ≤ VDD < 4.0 V 1600 ns 3200 ns t KCY1/2–50 ns t KCY1/2–100 ns 4.0 V ≤ VDD ≤ 5.5 V 100 ns 2.7 V ≤ VDD < 4.0 V 150 ns 300 ns VDD = 4.0 to 5.5 V t KL1 SI30 setup time (to SCK30) MIN. t KSI1 400 ns t KSO1 C = 100 pFNote 300 ns MAX. Unit C is the load capacitance of the SCK30 and SO30 output lines. (b) 3-wire serial I/O mode (SCK30... external clock input) Parameter SCK30 cycle time SCK30 high-/low-level width Symbol t KCY2 Conditions MIN. TYP. 4.0 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.0 V 1600 ns 3200 ns t KH2 4.0 V ≤ VDD ≤ 5.5 V 400 ns t KL2 2.7 V ≤ VDD < 4.0 V 800 ns 1600 ns SI30 setup time (to SCK30) t SIK2 100 ns SI30, SI31 hold time (from SCK30) t KSI2 400 ns SO30 output delay time from SCK30 t KSO2 Note 32 C = 100 pFNote C is the load capacitance of the SO30 output line. Data Sheet U14041EJ1V0DS00 300 ns µPD78F0034AY (c) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate Conditions MIN. TYP. MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V 131031 bps 2.7 V ≤ VDD < 4.0 V 78125 bps 39063 bps MAX. Unit (d) UART mode (External clock input) Parameter Symbol ASCK0 cycle time t KCY3 Conditions MIN. TYP. 4.0 V ≤ VDD ≤ 5.5 V 800 ns 2.7 V ≤ VDD < 4.0 V 1600 ns 3200 ns ASCK0 high-/low-level t KH3, 4.0 V ≤ VDD ≤ 5.5 V 400 ns width t KL3 2.7 V ≤ VDD < 4.0 V 800 ns 1600 ns Transfer rate 4.0 V ≤ VDD ≤ 5.5 V 39063 bps 2.7 V ≤ VDD < 4.0 V 19531 bps 9766 bps MAX. Unit (e) UART mode (Infrared data transfer mode) Parameter Symbol Conditions MIN. Transfer rate VDD = 4.0 to 5.5 V 131031 bps Bit rate allowable error VDD = 4.0 to 5.5 V ±0.87 % Output pulse width VDD = 4.0 to 5.5 V 1.2 0.24/fbrNote µs Input pulse width VDD = 4.0 to 5.5 V 4/f X Note µs fbr: set baud rate Data Sheet U14041EJ1V0DS00 33 µPD78F0034AY (f) I2C bus Mode Standard Mode Parameter High-speed Mode Symbol Unit MIN. MAX. MIN. MAX. SCL0 clock frequency f CLK 0 100 0 400 kHz Bus free time (between stop and start condition) t BUF 4.7 — 1.3 — µs Hold timeNote 1 t HD:STA 4.0 — 0.6 — µs SCL0 clock low-level width t LOW 4.7 — 1.3 — µs SCL0 clock high-level width t HIGH 4.0 — 0.6 — µs Start/restart condition setup time tSU:STA 4.7 — 0.6 — µs Data hold time t HD:DAT 5.0 — — — µs — 0Note 2 0.9Note 3 µs — 100Note 4 CBUS compatible master I 2C 0Note 2 bus Data setup time t SU:DAT SDA0 and SCL0 signal rise time tR 250 — 1000 — ns Note 5 300 ns 0.1CbNote 5 300 ns 20 + 0.1Cb SDA0 and SCL0 signal fall time tF — 300 20 + Stop condition setup time t SU:STO 4.0 — 0.6 — µs Spike pulse width controlled by input filter t SP — — 0 50 ns Capacitive load per each bus line Cb — 400 — 400 pF Notes 1. In the start condition, the first clock pulse is generated after this hold time. 2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal). 3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time t HD:DAT needs to be fulfilled. 4. The high-speed mode I2C bus is available in a standard mode I 2C bus system. At this time, the conditions described below must be satisfied. • If the device does not extend the SCL0 signal low state hold time tSU:DAT ≥ 250 ns • If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns by standard mode I2C bus specification). 5. Cb: Total capacitance per one bus line (unit: pF) 34 Data Sheet U14041EJ1V0DS00 µPD78F0034AY AC Timing Test Point (Excluding X1, XT1 Input) 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD Test points Clock Timing 1/fX tXL tXH VIH4 (MIN.) VIL4 (MAX.) X1 input 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.) XT1 input TI Timing tTIL0 tTIH0 TI00, TI01 1/fTI5 tTIL5 tTIH5 TI50, TI51 Data Sheet U14041EJ1V0DS00 35 µPD78F0034AY Read/Write Operation External Fetch (No Wait): A8 to A15 Higher 8-bit address tADD1 Hi-Z Lower 8-bit address AD0 to AD7 tADS Instruction code tRDAD tRDD1 tADH tRDADH tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH External Fetch (Wait Insertion): A8 to A15 Higher 8-bit address tADD1 AD0 to AD7 Hi-Z Lower 8-bit address tADS tADH tRDAD Instruction code tRDADH tRDD1 tASTH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 36 tWTL Data Sheet U14041EJ1V0DS00 tWTRD µPD78F0034AY External Data Access (No Wait): A8 to A15 Higher 8-bit address tADD2 AD0 to AD7 Hi-Z tRDAD tRDD2 Lower 8-bit address tADS tADH Read data tASTH Hi-Z Write data tRDH ASTB RD tASTRD tRDWD tRDL2 tWDS tWDH tWRADH tWRWD WR tASTWR tWRL1 External Data Access (Wait Insertion): A8 to A15 Higher 8-bit address tADD2 AD0 to AD7 Lower 8-bit address tADS tADH tASTH Hi-Z Read data Hi-Z Write data tRDAD tRDH tRDD2 ASTB tASTRD RD tRDWD tRDL2 tWDS tWDH tWRWD WR tASTWR tWRL1 tWRADH WAIT tRDWT2 tWTL tWTRD tWTL tWRWT Data Sheet U14041EJ1V0DS00 tWTWR 37 µPD78F0034AY Serial Transfer Timing 3-Wire Serial I/O Mode: tKCYm tKLm tKHm SCK30 tSIKm SI30 tKSIm Input data tKSOm SO30 Output data m = 1, 2 UART Mode (External Clock Input): t KCY3 t KL3 t KH3 ASCK0 I2C Bus Mode: tLOW tR SCL0 tHD:DAT tHD:STA tHIGH tSU:DAT tF tSU:STA tHD:STA tSP tSU:STO SDA0 tBUF Stop condition 38 Start condition Restart condition Data Sheet U14041EJ1V0DS00 Stop condition µPD78F0034AY A/D Converter Characteristics (T A = –40 to +85 °C, V DD = AVDD = AVREF = 1.8 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 10 10 10 bit 4.0 V ≤ AVREF ≤ 5.5 V ±0.2 ±0.4 %FSR 2.7 V ≤ AVREF < 4.0 V ±0.3 ±0.6 %FSR 1.8 V ≤ AVREF < 2.7 V ±0.6 ±1.2 %FSR Resolution Overall errorNotes 1, 2 Conversion time Zero-scale Full-scale t CONV offsetNotes 1, 2 offsetNotes 1, 2 Integral linearity errorNote 1 Differential linearity errorNote 1 Analog input voltage VIAN Reference voltage AVREF Resistance between AVREF and AVSS RREF 4.0 V ≤ AVREF ≤ 5.5 V 14 96 µs 2.7 V ≤ AVREF < 4.0 V 19 96 µs 1.8 V ≤ AVREF < 2.7 V 28 96 µs 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR 1.8 V ≤ AVREF < 2.7 V ±1.2 %FSR 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR 1.8 V ≤ AVREF < 2.7 V ±1.2 %FSR 4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB 2.7 V ≤ AVREF < 4.0 V ±4.5 LSB 1.8 V ≤ AVREF < 2.7 V ±8.5 LSB 4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB 2.7 V ≤ AVREF ≤ 4.0 V ±2.0 LSB 1.8 V ≤ AVREF < 2.7 V ±3.5 LSB 0 AVREF V 1.8 AVDD V A/D conversion is not performed 20 40 kΩ Notes 1. Excluding quantization error (±1/2 LSB). 2. Shown as a percentage of the full scale value. Remark When the µ PD78F0034AY is used as an 8-bit resolution A/D converter, the specifications are the same as for the µ PD780024AY Subseries A/D converter. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current I DDDR Release signal set time t SREL Oscillation stabilization wait time t WAIT Note Test Conditions MIN. TYP. 1.6 VDDDR = 1.6 V Subsystem clock unassigned and feed-back resistor disconnected 0.1 MAX. Unit 5.5 V 30 µA µs 0 Release by RESET 217/fx ms Release by interrupt request Note ms Selection of 212 /fX and 214 /fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Data Sheet U14041EJ1V0DS00 39 µPD78F0034AY Data Retention Timing (STOP Mode Release by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (Interrupt request) tWAIT 40 Data Sheet U14041EJ1V0DS00 µPD78F0034AY Interrupt Request Input Timing tINTH tINTL INTP0 to INTP2 tINTL INTP3 RESET Input Timing tRSL RESET Data Sheet U14041EJ1V0DS00 41 µPD78F0034AY Flash Memory Programming Characteristics (VDD = 2.7 to 5.5 V, V SS = 0 V, VPP = 9.7 to 10.3 V) (1) Basic characteristics Parameter Operating frequency Symbol fX Supply voltage Conditions MIN. MAX. Unit 4.0 ≤ VDD ≤ 5.5 V 1.0Note 1 TYP. 8.38 MHz 2.7 ≤ VDD < 4.0 V 1.0Note 1 5.0 MHz 2.7 5.5 V 0.2 VDD V VDD Operation voltage when writing VPPL Upon VPP low-level detection 0 VPP Upon VPP high-level detection 0.8 VDD VDD 1.2 VDD V Upon VPP high-voltage detection 9.7Note 2 10.0Note 2 10.3Note 2 V 10 mA 100 mA 500 µs 20Note 3 Times 1 20 s +10 +40 °C VPPH VDD supply current I DD VPP supply current I PP Write time (per byte) TWRT VPP =10.0 V 75 50 Number of rewrites CWRT Erase time TERASE Programming temperature TPRG Notes 1. When writing to flash memory by using I2 C bus, the operating frequency is 4.19 MHz (MIN.). 2. For the products specified as K, E, or P, 10.2 V (MIN.), 10.3 V (TYP.), and 10.4 V (MAX.) are applied. 3. For the products specified as K or E, the number is 1 (MAX.). (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit VPP set time t PSRON VPP high voltage 1.0 µs VPP↑ set time from V DD↑ t DRPSR VPP high voltage 1.0 µs RESET↑ set time from V PP↑ t PSRRF VPP high voltage 1.0 µs VPP count start time from RESET↑ t RFCF 1.0 µs Count execution time t COUNT VPP counter high-level width tCH 8.0 µs VPP counter low-level width t CL 8.0 µs VPP counter noise elimination width t NFW 2.0 40 Flash Memory Write Mode Set Timing VDD VDD 0V tDRPSR tRFCF tCH VPPH VPP VPP tCL VPPL tPSRON tPSRRF tCOUNT VDD RESET (input) 0V 42 Data Sheet U14041EJ1V0DS00 ms ns µPD78F0034AY 6. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 32 A K J L I H F D C N B M R M G NOTES 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 3. Item "K" to center of leads when formed parallel. ITEM MILLIMETERS INCHES A 58.0 +0.68 –0.20 2.283 +0.028 –0.008 B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.) D 0.50±0.10 0.020 +0.004 –0.005 F 0.9 MIN. 0.035 MIN. G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN. I 4.05 +0.26 –0.20 0.159 +0.011 –0.008 J 5.08 MAX. 0.200 MAX. K 19.05 (T.P.) 0.750 (T.P.) L 17.0±0.2 0.669 +0.009 –0.008 M 0.25 +0.10 –0.05 0.010 +0.004 –0.003 N 0.17 0.007 R 0 to 15° 0 to 15° P64C-70-750A,C-3 Remark The package and material of ES products are the same as mass produced products. Data Sheet U14041EJ1V0DS00 43 µPD78F0034AY 64 PIN PLASTIC QFP ( 14) A B 48 49 33 32 detail of lead end S C D Q 64 1 R 17 16 F J G H I M P K S N S L M NOTE 1. Controlling dimension ITEM millimeter. 2. Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 17.6±0.4 B 14.0±0.2 0.693±0.016 0.551 +0.009 –0.008 C 14.0±0.2 0.551 +0.009 –0.008 D 17.6±0.4 0.693±0.016 F G 1.0 1.0 0.039 0.039 H 0.37 +0.08 –0.07 0.015 +0.003 –0.004 0.006 I 0.15 J 0.8 (T.P.) 0.031 (T.P.) K 1.8±0.2 0.071±0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.17 +0.08 –0.07 0.007 +0.003 –0.004 N 0.10 0.004 P 2.55±0.1 0.100±0.004 Q 0.1±0.1 0.004±0.004 R S 5°±5° 2.85 MAX. 5°±5° 0.113 MAX. P64GC-80-AB8-4 Remark The package and material of ES products are the same as mass produced products. 44 Data Sheet U14041EJ1V0DS00 µPD78F0034AY 64 PIN PLASTIC LQFP (12x12) A B 48 49 33 32 detail of lead end S C D R Q 64 17 16 1 F J G H I M ITEM K P S N S L M NOTES 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS INCHES A 14.8±0.4 0.583±0.016 B 12.0±0.2 0.472+0.009 −0.008 C 12.0±0.2 0.472+0.009 −0.008 D F 14.8±0.4 1.125 0.583±0.016 0.044 G 1.125 0.044 H 0.32±0.08 0.013+0.003 −0.004 I J K 0.13 0.65 (T.P.) 1.4±0.2 0.005 0.026 0.055±0.008 L 0.6±0.2 0.024+0.008 −0.009 M 0.17 +0.08 −0.07 0.007+0.003 −0.004 N 0.10 0.004 P 1.4±0.1 0.055+0.004 −0.005 Q R S 0.125±0.075 5°±5° 1.7 MAX. 0.005±0.003 5°±5° 0.067 MAX. P64GK-65-8A8-2 Remark The package and material of ES products are the same as mass produced products. Data Sheet U14041EJ1V0DS00 45 µPD78F0034AY 7. RECOMMENDED SOLDERING CONDITIONS The µ PD78F0034AY should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 7-1. Surface Mounting Type Soldering Conditions (1) µPD78F0034AYGC-AB8: 64-pin plastic QFP (14 × 14 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds Max. (at 210°C or higher), Count: Two times or less IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 seconds Max. (at 200°C or higher), Count: Two times or less VP15-00-2 Wave soldering Solder bath temperature: 260°C Max., Time: 10 seconds Max., Count: Once, Preheating temperature: 120°C Max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C Max., Time: 3 seconds Max. (per pin row) – Caution Do not use different soldering methods together (except for partial heating). (2) µPD78F0034AYGK-8A8: 64-pin plastic LQFP (12 × 12 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds Max. (at 210°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after 7 days, prebake at 125°C for 10 hours) IR35-107-2 VPS Package peak temperature: 215°C, Time: 40 seconds Max. (at 200°C or higher), Count: Two times or less, Exposure limit: 7 daysNote (after 7 days, prebake at 125°C for 10 hours) VP15-107-2 Wave soldering Solder bath temperature: 260°C Max., Time: 10 seconds Max., Count: Once, Preheating temperature: 120°C Max. (package surface temperature) Exposure limit: 7 daysNote (after 7 days, prebake at 125°C for 10 hours) WS60-107-1 Partial heating Pin temperature: 300°C Max., Time: 3 seconds Max. (per pin row) Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 46 – Data Sheet U14041EJ1V0DS00 µPD78F0034AY Table 7-2. Through-Hole Type Soldering Conditions µ PD78F0034AYCW: 64-pin plastic shrink DIP (750 mils) Soldering Method Soldering Conditions Wave soldering (pin only) Solder bath temperature: 260°C Max., Time: 10 seconds Max. Partial heating Pin temperature: 300°C Max., Time: 3 seconds Max. (per pin row) Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. Data Sheet U14041EJ1V0DS00 47 µPD78F0034AY APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µ PD78F0034AY Subseries. Also refer to (5) Cautions on Using Development Tools. (1) Language Processing Software RA78K/0 Assembler package common to 78K/0 Series CC78K/0 C compiler package common to 78K/0 Series DF780034 Device file common to µ PD780034A Subseries CC78K/0-L C compiler library source file common to 78K/0 Series (2) Flash Memory Writing Tools Flashpro II (type No. FL-PR2), Flashpro III (type No. FL-PR3, PG-FP3) Flash programmer dedicated to microcontrollers with on-chip flash memory FA-64CW, FA-64GC, FA-64GK Adapter for flash memory writing (3) Debugging Tools When IE-78K0-NS in-circuit emulator is used IE-78K0-NS In-circuit emulator common to 78K/0 Series IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-78K0-NS-PANote Performance board that enhances and expands the IE-78K0-NS functions IE-70000-98-IF-C Interface adapter used when PD-9800 Series PC (except notebook type) is used as host machine (C bus supported) IE-70000-CD-IF-A PC card and interface cable when PC-9800 Series notebook PC is used as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/ATTM or compatible as host machine (ISA bus supported) IE-70000-PCI-IF Adapter necessary when using PCI-bus incorporated personal computer as host machine IE-780034-NS-EM1 Emulation board to emulate the µPD780034AY Subseries NP-64CW Emulation probe for 64-pin plastic shrink DIP (CW type) NP-64GC Emulation probe for 64-pin plastic QFP (CG-AB8 type) NP-64GK Emulation probe for 64-pin plastic LQFP (CG-8A8 type) TGK-064SBW Conversion adapter to connect the NP-64GK and a target system board on which the 64-pin plastic LQFP (GC-8A8 type) can be mounted EV-9200GC-64 Socket mounted on target system board for the 64-pin plastic QFP (GC-AB8 type) ID78K0-NS Integrated debugger for IE-78K0-NS SM78K0 System simulator common to 78K/0 Series DF780034 Device file common to µ PD780034A Subseries Note 48 Under development Data Sheet U14041EJ1V0DS00 µPD78F0034AY When using in-circuit emulator IE-78001-R-A IE-78001-R-A In-circuit emulator common to 78K/0 Series IE-70000-98-IF-C Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported) IE-70000-PCI-IF Adapter necessary when using PCI-bus incorporated personal computers as host machine. IE-78000-R-SV3 Interface adapter and cable when using EWS as host machine IE-780034-NS-EM1 Emulation board to emulate µPD780034AY Subseries IE-78K0-R-EX1 Emulation probe conversion board to use IE-780034-NS-EM1 on IE-78001-R-A EP-78240CW-R Emulation probe for 64-pin plastic shrink DIP (CW type) EP-78240GC-R Emulation probe for 64-pin plastic QFP (GC-AB8 type) EP-78012GK-R Emulation probe for 64-pin plastic LQFP (GK-8A8 type) TGK-064SBW Conversion adapter for connecting target system board designed to allow mounting of 64-pin plastic LQFP (GK-8A8) and NP-64GK. EV-9200GC-64 Socket to be mounted on target system board manufactured for 64-pin plastic QFP (GC-AB8 type) ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator common to 78K/0 Series DF780034 Device file common to µ PD780034A Subseries (4) Real-time OS RX78K/0 Real-time OS for 78K/0 Series MX78K0 OS for 78K/0 Series Data Sheet U14041EJ1V0DS00 49 µPD78F0034AY (5) Cautions on using development tools • The ID-78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034. • The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and the DF780034. • The FL-PR2, FL-PR3, FA-64CW, FA-64GC, FA64GK, NP-64CW, NP64GC, and NP-64GK are products made by Naito Densei Machida Mfg. Co., Ltd. (+81-44-822-3813). Contact an NEC distributor regarding the purchase of these products. • The TGK-064SBW is a product made by TOKYO ELETECH CORPORATION. For further information contact Daimaru Kogyo, Ltd. Tokyo Electronic Division (+81-3-3820-7112) Osaka Electronic Division (+81-6-6244-6672) • For third party development tools, see the 78K/0 Series Selection Guide (U11126E). • The host machines and OSs supporting each software are as follows. Host Machine PC EWS Software PC-9800 series [WindowsTM] IBM PC/AT or compatibles [Japanese/English Windows] HP9000 series 700 TM [HP-UXTM] SPARCstationTM [SunOSTM, SolarisTM] NEWSTM (RISC) [NEWS-OSTM] RA78K/0 √Note √ CC78K/0 √Note √ ID78K0-NS √ – ID78K0 √ √ SM78K0 √ – RX78K/0 √Note √ MX78K0 √Note √ [OS] Note 50 DOS-based software Data Sheet U14041EJ1V0DS00 µPD78F0034AY Conversion Socket Drawing (EV-9200GC-64) and Footprints Figure A-1. EV-9200GC-64 Drawing (For Reference Only) A N O L K T J C D S F Q M R B E EV-9200GC-64 1 P No.1 pin index G H I EV-9200GC-64-G0 ITEM MILLIMETERS INCHES A 18.8 0.74 B 14.1 0.555 C 14.1 0.555 D 18.8 0.74 E 4-C 3.0 4-C 0.118 F 0.8 0.031 G 6.0 0.236 H 15.8 0.622 I 18.5 0.728 J 6.0 0.236 K 15.8 0.622 L 18.5 0.728 M 8.0 0.315 N 7.8 0.307 O 2.5 0.098 P 2.0 0.079 Q 1.35 0.053 R 0.35 ± 0.1 0.014 +0.004 –0.005 S φ 2.3 φ 0.091 T φ 1.5 φ 0.059 Data Sheet U14041EJ1V0DS00 51 µPD78F0034AY Figure A-2. EV-9200GC-64 Footprints (For Reference Only) G J H D E F K I L C B A EV-9200GC-64-P1E ITEM MILLIMETERS A 19.5 0.768 B 14.8 0.583 C +0.003 0.8±0.02 × 15=12.0±0.05 0.031+0.002 –0.001 × 0.591=0.472 –0.002 D +0.003 0.8±0.02 × 15=12.0±0.05 0.031+0.002 –0.001 × 0.591=0.472 –0.002 E 14.8 0.583 F 19.5 0.768 G 6.00 ± 0.08 0.236 +0.004 –0.003 H 6.00 ± 0.08 0.236 +0.004 –0.003 I 0.5 ± 0.02 0.197 +0.001 –0.002 J φ 2.36 ± 0.03 φ 0.093 +0.001 –0.002 K φ 2.2 ± 0.1 φ 0.087 +0.004 –0.005 L φ 1.57 ± 0.03 φ 0.062 +0.001 –0.002 Caution 52 INCHES DimensionsofmountpadforEV-9200andthatfortargetdevice (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Data Sheet U14041EJ1V0DS00 µPD78F0034AY Conversion Adapter Drawing (TGK-064SBW) Figure A-3. TGK-064SBW Drawing (For Reference Only) A B K L X M C T G F E D H I J Protrusion height U S V Q W R N O P a Z e Y d k j h i c b f g ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES 18.4 0.724 a φ 0.3 φ 0.012 B 0.65x15=9.75 0.026x0.591=0.384 b 1.85 0.073 C D 0.65 0.026 0.305 c d 3.5 2.0 0.138 0.079 0.400 0.494 0.589 e f 3.9 1.325 0.154 0.052 A E F G 7.75 10.15 12.55 14.95 g 1.325 0.052 H I 0.65x15=9.75 11.85 0.026x0.591=0.384 0.467 h i 5.9 0.8 0.232 0.031 J K 18.4 C 2.0 0.724 C 0.079 j k 2.4 2.7 0.094 0.106 L M 12.45 10.25 0.490 0.404 N O 7.7 10.02 0.303 0.394 P 14.92 0.587 Q R 11.1 1.45 0.437 0.057 S 1.45 0.057 T 4- φ 1.3 U 1.8 4-φ 0.051 0.071 V 5.0 0.197 W φ 5.3 φ 0.209 X 4-C 1.0 4-C 0.039 Y Z φ 3.55 φ 0.9 φ 0.140 φ 0.035 TGK-064SBW-G0E Note: Product made by TOKYO ELETECH CORPORATION. Data Sheet U14041EJ1V0DS00 53 µPD78F0034AY APPENDIX B. RELATED DOCUMENTS Device Related Documents Document Name Document No. (English) Document No. (Japanese) µ PD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual U14046E U14046J µ PD780031AY, 780032AY, 780033AY, 780034AY Data Sheet U14043E U14043J µ PD78F0034AY Data Sheet This manual U14041J 78K/0 Series User’s Manual Instruction U12326E U12326J 78K/0 Series Instruction Table — U10903J 78K/0 Series Instruction Set — U10904J Development Tool Documents (User’s Manuals) Document Name RA78K0 Assembler Package Document No. (English) Document No. (Japanese) Operation U11802E U11802J Assembly Language U11801E U11801J Structured Assembly Language U11789E U11789J RA78K Series Structured Assembler Preprocessor EEU-1402 U12323J Operation U11517E U11517J Language U11518E U11518J Programming Know-how U13034E U13034J IE-78K0-NS To be prepared To be prepared IE-78001-R-A To be prepared To be prepared IE-780034-NS-EM1 To be prepared To be prepared EP-78240 U10332E EEU-986 EP-78012GK-R EEU-1538 EEU-5012 CC78K/0 C Compiler CC78K/0 C Compiler Application Note SM78K0 System Simulator-Windows based Reference U10181E U10181J SM78K Series System Simulator External Part User Open Interface Specifications U10092E U10092J ID78K0-NS Integrated Debugger Windows based Reference U12900E U12900J ID78K0 Integrated Debugger EWS based Reference ID78K0 Integrated Debugger PC based Reference U11539E U11539J ID78K0 Integrated Debugger Windows based Guide U11649E U11649J — U11151J Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing. 54 Data Sheet U14041EJ1V0DS00 µPD78F0034AY Embedded Software Documents (User’s Manuals) Document Name 78K/0 Series Real-time OS 78K/0 Series OS MX78K0 Document No. (English) Document No. (Japanese) Fundamental U11537E U11537J Installation U11536E U11536J Fundamental U12257E U12257J Other Documents Document Name Document No. (English) Document No. (Japanese) SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892J Guide to Microcomputer - Related Products by Third Party — U11416J Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing. Data Sheet U14041EJ1V0DS00 55 µPD78F0034AY [MEMO] 56 Data Sheet U14041EJ1V0DS00 µPD78F0034AY [MEMO] Data Sheet U14041EJ1V0DS00 57 µPD78F0034AY NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC I2 C components conveys a license under the Philips I2 C patent Rights to use these components in an I2 C system, provided that the system conforms to the I 2 C Standard Specification as defined by Philips. 58 Data Sheet U14041EJ1V0DS00 µPD78F0034AY Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U14041EJ1V0DS00 59 µ PD78F0034AY FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98.8