V55C2256164VB 256Mbit MOBILE SDRAM 2.5 VOLT FBGA PACKAGE 16M X 16 7 8PC 10 System Frequency (fCK) 143 MHz 125 MHz 100MHz Clock Cycle Time (tCK3) 7 ns 8 ns 10 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 6 ns 7 ns Clock Access Time (tAC2) CAS Latency = 2 6 ns 6 ns 8 ns Clock Access Time (tAC1) CAS Latency = 1 19 ns 19 ns 22 ns ■ Programmable Power Reduction Feature by partial array activation during Self-Refresh ■ Operating Temperature Range Commercial (0°C to 70°C) Industrial (-40°C to +85°C) Features ■ 4 banks x 4Mbit x 16 organization ■ High speed data transfer rates up to 143 MHz ■ Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge ■ Single Pulsed RAS Interface ■ Data Mask for Read/Write Control ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency:1, 2, 3 ■ Programmable Wrap Sequence: Sequential or Interleave ■ Programmable Burst Length: 1, 2, 4, 8, Full page for Sequential Type 1, 2, 4, 8 for Interleave Type ■ Multiple Burst Read with Single Write Operation ■ Automatic and Controlled Precharge Command ■ Random Column Address every CLK (1-N Rule) ■ Power Down Mode and Clock Suspend Mode ■ Deep Power Mode ■ Auto Refresh and Self Refresh ■ Refresh Interval: 8192 cycles/64 ms ■ Available in 54-ball FBGA, with 9x6 ball array with 3 depupulated rows, 13x8 mm and 54 pin TSOP II ■ VDD=2.5V, VDDQ=1.8V Device Usage Chart Operating Temperature Range Package Outline C/T 7 8PC 10 Temperature Mark 0°C to 70°C • • • • Commercial -40°C to 85°C • • • • Extended V55C2256164VB Rev. 1.0 April 2005 Access Time (ns) 1 ProMOS TECHNOLOGIES V55C2256164VB Part Number Information V 5 5 C 2 2 5 6 1 6 4 V B T 7 ORGANIZATION ProMOS & REFRESH OTHER 16Mx16, 8K : 25616 PC 53 : CL2 BLANK: CL3 TYPE DRAM 54 SDRAM TEMPERATURE 55 MOBILE SDRAM BLNK: 0 - 70C I: -40 - 85C E: -40 - 125C CMOS BANKS VOLTAGE SPEED 2 : 2 BANKS I/O V: LVTTL 3: 3.3 V 4 : 4 BANKS 2: 2.5 V 8 : 8 BANKS 1: 1.8 V 7 : 143MHz 8 : 125MHz: 6 : 166MHz 75 : 133MHz 5 : 200MHz REV LEVEL A: 1st C: 3rd PACKAGE B: 2nd D: 4th LEAD PLATING T V55C2256164VB Rev. 1.0 April 2005 10 : 100MHz LEAD FREE E GREEN PACKAGE DESC. I TSOP SPECIAL FEATURE S F J 60-Ball FBGA L: STANDARD LOW POWER C G K 54-Ball FBGA U: ULTRA LOW POWER B H M BGA TS TE TI Die-Stacked TSOP SS SF SI Die-Stacked FBGA 2 ProMOS TECHNOLOGIES V55C2256164VB Description Pkg. Pin Count C 54 FBGA 60 Pin WBGA PIN CONFIGURATION Top View Pin Configuration for x16 devices: 1 2 3 7 8 9 VSS DQ15 VSSQ A VDDQ DQ0 VDD DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5 DQ8 NC VSS E VDD LDQM DQ7 UDQM CLK CKE F CAS RAS WE A12 A11 A9 G BA0 BA1 CS A8 A7 A6 H A0 A1 A10 VSS A5 A4 J A3 A2 VDD < Top-view > V55C2256164VB Rev.1.0 April 2005 3 ProMOS TECHNOLOGIES V55C2256164VB Description TSOP-II Pkg. Pin Count T 54 54 Pin Plastic TSOP-II PIN CONFIGURATION Top View VCC I/O1 VCCQ NC I/O2 VSSQ NC I/O3 VCCQ NC I/O4 VSSQ NC VCC NC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Pin Names VSS I/O8 VSSQ NC I/O7 VCCQ NC I/O6 VSSQ NC I/O5 VCCQ NC VSS NC DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS 356804V-01 V55C2256164VB Rev. 1.0 April 2005 4 CLK Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable A0–A12 Address Inputs BA0, BA1 Bank Select I/O1–I/O16 Data Input/Output LDQM, UDQM Data Mask VCC Power (+3.3V) VSS Ground VCCQ Power for I/O’s (+3.3V) VSSQ Ground for I/O’s NC Not connected ProMOS TECHNOLOGIES V55C2256164VB Description The V55C2256164VB is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16. The V55C2256164VB achieves high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is possible depending on burst length, CAS latency and speed grade of the device. Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A12 Input Level — During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organization: • 8M x 16 SDRAM CA0–CA8. In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input Level — Selects which bank is to be active. DQx Input Output Level — Data Input/Output pins operate in the same manner as on conventional DRAMs. LDQM UDQM Input Pulse Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. VCC, VSS Supply VCCQ VSSQ Supply Power and ground for the input buffers and the core logic. — V55C2256164VB Rev. 1.0 April 2005 — Isolated power supply and ground for the output buffers to provide improved noise immunity. 5 ProMOS TECHNOLOGIES V55C2256164VB Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the thruth table for the operation commands. Device State CKE n-1 CKE n CS RAS CAS WE DQM A0-9, A11 A10 BS0 BS1 Idle3 H X L L H H X V V V Active3 H X L H L H X V L V Active 3 H X L H L H X V H V Write Active 3 H X L H L L X V L V Write with Autoprecharge Active3 H X L H L L X V H V Row Precharge Any H X L L H L X X L V Precharge All Any H X L L H L X X H X Mode Register Set Idle H X L L L L X V V V No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Auto Refresh Idle H H L L L H X X X X Self Refresh Entry Idle H L L L L H X X X X Idle (Self Refr.) H X X X L H L H H X X X X X Idle Active4 H X X X H L L H H X X X X X Any (Power Down) H X X X L H L H H L X X X X Data Write/Output Enable Active H X X X X X L X X X Data Write/Output Disable Active H X X X X X H X X X Idle H L L H H L H X X X Deep powerDown L H X X X X H X X X Operation Row Activate Read Read w/Autoprecharge Self Refresh Exit Power Down Entry Power Down Exit Deep Pwoer Down Entry Deep Pwoer Down Exit Notes: 1. V = Valid , x = Don’t Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. These are state of bank designated by BS0, BS1 signals. 4. Power Down Mode can not entry in the burst cycle. 5. After Deep Power Down mode exit a full new initialization of memory device is mandatory V55C2256164VB Rev. 1.0 April 2005 6 ProMOS TECHNOLOGIES V55C2256164VB rameters to be set as shown in the previous table. Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VCC and VCCQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of both banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register and Low Power Mode Register Set Command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable startup modes. Low Power Mode Register The Low Power Mode Register controls functions beyond those controlled by the Mode Register. These additional functions are unique to the LowPower DRM and includes a Refresh Period field (TCR) for temperature compensated self-refresh and a Partial-Array Self-Refresh field (PAS). The PASR field is used to specify whether only one quarter (bank 0), one half (bank 0+1) or all banks of the SDRAM array are enabled. Disabled banks will not be refreshed in Self-Refresh mode and written data will be lost. When only bank 0 is selected, it’s possible to partially select only half or mone quarter of bank 0. The TCR field has four entries to set Refresh Period during self-refresh depending on the case temperature of the Low power RAM. It’s required during the initialization seuqence and can be modified when the part id idle. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 125 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines pa- V55C2256164VB Rev.1.0 April 2005 7 ProMOS TECHNOLOGIES V55C2256164VB Address Input for Mode Set (Mode Register Operation) A12 ... A7 BA1 BA0 A6 Operation Mode A5 A4 A3 A2 CAS Latency BT Burst Length A0 Address Bus (Ax) Mode Register Burst Type Operation Mode BA1 BA0 A12 A11 A10 A9 A8 A7 Mode A3 Type 0 Sequential 1 Interleave 0 0 0 0 0 0 0 0 Burst Read/Burst Write 0 0 0 0 0 1 0 0 Burst Read/Single Write Burst Length CAS Latency A6 0 0 A5 0 0 A4 0 1 Length Latency A2 A1 A0 Reserve Sequential Interleave 0 0 0 1 1 2 0 0 1 2 2 4 1 0 1 0 0 1 1 3 0 1 0 4 1 0 0 Reserve 0 1 1 8 8 1 0 1 Reserve 1 0 0 Reserve Reserve 1 1 0 Reserve 1 0 1 Reserve Reserve 1 1 1 Reserve 1 1 0 Reserve Reserve 1 1 1 Full page Reserve with an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be done between different pages. Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies V55C2256164VB Rev. 1.0 April 2005 A1 8 ProMOS TECHNOLOGIES V55C2256164VB Low Power Mode Register Table BA1 BA0 1*) 0*) A12 to A5 A4 all have to be set to "0" A3 A2 TCR A1 Address Bus (Ax) A0 Mode Register PASR Self-Refresh: Temperature-Compensated A4 A3 Max case temp 0 0 70OC 0 1 45OC 1 0 15OC 1 1 85OC Partial-Array Self Refresh: A1 A0 banks to be self-refreshed 0 0 0 all banks 0 0 1 1/2 array (BA1=0) 0 1 0 1/4 array (BA1=0, BA0=0) 0 1 1 Reserved 1 0 0 Reserved 1 0 1 1/8 array (BA1=BA0=0, A11=0) 1 1 0 1/16 array (BA1=BA0=0, A11=A10=0) 1 1 1 Reserved A2 *)BA1 and BA0 must be 1, 0 to select the Extended Mode Register (Vs. the Mode Register) The Low Power Mode Register must be set during the initialization sequence. Once the device is operational, the Low Power Mode Register set can be issued anytime when the part is idle. V55C2256164VB Rev. 1.0 April 2005 9 ProMOS TECHNOLOGIES V55C2256164VB Burst Length and Sequence: Burst Starting Address Length (A2 A1 A0) 2 xx0 xx1 4 x00 x01 x10 x11 8 000 001 010 011 100 101 110 111 Full Page nnn Sequential Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3, 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 0, 1 1, 0 1, 2, 3, 0, 2, 3, 0, 1, 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 0, 1, 2, 3, 3 0 1 2 5 6 7 0 1 2 3 4 Cn, Cn+1, Cn+2 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 1, 0, 3, 2, 3 2 1 0 7 6 5 4 2, 3, 0, 1, 4 5 6 7 0 1 2 3 3 2 1 0 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Not supported a data mask function for writes. When DQM is a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for mode entry and exit. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for CAS latencies 2, two clocks for CAS latencies 3 and three clocks for CAS latencies 4. If CA10 is high when a Write Command is issued, the Write DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to “high” at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ ). It also provides V55C2256164VB Rev. 1.0 April 2005 Interleave Burst Addressing (decimal) 10 ProMOS TECHNOLOGIES V55C2256164VB with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (Write recovery time) after the last data in. Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid I/O contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the I/O pins before the Burst Stop Command is registered will be written to the memory. Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS latency = 3. Writes require a time delay twr from the last data out to apply the precharge command. Bank Selection by Address Bits: A10 BA0 BA1 0 0 0 Bank 0 0 0 1 Bank 1 0 1 0 Bank 2 0 1 1 Bank 3 1 X X all Banks Deep Power Down Mode TheDeep Power Down mode is an unique functi on with very low standby currents. All internal volat ge generators inside the RAM are stopped and all memory data is lost in this mode. To enter the Deep Power Down mode all banks must be precharged. Recommended Operation and Characteristics TA = 0 to 70 °C(Commercial)/-40 to 85 °C(Extended); VSS = 0 V; VCC= 2.5 V,VCCQ = 1.8V Limit Values Parameter Symbol min. max. Unit VCC 2.3 2.9 V I/O Supply Voltage VCCQ 1.65 2.9 V 1, 2 Input high voltage VIH 0.8xVCCQ Vcc+0.3 V 1, 2 Input low voltage VIL – 0.3 0.3 V 1, 2 Output high voltage (IOUT = – 4.0 mA) VOH VCCQ-0.2 – V Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) –5 5 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC ) IO(L) –5 5 µA Supply voltage Notes Note: 1. All voltages are referenced to VSS. 2. VIH may overshoot to VCC + 0.8 V for pulse width of < 4ns with 2.5V. VIL may undershoot to -0.8 V for pulse width < 4.0 ns with 2.5V. Pulse width measured at 50% points with amplitude measured peak to DC reference. V55C2256164VB Rev. 1.0 April 2005 11 ProMOS TECHNOLOGIES V55C2256164VB Absolute Maximum Ratings* Operating temperature range (commercial)0 to 70 °C Operating temperature range (extended) -25 to 85 °C Storage temperature range ............... -55 to 150 °C Input/output voltage .................. -0.3 to (VCC+0.3) V Power supply voltage .......................... -0.3 to 3.6 V Power dissipation .......................................... 0.7 W Data out current (short circuit) ...................... 50 mA *Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Currents TA = 0 to 70 °C(Commercial)/-40 to 85 °C(Extended); VSS = 0 V; VCC= 2.5 V,VCCQ = 1.8V(Recommended Operating Conditions unless otherwise noted) Max. Symbol Parameter & Test Condition -7 -8PC 10 Unit Note ICC1 Operating Current tRC = tRCMIN., tRC = tCKMIN. Active-precharge command cycling, without Burst Operation 1 bank operation 110 100 90 mA 7 Precharge Standby Current in Power Down Mode CS =VIH, CKE≤ VIL(max) tCK = min. 0.5 0.5 0.5 mA 7 tCK = Infinity 0.5 0.5 0.5 mA 7 Precharge Standby Current in Non-Power Down Mode ICC2NS CS =VIH, CKE≥ VIL(max) tCK = min. 20 20 20 mA tCK = Infinity 5 5 5 mA CKE ≥ VIH(MIN.) 25 25 25 mA CKE ≤ VIL(MAX.) (Power down mode) 5 5 5 mA ICC2P ICC2PS ICC2N ICC3N ICC3P No Operating Current tCK = min, CS = VIH(min) bank ; active state ( 4 banks) ICC4 Burst Operating Current tCK = min Read/Write command cycling 110 90 70 mA 7,8 ICC5 Auto Refresh Current tCK = min Auto Refresh command cycling 165 155 150 mA 7 ICC7 Deep Power down Current 10 10 10 uA Notes: 7. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 8. These parameter depend on output loading. Specified values are obtained with output open. V55C2256164VB Rev. 1.0 April 2005 12 ProMOS TECHNOLOGIES V55C2256164VB Temperature Compensated/Partial Array Self-Refresh Currents Parameter & Test Condition Self Refresh Current Self refresh Mode CKE=0.2V, tck=infinity, full array activations, all banks Self Refresh Current Self refresh Mode CKE=0.2V, tck=infinity, 1/2 array activations, Bank 0+1 Self Refresh Current Self refresh Mode CKE=0.2V, tck=infinity, 1/4 array activations, Bank 0 Self Refresh Current Self refresh Mode CKE=0.2V, tck=infinity, 1/8 array activations, Bank 0 Self Refresh Current Self refresh Mode CKE=0.2V, tck=infinity, 1/16 array activations, Bank 0 V55C2256164VB Rev. 1.0 April 2005 Symb. Max. Unit ICC6 900 uA 70OC max 600 uA 45OC max 500 uA 15OC max 400 uA 600 uA 70OCmax 500 uA 45OC max 400 uA 15OCmax 350 uA 450 uA 70OC max 420 uA 45OC max 350 uA 15OC max 300 uA 400 uA 70OC max 350 uA 45OC max 310 uA 15OC max 290 uA 350 uA 70OC max 320 uA 45OC max 295 uA 15OC max 280 uA Extended Mode Register M[4:3] Tcase[OC] 85OC max 85OC max ICC6 85OC max ICC6 85OC max ICC6 85OC max ICC6 13 ProMOS TECHNOLOGIES V55C2256164VB AC Characteristics 1,2, 3 TA = 0 to 70 °C(Commercial)/-40 to 85 °C(Extended);VSS = 0 V; VCC= 2.5 V,VCCQ = 1.8V, tT=1 ns Limit Values -8PC -7 # Symbol Parameter -10 Min. Max. Min. Max. Min. Max. Unit Clock Cycle Time CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 7 10 20 – – – 8 10 20 – – – 10 12 25 – – – ns ns ns Clock Frequency CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 – – – 143 100 50 – – – 125 100 50 – – – 100 83 40 MHz MHz MHz Access Time from Clock CAS Latency = 3 CAS Latency = 2 CAS Latency = 1 – _ _ 5.4 6 19 – _ _ 6 6 19 – _ _ 7 8 22 ns ns ns Note Clock and Clock Enable 1 2 3 tCK tCK tAC 2, 4 4 tCH Clock High Pulse Width 2.5 – 3 – 3 – ns 5 tCL Clock Low Pulse Width 2.5 – 3 – 3 – ns 6 tT Transition Tim 0.3 1.2 0.5 10 0.5 10 ns Setup and Hold Times 7 tIS Input Setup Time 1.5 – 2 – 2.5 – ns 5 8 tIH Input Hold Time 0.8 – 1 – 1 – ns 5 9 tCKS Input Setup Time 1.5 – 2 – 2.5 – ns 5 10 tCKH CKE Hold Time 0.8 – 1 – 1 – ns 5 11 tRSC Mode Register Set-up Time 14 – 16 – 20 – ns 12 tSB Power Down Mode Entry Time 0 7 0 8 0 8 ns Row to Column Delay Time 15 – 20 – 20 – ns 6 Common Parameters 13 tRCD 14 tRP Row Precharge Time 15 – 20 – 20 – ns 6 15 tRAS Row Active Time 42 100K 45 100k 50 100k ns 6 16 tRC Row Cycle Time 60 – 60 – 70 – ns 6 17 tRRD Activate(a) to Activate(b) Command Period 14 – 16 – 20 – ns 6 18 tCCD CAS(a) to CAS(b) Command Period 1 – 1 – 1 – CLK V55C2256164VB Rev. 1.0 April 2005 14 ProMOS TECHNOLOGIES V55C2256164VB AC Characteristics (Cont’d) Limit Values -8PC -7 # Symbol Parameter -10 Min. Max. Min. Max. Min. Max. Unit Refresh Period (8192 cycles) — 64 — 64 — 64 ms Self Refresh Exit Time 1 — 1 — 1 — CLK Note Refresh Cycle 19 tREF 20 tSREX Read Cycle 21 tOH Data Out Hold Time 3 – 3 – 3 – ns 22 tLZ Data Out to Low Impedance Time 1 – 1 – 1 – ns 23 tHZ Data Out to High Impedance Time 3 7 3 7 3 7 ns 24 tDQZ DQM Data Out Disable Latency – 2 – 2 – 2 CLK Write Recovery Time 1 – 1 – 1 – CLK DQM Write Mask Latency 0 – 0 – 0 – CLK 2 7 Write Cycle 25 tWR 26 tDQW Notes for AC Parameters: 1. For proper power-up see the operation section of this data sheet. 2. AC timing tests are referenced to the 0.9V crossover point for VCCQ=1.8V components. The transition time is measured between VIH and V IL. All AC measurements assume tT = 1ns with the AC output load circuit shown in Figure 1. tCK VIH CLK VIL + 1.4 V tT tCS tCH 50 Ohm 1.4V COMMAND Z=50 Ohm tLZ I/O tAC tAC 50 pF tOH 1.4V OUTPUT tHZ Figure 1. 4. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter. 5. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter. 6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. V55C2256164VB Rev. 1.0 April 2005 15 ProMOS TECHNOLOGIES V55C2256164VB Timing Diagrams 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. Burst Termination 8.1 Termination of a Burst Write Operation 8.2 Termination of a Burst Write Operation 9. AC- Parameters 9.1 AC Parameters for a Write Timing 9.2 AC Parameters for a Read Timing 10. Mode Register Set 11. Power on Sequence and Auto Refresh (CBR) 12. Power Down Mode 13. Self Refresh (Entry and Exit) 14. Auto Refresh (CBR) V55C2256164VB Rev. 1.0 April 2005 16 ProMOS TECHNOLOGIES V55C2256164VB Timing Diagrams (Cont’d) 15. Random Column Read ( Page within same Bank) 15.1 CAS Latency = 2 15.2 CAS Latency = 3 16. Random Column Write ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Row Read ( Interleaving Banks) with Precharge 17.1 CAS Latency = 2 17.2 CAS Latency = 3 18. Random Row Write ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Precharge Termination of a Burst 19.1 CAS Latency = 2 19.2 CAS Latency = 3 V55C2256164VB Rev. 1.0 April 2005 17 ProMOS TECHNOLOGIES V55C2256164VB 1. Bank Activate Command Cycle (CAS latency = 3) T0 T1 T T T T T CLK .......... ADDRESS Bank A Col. Addr. Bank A Row Addr. Bank A Row Addr. Bank B Row Addr. .......... tRCD COMMAND Bank A Activate tRRD NOP Write A with Auto Precharge NOP Bank B Activate .......... Bank A Activate NOP : “H” or “L” tRC 2. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A CAS latency = 2 tCK2, I/O’s CAS latency = 3 tCK3, I/O’s V55C2256164VB Rev. 1.0 April 2005 NOP NOP DOUT A0 NOP NOP DOUT A2 DOUT A1 DOUT A0 18 DOUT A1 NOP NOP DOUT A3 DOUT A2 DOUT A3 NOP NOP ProMOS TECHNOLOGIES V55C2256164VB 3. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 READ A READ B T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 NOP DOUT A0 tCK2, I/O’s CAS latency = 3 tCK3, I/O’s NOP NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 T3 T4 T5 T6 NOP NOP DOUT B3 4.1 Read to Write Interval (Burst Length = 4, CAS latency = 3) T0 T1 T2 T7 T8 CLK Minimum delay between the Read and Write Commands = 4+1 = 5 cycles tDQW DQM tDQZ COMMAND NOP I/O’s READ A NOP NOP NOP WRITE B DIN B0 DOUT A0 Must be Hi-Z before the Write Command : “H” or “L” V55C2256164VB Rev. 1.0 April 2005 NOP 19 NOP NOP DIN B1 DIN B2 ProMOS TECHNOLOGIES V55C2256164VB 4.2 Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK tDQW DQM tDQZ 1 Clk Interval COMMAND NOP NOP BANK A ACTIVATE NOP READ A WRITE A NOP NOP NOP DIN A1 DIN A2 DIN A3 Must be Hi-Z before the Write Command CAS latency = 2 DIN A0 tCK2, I/O’s : “H” or “L” 4.3 Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP DIN B0 DIN B1 DIN B2 DIN B0 DIN B1 DIN B2 CLK tDQW DQM tDQZ COMMAND NOP READ A NOP NOP READ A NOP WRITE B CAS latency = 2 tCK1, I/O’s DOUT A0 DOUT A1 Must be Hi-Z before the Write Command CAS latency = 3 tCK2, I/O’s DOUT A0 : “H” or “L” V55C2256164VB Rev. 1.0 April 2005 20 ProMOS TECHNOLOGIES V55C2256164VB 5. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP I/O’s WRITE A DIN A0 NOP NOP NOP DIN A1 DIN A2 DIN A3 The first data element and the Write are registered on the same clock edge. NOP NOP NOP NOP don’t care Extra data is ignored after termination of a Burst. 6.1 Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 WRITE A WRITE B T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP NOP NOP DIN B1 DIN B2 DIN B3 1 Clk Interval I/O’s V55C2256164VB Rev. 1.0 April 2005 DIN A0 DIN B0 21 NOP NOP NOP ProMOS TECHNOLOGIES V55C2256164VB 6.2 Write Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 WRITE A READ B T3 T4 T5 T6 T7 T8 CLK COMMAND NOP CAS latency = 2 tCK2, I/O’s CAS latency = 3 tCK3, I/O’s DIN A0 don’t care DIN A0 don’t care NOP NOP NOP DOUT B0 don’t care NOP NOP NOP DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the I/O’s at least one clock cycle before the Read dataAPpears on the outputs to avoid data contention. 7. Burst Write with Auto-Precharge Burst Length = 2, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND BANK A ACTIVE NOP NOP WRITE A NOP NOP Auto-Precharge I/O’s DIN A0 DIN A1 tWR NOP tRP tWR CAS latency = 2 NOP * tRP CAS latency = 3 I/O’s DIN A0 DIN A1 * Begin Autoprecharge Bank can be reactivated after trp V55C2256164VB Rev. 1.0 April 2005 22 NOP ProMOS TECHNOLOGIES V55C2256164VB 7.2 Burst Read with Auto-Precharge Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A CAS latency = 2 tCK2, I/O’s CAS latency = 3 tCK3, I/O’s NOP NOP DOUT A0 NOP NOP * DOUT A1 NOP * NOP NOP tRP DOUT A2 DOUT A0 NOP DOUT A1 DOUT A3 tRP DOUT A2 DOUT A3 * Begin Autoprecharge Bank can be reactivated after tRP V55C2256164VB Rev. 1.0 April 2005 23 ProMOS TECHNOLOGIES V55C2256164VB 8.1 Termination of a Burst Read Operation (CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP CAS latency = 2 tCK2, I/O’s NOP NOP Burst Stop DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 CAS latency = 3 tCK3, I/O’s NOP NOP NOP NOP DOUT A3 8.2 Termination of a Burst Write Operation (CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A NOP NOP DIN A1 DIN A2 Burst Stop NOP CAS latency = 2,3 I/O’s DIN A0 don’t care Input data for the Write is masked. V55C2256164VB Rev. 1.0 April 2005 24 NOP NOP NOP V55C2256164VB Rev. 1.0 April 2005 25 I/O DQM Addr AP BA WE CAS RAS CS CKE CLK Hi-Z tCH tAS tCKS T0 T3 tCK2 tRCD tAH tCH tCS T2 Ax0 CAx T4 Ax1 T5 Ax2 tRC RBx RBx T6 Ax3 T7 Bx0 CBx T9 T10 Bx1 Bx2 RAy RAy Bx3 tDS Begin Auto Precharge Bank A T8 Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank B Command Bank A Bank A Bank B RAx RAx tCL T1 9.1 AC Parameters for Write Timing T13 T14 Ay1 tDH Ay2 Ay3 Begin Auto Precharge Bank B T12 Write Command Bank A Ay0 RAy T11 T16 Precharge Command Bank A tDPL T15 tRP T20 Activate Command Bank B RBy RBy T19 tCKH tRRD T18 Activate Command Bank A RAz RAz T17 T21 T22 Burst Length = 4, CAS Latency = 2 ProMOS TECHNOLOGIES V55C2256164VB V55C2256164VB Rev. 1.0 April 2005 26 I/O DQM Addr AP BA WE CAS RAS CS CKE CLK Hi-Z tCL tCKS tCH T0 tAS RAx RAx tCS tRCD tAH tCH tCK2 T2 Activate Command Bank A T1 9.2 AC Parameters for Read Timing tRRD CAx T4 Read Command Bank A T3 tLZ tAC2 tAC2 Ax0 tOH tRAS RBx RBx T6 Activate Command Bank B T5 RBx T8 Read with Auto Precharge Command Bank B tHZ Ax1 tRC T7 T10 Precharge Command Bank A Bx0 Begin Auto Precharge Bank B T9 tHZ Bx1 tRP tCKH RAy RAy T12 Activate Command Bank A T11 T13 Burst Length = 2, CAS Latency = 2 ProMOS TECHNOLOGIES V55C2256164VB \ V55C2256164VB Rev. 1.0 April 2005 27 Addr AP BA WE CAS RAS CS CKE CLK T0 T2 Precharge Command All Banks T1 10. Mode Register Set T5 Mode Register Set Command T6 Any Command 2 Clock min. T4 Address Key T3 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ProMOS TECHNOLOGIES V55C2256164VB \ V55C2256164VB Rev. 1.0 April 2005 28 I/O DQM Addr AP BA WE CAS RAS CS CKE CLK T T TT Precharge 1st Auto Refresh Command Command All Banks tRP High level is required T Inputs must be stable for 200∝s Hi-Z T0 T T T T1 T T T 2nd Auto Refresh Command Minimum of 2 Refresh Cycles are required T 11. Power on Sequence and Auto Refresh (CBR) tRC T T TT Mode Register Set Command T T T Low Power Mode Register Set Command 2 Clock min. T Address Key T ProMOS TECHNOLOGIES V55C2256164VB \ V55C2256164VB Rev. 1.0 April 2005 29 Hi-Z I/O T1 Activate Command Bank A RAx Addr DQM RAx AP BA WE CAS RAS CS CKE CLK T0 12. Power Down Mode T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T15 Precharge Command Bank A T14 T16 T18 Power Down Mode Entry T17 tCKSP T19 T21 T22 Any Command Power Down Mode Exit T20 Burst Length = 4, CAS Latency = 2 ProMOS TECHNOLOGIES V55C2256164VB \ V55C2256164VB Rev. 1.0 April 2005 30 I/O DQM Addr AP BA WE CAS RAS CS CKE CLK All Banks must be idle Hi-Z T0 T1 T3 Self Refresh Entry T2 T4 13. Self Refresh (Entry and Exit) T5 T T T tRC T Begin Self Refresh Exit Command t CKSR tSREX T Self Refresh Exit Command issued T T Self Refresh Exit T T T T T T T T T T ProMOS TECHNOLOGIES V55C2256164VB V55C2256164VB Rev. 1.0 April 2005 31 Hi-Z Precharge Command All Banks T4 T5 tRC T6 T7 T9 Auto Refresh Command T8 T10 T12 tRC T11 T13 T14 T15 I/O DQM Auto Refresh Command (Minimum Interval) Activate Command Bank A RAx T3 Addr T2 RAx tRP tCK2 T1 AP BA WE CAS RAS CS CKE CLK T0 14. Auto Refresh (CBR) CAx T17 Read Command Bank A T16 T18 Ax0 T19 Ax1 T20 Ax2 T22 Ax3 T21 Burst Length = 4, CAS Latency = 2 ProMOS TECHNOLOGIES V55C2256164VB \ V55C2256164VB Rev. 1.0 April 2005 32 I/O Activate Command Bank A RAw Addr Hi-Z RAw DQM T1 tCK2 AP BA WE CAS RAS CS CKE CLK T0 CAw T3 Read Command Bank A T2 T4 Aw0 T5 Aw2 CAx T7 Read Command Bank A Aw1 T6 Ax0 CAy T9 Read Command Bank A Aw3 T8 Ax1 Ay2 T13 Precharge Command Bank A T12 Ay1 T11 Ay0 T10 15.1 Random Column Read (Page within same Bank) (1 of 2) Ay3 RAz RAz T15 Activate Command Bank A T14 T17 Read Command Bank A CAz T16 T18 Az0 T19 Az1 T20 Az2 T21 Az3 T22 Burst Length = 4, CAS Latency = 2 ProMOS TECHNOLOGIES V55C2256164VB \) V55C2256164VB Rev. 1.0 April 2005 33 I/O Activate Command Bank A RAw Addr Hi-Z RAw DQM T1 tCK3 AP BA WE CAS RAS CS CKE CLK T0 T2 CAw T4 Read Command Bank A T3 T5 T6 Aw1 CAx T8 Read Command Bank A Aw0 T7 Aw3 CAy T12 Ax1 T11 Ax0 T10 Read Command Bank A Aw2 T9 15.2 Random Column Read (Page within same Bank) (2 of 2) Ay0 T13 Ay1 Ay2 T16 Ay3 T15 Precharge Command Bank A T14 T18 Activate Command Bank A RAz RAz T17 T19 T21 Read Command Bank A CAz T20 T22 Burst Length = 4, CAS Latency = 3 ProMOS TECHNOLOGIES V55C2256164VB \) V55C2256164VB Rev. 1.0 April 2005 34 I/O Activate Command Bank B RBz Addr Hi-Z RBz DQM T1 tCK2 AP BA WE CAS RAS CS CKE CLK T0 CBz T3 T4 T5 T6 CBx T7 T8 CBy T9 T10 T11 Write Command Bank B Write Command Bank B Write Command Bank B T13 Precharge Command Bank B T12 DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 T2 16.1 Random Column Write (Page within same Bank) (1 of 2) T15 Activate Command Bank B RAw RBz RAw RBz T14 CAx CBz T17 T18 T19 T20 Write Command Bank B DBz0 DBz1 DBz2 DBz3 T16 T21 T22 Burst Length = 4, CAS Latency = 2 ProMOS TECHNOLOGIES V55C2256164VB \) V55C2256164VB Rev. 1.0 April 2005 35 I/O Activate Command Bank B RBz Addr Hi-Z RBz DQM T1 tCK3 AP BA WE CAS RAS CS CKE CLK T0 T2 CBz T4 T5 T6 T7 CBx T8 T9 CBy T10 T11 T12 T13 Write Command Bank B Write Command Bank B Write Command Bank B DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 T3 16.2 Random Column Write (Page within same Bank) (2 of 2) T15 Precharge Command Bank B T14 T16 T18 Activate Command Bank B RBz RBz T17 T19 T21 T22 Write Command Bank B DBz0 DBz1 CBz T20 Burst Length = 4, CAS Latency = 3 ProMOS TECHNOLOGIES V55C2256164VB \) V55C2256164VB Rev. 1.0 April 2005 36 I/O tRCD Activate Command Bank B Hi-Z RBx A0 - A9 DQM RBx High A10 A11(BS) WE CAS RAS CS CKE CLK T0 tAC2 T2 Read Command Bank B CBx tCK2 T1 T3 Bx0 T4 Bx1 T5 Bx2 T6 Bx4 RAx RAx T8 Activate Command Bank A Bx3 T7 17.1 Random Row Read (Interleaving Banks) (1 of 2) Bx6 CAx Ax1 RBy RBy T13 Activate Command Bank B T12 Ax0 tRP T11 Bx7 T10 Precharge Command Bank B Read Command Bank A Bx5 T9 Ax2 T14 Ax3 Ax5 T16 Ax4 T15 Ax6 T17 T19 Read Command Bank B Ax7 CBy T18 By0 T20 By1 T21 T22 Burst Length = 8, CAS Latency = 2 ProMOS TECHNOLOGIES V55C2256164VB V55C2256164VB Rev. 1.0 April 2005 37 I/O Activate Command Bank B Hi-Z RBx A0 - A9 DQM RBx High A10 A11(BS) WE CAS RAS CS CKE CLK T0 tRCD tCK3 T1 CBx T3 Read Command Bank B T2 tAC3 T4 T5 Bx0 T6 Bx2 RAx RAx T8 Activate Command Bank A Bx1 T7 T9 Bx3 17. 2 Random Row Read (Interleaving Banks) (2 of 2) Bx4 Bx7 tRP RBy RBy Activate Command Bank B Ax3 T16 Ax2 T15 Ax1 T14 Ax0 T13 Precharge Command Bank B T12 Bx6 T11 Read Command Bank A Bx5 CAx T10 Ax4 T17 Ax6 T19 Read Command Bank B Ax5 CBy T18 By0 T21 Precharge Command Bank A Ax7 T20 T22 Burst Length = 8, CAS Latency = 3 ProMOS TECHNOLOGIES V55C2256164VB V55C2256164VB Rev. 1.0 April 2005 38 I/O Activate Command Bank A Hi-Z RAx A0 - A9 DQM RAx High A10 A11(BS) WE CAS RAS CS CKE CLK T0 T3 T4 T5 T6 T7 RBx RBx T8 CBx tDPL T9 T10 T12 tRP T11 RAy RAy T13 T14 T15 T16 tDPL CAy T17 T18 T19 T20 T21 T22 Burst Length = 8, CAS Latency = 2 Activate Command Bank B Precharge Command Bank A Write Command Bank B Activate Command Bank A Precharge Command Bank B Write Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 T2 Write Command Bank A tRCD CAy CAX tCK2 T1 18.1 Random Row Write (Interleaving Banks) (1 of 2) ProMOS TECHNOLOGIES V55C2256164VB V55C2256164VB Rev. 1.0 April 2005 39 I/O Activate Command Bank A Hi-Z RAx A0 - A9 DQM RAx High A10 A11(BS) WE CAS RAS CS CKE CLK T0 tRCD tCK3 T1 CAX T3 T4 T5 T6 T7 RBx RBx T8 T9 T11 tDPL CBx T10 T12 T13 tRP T14 T15 RAy RAy T16 T17 T19 tDPL CAy T18 T20 T21 T22 Burst Length = 8, CAS Latency = 3 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 T2 18.2 Random Row Write (Interleaving Banks) (2 of 2) ProMOS TECHNOLOGIES V55C2256164VB V55C2256164VB Rev. 1.0 April 2005 40 I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BA WE CAS RAS CS CKE CLK T0 T2 T3 T4 T5 T6 Write Precharge Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked. DAx0 DAx1 DAx2 DAx3 CAx tCK2 T1 tRP 19.1 Precharge Termination of a Burst (1 of 2) RAy RAy T8 Activate Command Bank A T7 CAy T10 Read Command Bank A T9 T11 Ay1 T13 Precharge Command Bank A Ay0 T12 RAz RAz T15 Activate Command Bank A Ay2 tRP T14 T17 T18 Az1 T21 Az2 tRP T20 Precharge Command Bank A Az0 T19 Precharge Termination of a Read Burst. Read Command Bank A CAz T16 Burst Length = 8, CAS Latency = 2 T22 ProMOS TECHNOLOGIES V55C2256164VB V55C2256164VB Rev. 1.0 April 2005 41 I/O Activate Command Bank A Hi-Z RAx Addr DQM RAx High AP BA WE CAS RAS CS CKE CLK T0 CAx T3 Write Command Bank A DAx0 T2 Write Data is masked tCK3 T1 T5 tRP T6 RAy RAy T8 Activate Command Bank A T7 Precharge Termination of a Write Burst. Precharge Command Bank A T4 19.2 Precharge Termination of a Burst (2 of 2) T9 T11 Read Command Bank A CAy T10 T12 T13 Ay1 T15 Precharge Command Bank A Ay0 T14 Ay2 tRP T16 T18 T19 T20 T21 Precharge Termination of a Read Burst. Activate Command Bank A RAz RAz T17 T22 Burst Length = 4, 8, CAS Latency = 3 ProMOS TECHNOLOGIES V55C2256164VB ProMOS TECHNOLOGIES V55C2256164VB 20.1 Deep Power Down Mode Entry CLK CKE CS WE CAS RAS Addr. DQM DQ input DQ output High-Z t RP Precharge Command Deep Power Down Entry Deep Power Down Mode Normal Mode DP1.vsd The deep power down mode has to be maintained for a minimum of 100µs. V55C2256164VB Rev. 1.0 April 2005 42 ProMOS TECHNOLOGIES V55C2256164VB 20.2 Deep Power Down Exit The deep power down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command: 1. Maintain NOP input conditions for a minimum of 200 µs 2. Issue precharge commands for all banks of the device 3. Issue eight or more autorefresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extende mode register CLK CK E CS RAS CAS WE 200 s Deep Power Do wn exi t V55C2256164VB Rev. 1.0 April 2005 tRP All banks prec harge tRC Auto refresh Au to refresh 43 Mode Register Set Exte nded Mode Regis ter Set New Com mand Acce pted Here ProMOS TECHNOLOGIES V55C2256164VB Package Diagram 54-Pin Plastic TSOP-II (400 mil) 0.047 [1.20] MAX 0.400 ±0.005 [10.16 ±0.13] 0.04 ±0.002 [1 ±0.05] 0°–5° .004 [0.1] 0.031 [0.80] +0.002 0.016 -0.004 +0.05 0.40 -0.10 0.006 [0.15] MAX 0.463 ± 0.008 [11.76 ± 0.20] .008 [0.2] M 54x 54 28 Index Marking 27 1 1 0.881 -0.01 [22.38 -0.25] 1 Does not include plastic or metal protrusion of 0.15 max. per side V55C2256164VB Rev. 1.0 April 2005 +0.004 0.006 -0.002 +0.01 0.15 -0.05 44 Unit in inches [mm] 0.024 ± 0.008 [0.60 ± .020] ProMOS TECHNOLOGIES V55C2256164VB FBGA-BOC package 54 BGA package with 3 depop. rows 13 Units (mm) V55C2256164VB Rev. 1.0 April 2005 45 ProMOS TECHNOLOGIES V55C2256164VB WORLDWIDE OFFICES SALES OFFICES: JAPAN TAIWAN(Hsinchu) USA(West) NO. 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-566-3952 FAX: 886-3-578-6028 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 TAIWAN(Taipei) USA(East) 7F, NO. 102 MIN-CHUAN E. ROAD SEC. 3, Taipei, Taiwan, R.O.C PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 25 Creekside Road Hopewell Jct, NY 12533 PHONE:845-223-1689 FAX:845-223-1684 © Copyright ,ProMOS TECHNOLOGY. Printed in U.S.A. ProMOS TECH subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. ProMOS TECH does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. The information in this document is subject to change without notice. ProMOS TECH makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of ProMOS TECH. V55C2256164VB Rev. 1.0 April 2005 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 81-3-3537-1400 FAX: 81-3-3537-1402 46