MOSEL V53C8125H45

MOSEL VITELIC
PRELIMINARY
V53C8125H
ULTRA-HIGH PERFORMANCE,
128K X 8 FAST PAGE MODE
CMOS DYNAMIC RAM
HIGH PERFORMANCE
30
35
40
45
50
Max. RAS Access Time, (tRAC)
30 ns
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (tCAA)
16 ns
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode Cycle Time, (tPC)
19 ns
21 ns
23 ns
25 ns
28 ns
Min. Read/Write Cycle Time, (tRC)
65 ns
70 ns
75 ns
80 ns
90 ns
Features
Description
■ 128K x 8-bit organization
■ RAS access time: 30, 35, 40, 45, 50 ns
■ Fast Page Mode supports sustained data rates
up to 53 MHz
■ Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
■ Refresh Interval: 256 cycles/8 ms
■ Available in 26/24 pin 300 mil SOJ and 28 pin
TSOP-I packages
The V53C8125H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8125H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
columns (x9) bits within a row with cycle times as
short as 19 ns. Because of static circuitry, the CAS
clock is not in the critical timing path. The flowthrough column address latches allow address
pipelining while relaxing many critical system timing
requirements for fast usable speed. These features
make the V53C8125H ideally suited for graphics,
digital signal processing and high performance peripherals.
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
Package Outline
K
T
.
.
V53C8125H Rev. 1.7 August 1998
Access Time (ns)
30
.
Power
35
40
45
50
Std.
Temperature
Mark
.
.
.
.
.
Blank
1
V53C8125H
MOSEL VITELIC
V
5
3
C
8
1
FAMILY
Description
Pkg.
Pin Count
SOJ
K
26/24
TSOP-II
T
28
2
5
H
DEVICE
PKG
RAS
A0
A1
A2
A3
VCC
8
9
10
26
25
300 mil
1
2
3
4
5
6
11
12
13
24
23
22
21
V SS
I/O8
I/O7
I/O6
I/O5
CAS
19
18
17
16
15
14
OE
A8
A7
A6
A5
A4
Address Inputs (A8: Column Address only)
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O1- I/O8
Data Input, Output
VCC
+5V Supply
VSS
0V Supply
NC
No Connect
August 1998
(30 ns)
(35 ns)
(40 ns)
(45 ns)
(50 ns)
8125H 01
28 Lead TSOP-I
PIN CONFIGURATION
Top View
CAS
I/O5
I/O6
I/O7
I/O8
VSS
VSS
NC
I/O1
I/O2
I/O3
I/O4
NC
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
8125H 03
Pin Names
A0-A 8
BLANK (0°C to 70°C)
BLANK (NORMAL)
30
35
40
45
50
8125H 02
V53C8125H Rev. 1.7
TEMP.
PWR.
K (SOJ)
T (TSOP)
26/24 Lead SOJ
PIN CONFIGURATION
Top View
VSS
I/O1
I/O2
I/O3
I/O4
WE
SPEED
( t RAC)
2
OE
A8
A7
A6
A5
A4
NC
VCC
NC
A3
A2
A1
A0
RAS
V53C8125H
MOSEL VITELIC
Absolute Maximum Ratings*
Capacitance*
TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V
Ambient Temperature
Under Bias ................................. ñ10°C to +80°C
Storage Temperature (plastic) ..... ñ55°C to +125°C
Voltage Relative to VSS .................ñ1.0 V to +7.0 V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
Symbol
Parameter
Typ.
Max.
Unit
CIN1
Address Input
3
4
pF
CIN2
RAS, CAS, WE, OE
4
5
pF
COUT
Data Input/Output
5
7
pF
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
128K x 8
OE
WE
CAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
I/O 1
DATA I/O BUS
I/O2
COLUMN DECODERS
Y0ñY8
I/O3
I/O
BUFFER
I/O4
I/O 5
SENSE AMPLIFIERS
I/O6
REFRESH
COUNTER
I/O7
I/O8
512 x 8
A1
ï
ï
ï
A7
A8
V53C8125H Rev. 1.7 August 1998
X0ñX7
ROW
DECODERS
A0
ADDRESS BUFFERS
AND PREDECODERS
9
256
MEMORY
ARRAY
8125H 16
3
V53C8125H
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C8125H
Min.
Typ.
Max.
Unit
Test Conditions
Notes
ILI
Input Leakage Current
(any input pin)
Ò10
10
µA
VSS ≤ VIN ≤ VCC
ILO
Output Leakage Current
(for High-Z State)
Ò10
10
µA
VSS ≤ VOUT ≤ VCC
RAS, CAS at VIH
ICC1
VCC Supply Current,
Operating
30
180
mA
t RC = tRC (min.)
35
160
40
150
45
145
50
135
4
mA
RAS, CAS at VIH,
other inputs ≥ VSS
30
180
mA
t RC = tRC (min.)
2
35
160
40
150
45
145
50
135
30
110
mA
Minimum Cycle
1, 2
35
95
40
90
45
85
50
80
ICC2
VCC Supply Current,
TTL Standby
ICC3
VCC Supply Current,
RAS-Only Refresh
ICC4
VCC Supply Current,
Fast Page Mode Operation
1, 2
ICC5
VCC Supply Current,
Standby Output Enable
other inputs ≥ VSS
2
mA
RAS = VIH
CAS = VIL
ICC6
VCC Supply Current,
CMOS Standby
1
mA
RAS ≥ VCC Ò 0.2 V,
CAS ≥ VCC Ò 0.2 V,
All other inputs ≥ VSS
VCC
Supply Voltage
4.5
5.5
V
VIL
Input Low Voltage
Ò1
0.8
V
3
VIH
Input High Voltage
2.4
VCC + 1
V
3
VOL
Output Low Voltage
0.4
V
IOL = 4.2 mA
VOH
Output High Voltage
2.4
V
IOH = Ò5 mA
V53C8125H Rev. 1.7 August 1998
2.4
4
1
V53C8125H
MOSEL VITELIC
AC Characteristics
TA = 0°C to 70°C, VCC = 5 V ±10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
30
35
40
45
50
#
Symbol
Parameter
1
tRAS
RAS Pulse Width
30
2
tRC
Read or Write Cycle Time
65
70
75
80
90
ns
3
tRP
RAS Precharge Time
25
25
25
25
30
ns
4
tCSH
CAS Hold Time
30
35
40
45
50
ns
5
tCAS
CAS Pulse Width
5
6
7
8
9
ns
6
tRCD
RAS to CAS Delay
15
7
tRCS
Read Command Setup Time
0
0
0
0
0
ns
8
tASR
Row Address Setup Time
0
0
0
0
0
ns
9
tRAH
Row Address Hold Time
5
6
7
8
9
ns
10
tASC
Column Address Setup Time
0
0
0
0
0
ns
11
tCAH
Column Address Hold Time
5
5
5
6
7
ns
12
tRSH (R)
RAS Hold Time (Read Cycle)
10
10
10
10
10
ns
13
tCRP
CAS to RAS Precharge Time
5
5
5
5
5
ns
14
tRCH
Read Command Hold Time
Referenced to CAS
0
0
0
0
0
ns
15
tRRH
Read Command Hold Time
Referenced to RAS
16
tROH
RAS Hold Time
Referenced to OE
17
tOAC
Access Time from OE
10
11
12
13
14
ns
12
18
tCAC
Access Time from CAS
10
11
12
13
14
ns
6,7,14
19
tRAC
Access Time from RAS
30
35
40
45
50
ns
6, 8, 9
20
tCAA
Access Time from Column
Address
16
18
20
22
24
ns
6,7,10
21
tLZ
OE or CAS to Low-Z Output
0
ns
16
22
tHZ
OE or CAS to High-Z Output
0
ns
16
23
tAR
Column Address Hold Time from
RAS
26
24
tRAD
RAS to Column Address
Delay Time
10
25
tRSH (W)
RAS or CAS Hold Time in
Write Cycle
10
10
10
10
10
ns
26
tCWL
Write Command to CAS
Lead Time
10
11
12
13
14
ns
27
tWCS
Write Command Setup Time
0
0
0
0
0
ns
28
tWCH
Write Command Hold Time
5
5
5
6
7
ns
V53C8125H Rev. 1.7 August 1998
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
75K
20
35
16
75K
24
0
6
28
0
28
11
5
32
0
6
12
19
75K
36
0
13
0
8
40
23
ns
4
5
14
ns
ns
0
7
ns
0
10
35
20
50
0
0
30
17
18
75K
9
0
6
45
0
8
0
14
17
75K
0
7
5
40
ns
26
ns
11
12, 13
5
V53C8125H
MOSEL VITELIC
AC Characteristics (ContÌd)
30
35
40
45
50
#
Symbol
Parameter
29
tWP
Write Pulse Width
5
5
5
6
7
ns
30
tWCR
Write Command Hold Time
from RAS
26
28
30
35
40
ns
31
tRWL
Write Command to RAS
Lead Time
10
11
12
13
14
ns
32
tDS
Data in Setup Time
0
0
0
0
0
ns
14
33
tDH
Data in Hold Time
5
5
5
6
7
ns
14
34
tWOH
Write to OE Hold Time
5
5
6
7
8
ns
14
35
tOED
OE to Data Delay Time
5
5
6
7
8
ns
14
36
tRWC
Read-Modify-Write Cycle Time
100
105
110
115
130
ns
37
tRRW
Read-Modify-Write Cycle
RAS Pulse Width
65
70
75
80
87
ns
38
tCWD
CAS to WE Delay
26
28
30
32
34
ns
12
39
tRWD
RAS to WE Delay in ReadModify-Write Cycle
50
54
58
62
68
ns
12
40
tCRW
CAS Pulse Width (RMW)
44
46
48
50
52
ns
41
tAWD
Col. Address to WE Delay
32
35
38
41
42
ns
42
tPC
Fast Page Mode Read
or Write Cycle Time
19
21
23
25
28
ns
43
tCP
CAS Precharge Time
4
4
5
6
7
ns
44
tCAR
Column Address to RAS
Setup Time
16
18
20
22
24
ns
45
tCAP
Access Time from Column
Precharge
46
tDHR
Data in Hold Time Referenced
to RAS
26
28
30
35
40
ns
47
tCSR
CAS Setup Time CAS- beforeRAS Refresh
10
10
10
10
10
ns
48
tRPC
RAS to CAS Precharge Time
0
0
0
0
0
ns
49
tCHR
CAS Hold Time CAS-beforeRAS Refresh
7
8
8
10
12
ns
50
tPCM
Fast Page Mode Read-ModifyWrite Cycle Time
56
58
60
51
tT
Transition Time (Rise and Fall)
3
52
tREF
Refresh Interval (512 Cycles)
V53C8125H Rev. 1.7 August 1998
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
19
50
21
3
8
50
8
6
23
3
25
65
50
8
27
70
3
50
8
ns
12
7
ns
3
50
ns
15
8
ms
17
V53C8125H
MOSEL VITELIC
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in Fast Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to Ò1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) ≥ VSS and VIH (max.) ≤ VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to two TTL inputs and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8.
Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD
exceeds tRAD (max.).
9. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD ≥ tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 µs pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C8125H Rev. 1.7 August 1998
7
V53C8125H
MOSEL VITELIC
Waveforms of Read Cycle
t RC (2)
t RAS (1)
RAS
t RP (3)
t AR (23)
VIH
VIL
t CSH (4)
t CRP (13)
CAS
t RCD (6)
VIL
t CRP (13)
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RSH (R)(12)
t CAS (5)
VIH
VIH
ROW ADDRESS
VIL
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t RCH (14)
t CAR (44)
t RCS (7)
WE
t RRH (15)
VIH
VIL
t ROH (16)
t CAA (20)
OE
t OAC (17)
VIH
VIL
t CAC (18)
t RAC (19)
I/O
t HZ (22)
t HZ (22)
VOH
VALID DATA-OUT
VOL
t LZ (21)
8125H 04
Waveforms of Early Write Cycle
t RC (2)
t RAS (1)
RAS
t RP (3)
t AR (23)
V IH
V IL
t CSH (4)
t CRP (13)
CAS
t RCD (6)
t RSH (W)(25)
t CAS (5)
V IH
V IL
t CAR (44)
t CAH (11)
t RAH (9)
t ASR (8)
ADDRESS
t CRP (13)
V IH
V IL
t ASC (10)
ROW ADDRESS
COLUMN ADDRESS
t WCH (28)
t RAD (24)
t CWL (26)
WE
t WP (29)
t WCS (27)
V IH
V IL
t WCR (30)
t RWL (31)
OE
V IH
V IL
t DHR (46)
t DS (32)
I/O
V IH
V IL
t DH (33)
VALID DATA-IN
HIGH-Z
8125H 05
Donít Care
V53C8125H Rev. 1.7 August 1998
8
Undefined
V53C8125H
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t RC (2)
t RAS (1)
RAS
V IL
t CSH (4)
t CRP (13)
CAS
t RCD (6)
t RSH (W)(12)
t CAS (5)
V IH
t CRP (13)
V IL
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RP (3)
t AR (23)
V IH
V IH
t ASC (10)
ROW ADDRESS
V IL
t CAR (44)
t CAH (11)
COLUMN ADDRESS
t CWL (26)
t RWL (31)
t WP (29)
WE
V IH
V IL
t WOH (34)
OE
V IH
V IL
t OED (35)
I/O
t DH (33)
t DS (32)
V IH
VALID DATA-IN
V IL
8125H 06
Waveforms of Read-Modify-Write Cycle
t RWC (36)
tRRW (37)
RAS
t RP (3)
t AR (23)
VIH
VIL
t CSH (4)
t CRP (13)
CAS
t RCD (6)
t RSH (W)(25)
t CRW (40)
VIH
VIL
t
t RAH (9)
VIH
ROW
ADDRESS
VIL
COLUMN
ADDRESS
t AWD (41)
t CWD (38)
t RAD (24)
t RWD (39)
WE
OE
CAH (11)
t ASC (10)
t ASR (8)
ADDRESS
t CRP (13)
t RWL (31)
t WP (29)
VIH
VIL
t CAA (20)
t OAC (17)
VIH
VIL
t OED (35)
t CAC (18)
t RAC (19)
I/O
t CWL (26)
VIH
VOH
VIL
VOL
t DH (33)
t HZ (22)
t DS (32)
VALID
DATA-OUT
VALID
DATA-IN
t LZ (21)
8125H 07
Donít Care
V53C8125H Rev. 1.7 August 1998
9
Undefined
V53C8125H
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
RAS
t PC (42)
t CP (43)
t CSH (4)
t RAH (9)
t CAR (44)
t ASC (10)
t CAH (11)
t ASC (10)
V IH
ROW
ADDRESS
COLUMN
ADDRESS
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t RCS (7)
t RCS (7)
t RCS (7)
V IL
t CAA (20)
t CAA (20)
t CAP (45)
t OAC (17)
t RRH (15)
t OAC (17)
V IH
V IL
t HZ (22)
t RAC (19)
t CAC (18)
t LZ (21)
t CAC (18)
t CAC (18)
t HZ (22)
V OH
t HZ (22)
t HZ (22)
VALID
DATA OUT
V OL
t HZ (22)
t HZ (22)
t LZ (21)
t LZ (21)
I/O
t RCH (14)
V IH
t OAC (17)
OE
t CRP (13)
t CAS (5)
t CAS (5)
V IL
V IL
WE
t RSH (R)(12)
t CAS (5)
V IH
t ASR (8)
ADDRESS
RP (3)
V IL
t RCD (6)
t CRP (13)
CAS
t
t RAS (1)
t AR (23)
V IH
VALID
DATA OUT
VALID
DATA OUT
8125H 08
Waveforms of Fast Page Mode Write Cycle
t RP (3)
t AR (23)
RAS
t RAS (1)
V IH
V IL
t CRP (13)
t RCD (6)
CAS
t PC (42)
t CP (43)
t CAS (5)
V IH
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CAS (5)
V IL
t CSH (4)
t RAH (9)
t CAR (44)
t ASC (10)
t ASR (8)
ADDRESS
V IH
ROW
ADD
V IL
t ASC (10)
t CAH (11)
t CAH (11)
COLUMN
ADDRESS
t RAD (24)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
OE
t WCH (28)
t WCH (28)
t RWL (31)
t WCH (28)
t WP (29)
t WP (29)
V IH
V IL
VIH
V IL
V IH
V IL
t DS (32)
t DH (33)
t DS (32)
t DH (33)
t DS (32)
I/O
t CWL (26)
t WCS (27)
t WP (29)
WE
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t CAH (11)
VALID
DATA IN
VALID
DATA IN
OPEN
t DH (33)
VALID
DATA IN
OPEN
8125H 09
Donít Care
V53C8125H Rev. 1.7 August 1998
10
Undefined
V53C8125H
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
RAS
t RAS (1)
VIH
V
IL
t CSH (4)
t RCD (6)
t RP (3)
t PCM (50)
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CP (43)
t CAS (5)
V
CAS
IH
V
t CAS (5)
t RAD (24)
IL
t RAH (9)
t CAR (44)
t ASC (10)
ADDRESS
IH
ROW
ADD
V
IL
t ASC (10)
t CAH (11)
t ASR (8)
V
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
t CAH (11)
COLUMN
ADDRESS
t RWD (39)
COLUMN
ADDRESS
t CWD (38)
t RCS (7)
t CWD (38)
t RWL (31)
t CWL (26)
t CWL (26)
t CWD (38)
t CWL (26)
V
WE
IH
V
IL
t AWD (41)
t AWD (41)
t AWD (41)
t WP (29)
t CAA (20)
t OAC (17)
t WP (29)
t WP (29)
t OAC (17)
t OAC (17)
V
OE
IH
V
IL
t CAP (45)
t CAP (45)
t CAA (20)
t CAA (20)
t OED (35)
t CAC (18)
t RAC (19)
t OED (35)
t CAC (18)
t HZ (22)
t HZ (22)
t DH (33)
t DH (33)
t DS (32)
t DS (32)
I/O
V I/OH
OUT
V I/OL
OUT
IN
t LZ (21)
t LZ (21)
t OED (35)
t CAC (18)
t HZ (22)
t DH (33)
t DS (32)
OUT
IN
IN
8125H 10
t LZ (21)
Waveforms of RAS-Only Refresh Cycle
t RC (2)
RAS
t RAS (1)
V IH
t RP (3)
V IL
t CRP (13)
CAS
V IH
V IL
t ASR (8)
ADDRESS
V IH
t RAH (9)
ROW ADDR
V IL
8125H 11
NOTE:
WE, OE = Donít care
Donít Care
V53C8125H Rev. 1.7 August 1998
11
Undefined
V53C8125H
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1)
RAS
t RP (3)
V IH
V IL
t CSR (47)
CAS
ADDRESS
t CHR (49)
t RSH (W)(25)
t CAS (5)
t CP (43)
V IH
V IL
V IH
V IL
READ CYCLE
WE
t RRH (15)
t RCH (14)
t RCS (7)
V IH
V IL
t ROH (16)
t OAC (17)
OE
V IH
V IL
t HZ (22)
t HZ (22)
t LZ (21)
I/O
V IH
DOUT
V IL
t RWL (31)
t CWL (26)
WRITE CYCLE
WE
OE
V IL
V IH
V IL
t
I/O
t WCH (28)
t WCS (27)
V IH
DS (32)
V IH
t DH (33)
D IN
V IL
8125H 12
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2)
t RP (3)
RAS
t RAS (1)
t RP (3)
V IH
V IL
t RPC (48)
t CP (43)
t CHR (49)
t CSR (47)
CAS
V IH
V IL
t HZ (22)
I/O
V OH
V OL
8125H 13
NOTE: WE, OE, A 0 ñA 7 = Donít care
Donít Care
V53C8125H Rev. 1.7
August 1998
12
Undefined
V53C8125H
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2)
RAS
V IH
t RSH (R)(12)
t CRP (13)
V IL
V IH
t RAD (24)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
ROW
ADD
V IL
t RCS (7)
WE
t CHR (49)
V IH
t ASR (8)
t RAH (9)
ADDRESS
t RP (3)
t RAS (1)
V IL
t RCD (6)
t CRP (13)
CAS
t RC (2)
tRP (3)
t RAS (1)
t AR (23)
t RRH (15)
V IH
V IL
t CAA (20)
t OAC (17)
OE
V IH
V IL
t CAC (18)
t LZ (21)
t RAC (19)
t HZ (22)
t HZ (22)
V OH
I/O
VALID DATA
V OL
8125H 14
Waveforms of Hidden Refresh Cycle (Write)
t RC (2)
V IH
RAS
t RAS (1)
t RP (3)
V IL
t RCD (6)
t CRP (13)
CAS
t RC (2)
t RP (3)
t RAS (1)
t AR (23)
t RSH (12)
t CHR (49)
t CRP (13)
V IH
V IL
t RAD (24)
t ASC (10)
t ASR (8)
t RAH (9)
ADDRESS
V IH
V IL
t CAH (11)
ROW
ADD
COLUMN
ADDRESS
t WCH (28)
t WCS (27)
WE
V IH
V IL
OE
V IH
V IL
t DS (32)
I/O
V IH
V IL
t DH (33)
VALID DATA-IN
t DHR (46)
8125H 15
Donít Care
V53C8125H Rev. 1.7 August 1998
13
Undefined
V53C8125H
MOSEL VITELIC
Functional Description
Refresh Cycle
The V53C8125H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional
dynamic RAM. The V53C8125H reads and writes
data by multiplexing an 17-bit address into a 8-bit
row and an 9-bit column address. The row address
is latched by the Row Address Strobe (RAS). The
column address ìflows throughî an internal address
buffer and is latched by the Column Address Strobe
(CAS). Because access time is primarily dependent
on a valid column address rather than the precise
time that the CAS edge occurs, the delay time from
RAS to CAS has little effect on the access time.
To retain data, 256 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1.
2.
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and
data integrity. A new cycle must not be initiated until
the minimum precharge time tRP/tCP has elapsed.
By clocking each of the 512 row addresses (A0
through A8) with RAS at least once every 8 ms.
Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row.
Using a CAS-before-RAS Refresh Cycle. If
CAS makes a transition from low to high to low
after the previous cycle and before RAS falls,
CAS-before-RAS refresh is activated. The
V53C8125H uses the output of an internal 9-bit
counter as the source of row addresses and ignore external address inputs.
CAS-before-RAS is a ìrefresh-onlyî mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the cycle. A CAS-before-RAS counter test mode is provided to ensure reliable operation of the internal
refresh counter.
Read Cycle
Fast Page Mode Operation
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only
when tOAC, tRAC, tCAA and tCAC are all satisifed. As
a result, the access time is dependent on the timing
relationships between these parameters. For example, the access time is limited by tCAA when tRAC,
tCAC and tOAC are all satisfied.
Fast Page Mode operation permits all 256 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining
RAS low while performing successive CAS cycles
retains the row address internally and eliminates the
need to reapply it for each cycle. The column address buffer acts as a transparent or flow-through
latch while CAS is high. Thus, access begins from
the occurrence of a valid column address rather
than from the falling edge of CAS, eliminating tASC
and tT from the critical timing path. CAS latches the
address into the column address buffer and acts as
an output enable. During Fast Page Mode operation, Read, Write, Read-Modify-Write or ReadWrite-Read cycles are possible at random addresses within a row. Following the initial entry cycle into
Fast Page Mode, access is tCAA or tCAP controlled.
If the column address is valid prior to the rising edge
of CAS, the access time is referenced to the CAS
rising edge and is specified by tCAP. If the column
address is valid after the rising CAS edge, access
is timed from the occurrence of a valid address and
is specified by tCAA. In both cases, the falling edge
of CAS latches the address and enables the output.
Write Cycle
A Write Cycle is performed by taking WE and
CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be
WE controlled or CAS controlled depending on
whether WE or CAS falls later. Consequently, the
input data must be valid at or before the falling edge
of WE or CAS, whichever occurs last. In the CAScontrolled Write Cycle, when the leading edge of
WE occurs prior to the CAS low transition, the I/O
data pins will be in the High-Z state at the beginning
of the Write function. Ending the Write with RAS or
CAS will maintain the output in the High-Z state.
In the WE controlled Write Cycle, OE must be in
the high state and tOED must be satisfied.
V53C8125H Rev. 1.7 August 1998
14
V53C8125H
MOSEL VITELIC
Power-On
Fast Page Mode provides sustained data rates
up to 53 MHz for applications that require high data
rates such as bit-mapped graphics or high-speed
signal processing. The following equation can be
used to calculate the maximum data rate:
After application of the VCC supply, an initial
pause of 200 µs is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C8125H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and IDD will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
256
Data Rate = ---------------------------------------t RC + 255 × t PC
Data Output Operation
The V53C8125H Input/Output is controlled by
OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected
row address in the Memory Array. A RAS high transition disables data transfer and latches the output
data if the output is enabled. After a memory cycle
is initiated with a RAS low transition, a CAS low
transition or CAS low level enables the internal I/O
path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has
no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled,
can be disabled by holding OE high. The OE signal
has no effect on any data stored in the output latches. A WE low level can also disable the output drivers when CAS is low. During a Write cycle, if WE
goes low at a time in relationship to CAS that would
normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to
the WE low transition to allow Data In Setup Time
(tDS) to be satisfied.
V53C8125H Rev. 1.7 August 1998
Table 1. V53C8125H Data Output
Operation for Various Cycle Types
15
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
Fast Page Mode
Read
Data from Addressed
Memory Cell
Fast Page Mode Write
Cycle (Early Write)
High-Z
Fast Page Mode Read-ModifyWrite Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C8125H
MOSEL VITELIC
Package Diagrams
26/24-pin 300 mil SOJ
0.332 ñ 0.342
[8.43 ñ 8.69]
Unit in inches [mm]
0.296 ñ 0.304
[7.52 ñ 7.72]
0.665 ñ 0.698
[16.89 ñ 17.73]
0.125 ñ 0.135
[3.175 ñ 3.429]
0.082 ñ 0.093
[2.08 ñ 2.36]
0.028 Typ.
[0.711 Typ.]
0.05 Typ.
[1.27 Typ.]
0.018 Typ.
[0.457 Typ.]
0.025 Min.
[0.635 Min.]
0.255 ñ 0.275
[6.477 ñ 6.985]
28-pin TSOP-I
Unit in inches
.035 ñ .043
Detail ì Aî
.520 ñ .535
.039 DIA.
Pin # 1 I.D.
.004
.047
.461 ñ .469
.035 ñ .043
.000
.079 DIA. x .004 Deep
Fixed Pin (1 Plcs.)
.002 ñ .006
.022
.311 ñ .319
.022
C.O.O. denotes
country of orgin
.055 ñ .063
.010
Top View
.022
Bottom View
See Detail ìBî
.055 ñ .063
D
.037 ñ .041
See Detail ìAî
D
.007 ñ .011
.007 ñ .009
.08 ñ .20
0∞ñ 6∞
Gage Plane
.012 MAX
.004 ñ .008
With Plating
.020 ñ .028
Base Metal
.004 ñ .006
Detail ì Aî
Section ì D-Dî
V53C8125H Rev. 1.7 August 1998
16
0.25 BSC
Detail ì Bî
MOSEL VITELIC
WORLDWIDE OFFICES
V53C8125H
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© Copyright 1998, MOSEL VITELIC Inc.
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC
7/98
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461