To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-10167-3E MEMORY CMOS 2 M × 8 BIT FAST PAGE MODE DYNAMIC RAM MB8117800A-60/-70 CMOS 2,097,152 × 8 Bit Fast Page Mode Dynamic RAM ■ DESCRIPTION The Fujitsu MB8117800A is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory cells accessible in 8-bit increments. The MB8117800A features a “fast page” mode of operation whereby highspeed random access of up to 1,024-bits of data within the same row can be selected. The MB8117800A DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. Since the standby current of the MB8117800A is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. The MB8117800A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and twolayer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for the MB8117800A are not critical and all inputs are TTL compatible. ■ PRODUCT LINE & FEATURES Parameter MB8117800A-60 MB8117800A-70 RAS Access Time 60 ns max. 70 ns max. Random Cycle Time 110 ns min. 130 ns min. Address Access Time 30 ns max. 35 ns max. CAS Access Time 15 ns max. 17 ns max. Hyper Page Mode Cycle Time 40 ns min. 45 ns min. 715 mW max. 660 mW max. Low Power Dissipation • • • • • • Operating Current Standby Current 11 mW max. (TTL level) / 5.5 mW max. (CMOS level) 2,097,152 words × 8 bit organization Silicon gate, CMOS, Advanced Capacitor Cell All input and output are TTL compatible 2048 refresh cycles every 32.8ms Self refresh function Early write or OE controlled write capability • RAS-only, CAS-before-RAS, or Hidden Refresh • Fast Page Mode, Read-Modify-Write capability • On chip substrate bias generator for high performance 1 To Top / Lineup / Index MB8117800A-60/-70 ■ PACKAGE 28-pin plastic SOJ 28-pin plastic TSOP (II) (LCC-28P-M07) (FPT-28P-M14) (Normal Bend) Package and Ordering Information – 28-pin plastic (400mil) SOJ, order as MB8117800A-××PJ – 28-pin plastic (400mil) TSOP-II with normal bend leads, order as MB8117800A-××PFTN 2 To Top / Lineup / Index MB8117800A-60/-70 ■ PIN ASSIGNMENTS AND DESCRIPTIONS 26-Pin SOJ (TOP VIEW) <LCC-28P-M07> VCC DQ1 DQ2 DQ3 DQ4 WE RAS N.C. A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 1 Pin Index 26 25 24 23 22 21 20 19 18 17 16 15 Designator VSS DQ8 DQ7 DQ6 DQ5 CAS OE A9 A8 A7 A6 A5 A4 VSS A0 to A10 Function Address inputs row : A0 to A10 column : A0 to A9 refresh : A0 to A10 RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable DQ1 to DQ8 Data Input/Output VCC +5.0 volt power supply VSS Circuit ground N.C. No Connection 28-Pin TSOP (II) (TOP VIEW) <Normal Bend: FPT-28P-M14> VCC DQ1 DQ2 DQ3 DQ4 WE RAS N.C. A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 1 Pin Index 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ8 DQ7 DQ6 DQ5 CAS OE A9 A8 A7 A6 A5 A4 VSS 3 To Top / Lineup / Index MB8117800A-60/-70 ■ BLOCK DIAGRAM Fig. 1 – MB8117800A DYNAMIC RAM – BLOCK DIAGRAM RAS Clock Gen #1 CAS Write Clock Gen WE Mode Control Clock Gen #2 Data In Buffer A0 A1 Column Decoder A2 A3 A4 A5 Address Buffer & PreDecoder DQ1 to DQ8 Sense Ampl & I/O Gate A6 Row Decoder A7 16,777,216 Bit Storage Cell Data Out Buffer A8 A9 OE A10 4 Refresh Address Counter Substrate Bias Gen VCC VSS To Top / Lineup / Index MB8117800A-60/-70 ■ FUNCTIONAL TRUTH TABLE Operation Mode Clock Input Address Input Data Refresh Note RAS CAS WE OE Row Column Input Output Standby H H X X — — — High-Z — Read Cycle L L H L Valid Valid — Valid Yes* tRCS ≥ tRCS (min) Write Cycle (Early Write) L L L X Valid Valid Valid High-Z Yes* tWCS ≥ tWCS (min) Read-ModifyWrite Cycle L L Valid Valid Valid Valid Yes* RAS-only Refresh Cycle L H X X Valid — — High-Z Yes CAS-beforeRAS Refresh Cycle L L X X — — — High-Z Yes tCSR ≥ tCSR (min) H→L L H→X L — — — Valid Yes Previous data is kept. Hidden Refresh Cycle H→L L→H X; “H” or “L” *; It is impossible in Fast Page Mode. ■ FUNCTIONAL OPERATION ADDRESS INPUTS Twenty-one input bits are required to decode any eight of 16,777,216 cell addresses in the memory matrix. Since only eleven address bits (A0 to A10) are available, the row and column inputs are separately strobed by RAS and CAS as shown in Figure 1. First, eleven row address bits are input on pins A0-through-A10 and latched with the row address strobe (RAS) then, ten column address bits are input and latched with the column address strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS, respectively. The address latches are of the flow-through type; thus, address information appearing after tRAH (min) + tT is automatically treated as the column address. WRITE ENABLE The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is selected. During the read mode, input data is ignored. DATA INPUTS Input data is written into memory in either of three basic ways-an early write cycle, an OE (delayed) write cycle, and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data (DQ1-DQ8) is strobed by CAS and the setup/hold times are referenced to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal. 5 To Top / Lineup / Index MB8117800A-60/-70 DATA OUTPUTS The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: tRAC : tCAC : tAA : tOEA : from the falling edge of RAS when tRCD (max) is satisfied. from the falling edge of CAS when tRCD is greater than tRCD (max). from column address input when tRAD is greater than tRAD (max). from the falling edge of OE when OE is brought Low after tRAC, tCAC, or tAA. The data remains valid until either CAS or OE returns to a High logic level. When an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. FAST PAGE MODE OF OPERATION The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For each fast page of memory, any of 1,024 x 8-bits can be accessed and, when multiple MB8117800As are used, CAS is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. 6 To Top / Lineup / Index MB8117800A-60/-70 ■ ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Value Unit VIN, VOUT –0.5 to +7.0 V Voltage of VCC supply relative to VSS VCC –0.5 to +7.0 V Power Dissipation PD 1.0 W Short Circuit Output Current — 50 mA Operating Temperature TOPE 0 to 70 °C Storage Temperature TSTG –55 to +125 °C Voltage at any pin relative to VSS WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Notes Symbol Min. Typ. Max. VCC 4.5 5.0 5.5 VSS 0 0 0 Unit Ambient Operating Temp V Supply Voltage *1 Input High Voltage, all inputs *1 VIH 2.4 — 6.5 V Input Low Voltage, all inputs* *1 VIL –3.0 — 0.8 V 0°C to + 70°C * : Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. ■ CAPACITANCE (TA = 25°C, f = 1 MHz) Parameter Symbol Max. Unit Input Capacitance, A0 to A10 CIN1 5 pF Input Capacitance, RAS, CAS, WE, OE CIN2 5 pF Input/Output Capacitance, DQ1 to DQ8 CDQ 7 pF 7 To Top / Lineup / Index MB8117800A-60/-70 ■ DC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Note 3 Parameter Notes Symbol Values Min. Typ. Max. Output high voltage VOH IOH = –5.0 mA 2.4 — — Output low voltage VOL IOL = +4.2 mA — — 0.4 I I(L) 0 V ≤ VIN ≤ VCC; 4.5 V ≤ VCC ≤ 5.5 V; VSS = 0 V; All other pins not under test = 0 V –10 — 10 IDQ(L) 0 V≤ VOUT ≤ VCC; Data out disabled –10 — ICC1 RAS & CAS cycling; tRC = min — — Input leakage current (any input) Output leakage current Operating current (Average power supply current) MB8117800A-60 *2 MB8117800A-70 TTL level Standby current (Power supply current) CMOS level Fast Page Mode Current Refresh current #2 (Average power supply current) Refresh current #3 (Average power supply current) ICC3 MB8117800A-60 *2 ICC4 MB8117800A-70 MB8117800A-60 ICC5 *2 MB8117800A-70 MB8117800A-60 ICC9 MB8117800A-70 RAS = CAS ≥ VCC – 0.2 V Unit V µA 10 130 mA 120 RAS = CAS = VIH ICC2 MB8117800A-60 Refresh current #1 (Average power supply current) *2 MB8117800A-70 8 Condition 2.0 — — mA 1.0 130 CAS = VIH, RAS cycling; tRC = min — RAS = VIL, CAS cycling; tPC = min — RAS cycling; CAS-before-RAS; tRC = min — RAS = VIL, CAS = VIL Self refresh; tRASS = min — — mA 120 120 — mA 110 120 — mA 110 — 1000 µA To Top / Lineup / Index MB8117800A-60/-70 ■ AC CHARACTERISTICS (At recommended operating conditions unless otherwise noted.) Notes 3, 4, 5 No. Parameter Notes Symbol MB8117800A-60 MB8117800A-70 Min. Max. Min. Max. Unit 1 Time Between Refresh tREF — 32.8 — 32.8 ms 2 Random Read/Write Cycle Time tRC 110 — 130 — ns 3 Read-Modify-Write Cycle Time tRWC 150 — 174 — ns 4 Access Time from RAS *6, 9 tRAC — 60 — 70 ns 5 Access Time from CAS *7, 9 tCAC — 15 — 17 ns 6 Column Address Access Time *8, 9 tAA — 30 — 35 ns 7 Output Hold Time tOH 3 — 3 — ns 8 Output Buffer Turn On Delay Time tON 0 — 0 — ns 9 Output Buffer Turn Off Delay Time tOFF — 15 — 17 ns 10 Transition Time tT 3 50 3 50 ns 11 RAS Precharge Time tRP 40 — 50 — ns 12 RAS Pulse Width tRAS 60 100000 70 100000 ns 13 RAS Hold Time tRSH 15 — 17 — ns 14 CAS to RAS Precharge Time tCRP 5 — 5 — ns 15 RAS to CAS Delay Time tRCD 20 45 20 53 ns 16 CAS Pulse Width tCAS 15 — 17 — ns 17 CAS Hold Time tCSH 60 — 70 — ns 18 CAS Precharge Time (Normal) tCPN 10 — 10 — ns 19 Row Address Set Up Time tASR 0 — 0 — ns 20 Row Address Hold Time tRAH 10 — 10 — ns 21 Column Address Set Up Time tASC 0 — 0 — ns 22 Column Address Hold Time tCAH 15 — 15 — ns 23 Column Address Hold Time from RAS tAR 35 — 35 — 24 RAS to Column Address Delay Time tRAD 15 30 15 35 ns 25 Column Address to RAS Lead Time tRAL 30 — 35 — ns 26 Column Address to CAS Lead Time tCAL 30 — 35 — ns 27 Read Command Set Up Time tRCS 0 — 0 — ns 28 Read Command Hold Time Referenced to RAS *14 tRRH 0 — 0 — ns 29 Read Command Hold Time Referenced to CAS *14 tRCH 0 — 0 — ns 30 Write Command Set Up Time *15, 20 tWCS 0 — 0 — ns *10 *11, 12 *19 *13 9 To Top / Lineup / Index MB8117800A-60/-70 (Continued) No. 10 Parameter Notes Symbol MB8117800A-60 MB8117800A-70 Min. Max. Min. Max. Unit 31 Write Command Hold Time tWCH 15 — 15 — ns 32 Write Hold Time from RAS tWCR 35 — 35 — ns 33 WE Pulse Width tWP 15 — 15 — ns 34 Write Command to RAS Lead Time tRWL 15 — 17 — ns 35 Write Command to CAS Lead Time tCWL 15 — 17 — ns 36 DIN Setup Time tDS 0 — 0 — ns 37 DIN Hold Time tDH 15 — 15 — ns 38 Data Hold Time from RAS tDHR 35 39 RAS to WE Delay Time *20 tRWD 80 — 92 — ns 40 CAS to WE Delay Time *20 tCWD 35 — 39 — ns 41 Column Address to WE Lead Time *20 tAWD 50 — 57 — ns 42 RAS Precharge Time to CAS Active Time (Refresh cycles) tRPC 5 — 5 — ns 43 CAS Setup Time for CAS -before- RAS Refresh tCSR 0 — 0 — ns 44 CAS Hold Time for CAS -before- RAS Refresh tCHR 10 — 12 — ns 45 Access Time from OE *9 tOEA — 15 — 17 ns 46 Output Buffer Turn Off Delay from OE *10 tOEZ — 15 — 17 ns 47 OE to RAS Lead Time for Valid Data tOEL 10 — 10 — ns 48 OE Hold Time Referenced to WE tOEH 5 — 5 — ns 49 OE to Data In Delay Time tOED 15 — 17 — ns 50 CAS to Data In Delay Time tCDD 15 — 17 — ns 51 DIN to CAS Delay Time *17 tDZC 0 — 0 — ns 52 DIN to OE Delay Time *17 tDZO 0 — 0 — ns 60 Fast Page Mode RAS Pulse width tRASP — 100000 — 100000 ns 61 Fast Page Mode Read/Write Cycle Time tPC 40 — 45 — ns 62 Fast Page Mode Read-Modify-Write Cycle Time tPRWC 80 — 89 — ns 63 Access Time from CAS Precharge tCPA — 35 — 40 ns 64 Fast Page Mode CAS Precharge Time tCP 10 — 10 — ns 65 Fast Page Mode RAS Hold Time from CAS Precharge tRHCP 35 — 40 — ns 66 Fast Page Mode CAS Precharge to WE Delay Time tCPWD 55 — 62 — ns *16 *9, 18 35 ns To Top / Lineup / Index MB8117800A-60/-70 Notes: *1. Referenced to VSS. *2. ICC depends on the output load conditions and cycle rates; The specified values are obtained with the output open. ICC depends on the number of address change as RAS = VIL, CAS = VIH and VIL > –0.3 V. ICC1, ICC3, ICC4 and ICC5 are specified at one time of address change during RAS = VIL and CAS = VIH. ICC2 is specified during RAS = VIH and VIL > –0.3 V. *3. An initial pause (RAS = CAS = VIH) of 200 µs is required after power-up followed by any eight RAS-only cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of eight CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. *4. AC characteristics assume tT = 5 ns. *5. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also transition times are measured between VIH (min) and VIL (max). *6. Assumes that tRCD ≤ tRCD (max), tRAD ≤ tRAD (max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that tRCD exceeds the value shown. Refer to Fig.2 and 3. *7. If tRCD ≥ tRCD (max), tRAD ≥ tRAD (max), and tASC ≥ tAA – tCAC – tT, access time is tCAC. *8. If tRAD ≥ tRAD (max) and tASC ≤ tAA – tCAC – tT, access time is tAA. *9. Measured with a load equivalent to two TTL loads and 100 pF. *10. tOFF and tOEZ is specified that output buffer change to high impedance state. *11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC or tAA. *12. tRCD (min) = tRAH (min) + 2 tT + tASC (min). *13. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled exclusively by tCAC or tAA. *14. Either tRRH or tRCH must be satisfied for a read cycle. *15. tWCS is specified as a reference point only. If tWCS ≥ tWCS (min) the data output pin will remain High-Z state through entire cycle. *16. Assumes that tWCS < tWCS (min). *17. Either tDZC or tDZO must be satisfied. *18. tCPA is access time from the selection of a new column address (that is caused by changing CAS from “L” to “H”). Therefore, if tCP is long, tCPA is longer than tCPA (max). *19. Assumes that CAS-before-RAS refresh. *20. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristic only. If tWCS ≥ tWCS (min), the cycle is an early write cycle and DOUT pin will maintain high impedance state through-out the entire cycle. If tCWD ≥ tCWD (min), tRWD ≥ tRWD (min), tAWD ≥ tAWD (min) and tCPWD ≥ tCPWD (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the DOUT pin. If neither of the above conditions is satisfied, the cycle is a delayed write cycle and invalid data will appear the DOUT pin, and write operation can be executed by satisfying tRWL, tCWL, and tRAL specifications. 11 To Top / Lineup / Index MB8117800A-60/-70 Fig. 2 – tRAC vs. tRCD tRAC (ns) Fig. 3 – tRAC vs. tRAD Fig. 4 – tCPA vs. tCP tRAC (ns) tCPA (ns) 120 90 70 100 80 60 80 70 60 70ns version 60ns version 70ns version 50 70ns version 60ns version 60 40 60ns version 40 50 0 20 40 60 80 100 tRCD (ns) 12 30 0 20 30 40 50 60 tRAD (ns) 0 10 20 30 40 50 tCP (ns) To Top / Lineup / Index MB8117800A-60/-70 Fig. 5 – READ CYCLE tRC tRAS RAS tAR VIH VIL tCRP tCSH tRP tRCD CAS tCAS VIH VIL tRAD tASR A0 to A10 VIH VIL tRSH tCDD tRAL tCAL tRAH tCAH tASC ROW ADD tOEL COLUMN ADD tRRH tRCS WE tRCH VIH VIL tAA tOH tCAC tRAC VOH DQ (Output) VOL HIGH-Z tDZC DQ (Input) VIH VIL tON tOEZ tOEA HIGH-Z tOH tDZO OE tOFF tON tOED VIH VIL “H” or “L” DESCRIPTION To implement a read operation, a valid address is latched in by the RAS and CAS address strobes and with WE set to a High level and OE set to a low level, the output is valid once the memory access time has elapsed. The access time is determined by RAS(tRAC), CAS(tCAC), OE(tOEA) or column addresses (tAA) under the following conditions: If tRCD > tRCD (max), access time = tCAC. If tRAD > tRAD (max), access time = tAA. If OE is brought Low after tRAC, tCAC, or tAA(whichever occurs later), access time = tOEA. However, if either CAS or OE goes High, the output returns to a high-impedance state after tOH is satisfied. 13 To Top / Lineup / Index MB8117800A-60/-70 Fig. 6 – EARLY WRITE CYCLE (OE = “H” or “L”) tRC tRAS RAS VIH VIL tCRP tCSH tRCD CAS tRP tRSH tCAS VIH VIL tAR tASR A0 to A10 VIH VIL tRAH tASC ROW ADD tCAH COLUMN ADD tWCR tWCS WE tWCH VIH VIL tDHR tDS DQ (Input) VIH VIL VOH DQ (Output) VOL tDH VALID DATA IN HIGH-Z “H” or “L” DESCRIPTION A write cycle is similar to a read cycle except WE is set to a Low state and OE is an “H” or “L” signal. A write cycle can be implemented in either of three ways - early write, delayed write or read-modify-write. During all write cycles, timing parameters tRWL, tCWL, and tRAL must be satisfied. In the early write cycle shown above tWCS satisfied, data on the DQ pin is latched with the falling edge of CAS and written into memory. 14 To Top / Lineup / Index MB8117800A-60/-70 Fig. 7 – DELAYED WRITE CYCLE tRC tRAS RAS tAR VIH VIL tRP tCSH tRCD tCRP tCAS tRSH CAS VIH VIL tASR A0 to A10 VIH VIL tRAH tASC COL ADD tCAH COL ADD tCWL tRCS tWCH tWP WE tRWL VIH VIL tDS tDH tDZC DQ (Input) VIH VIL HIGH-Z tOED VALID DATA IN tON VOH DQ (Output) VOL HIGH-Z HIGH-Z tDZO tOEH tON tOEZ OE VIH VIL “H” or “L” Invalid Data DESCRIPTION In the delayed write cycle, tWCS is not satisfied; thus, the data on the DQ pins is latched with the falling edge of WE and written into memory. The Output Enable (OE) signal must be changed from Low to High before WE goes Low (tOED + tDS). 15 To Top / Lineup / Index MB8117800A-60/-70 Fig. 8 – READ-MODIFY-WRITE CYCLE tRWC tRAS RAS tAR VIH VIL CAS VIH VIL tRAD tASR A0 to A10 VIH VIL tRP tRCD tCRP tRAH tASC ROW ADD tCAH COL ADD tCWL tRWL tRWD tAWD tCWD tRCS WE VIH VIL tDS tDZC DQ (Input) tWP tDH VIH VIL VALID DATA IN tOED tCAC tRAC VOH DQ (Output) VOL tAA HIGH-Z tDZO VALID tON tOEA tON HIGH-Z tOEH tOEZ OE VIH VIL tOH “H” or “L” DESCRIPTION The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the read-modifywrite cycle, OE must be changed from Low to High after the memory access time. 16 To Top / Lineup / Index MB8117800A-60/-70 Fig. 9 – FAST PAGE MODE READ CYCLE tRASP tRCD RAS tRHCP VIH VIL tRAD tCRP CAS tPC tCP tCSH tRSH tASR tAR tRRH tCAH tASC tCAH tASC tRAH tCAS tCAS tCAS VIH VIL tASC tRAL tCAH A0 to A10 VIH VIL ROW ADD COL ADD COL ADD WE tRCS VIH VIL tDZC tCDD HIGH-Z HIGH-Z tDZO tOH tON tRAC tOH tCAC tCAC DQ VOH (Output) VOL tRCH tOEL tCPA tDZC tDZO tDZO tOFF tON tOFF HIGH-Z tAA tAA tOEZ tOEA tOEA OE tRCH VIH VIL tDZC DQ (Input) COL ADD tRCS tRCH tRCS tRP tOEZ VIH VIL tOED tOH tOED tOH “H” or “ L” Valid Data DESCRIPTION The fast page mode of operation permits faster sucessive memory operations at multiple column locations of the same row address. This operations is performed by strobing in the row address and maintaining RAS at a Low level and WE at a Hight level druing all successive memory cycles in which the row address is latched. The address time is determined by tCAC, tAA, tCPA, or tOEA, whichever one is the latest in occurring. 17 To Top / Lineup / Index MB8117800A-60/-70 Fig. 10 – FAST PAGE MODE EARLY WRITE CYCLE (OE = “H” or “L”) tRASP RAS VIH VIL tCSH tCRP tPC tRCD CAS tCAS tAR tCAH tASR VIH VIL ROW ADD tCAS tCAH tCAH tASC tASC COL ADD COL ADD COL ADD tWCH tWCS tWCS tWCH tWCS tWCH VIH VIL tDHR tDS DQ (Input) tCAS tASC tWCR WE tCP tRP VIH VIL tRAH A0 to A10 tRSH VIH VIL DQ VOH (Output) VOL VALID DATA tDH tDS tDH VALID DATA tDS tDH VALID DATA HIGH-Z “H” or “ L” DESCRIPTION The fast page mode early write cycle is executed in the same manner as the fast page mode read cycle except the states of WE and OE are reversed. Data appearing on the DQ pins is latched on the falling edge of CAS and written into memory. During the fast page mode early write cycle, including the delayed (OE) write and read-modify-write cycles, tCWL must be satisfied. 18 To Top / Lineup / Index MB8117800A-60/-70 Fig. 11 – FAST PAGE MODE DELAYED WRITE CYCLE RAS tRASP VIH VIL tCSH tCPR CAS tCAS VIH VIL tRAH tASC tAR tASC ROW ADD COL ADD COL ADD tCWL tWCH tRWL tWCH tWP VIH VIL VALID tOED tON OE VIH VIL tDH tDH VIH VIL tOEH VALID tON tON tDZO tWP tDS tDS DQ VOH (Output) VOL tCWL tCAH tCAH tDZC DQ (Input) tRP tRSH tCAS tRCS WE tCP VIH VIL tASR A0 to A10 tPC tRCD tON tOEZ tOED tOEH tOEZ “H” or “ L” Valid Data DESCRIPTION The fast page mode delayed write cycle is executed in the same manner as the fast page mode early write cycle except for the states of WE and OE. Input data on the DQ pins are latched on the falling edge of WE and written into memory. In the fast page mode delayed write cycle, OE must me changed from Low to High before WE goes Low (tOED + tT + tDS). 19 To Top / Lineup / Index MB8117800A-60/-70 Fig. 12 – FAST PAGE MODE READ-MODIFY-WRITE CYCLE RAS tRASP VIH VIL tRWL tCRP CAS tRCD VIH VIL tRPWC tCWD tRAH A0 to A10 VIH VIL tCP tRAD tCAH ROW ADD tCAH COL ADD COL ADD tCPWD tAWD tWCL tWP tRCS WE tCWD tASC tASC tASR VIH VIL tWP tDS tDS tDZC VIH VIL tOED tAA DQ VOH (Output) VOL tDH VALID VALID tOED tCAC tAA tCAC tON tON tON tON tDZO OE tDH HIGH-Z tRAS tWCL tRCS tRWD DQ (Input) tRP tOEZ tOEH tOEA tOEZ tOEH VIH VIL tOEA tCPA “H” or “ L” Valid Data DESCRIPTION During the fast page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input data appears at the DQ pins during a normal cycle. 20 To Top / Lineup / Index MB8117800A-60/-70 Fig. 13 – RAS-ONLY REFRESH (WE = OE = “H” or “L”) tRC RAS VIH VIL tRAS tRP tASR A0 to A10 VIH VIL tRAH tRPC ROW ADDRESS tCRP tCRP CAS VIH VIL tOFF tOH VOH DQ (Output) VOL HIGH-Z “H” or “L” DESCRIPTION Referesh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row addresses every 32.8-milliseconds. Three refresh modes are available: RAS-only refresh, CAS-before-RAS refresh, and hidden refresh. RAS-only refresh is performed by keeping RAS Low and CAS High throughout the cycle; the row address to be refreshed is latched on the falling edge of RAS. During RAS-only refresh, DOUT pins are kept in a high-impedance state. Fig. 14 – CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = “H” or “L”) tRC RAS tCPN CAS VIH VIL tRP tRAS VIH VIL tCSR tCHR tRPC tOFF tOH VOH DQ (Output) VOL HIGH-Z “H” or “L” DESCRIPTION CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If CAS is held Low for the specified setup time (tCSR) before RAS goes Low, the on-chip refresh control clock generators and refresh address counter are enabled. An internal refresh operating automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-before-RAS refresh operation. 21 To Top / Lineup / Index MB8117800A-60/-70 Fig. 15 – HIDDEN REFRESH CYCLE tRC tRC tRP tRAS RAS tOEL VIH VIL tRCD tRP tCRP tRSH tCHR tRAD CAS VIH VIL tRAH tASR tASC tRAL tAR A0 to A10 VIH VIL ROW ADDRESS tCAH COLUMN ADDRESS tRRH tRCS WE tRAS VIH VIL tAA tRAC DQ (Input) tCDD tCAC tDZC VIH VIL HIGH-Z tOFF tON VOH DQ (Output) VOL HIGH-Z tDZO OE tOH VALID DATA OUT tOEA tOEZ tOED VIH VIL “H” or “L” DESCRIPTION A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of CAS and cycling RAS. The refresh row address is provided by the on-chip refresh address counter. This eliminates the need for the external row address that is required by DRAMs that do not have CAS-before-RAS refresh capability. 22 To Top / Lineup / Index MB8117800A-60/-70 Fig. 16 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE RAS VIH VIL tRCD CAS A0 to A10 tCP VIH VIL COLUMN ADDRESSES tCWL tRWL tFCWD tRCS VIH VIL WE tFCAH tASC VIH VIL tDZC tWP tDS DQ (Input) VIH VIL tDH VALID DATA IN HIGH-Z tOED tFCAC VOH DQ (Output) VOL HIGH-Z HIGH-Z tDZO VIH VIL OE tRP tFRSH tFCAS tCRP tON tOEA tOEH tOEZ “H” or “L” Valid Data DESCRIPTION A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function of CAS-before-RAS refresh circuitry. If, a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows: Row Address: Bits A0 through A10 are defined by the on-chip refresh counter. Column Address: Bits A0 through A9 are defined by latching levels on A0-A9 at the second falling edge of CAS. The CAS-before-RAS Counter Test procedure is as follows ; 1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles. 2) Use the same column address throughout the test. 3) Write “0” to all 2048 row addresses at the same column address by using normal write cycles. 4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CASbefore-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 2048 times with addresses generated by the internal refresh address counter. 5) Read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5). (At recommended operating conditions unless otherwise noted.) No. Parameter Symbol 90 Access Time from CAS 91 92 Column Address Hold Time 93 94 CAS to WE Delay Time CAS Pulse Width RAS Hold Time tFCAC tFCAH tFCWD tFCAS tFRSH MB817800A-60 Min. Max. — 50 MB817800A-70 Min. Max. — 55 Unit ns 35 — 35 — ns 70 90 90 — 77 99 99 — ns — ns — ns — — Note: Assumes that CAS-before-RAS refresh counter test cycle only. 23 To Top / Lineup / Index MB8117800A-60/-70 Fig. 17 – SELF REFRESH CYCLE (A0-A10 = WE = OE = “H” or “L”) RAS tCPN tRPC tCSR tCHS VIH VIL CAS tRPS tRASS VIH VIL tOFF tOH VOH DQ (Output) VOL HIGH-Z “H” or “L” A0 to A10, WE, OE = “H” or “L” (At recommended operating conditions unless otherwise noted.) No. Parameter Symbol 100 RAS Pulse Width 101 RAS Precharge Time tRASS tRPS 102 CAS Hold Time tCHS MB817800A-60 Min. Max. — 100 MB817800A-70 Min. Max. 100 — 110 — 125 — ns –50 — –50 — ns Unit µs Note: Assumes self refresh cycle only DESCRIPTION The self refresh cycle provides a refresh operation without external clock and external Address. Self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing generator. If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of tRASS (more than 100 µs), the device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed intervals using internal refresh address counter during “RAS = L” and “CAS = L”. Exit from self refresh cycle is performed by togging RAS and CAS to “H” with specified tCHS min.. In this time, RAS must be kept “H” with specified tRPS min.. Using self refresh mode, data can be retained without external CAS signal during system is in standby. Restriction for Self Refresh operation; For self refresh operation, the notice below must be considered. 1) In the case that distributed CBR refresh are operated between read/write cycles Self refresh cycles can be executed without special rule if 2,048 cycles of distributed CBR refresh are executed within tREF max.. 2) In the case that burst CBR refresh or distributed burst RAS-only refresh are operated between read/write cycles 2,048 times of burst CBR refresh or 2,048 times of burst RAS-only refresh must be executed before and after Self refresh cycles. Read/Write operation RAS Self Refresh operation Read/Write operation tRASS VIH VIL tNS < 2 ms 2,048 burst refresh cycle tSN < 2 ms * 2,048 burst refresh cycle * * read/write operation can be performed non refresh time within tNS or tSN 24 To Top / Lineup / Index MB8117800A-60/-70 ■ PACKAGE DIMENSIONS (Suffix: -PJ) 28-pin plastic SOJ (LCC-28P-M07) +0.35 3.40 −0.20 +.014 .134 −.008 28 * 18.42±0.13(.725±.005) 2.75(.108)NOM 0.64(.025)MIN 15 R0.81(.032)TYP 10.16 (.400) 10.97±0.13 (.432±.005) NOM 9.40±0.51 (.370±.020) INDEX LEAD No 1 +0.05 1.27±0.13 (.050±.005) 0.20 −0.02 +.002 .008 −.001 14 16.51(.650)REF Details of "A" part 2.50(.098)NOM 0.10(.004) 0.81(.032)MAX "A" 0.43±0.10(.017±.004) C 1995 FUJITSU LIMITED C28058S-2C-1 Dimensions in inches (mm) 25 To Top / Lineup / Index MB8117800A-60/-70 (Continued) (Suffix: -PFTN) 28-pin plastic TSOP (II) (FPT-28P-M14) 15 28 Details of "A" part 0.15(.006) 0.25(.010) 0.15(.006) MAX 0.50(.020) MAX INDEX LEAD No. 1 "A" 14 * 18.41±0.10 (.725±.004) 0.40±0.10 (.016±.004) 1.27(.050) TYP. 0.21(.008) 26 1994 FUJITSU LIMITED F28040S-2C-1 M 1.15±0.05(.045±.002) 0.10(.004) 16.51(.650) REF. C 11.76±0.20 (.463±.008) 0.50±0.10 (.020±.004) 10.16±0.10 (.400±.004) 0.125±0.05 (.005±.002) 10.76±0.20 (.424±.008) 0.05(.002)MIN (STAND OFF) Dimensions in inches (mm) To Top / Lineup / Index MB8117800A-60/-70 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. 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Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. http://www.fmap.com.sg/ F9801 FUJITSU LIMITED Printed in Japan 27