V62C1162048L(L) Ultra Low Power 128K x 16 CMOS SRAM Features Functional Description • Low-power consumption - Active: 35mA ICC at 70ns - Stand-by: 10 µA (CMOS input/output) 2 µA (CMOS input/output, L version) The V62C1162048L is a Low Power CMOS Static RAM organized as 131,072 words by 16 bits. Easy Memory expansion is provided by an active LOW (CE) and (OE) pin. • 70/85/100/120 ns access time This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the upper bits I/O9 - I/O16. • Equal access and cycle time • Single +1.8V to2.2V Power Supply • Tri-state output Writing to these devices is performed by taking Chip Enable (CE) with Write Enable (WE) and Byte Enable (BLE/BHE) LOW. • Automatic power-down when deselected • Multiple center power and ground pins for improved noise immunity Reading from the device is performed by taking Chip Enable (CE) with Output Enable (OE) and Byte Enable (BLE/BHE) LOW while Write Enable (WE) is held HIGH. • Individual byte controls for both Read and Write cycles • Available in 44 pin TSOPII / 48-fpBGA / 48-µBGA Logic Block Diagram TSOPII / 48-fpBGA / 48-µBGA (See nest page) Pre-Charge Circuit A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 A0 A1 A3 A4 A5 A6 Row Select A2 A7 Vcc Vss Memory Array 1024 X 2048 A8 A9 I/O1 - I/O8 Data Cont I/O9 - I/O16 Data Cont I/O Circuit Column Select A10 A11 A12 A13 A14 A15 A16 WE OE BHE BLE CE 1 REV. 1.2 May 2001 V62C1162048L(L) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC V62C1162048L(L) MOSEL VITELIC V62C1162048L(L)M 1 2 3 4 5 6 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC B I/O9 BHE A3 A4 CE I/O1 C I/O10 I/O11 A5 A6 I/O2 I/O3 D VSS I/O12 NC A7 I/O4 VCC E VCC I/O13 NC A16 I/O5 VSS F I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 NC A12 A13 WE I/O8 NC A8 A9 A10 A11 NC H Note: NC means no Ball. Top View Top View 48 Ball - 6 x 8 µ BGA (Ultra Low Power) A1 C PACKAGE OUTLINE DWG. SYMBOL UNIT:MM A 1.10+0.10 A1 0.22+0.05 A aaa SIDE VIEW D D1 e 6 5 E E1 4 3 2 1 A B C D E F G H b SOLDER BALL BOTTOM VIEW 2 REV. 1.2 May 2001 V62C1162048L(L) b 0.35 c 0.36(TYP) D 8.00+0.10 D1 5.25 E 6.00+0.10 E1 3.75 e 0.75TYP aaa 0.10 V62C1162048L(L) Absolute Maximum Ratings * Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 +4.0 V Power Dissipation PT − 1.0 W Storage Temperature (Plastic) Tstg -55 +150 0 Temperature Under Bias Tbias -40 +85 0C C * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth Table CE OE WE H L L L L L L L L X L L L X X X H X X H H H L L L H X BLE BHE I/O1-I/O8 I/O9-I/O16 X L H L L L H X H X H L L L H L X H High-Z Data Out High-Z Data Out Data In Data In High-Z High-Z High-Z High-Z High-Z Data Out Data Out Data In High-Z Data In High-Z High-Z Power Standby Active Active Active Active Active Active Active Active Mode Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Output Disable Output Disable * Key: X = Don’t Care, L = Low, H = High Recommended Operating Conditions (TA = 0oC to +70oC / -40oC to 85oC**) Parameter Supply Voltage Input Voltage Symbol Min Typ Max Unit VCC 1.8 2.0 2.2 V Gnd 0.0 0.0 0.0 V VIH 1.6 - VCC + 0.2 V VIL -0.5* - 0.4 V * VIL min = -2.0V for pulse width less than tRC/2. ** For Industrial Temperature 3 REV. 1.2 May 2001 V62C1162048L(L) V62C1162048L(L) DC Operating Characteristics (Vcc =1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter Sym Test Conditions -70 -85 -100 -120 Min Max Min Max Min Max Min Max Unit Input Leakage Current IILII Vcc = Max, Vin = Gnd to Vcc - 1 - 1 - 1 - 1 µA Output Leakage Current IILOI CE = VIH or Vcc= Max, VOUT = Gnd to Vcc - 1 - 1 - 1 - 1 µA Operating Power Supply Current ICC CE = VIL , VIN = VIH or VIL , IOUT = 0 - 5 - 5 - 5 - 5 mA Average Operating Current ICC1 IOUT = 0mA, Min Cycle, 100% Duty - 35 - 35 - 30 - 30 mA ICC2 CE < 0.2V IOUT = 0mA, - 3 - 3 - 3 - 3 mA Cycle Time=1µs, Duty=100% Standby Power Supply Current (TTL Level) ISB CE = VIH - 0.5 - 0.5 - 0.5 - 0.5 mA Standby Power Supply Current (CMOS Level) ISB1 CE > Vcc - 0.2V VIN < 0.2V or VIN > Vcc- 0.2V - 10 - 10 - 10 - 10 µA - 2 - 2 - 2 - 2 µA L Output Low Voltage VOL IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V Output High Voltage VOH IOH = -1 mA 1.6 - 1.6 - 1.6 - 1.6 - V Capacitance (f = 1MHz, TA = 250C) Parameter* Symbol Test Condition Max Unit Input Capacitance Cin Vin = 0V 7 pF I/O Capacitance CI/O Vin = Vout = 0V 8 pF * This parameter is guaranteed by device characterization and is not production tested. AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Condition 70ns/85ns Load for 100ns/120ns 0.4V to 1.6V 5ns CL* 1.0V CL = 30pf + 1TTL Load CL = 100pf + 1TTL Load Figure A. 4 REV. 1.2 May 2001 V62C1162048L(L) TTL * Including Scope and Jig Capacitance V62C1162048L(L) Read Cycle (9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Sym -70 -85 -100 Unit -120 Note Min Max Min Max Min Max Min Max Read Cycle Time tRC 70 - 85 - 100 - 120 - ns Address Access Time tAA - 70 - 85 - 100 - 120 ns Chip Enable Access Time tACE - 70 - 85 - 100 - 120 ns Output Enable Access Time tOE - 40 - 40 - 50 - 60 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tLZ 10 - 10 - 10 - 10 - ns 4,5 Chip Disable to Output in High-Z tHZ - 30 - 35 - 40 - 45 ns 3,4,5 Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns Output Disable to Output in High-Z tOHZ - 25 - 30 - 35 - 40 ns BLE, BHE Enable to Output in Low-Z tBLZ 5 - 5 - 5 - 5 - ns 4,5 BLE, BHE Disable to Output in High-Z tBHZ - 25 - 30 - 35 - 40 ns 3,4,5 BLE, BHE Access Time tBA - 40 - 40 - 50 - 60 ns Write Cycle (11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol -70 -85 -100 Unit -120 Min Max Min Max Min Max Min Max Write Cycle Time tWC 70 - 85 - 100 - 120 - ns Chip Enable to Write End tCW 60 - 70 - 80 - 90 - ns Address Setup to Write End tAW 60 - 70 - 80 - 90 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 50 - 60 - 70 - 80 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 30 - 35 - 40 - 45 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWHZ - 30 - 35 - 40 - 45 ns Output Active from Write End tOW 5 - 5 - 5 - 5 - ns BLE, BHE Setup to Write End tBW 60 - 70 - 80 - 90 - ns 5 REV. 1.2 May 2001 V62C1162048L(L) Note V62C1162048L(L) Timing Waveform of Read Cycle 1 (Address Controlled) tRC Address tAA tOH Data Out Previous Data Valid Data Valid Timing Waveform of Read Cycle 2 tRC Address tAA CE (BLE/BHE) OE Data Out tHZ(3,4,5) tACE High-Z tLZ(4,5) tBA tBHZ(3,4,5) tBLZ(4,5) tOE tOHZ tOH tOLZ Data Valid Notes (Read Cycle) 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE = VIL. 7. Address valid prior to coincident with CE transition Low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. For test conditions, see AC Test Condition, Figure A. 6 REV. 1.2 May 2001 V62C1162048L(L) V62C1162048L(L) Timing Waveform of Write Cycle 1 (Address Controlled) tWC Address tAW CE tWR (5) tCW (3) tBW BLE/BHE tAS (4) tWP (2) WE tDW Data In tDH High-Z tOHZ (6) tOW High-Z (8) Data Out Timing Waveform of Write Cycle 2 (CE Controlled) tWC Address tAW CE tAS (4) tWR (5) tCW (3) tBW BLE/BHE tWP (2) WE tDW Data In High-Z Data Out High-Z tDH tWHZ (6) tLZ High-Z (8) Timing Waveform of Write Cycle 3 (BLE/BHE Controlled) tWC Address tAW CE tAS (4) tWR (5) tCW (3) tBW BLE/BHE tWP (2) WE tDW Data In High-Z Data Out High-Z REV. 1.2 May 2001 V62C1162048L(L) tDH tWHZ (6) tBLZ High-Z (8) 7 V62C1162048L(L) Notes (Write Cycle) 1. 2. All write timing is referenced from the last valid address to the first transition address. A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going low: A write ends at the earliest transition among CE going high and WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CE going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. 6. If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should not be applied. 11. For test conditions, see AC Test Condition, Figure A. 8 REV. 1.2 May 2001 V62C1162048L(L) V62C1162048L(L) Data Retention Characteristics (L Version Only)(1) Parameter Symbol Test Condition VCC for Data Retention VDR Data Retention Current ICCDR Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or Operation Recovery Time(2) tR VIN < 0.2V CE > VCC - 0.2V Min Max Unit 1.0 - V - 1 µA 0 - ns tRC - ns Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C) Data Retention Mode VCC Vcc_typ V DR > 1.0V tCDR CE Vcc_typ tR V DR V IH V IH Notes (Write Cycle) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is High for read cycle. CE and OE are LOW for read cycle. Address valid prior to or coincident with CE transition LOW. All read cycle timings are referenced from the last valid address to the first transtion address. CE or WE must be HIGH during address transition. All write cycle timings are referenced from the last valid address to the first transition address. 9 REV. 1.2 May 2001 V62C1162048L(L) V62C1162048L(L) Ordering Information Device Type* Speed Package V62C1162048L-70T V62C1162048L-85T V62C1162048L-100T V62C1162048L-120T 70 ns 85 ns 100 ns 120 ns 44-pin TSOP Type 2 V62C1162048LL-70T V62C1162048LL-85T V62C1162048LL-100T V62C1162048LL-120T 70 ns 85 ns 100 ns 120 ns V62C1162048L(L)-70B V62C1162048L(L)-85B V62C1162048L(L)-100B V62C1162048L(L)-120B 70 ns 85 ns 100 ns 120 ns 48-fpBGA V62C1162048L(L)-70M V62C1162048L(L)-85M V62C1162048L(L)-100M V62C1162048L(L)-120M 70 ns 85 ns 100 ns 120 ns 48-µBGA * For Industrial temperature tested devices, an “I” designator will be added to the end of the device number. 10 REV. 1.2 May 2001 V62C1162048L(L) MOSEL VITELIC V62C1162048L(L) WORLDWIDE OFFICES U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888 JAPAN SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 44-1698-748515 FAX: 44-1698-748516 ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402 GERMANY (CONTINENTAL EUROPE & ISRAEL) BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22 U.S. SALES OFFICES NORTHWESTERN SOUTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807 © Copyright 2001, MOSEL VITELIC Inc. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC CENTRAL, NORTHEASTERN & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 214-826-6176 FAX: 214-828-9754 5/01 Printed in U.S.A. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. 3910 N. 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