VCA VCA8613 ® 861 3 SBOS200C – APRIL 2003 – REVISED MARCH 2004 8-Channel VARIABLE GAIN AMPLIFIER ● INTEGRATED INPUT CLAMP DIODES FEATURES ● DIFFERENTIAL OUTPUT ● 3V OPERATION ● LOW INPUT NOISE: 1.2nV √Hz at fIN = 5MHz ● EXTREMELY LOW POWER OPERATION: 75mW/CHANNEL ● INTEGRATED LOW-PASS, 2-POLE FILTER 14MHz BANDWIDTH ● INTEGRATED INPUT LNA ● READABLE CONTROL REGISTERS ● INTEGRATED CONTINUOUS WAVE (CW) PROCESSOR DESCRIPTION The VCA8613 is an 8-channel variable gain amplifier ideally suited to portable ultrasound applications. Excellent dynamic performance enables use in low-power, high-performance portable applications. Each channel consists of a Low-Noise pre-Amplifier (LNA) and a Variable Gain Amplifier (VGA). The differential outputs of the LNA can be switched through the 8x10 cross-point switch, which is programmable through the serial interface input port. The output of the LNA is fed directly into the VGA stage. The VGA consists of two parts, a Voltage Controlled Attenuator (VCA) and a Programmable Gain Amplifier (PGA). The gain and gain range of the PGA can be digitally configured separately. The gain of the PGA can be varied between two discrete settings of 21dB and 26dB. The VCA has four programmable maximum attenuation settings: 29dB, 33dB, 36.5dB, and 40dB. Also, the VCA can be continuously varied by a control voltage from 0dB to a maximum of 29dB, 33dB, 36.5dB, and 40dB. The output of the PGA feeds directly into an integrated 2-pole, low-pass filter, allowing for direct connection to a differential input Analog-to-Digital Converter (ADC), such as the ADS5121 or ADS5122 from Texas Instruments. The VCA8613 is available in a TQFP-64 package. 5x8 FIFO D(0-3) CW(1-10) CW Processor DATA CLK Serial Interface Analog Control CS LNA LNAIN1 VLNA PGA • • • LNA LNAIN8 Attenuator 2-Pole Filter OutP(1) OutN(1) • • • Attenuator PGA 2-Pole Filter OutP(8) OutN(8) VLNA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2003-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +AVDD ............................................................................................... +3.6V Analog Input ......................................................... –0.3V to +AVDD + 0.3V Logic Input ............................................................ –0.3V to +AVDD + 0.3V Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature .................................................................... +150°C Thermal Resistance, Juction-to-Ambient (θJA) ........................... 66.6°C/W Thermal Resistance, Junction-to-Case (θJC) ............................... 4.3°C/W This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION(1) PRODUCT VCA8613 " PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING TQFP-64 PAG –40°C to +85°C VCA8613Y VCA8613YT Tape and Reel, 250 " " " " VCA8613YR Tape and Reel, 1500 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. 2 VCA8613 www.ti.com SBOS200C ELECTRICAL CHARACTERISTICS: AVDD = 3V At TA = +25°C, load resistance = 500Ω on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended, pre-amp gain is fixed at +24.5dB, fIN = 2MHz, PG = 01, and the output from the VCA is differential unless otherwise noted. VCA8613 PARAMETER PREAMPLIFIER Input Resistance Input Capacitance Input Bias Current Maximum Input Voltage(1) Input Voltage Noise (TGC) Input Voltage Noise (CW) Output Swing (Differential) Bandwidth Gain ACCURACY Gain Slope Gain Error Output Offset Voltage GAIN CONTROL INTERFACE Input Voltage (VCACNTRL) Range Input Resistance Response Time POWER SUPPLY Specified Operating Range Power-Down Delay Power-Up Delay Power Dissipation (TGC Mode) CONDITIONS MIN TYP MAX 4.5 80 1 110 1.2 1.6 2 70 25 fIN = 5MHz fIN = 5MHz 0.2V – 1.7V, VCACNTRL 0.2V – 1.7V, VCACNTRL Differential kΩ pF nA mVPP nV/ √Hz nV/ √Hz V MHz dB 20 20 dB/V dB mV 0 to 2.0 1 0.2 V MΩ µs 2 40dB Gain Change, PG = 11 2.85 Operating All Channels PROGRAMMABLE VGA AND LOW-PASS FILTER –3dB Cutoff (low-pass) –3dB Cutoff (high-pass) Slew Rate Output Impedance Crosstalk Output Common-Mode Output Swing (Differential)(2) 3rd-Harmonic Distortion 2nd-Harmonic Distortion Group Delay Variation 3.0 5 20 600 3.15 700 12 800 300 10 49 1 –65 –65 ±3 CONTINUOUS WAVE PROCESSOR CW Output Compliance Voltage V/ I Converter Transconductance Maximum CW Output Current 3 10.35 LOGIC INPUTS VIN LOW (input low voltage) VIN HIGH (input high voltage) Input Current Input Pin Capacitance Clock Input Frequency 11.5 2.0 0 2.1 2 –50 –50 V µs µs mW MHz kHz V/µs Ω dB V VPP dB dB ns 3.3 12.65 V mA/V mA 0.6 VDD ±1 V V µA pF Hz 5 10k UNITS 25M NOTES: (1) Under conditions that input signal is within linear range of LNA. (2) Under conditions that signal is within linear range of output amplifier. VCA8613 SBOS200C www.ti.com 3 AGND IN7 AGND IN8 AVDD CW0 CW2 CW4 CW6 CW8 AGND AVDD VCNTRL VLNA AGND VREF PIN CONFIGURATION 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 IN6 1 48 OUT8 AGND 2 47 OUT8 IN5 3 46 OUT7 AGND 4 45 OUT7 DVDD 5 44 OUT6 DGND 6 43 OUT6 DOUT 7 42 OUT5 CLK 8 DIN 9 40 OUT4 41 OUT5 VCA8613 20 21 22 23 24 25 26 27 28 29 30 31 32 VCM AGND VREFB 19 VFIL 18 AVDD 17 AGND 33 OUT1 CW9 IN3 16 CW7 34 OUT1 CW5 AGND 15 CW3 35 OUT2 CW1 IN4 14 AVDD 36 OUT2 IN1 37 OUT3 AGND 13 AGND 38 OUT3 DVDD 12 IN2 39 OUT4 AGND CS 10 DGND 11 PIN DESCRIPTIONS 4 PIN DESIGNATOR 5, 12 2, 4, 13, 15, 17, 19, 27, 31, 50, 54, 62, 64 1, 3, 14, 16, 18, 20, 61, 63 22-26, 55-59 51 29 30 34, 36, 38, 40, 42, 44, 46, 48 33, 35, 37, 39, 41, 43, 45, 47 52 9 10 8 7 21, 28, 53, 60 6, 11 49 32 DVDD AGND IN(1-8) CW(0-9) VLNA VFIL VCM OUT(1-8) OUT(1-8) VCNTRL DIN CS CLK DOUT AVDD DGND VREF VREFB DESCRIPTION Digital Supplies Analog Ground Single-Ended LNA Inputs Continuous Wave Outputs Reference Voltage For LNA—Internally Generated; Requires External Bypass Cap Reference Voltage for Output Filter—Internally Generated; Requires External Bypass Cap Common-Mode Voltage—Internally Generated; Requires External Bypass Cap Positive Polarity PGA Outputs Negative Polarity PGA Outputs Attenuator Control Input Serial Data Input Pin Serial Data Chip Select Serial Data Input Clock Serial Data Output Pin Analog Supplies Digital Ground Reference Voltage for Attenuator—Internally Generated; Requires External Bypass Bandgap Reference Voltage—Internally Generated; Requires External Bypass Cap VCA8613 www.ti.com SBOS200C INPUT REGISTER BIT MAPS Byte 1—Control Byte Register Map BIT # NAME DESCRIPTION LSB 1 2 3 4 5 6 MSB 1 W/R PWR A0 A1 Mode PG0 PG1 Start Bit Always a “1”—40-bit count-down starts upon first “1” after chip select. 1 = Write, 0 = Read—Read prevents latching of DATA only—Control register still latched. Entire Chip. Power Control—1 = Off—Otherwise chip is on. Attenuator Control Bit Attenuator Control Bit 1 = TGC Mode (CW Powered Down), 0 = CW Doppler Mode (TGC Powered Down) LSB of PGA Gain Control MSB of PGA Gain Control Byte 2—First Data Byte BIT # LSB 1 2 3 4 5 6 MSB NAME Data Data Data Data Data Data Data Data 1:0 1:1 1:2 1:3 2:0 2:1 2:2 2:3 DESCRIPTION Channel Channel Channel Channel Channel Channel Channel Channel 1, 1, 1, 1, 2, 2, 2, 2, LSB of Matrix Control Matrix Control Matrix Control MSB of Matrix Control LSB of Matrix Control Matrix Control Matrix Control MSB of Matrix Control Byte 3—Second Data Byte BIT # LSB 1 2 3 4 5 6 MSB NAME Data Data Data Data Data Data Data Data 3:0 3:1 3:2 3:3 4:0 4:1 4:2 4:3 DESCRIPTION Channel Channel Channel Channel Channel Channel Channel Channel 3, 3, 3, 3, 4, 4, 4, 4, LSB of Matrix Control Matrix Control Matrix Control MSB of Matrix Control Matrix Control Matrix Control Matrix Control MSB of Matrix Control Byte 4—Third Data Byte BIT # LSB 1 2 3 4 5 6 MSB NAME Data Data Data Data Data Data Data Data 5:0 5:1 5:2 5:3 6:0 6:1 6:2 6:3 DESCRIPTION Channel Channel Channel Channel Channel Channel Channel Channel 5, 5, 5, 5, 6, 6, 6, 6, LSB of Matrix Control Matrix Control Matrix Control MSB of Matrix Control Matrix Control Matrix Control Matrix Control MSB of Matrix Control Byte 5—Fourth Data Byte BIT # LSB 1 2 3 4 5 6 MSB NAME Data Data Data Data Data Data Data Data 7:0 7:1 7:2 7:3 8:0 8:1 8:2 8:3 DESCRIPTION Channel Channel Channel Channel Channel Channel Channel Channel 7, 7, 7, 7, 8, 8, 8, 8, LSB of Matrix Control Matrix Control Matrix Control MSB of Matrix Control Matrix Control Matrix Control Matrix Control MSB of Matrix Control VCA8613 SBOS200C www.ti.com 5 WRITE/READ TIMING Generally follows SPI Timing Specification: • • • • • All writes and reads will be 8 bytes at a time; Separate write and read data lines; Reads will follow the same bit stream pattern seen in the write cycle; Reads will extract data from the FIFO, not the latched register; DOUT data is continuously available and need not be enabled with a read cycle. Selecting a read cycle in the control register only prevents latching of data. The control register is still latched. WRITE CYCLE TIMING t0 t1 CLK 1 2 39 40 t3 t2 t4 t5 CS t7 LSB DATA 1 6 MSB t6 t0 = t1 = 12.5ns minimum t2 = t3 = t4 = t5 = t7 = 2ns minimum t6 = 1ns minimum NOTE: It is highly recommended that the clock be turned off after the required data has been programmed into the VCA8613. SERIAL PORT TIMING TABLE Chip Select (CS ) must be held low (active LOW) during transfer. CS can be held permanently low. PARAMETER t1 t2 t3 t4 t5 t6 t7 6 DESCRIPTION MIN Serial CLK Period Serial CLK HIGH Time Serial CLK LOW Time CS Falling Edge to Serial CLK Falling Edge Data Setup Time Data Hold Time Serial CLK Falling Edge to CS Rising Edge 40 13 13 10 5 5 10 TYP MAX UNITS ns ns ns ns ns ns ns VCA8613 www.ti.com SBOS200C DATA SHIFT SEQUENCE Shift Direction DIN A1, A0 0, 0, 1, 1, MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB DOUT MAXIMUM ATTENUATION PG1, PG0 PGA GAIN 29dB 33dB 36.5dB 40dB 0, 0 0, 1 21dB 26dB 0 1 0 1 TABLE II. PGA Gain Settings. TABLE I. Maximum Attenuation. CHANNEL CW CODING (MSB, LSB) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CHANNEL DIRECTED TO: Output 0 Output 1 Output 2 Output 3 Output 4 Output 5 Output 6 Output 7 Output 8 Output 9 Channel Tied Channel Tied Channel Tied Channel Tied Channel Tied Channel Tied to to to to to to +V +V +V +V +V +V (internal) (internal) (internal) (internal) (internal) (internal) Applies to bytes 2 through 5. TABLE III. CW Coding for Each Channel. VCA8613 SBOS200C www.ti.com 7 TYPICAL CHARACTERISTICS At TA = +25°C, fIN = 2MHz, ATN = 00, PG = 01, VCNTRL = 1.7V, unless otherwise noted. Differential output, 750mVPP, and AVDD = DVDD = 3.0V. GAIN vs VCNTRL (PG = 00) 60 55 55 50 50 45 45 Gain (dB) 35 30 25 ATN = 01 ATN = 11 ATN = 10 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VCNTRL (V) VCNTRL (V) GAIN ERROR vs VCNTRL (PG = 00) GAIN ERROR vs VCNTRL (PG = 01) 2.0 1.5 ATN = 00 ATN = 00 1.0 ATN = 01 0 –0.5 ATN = 11 Gain Error (dB) Gain Error (dB) 1.0 –1.0 0.5 ATN = 11 –0.5 ATN = 10 –1.5 –2.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VCNTRL (V) VCNTRL (V) GAIN ERROR vs VCNTRL GAIN ERROR vs VCNTRL 2.0 2MHz 1.5 1.0 10MHz 0.5 Gain (dB) Gain Error (dB) ATN = 01 0 –1.0 ATN = 10 –2.0 0 5MHz –1.0 –1.5 –2.0 8 ATN = 10 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.5 –0.5 ATN = 11 5 2.0 –1.5 ATN = 01 25 10 0 0.5 30 15 15 5 35 20 20 10 ATN = 00 40 ATN = 00 40 Gain (dB) GAIN vs VCNTRL (PG = 01) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 –40°C +25°C +85°C 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VCNTRL (V) VCNTRL (V) VCA8613 www.ti.com SBOS200C TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, fIN = 2MHz, ATN = 00, PG = 01, VCNTRL = 1.7V, unless otherwise noted. Differential output, 750mVPP, and AVDD = DVDD = 3.0V. GAIN MATCH (VCNTRL = 0.2V) TIME GAIN CONTROL (TGC) CURRENT vs TEMPERATURE 100 210 90 80 70 200 60 Units TGC Current (mA) 205 195 50 40 190 30 20 185 10 0 180 –20 0 20 40 60 80 –1.19 –1.09 –0.99 –0.88 –0.78 –0.68 –0.58 –0.47 –0.37 –0.27 –0.16 –0.06 0.04 0.15 0.25 0.35 0.46 0.56 0.66 0.77 0.87 0.97 1.08 1.18 1.28 –40 Temperature (°C) Delta Gain (dB) GAIN MATCH (VCNTL = 1.7V) CW ACCURACY 100 1600 90 1400 80 1200 70 1000 Units Units 60 50 800 40 600 30 400 20 200 10 0 –0.98 –0.89 –0.81 –0.72 –0.64 –0.55 –0.47 –0.39 –0.30 –0.22 –0.13 –0.05 0.04 0.12 0.20 0.29 0.37 0.46 0.54 0.63 0.71 0.79 0.88 0.96 1.05 11.01 11.08 11.16 11.23 11.31 11.38 11.46 11.53 11.61 11.68 11.76 11.83 11.91 11.98 12.06 12.13 12.20 12.28 12.35 12.50 0 Transconductance (mA/V) Delta Gain (dB) GAIN vs FREQUENCY (ATN = 00, VCNTRL = 1.7V) 50 45 40 35 30 25 20 15 10 5 0 –5 –10 –15 55 PG = 01 50 45 PG = 00 PG = 01 Gain (dB) Gain (dB) GAIN vs FREQUENCY (ATN = 00, VCNTRL = 0.2V) PG = 00 40 35 30 25 20 0.1 1 10 100 0.1 Frequency (MHz) 10 100 Frequency (MHz) VCA8613 SBOS200C 1 www.ti.com 9 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, fIN = 2MHz, ATN = 00, PG = 01, VCNTRL = 1.7V, unless otherwise noted. Differential output, 750mVPP, and AVDD = DVDD = 3.0V. OUTPUT REFERRED NOISE vs VCNTRL (ATN = 00, fIN = 5MHz) 600 600 500 500 Noise (nV/√Hz) Noise (nV/√Hz) OUTPUT REFERRED NOISE vs VCNTRL (ATN = 00, fIN = 2MHz) 400 300 PG = 01 200 PG = 00 100 300 PG = 01 200 PG = 00 100 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.2 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.6 1.8 2.0 1.6 1.8 2.0 VCNTRL (V) INPUT REFERRED NOISE vs VCNTRL (ATN = 00, fIN = 2MHz) INPUT REFERRED NOISE vs VCNTRL (ATN = 00, fIN = 5MHz) 14 14 12 12 10 10 8 0.4 VCNTRL (V) Noise (nV/√Hz) Noise (nV/√Hz) 400 PG = 00 6 PG = 01 8 PG = 00 6 4 4 2 2 PG = 01 0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.2 42 39 39 36 PG = 00 PG = 01 24 36 1.2 1.4 PG = 00 33 30 PG = 01 27 24 21 21 18 18 15 15 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.2 VCNTRL (V) 10 1.0 NOISE FIGURE vs VCNTRL (ATN = 00, fIN = 5MHz) 45 27 0.8 NOISE FIGURE vs VCNTRL (ATN = 00, fIN = 2MHz) 42 30 0.6 VCNTRL (V) 45 33 0.4 VCNTRL (V) Noise Figure (dB) Noise Figure (dB) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VCNTRL (V) VCA8613 www.ti.com SBOS200C TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, fIN = 2MHz, ATN = 00, PG = 01, VCNTRL = 1.7V, unless otherwise noted. Differential output, 750mVPP, and AVDD = DVDD = 3.0V. DISTORTION vs FREQUENCY (ATN = 00, PG = 00, VCNTRL = 2.0V) 3.0 –30 2.8 –35 2.6 –40 2.4 –45 Distortion (dB) Noise (nV/√Hz) INPUT REFERRED NOISE (CW Output) 2.2 2.0 1.8 2nd-Harmonic –60 –65 1.4 –70 1.2 –75 3rd-Harmonic –80 1 1 10 10 Frequency (MHz) Frequency (MHz) DISTORTION vs FREQUENCY (ATN = 00, PG = 01, VCNTL = 2.0V) DISTORTION vs VCNTRL (ATN = 00, PG = 01, fIN = 2MHz, 750mVPP) –30 –30 –35 –35 –40 –40 –45 –50 Distortion (dB) Distortion (dB) –55 1.6 1.0 2nd-Harmonic –55 –60 –65 3rd-Harmonic –70 –45 –50 2nd-Harmonic –55 –60 –65 3rd-Harmonic –70 –75 –75 –80 1 10 0.2 0.5 0.8 1.1 1.4 Frequency (MHz) VCNTRL (V) DISTORTION vs VCNTRL (ATN = 01, PG = 01, fIN = 2MHz, 750mVPP) DISTORTION vs VCNTRL (ATN = 00, PG = 00, 500mVPP) 2nd-Harmonic 1.7 2.0 –30 –30 Under this test condition, at the lowest control voltage, the LNA is overloaded. –35 –40 –40 –45 –45 –50 2nd-Harmonic –55 –60 Under this test condition, at the lowest control voltage, the LNA is overloaded. –35 Distortion (dB) Distortion (dB) –50 –50 2MHz 5MHz –55 10MHz –60 –65 –65 –70 –70 3rd-Harmonic –75 –75 1MHz –80 0.2 0.5 0.8 1.1 1.4 1.7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 –80 2.0 VCNTRL (V) VCNTRL (V) VCA8613 SBOS200C www.ti.com 11 TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, fIN = 2MHz, ATN = 00, PG = 01, VCNTRL = 1.7V, unless otherwise noted. Differential output, 750mVPP, and AVDD = DVDD = 3.0V. DISTORTION vs VCNTRL (ATN = 00, PG = 00, 500mVPP) 3rd-Harmonic –30 –30 –35 –35 –40 –40 –45 –45 –50 Distortion (dB) Distortion (dB) DISTORTION vs VCNTRL (ATN = 00, PG = 01, 500mVPP) 2nd-Harmonic 2MHz –55 –60 –65 5MHz 10MHz –55 –60 –70 1MHz –80 –80 5MHz 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 –75 1MHz 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 –75 VCNTRL (V) VCNTRL (V) DISTORTION vs VCNTRL (ATN = 00, PG = 01, 500mVPP) 3rd-Harmonic CROSSTALK vs VCNTRL (ATN = 00, fIN = 2MHz) CH4 to CH5 –30 –30 –35 –35 –40 –40 –45 Crosstalk (dB) Distortion (dB) –50 –65 10MHz –70 2MHz –50 10MHz –55 –60 –65 –45 PG = 01 –50 PG = 00 –55 –60 –70 5MHz 1MHz –75 –65 –70 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 –80 VCNTRL (V) VCNTRL (V) CROSSTALK vs VCNTRL (ATN = 00, fIN = 5MHz) CH4 to CH5 CROSSTALK vs VCNTRL (ATN = 00, fIN = 10MHz) CH4 to CH5 –30 –30 –35 –35 –40 –40 Crosstalk (dB) Crosstalk (dB) 2MHz –45 PG = 01 –50 PG = 00 –55 –45 –50 PG = 00 –55 PG = 01 –60 –60 –65 –65 –70 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 –70 2.0 VCNTRL (V) 12 VCNTRL (V) VCA8613 www.ti.com SBOS200C TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, fIN = 2MHz, ATN = 00, PG = 01, VCNTRL = 1.7V, unless otherwise noted. Differential output, 750mVPP, and AVDD = DVDD = 3.0V. OVERLOAD RECOVERY vs TIME (ATN = 00, PG = 00, VCNTRL = 1V) OVERLOAD RECOVERY vs TIME (ATN = 00, PG = 01, VCNTRL = 2V) Channel 1 (Output) (2V/div) Channel 1 (Output) (2V/div) The signal is greater than 2VPP input, so the LNA is severely overloaded. Overload recovery time is 192ns. The signal is greater than 40mVPP input, so the LNA is in the linear region and the output amplifier is overloaded. Overload recovery time is 584ns. Channel 2 (Input) (20mV/div) Channel 2 (Input) (1V/div) Time (400ns/div) Time (400ns/div) CW DOPPLER PROCESSOR APPLICATION INFORMATION INPUT CIRCUIT The input of the VCA8613 integrates several commonly used elements. Prior to reaching the input of the VCA, the receive signal should be coupled with a capacitor of at least 1nF, preferably more. When this AC coupling element is inserted, the LNA input bias point is held to a common-mode value of 2.4V by an integrated 4.5kΩ resistor. This common-mode value will change with temperature and may also vary from chip to chip, but for each chip, it will be held constant. In parallel with this resistor are two back-to-back clipping diodes. These diodes prevent excessive input voltages from passing through to the LNA input, preventing deep saturation effects in the LNA itself. LOW-NOISE PRE-AMPLIFIER (LNA) The VCA8613 integrates a low-noise pre-amplifier. Because of the high level of integration in the system, noise performance was traded for power consumption, resulting in an extremely low-power pre-amplifier, with 1.2nV/√Hz noise performance at 5MHz. The LNA is configured as a fixed-gain 25dB amplifier. Of this total gain, 6dB results from the singleended to differential conversion accomplished within the LNA itself. The output of the LNA is limited to a little over 2V differential swing. This implies a maximum input voltage swing of approximately 110mV to be operating in the linear range at 5MHz. Larger input signals can be accepted by the LNA, but distortion performance will degrade with high-level input signals. The VCA8613 integrates many of the elements necessary to allow for the implementation of a simple CW Doppler processing circuit. One circuit that was integrated was a V/I converter following the LNA (see Figure 1). The V/I converter converts the LNA voltage output to a current which is then passed through an 8x10 switch matrix (see Figure 2). Within this switch matrix, any of the eight LNA outputs can be connected to any of ten CW output pins. This is a simple current-summing circuit such that each CW output can represent the sum of any or all the channel currents. The output current for each LNA is equal to the single-ended LNA output voltage swing divided by an internally integrated 700Ω resistor. This resistor value may change ±5% from chip to chip. The CW output pins need a compliance voltage between 3V to 3.3V. The 3V to 3.3V can be applied through either an inductor (see Figure 3) tied to the 3V to 3.3V source or from the inverting input of an op amp circuit (see Figure 4). The architecture of the V/I converter requires a 2mA to 2.5mA current that is generated by the compliance voltage. The CW outputs are typically routed to a passive delay line, allowing coherent summing of the signals. After summing, IQ separation and down conversion to base-band precedes a pair of high-resolution, low sample rate ADCs. VCA8613 SBOS200C www.ti.com 13 VCA8613 VLNACM DC V/I Stage VCM = +1.5V Cross Point Switch I = 2mA to 2.5mA Input LNA CW Output Control Logic Buffer +1.5VDC +700Ω FIGURE 1. Basic CW Processing Block Diagram. V/I Converter Channel 1 Input CW0 CW1 SDI CW2 CW3 Decode Logic CLK CW4 CW5 CW6 SDO CW7 CW8 CW9 +V V/I Converter Channel 8 Input SDI Decode Logic SDO FIGURE 2. Basic CW Cross Point Switch Matrix for All Eight Channels. 3V to 3.3V 3V to 3.3V R To CW Circuitry CW Output I = 2mA to 2.5mA To CW Circuitry CW Output OPA I = 2mA to 2.5mA 3V to 3.3V FIGURE 3. Inductor. 14 FIGURE 4. Op Amp. VCA8613 www.ti.com SBOS200C VOLTAGE-CONTROLLED ATTENUATOR (VCA)—DETAIL The VCA is designed to have a dB-linear attenuation characteristic; that is, the gain loss in dB is constant for each equal increment of the VCACNTRL control voltage. Figure 5 shows a block diagram of the VCA. The attenuator is essentially a variable voltage divider consisting of one series input resistor, RS, and ten identical shunt FETs, placed in parallel and controlled by sequentially-activated clipping amplifiers. Each clipping amplifier can be thought of as a specialized voltage comparator with a soft transfer characteristic and well-controlled output limit voltages. The reference voltages V1 through V10 are equally spaced over the 0V to 1.8V control voltage range. As the control voltage rises through the input range of each clipping amplifier, the amplifier output will rise from 0V (FET completely ON) to VCM – VT (FET nearly OFF), where VCM is the common source voltage and VT is the threshold voltage of the FET. As each FET approaches its OFF state and the control voltage continues to rise, the next clipping amplifier/FET combination takes over for the next portion of the piecewise-linear attenuation characteristic. Thus, low control voltages have most of the FETs turned ON, while high control voltages have most turned OFF. Each FET acts to decrease the shunt resistance of the voltage divider formed by RS and the parallel FET network. The attenuator is comprised of two sections, with five parallel clipping amplifier/FET combinations in each. Special reference circuitry is provided so that the (VCM – VT) limit voltage will track temperature and IC process variations, minimizing the effects on the attenuator control characteristic. In addition to the analog VCACNTRL gain setting input, the attenuator architecture provides digitally-programmable adjustment in eight steps, via the two attenuation bits. These adjust the maximum achievable gain (corresponding to minimum attenuation in the VCA, with VCACNTRL = 1.8V) in 5dB increments. This function is accomplished by providing multiple FET sub-elements for each of the Q1 to Q10 FET shunt elements (see Figure 6). In the simplified diagram of Figure 5, each shunt FET is shown as two sub-elements, QNA and QNB. Selector switches, driven by the MGS bits, activate either or both of the sub-element FETs to adjust the maximum RON and thus achieve the stepped attenuation options. The VCA can be used to process either differential or singleended signals. Fully differential operation will reduce 2ndharmonic distortion by about 10dB for full-scale signals. Input impedance of the VCA will vary with gain setting, due to the changing resistances of the programmable voltage divider structure. At large attenuation factors (that is, low gain settings), the impedance will approach the series resistor value of approximately 120Ω. As with the LNA stage, the VCA output is AC-coupled into the PGA. This means that the attenuation-dependent DC common-mode voltage will not propagate into the PGA, and so the PGA’s DC output level will remain constant. Finally, note that the VCACNTRL input consists of FET gate inputs. This provides very high impedance and ensures that multiple VCA8613 devices may be connected in parallel with no significant loading effects. The nominal voltage range for the VCACNTRL input spans from 0V to 1.8V. Overdriving this input (> 3V) does not affect the performance. PGA POST–AMPLIFIER Figure 7 shows a simplified circuit diagram of the PGA block. PGA gain is programmed through the serial port, and can be configured to 2 different gain settings of 21dB and 26dB, as shown in Table III. A patented circuit has been implemented in the PGA that allows for exceptional overload signal recovery. PGA GAIN 00 01 21 26 TABLE III. PGA Gain Settings. RS OUTPUT INPUT Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B Q5A Q5B VCM A0 A1 Programmable Attenuator Section FIGURE 5. Programmable Attenuator Section. VCA8613 SBOS200C www.ti.com 15 Attenuator Input RS A1-A10 Attenuator Stages Attenuator Output QS Q1 VCM A1 Q2 A2 C1 A3 C2 V1 Q3 A4 C3 V2 Q4 A5 C4 V3 V4 Control Input Q5 Q6 A6 C5 A7 C6 V5 Q7 V6 Q8 A8 C7 V7 Q9 A9 C8 Q10 A10 C9 V8 V9 C10 V10 C1-C10 Clipping Amplifiers 0dB –4dB Attenuation Characteristic of Individual FETs VCM-VT 0 V1 V2 V3 V4 V5 V6 V7 V8 V9 Characteristic of Attenuator Control Stage Output V10 Overall Control Characteristics of Attenuator 0dB –40dB 0.2V Control Signal 1.8V FIGURE 6. Piecewise Approximation to Logarithmic Control Characteristics. 16 VCA8613 www.ti.com SBOS200C PGA BANDWIDTH 00 01 13MHz to 14MHz 11MHz to 12MHz 2MΩ VCM TABLE IV. Cutoff Frequency for PGA Settings. 1kΩ SERIAL INTERFACE OUT+ 80pF Attenuator 80pF OUT– 1kΩ VCM The serial interface of the VCA8613 allows the user flexibility in the use of the part. The following are set from the serial control registers: • Mode • TGC Mode • CW Mode • Attenuation Range • PGA Gain • Power-Down (this is the default state in which the VCA8613 powers up) • CW Output Selection For Each Input Channel The serial interface uses an SPI style of interface format. The Input Register Bit Maps (see page 5) show the functionality of each control register. 2MΩ FIGURE 7. Simplified PGA and Output Filter Circuit. LAYOUT CONSIDERATIONS OUTPUT FILTER The VCA8613 integrates a 2-pole low-pass Butterworth filter in the output stage, as shown in Figure 7. The cutoff frequency is implemented with passive semiconductor elements and as such, the cutoff frequency will not be precise. Table IV shows the cutoff frequency for the different PGA settings. The variation shown in Table IV reflects deviations as measured from chip to chip and over the specified temperature range. The VCA8613 is a multi-channel amplifier capable of high gains that has integrated digital controls. Layout of the VCA8613 is fairly straightforward. By connecting all of the grounds (including the digital grounds) to the analog ground, noise performance will help to be maintained. The analog ground should be a solid plane. Power-supply decoupling and decoupling of the control voltage (VCACNTRL) pin are essential in order to ensure that the noise performance be maintained. For further help in determining basic values, please refer to Figure 8. VCA8613 SBOS200C www.ti.com 17 J27 VCNTRL 1 C39 0.1µF C54 2.2µF +3V C83 0.1µF +3V 5 12 DOUT CLK DIN CS 7 8 9 10 6 11 Input 8 Input 7 Input 6 Input 5 Input 4 Input 3 Input 2 Input 1 61 63 1 3 14 16 18 20 62 64 2 4 13 15 17 19 DVDD VFIL DVDD VLNA DOUT CW0 CLK CW2 DIN CS DGND DGND IN8 IN7 IN6 IN5 IN4 IN3 IN2 IN1 AGND AGND AGND AGND AGND AGND AGND C55 2.2µF U15 VCA8613 CW4 CW6 CW8 CW9 CW7 CW5 CW3 CW1 OUT8 OUT8 OUT7 OUT7 OUT6 OUT6 OUT5 OUT5 OUT4 OUT4 OUT3 C84 0.1µF 29 51 59 58 57 56 55 26 25 24 23 22 48 47 46 45 44 43 42 41 40 39 38 CW0 C56 2.2µF C85 0.1µF CW2 CW4 CW6 CW8 CW9 CW7 CW5 CW3 CW1 OUT8 OUT8 OUT7 OUT7 OUT6 OUT6 OUT5 OUT5 OUT4 OUT4 OUT3 AGND FIGURE 8. Basic Connection Diagram. 18 VCA8613 www.ti.com SBOS200C PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY VCA8613YR ACTIVE TQFP PAG 64 1500 VCA8613YT ACTIVE TQFP PAG 64 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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