TI VCA8500

VCA8500
www.ti.com
SBOS390 – JANUARY 2008
8-Channel, Ultra-Low Power Variable Gain Amplifier
with Low-Noise Pre-Amp
FEATURES
APPLICATIONS
• Ultra-low Power: 63mW/Channel
• Low Noise: 0.8nV/√Hz
• Low-Noise Pre-amp (LNP):
– 20dB Fixed Gain
– 250mVPP Linear Input Range
• Variable Gain Amplifier:
– Gain Control Range: 45dB
– Selectable PGA Gain: 20dB, 25dB, 27dB,
30dB
– Fast Overload Recovery
– Output Clamping Control
• Integrated Low-Pass Filter:
– Second-Order, Linear Phase
– Bandwidth: 10MHz, 15MHz
• High Accuracy:
– Low Gain Error: ±0.25 dB
– Excellent Channel Matching: ±0.5dB
• Distortion, HD2: –50dBc at 5MHz
• Integrated CW Switch Matrix:
– Easy Current Summing
• Serial Control Interface
• Small Package: QFN-64, 9×9 mm
•
23
SDI
LNA
IN
Logic
LNA
20dB
Medical Imaging, Ultrasound Systems
– Portable Systems
– Low-, Mid-Range Systems
DESCRIPTION
The VCA8500 is an 8-channel variable gain amplifier
consisting of a Low-Noise Pre-amplifier (LNP) and a
Variable-Gain Amplifier (VGA). This combination,
along with the device features, makes it ideal for a
variety of ultrasound systems.
The LNP gain is fixed at 20dB, and has excellent
noise and signal handling characteristics. The gain of
the voltage-controlled attenuator can vary over a
45-dB range with a 0V to 1.2V control voltage
common to all channels of the VCA8500.
The Post-Gain Amplifier (PGA) can be programmed
for four gain settings: 20dB, 25dB, 27dB, or 30dB
gain. As a means to improve system overload
recovery time, the VCA8500 provides an internal
clamping function. The PGA settings as well the
clamp levels are controlled through the serial
interface.
The VCA8500 is built on TI’s BiCOM process and is
available in a small, 64-pin QFN PowerPAD™
package.
CW Switch Matrix
(8 in ´ 10 out)
VCA
(0dB to
-45dB)
CW
OUT
(1)
PGA
Clamping
Circuit
LPF
(Twopole)
OUT
OUT
VCA8500
(1 of 8 Channels)
Gain
Control
NOTE (1): 20dB, 25dB, 27dB, or 30dB gain setting.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2008, Texas Instruments Incorporated
PRODUCT PREVIEW
1
VCA8500
www.ti.com
SBOS390 – JANUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
(1)
(2)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
VCA8500
QFN-64
RGC
–40°C to +85°C
VCA8500
TRANSPORT
MEDIA, QUANTITY
Tape and Reel, 250
Tape and Reel, 2500
ECO STATUS (2)
Pb-Free, Green
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Eco-Status information: Additional details including specific material content can be accessed at www.ti.com/leadfree
GREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight.
N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go towww.ti.com/leadfree.
Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total
product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.
PRODUCT PREVIEW
NOTE
These packages conform to Lead-Free and Green Manufacturing Specifications.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
Input voltage range (2)
Voltage range at (tbd)
Voltage on outputs
VCA8500
UNIT
–0.3 to AVDD to +0.3
V
–0.3 to AVDD to +0.3
V
–0.3 to DVDD to +0.3
V
TBD
V
–0.3 to AVDD to +0.3
V
–0.3 to DVDD to +0.3
V
Peak output current
Internally limited
ESD rating, HBM
2k
V
ESD rating, CDM
500
V
Operating virtual junction temperature range, TJ
–40 to +150
°C
Operating ambient temperature range, TA
–40 to +85
°C
Storage temperature range, Tstg
–65 to +150
°C
(1)
(2)
2
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
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SBOS390 – JANUARY 2008
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (≤ 1µF) input configuration to the preamp
(LNA), fIN = 5MHz, VCNTL = 1.0V, VCA output is 2VPP differential, RLOAD = 1kΩ on each output to ground, unless otherwise noted.
VCA8500
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
PREAMPLIFIER (LNA)
LNA gain
Single-ended input to differential output
20
Accuracy
dB
±0.5
dB
kΩ
ZIN
Input resistance
At f = 4MHz
8
CIN
Input capacitance
Including internal ESD and clamping
diodes
30
VIN
Input voltage
Linear operation (THD ≤ –40dBc)
250
Maximum input voltage (2)
Internal diode limited
600
mVPP
eN, RTI
Input voltage noise
At f = 2MHz (calculated)
0.75
nV/√Hz
IN, RTI
Input current noise
At f = 2MHz
3.0
pA/√Hz
VCMI
Common-mode voltage, inputs
Internally generated
2.4
V
BW
Bandwidth
Small-signal, –3dB
70
MHz
SR
Slew rate
TBD
V/µs
PGA = 30dB, RS = 0Ω, f = 2MHz
0.8
nV/√Hz
PGA = 20dB
0.9
nV/√Hz
dc to 10MHz, Single-Ended,
Either Output
<1
Ω
TBD
mA
35
pF
mVPP
eN, RTI
Input voltage noise
ZOUT
Output impedance
IOUT-SC
Output short-circuit current
Overload distortion
(second-harmonic)
VIN = 250mVPP
–40
< –35
dBc
Crosstalk, channel-to-channel
Worst case; Gain = TBDdB
TBD
–55
dBc
Gain = max (50dB)
–50
dBc
Noise figure
RS = RIN = 50Ω (TBDdB max gain)
TBD
Group delay variation
1MHz to TBDMHz, full gain range
±2
Delay matching
Between channels
Overload recovery time
To within 1% of 2VPP output at 40dB gain
(VCNTL = TBDV + 30dB PGA)
CL
Maximum capacitive output loading
50Ω series R in each output
VOUT
Output voltage range (2)
Differential, non-clipped
VCMO
Output common-mode voltage
NF
HD2
Second-harmonic distortion
HD3
Third-harmonic distortion
IMD3
(1)
(2)
Two-tone intermodulation
dB
±3
ns
TBD
ns
1
µs
TBD
pF
2
VPP
1.65
VDC
fIN = 5MHz, VCNTL = TBDV;
Gain = TBD, VOUT = 1VPP
–50
TBD
dBc
fIN = 5MHz, VCNTL = TBDV;
Max gain, VOUT = 2VPP
–42
–50
dBc
fIN = 5MHz, VCNTL = TBDV;
Gain = TBD, VOUT = 1VPP
–48
TBD
dBc
fIN = 5MHz, VCNTL = TBDV;
Max gain, VOUT = 2VPP
–40
–48
dBc
–40
dBc
f1 = TBDMHz, f2 = TBDMHz,
VCNTL = TBDV; VOUT = 1VPP
PRODUCT PREVIEW
TGC SIGNAL PATH (LNA, VCA, PGA)
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
Second, third-harmonic distortion less than or equal to −TBDdB.
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SBOS390 – JANUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (≤ 1µF) input configuration to the preamp
(LNA), fIN = 5MHz, VCNTL = 1.0V, VCA output is 2VPP differential, RLOAD = 1kΩ on each output to ground, unless otherwise noted.
VCA8500
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
CW SIGNAL PATH
Output transconductance (V/I)
Signal current
15
mA/V
2.4 (±1.2)
mAPP
IOUT-CW
Dynamic CW output current
IOUT-DC
Static CW output current
0.9
mA
VCMO
Output common-mode voltage
2.5
VDC
VCout
Output compliance range
COUT
Output capacitance
ZOUT
Output impedance
Symmetric around VCMO
TBD
±0.5
TBD
< 10
V
pF
50
kΩ
HD2
TBD
dBc
PRODUCT PREVIEW
THDCW
Harmonic distortion
HD3
TBD
dBc
eN, RTI
Input voltage noise, CW mode
At f = 2MHz
1.1
nV/√Hz
Signal-dependent noise (RTO)
At 2kHz offset from
2MHz CW carrier
+2
dB
At 2kHz offset from
5MHz CW carrier
+2
dB
Output noise correlation factor
Summing of eight channels
[compared to ideal 0dB (SNR)]
0.6
dB
Low-pass filter (second-order)
–3dB point, VCNTL = 1.2V
FILTER
LPF
HPF
10
MHz
Tolerance
±10
±15
Group delay (variation)
TBD
ns
%
Gain flatness
–1dB point
TBD
MHz
High-pass filter (first-order, due to
internal ac coupling)
–3dB point, VCNTL = 1.2V
150
kHz
Gain error (VCA) (3)
VCNTL = 0V to 1.2V
Gain range
VCNTL = 0V to 1.2V
Gain slope
VCNTL = 0V to 1.2V
Gain matching, channel-to-channel
VCNTL = 0V to 1.2V
ACCURACY
Gain, PGA
VOS
TBD
±0.25
±0.5
45
TBD
37.5
±0.5
dB
dB/V
±1.5
20, 25, 27,
30
Selectable through SDI
dB
dB
dB
Output offset voltage
tab
Differential
–25
±5
+25
mV
tab
Common-mode
–50
±25
+50
mV
GAIN CONTROL INTERFACE
VCNTL
Input voltage range
Gain range = 45dB
Input resistance
Response time
Gain control bandwidth
DIGITAL INPUTS (SDI)
(4) (5)
VCNTL= 0V to 1.2V step;
to 90% Signal Level
0 to 1.2
V
25
kΩ
0.75
µs
1.5
MHz
(PD, DIN, DOUT, CLK, RST)
VIH
VIH, High-level input voltage
2.0
VD
VIL
VIL, Low-level input voltage
0
0.8
IIN
Input current
fCLK
Clock frequency
(3)
(4)
(5)
4
V
µA
±10
10k
V
20M
Hz
Input resistance
1
MΩ
Input capacitance
5
pF
Compared to a standard curve. This is also Gain Error vs VCONTROL.
Parameters ensured by design; not production tested.
Internal pull-up/pull-down resistors.
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SBOS390 – JANUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (≤ 1µF) input configuration to the preamp
(LNA), fIN = 5MHz, VCNTL = 1.0V, VCA output is 2VPP differential, RLOAD = 1kΩ on each output to ground, unless otherwise noted.
VCA8500
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Specified
3.14
3.3
3.47
V
Operating
3.0
3.3
3.6
V
Specified
3.14
3.3
3.47
V
Operating
3.0
3.3
3.6
TEST
LEVEL (1)
POWER SUPPLY
DVDD
Analog aupply voltage
Digital supply voltage
AVDD1 + DVDD quiescent current
AVDD2
TBD
Analog supply voltage (VCA, CW)
4.75
AVDD2 quiescent current
5.0
V
mA
5.25
8
V
mA
IQ
Total quiescent current
All channels, no signal
148
PDtot
Total power dissipation
TGC-mode
504
CW-mode
450
PDT
Power-down dissipation, total
IPD
Total power-down current
1.5
mA
Power-up response time
50
µs
Power-down response time
10
µs
18
mW
PDF
Power-down dissipation, fast-mode
PD to Valid output (90% level)
5
Power-down and power-up;
PD to Valid output (90% level)
Power-down, fast-mode
PSRR
Power-supply ripple rejection
TBD
Gain < max (TBD), f < 10kHz
mA
TBD
mW
mW
10
5
TBD
mW
PRODUCT PREVIEW
AVDD1
µs
dB
THERMAL CHARACTERISTICS
Temperature range
Thermal resistance, θJA
Thermal resistance, θJC
Ambient, operating
Soldered pad; four-layer PCB
with thermal vias
–40
+85
°C
22.5
°C/W
17.0
°C/W
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SBOS390 – JANUARY 2008
DEVICE INFORMATION
55
54
53
PD
56
CW0
57
CW2
58
CW1
59
CW4
D_OUT
60
CW3
RST
61
CLK
DVDD
62
D_IN
CW5
63
CW7
64
CW6
CW9
CW8
RGC PACKAGE
QFN-64
(TOP VIEW)
52
51
50
49
VBL1
1
48
VBL5
IN1
2
47
IN5
AVDD1
3
46
AVDD1
VBL6
4
45
VBL2
5
44
IN6
VBL3
6
43
VBL7
42
IN7
IN2
IN3
7
VBL4
8
IN4
9
VCA8500
TM
PowerPAD
41
VBL8
40
IN8
34
VREFL
33
AVDD1
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OUT8
17
OUT8
15
16
OUT7
VCM
AVDD1
OUT7
VREFH
OUT6
35
OUT6
14
OUT5
VB4
VB5
OUT5
VB6
36
OUT1
37
13
OUT1
12
VB1
OUT2
VB3
OUT2
VB2
OUT3
AVDD2
38
OUT3
39
11
OUT4
10
OUT4
PRODUCT PREVIEW
VCNTL
AVDD2
Table 1. TERMINAL FUNCTIONS
TERMINAL
6
PIN NO.
NAME
1
VBL1
I/O
DESCRIPTION
2
IN1
3
AVDD1
4
IN2
5
VBL2
6
VBL3
7
IN3
8
VBL4
9
IN4
10
VCNTL
11
AVDD2
12
VB3
Internal bias voltage; bypass with 0.1µF (min)
13
VB1
Internal bias voltage; bypass with 2.2µF (1.0µF min)
14
VB5
Internal bias voltage; bypass with 0.1µF (min)
15
VCM
Internal common-mode voltage; bypass with 0.1µF (min)
16
AVDD1
17
OUT4
O
PGA output channel 4 (inverted)
18
OUT4
O
PGA output channel 4
19
OUT3
O
PGA output channel 3 (inverted)
20
OUT3
O
PGA output channel 3
Internal bias voltage; bypass with 0.1µF (min)
I
LNA input channel 1
+3.3V analog supply
I
LNA input channel 2
Internal bias voltage; bypass with 0.1µF (min)
Internal bias voltage; bypass with 0.1µF (min)
I
LNA input channel 3
Internal bias voltage; bypass with 0.1µF (min)
LNA input channel 4
I
Attenuator control voltage input (all channels)
+5V Analog supply (VCA, CW)
+3.3V analog supply
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Table 1. TERMINAL FUNCTIONS (continued)
PIN NO.
NAME
I/O
DESCRIPTION
21
OUT2
O
PGA output channel 2 (inverted)
22
OUT2
O
PGA output channel 2
23
OUT1
O
PGA output channel 1 (inverted)
24
OUT1
O
PGA output channel 1
25
OUT5
O
PGA output channel 5 (inverted)
26
OUT5
O
PGA output channel 5
27
OUT6
O
PGA output channel 6 (inverted)
28
OUT6
O
PGA output channel 6
29
OUT7
O
PGA output channel 7 (inverted)
30
OUT7
O
PGA output channel 7
31
OUT8
O
PGA output channel 8 (inverted)
32
OUT8
O
PGA output channel 8
33
AVDD1
+3.3V analog supply
34
VREFL
Clamp level low, 2.0V; bypass with 0.1µF (min)
35
VREFH
Clamp level high, 2.7V; bypass with 0.1µF (min)
36
VB4
Internal bias voltage; bypass with 0.1µF (min)
37
VB6
Internal bias voltage; bypass with 0.1µF (min)
38
VB2
Internal bias voltage; bypass with 0.1µF (min)
39
AVDD2
40
IN8
41
VBL8
42
IN7
43
VBL7
44
IN6
PRODUCT PREVIEW
TERMINAL
+5V analog supply (VCA, CW)
I
LNA input channel 8
Internal bias voltage; bypass with 0.1µF (min)
I
LNA input channel 7
Internal bias voltage; bypass with 0.1µF (min)
I
LNA input channel 6
45
VBL6
46
AVDD1
Internal bias voltage; bypass with 0.1µF (min)
47
IN5
48
VBL5
49
PD
I
Power-down pin for fast mode; active high
50
CW0
O
CW channel 0 current output
51
CW1
O
CW channel 1 current output
52
CW2
O
CW channel 2 current output
53
CW3
O
CW channel 3 current output
54
CW4
O
CW channel 4 current output
55
D_IN
I
Serial data input
56
CLK
I
Clock input for serial interface
57
D_OUT
O
Serial data output
58
RST
I
Reset input; rising edge resets register to default values.
59
DVDD
60
CW5
CW channel 5 current output
61
CW6
CW channel 6 current output
62
CW7
CW channel 7 current output
63
CW8
CW channel 8 current output
64
CW9
CW channel 9 current output
—
GND
PowerPAD must be connected to the analog ground of the printed circuit board; use this ground for
bypass cap return ground.
+3.3V analog supply
I
LNA input channel 5
Internal bias voltage; bypass with 0.1µF (min)
+3.3V Digital supply; connect to analog supply plane (AVDD1)
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SBOS390 – JANUARY 2008
TYPICAL CONNECTION DIAGRAM
+5V
C16
1 mF
OUT8P
C25
2.2mF
C14
0.1mF
C15
1 mF
C24
2.2mF
C3
0.1mF
C13
1 mF
34
33
AVDD1
VREFL
VREFH
35
36
VB4
38
37
VB2
VB6
39
40
IN8
AVDD2
VBL8
41
42
IN7
43
44
IN6
VBL7
46
45
CW5
OUT2
CW6
OUT3
CW7
OUT3
C9
1 mF
C42
OUT6N
R11
0W
32
OUT5P
31
R10
0W
30
29
C41
OUT5N
28
27
26
25
24
23
22
R2
0W
21
20
OUT1P
19
R3
0W
18
C37
OUT1N
17
AVDD1
16
VB5
VB3
VCM
15
13
14
11
1
VB1
OUT4
AVDD2
OUT4
CW9
VBL1
CW8
Flag
PAD
C10
2.2mF
VBS6
IN5
OUT2
12
64
CW9
DVDD
VCNTL
63
CW8
OUT1
10
62
CW7
OUT1
RST
IN4
61
CW6
D_OUT
VBL4
CW5
OUT5
VCA8500
OUT_QFN_RGC-64
9
60
CLK
IN3
C1
0.1mF
OUT5
7
+3.3VD
OUT6
D_IN
8
59
CW4
VBL2
58
RST
OUT6
VBL3
57
CW3
5
CLK
DOUT
OUT7
6
56
OUT7
CW2
IN2
55
DD4
CW1
4
54
CW4
OUT8
AVDD1
53
CW0
IN1
52
OUT8
3
PRODUCT PREVIEW
51
AVDD1
48
VBL5
50
OUT6P
R12
0W
+3.3V
PD
2
49
R13
0W
C7
0.1mF
47
C22
2.2mF
CW3
C43
OUT7N
C31
2.2mF
IN5
CW2
OUT7P
R14
0W
C32
2.2mF
IN6
+3.3V
CW1
R15
0W
C33
2.2mF
C14
1 mF
C44
OUT8N
C34
2.2mF
C23
2.2mF
WC0
R16
0W
C35
2.2mF
IN7
PD
R17
0W
C36
2.2mF
IN8
R4
0W
+3.3V
OUT2P
C6
0.1mF
R5
0W
C30
2.2mF
C38
OUT2N
IN1
+3.3V
C17
2.2mF
C29
2.2mF
C10
1 mF
C2
0.1mF
IN2
R6
0W
OUT3P
C28
2.2mF
C19
2.2mF
R7
0W
C27
2.2mF
C20
2.2mF
C11
1 mF
OUT3N
C26
2.2mF
IN3
R8
0W
OUT4P
C5
0.1mF
C21
2.2mF
R9
0W
C12
1 mF
R1
1kW
C40
OUT4N
+5V
IN4
C39
C4
0.1mF
NOTES:
(1) VCONTROL: Values for R1 and C4 should be selected for a desired time constant.
(2) Outputs: Values for R2 – R17 and C37 – C44 should be selected based on the analog-to-digital converter selected.
(3) The +3.3V supply connections for DVDD and AVDD1 should be joined to a low-noise +3.3V system supply. Consider filtering any supply
noise with an LC filter.
8
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SBOS390 – JANUARY 2008
INPUT REGISTER BIT MAPS
Register Map
BYTE #1
BYTE #2
BYTE #3
BYTE #4
BYTE #5
D0:D7
D8:D11
D12:D15
D16:D19
D20:D23
D24:D27
D28:D31
D32:D35
D36:D39
Control
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
Table 2. Byte 1—Control Byte Register Map
BIT #
NAME
D0 (LSB)
1
DESCRIPTION
D1
R/W
1 = Write, 0 = Read; Read prevents latching of new data/bits. Control register remains
latched with previously loaded data.
D2
PWR
1 = Power-down mode enabled.
D3
BW
Low-pass filter bandwidth setting (see Table 7)
D4
CL
Clamp level setting (see Table 7)
D5
Mode
1 = TGC Mode, 0 = CW Doppler Mode (TGC powered down)
D6
PG0
LSB of PGA Gain Control (see Table 8)
D7 (MSB)
PG1
MSB of PGA Gain Control
PRODUCT PREVIEW
Start bit; must be a ‘1’ (high); 40-bit countdown starts with first falling clock edge.
Table 3. Byte 2—First Data Byte
BIT #
NAME
DESCRIPTION
D8 (LSB)
DB1:1
Channel 1; LSB of Matrix Control
D9
DB1:2
Channel 1, Matrix Control
D10
DB1:3
Channel 1, Matrix Control
D11
DB1:4
Channel 1, MSB of Matrix Control
D12
DB2:1
Channel 2; LSB of Matrix Control
D13
DB2:2
Channel 2, Matrix Control
D14
DB2:3
Channel 2, Matrix Control
D15 (MSB)
DB2:4
Channel 2, MSB of Matrix Control
Table 4. Byte 3—Second Data Byte
BIT #
NAME
DESCRIPTION
D16 (LSB)
DB3:1
Channel 3; LSB of Matrix Control
D17
DB3:2
Channel 3, Matrix Control
D18
DB3:3
Channel 3, Matrix Control
D19
DB3:4
Channel 3, MSB of Matrix Control
D20
DB4:1
Channel 4; LSB of Matrix Control
D21
DB4:2
Channel 4, Matrix Control
D22
DB4:3
Channel 4, Matrix Control
D23 (MSB)
DB4:4
Channel 4, MSB of Matrix Control
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Table 5. Byte 4—Third Data Byte
BIT #
NAME
DESCRIPTION
D24 (LSB)
DB5:1
Channel 5; LSB of Matrix Control
D25
DB5:2
Channel 5, Matrix Control
D26
DB5:3
Channel 5, Matrix Control
D27
DB5:4
Channel 5, MSB of Matrix Control
D28
DB6:1
Channel 6; LSB of Matrix Control
D29
DB6:2
Channel 6, Matrix Control
D30
DB6:3
Channel 6, Matrix Control
D31 (MSB)
DB6:4
Channel 6, MSB of Matrix Control
Table 6. Byte 5—Fourth Data Byte
PRODUCT PREVIEW
BIT #
NAME
DESCRIPTION
D32 (LSB)
DB7:1
Channel 7; LSB of Matrix Control
D33
DB7:2
Channel 7, Matrix Control
D34
DB7:3
Channel 7, Matrix Control
D35
DB7:4
Channel 7, MSB of Matrix Control
D36
DB8:1
Channel 8; LSB of Matrix Control
D37
DB8:2
Channel 8, Matrix Control
D38
DB8:3
Channel 8, Matrix Control
D39 (MSB)
DB8:4
Channel 8, MSB of Matrix Control
Table 7. Clamp Level and LPF Bandwidth Setting
NAME
BW
CL
SETTING
FUNCTION
D3 = 0
Bandwidth set to 10 MHz
D3 = 1
Bandwidth set to 15 MHz
D4 = 0
Clamps the output signal at 2 dB below the full-scale of 2 VPP (1.6 VPP) on each PGA output
channel
D4 = 1
Clamp transparent (disabled)
Table 8. PGA Gain Setting
10
PG1
PG0
FUNCTION
0
0
Set PGA gain to 20dB
0
1
Set PGA gain to 25dB
1
0
Set PGA gain to 27dB
1
1
Set PGA gain to 30dB
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SBOS390 – JANUARY 2008
Table 9. CW Switch Matrix Control for Each Channel
DBn:4
(MSB)
DBn:3
DBn:2
DBn:1
(LSB)
0
0
0
0
Output CW0
0
0
0
1
Output CW1
0
0
1
0
Output CW2
0
0
1
1
Output CW3
0
1
0
0
Output CW4
0
1
0
1
Output CW5
0
1
1
0
Output CW6
0
1
1
1
Output CW7
1
0
0
0
Output CW8
1
0
0
1
Output CW9
1
0
1
0
Connected to AVDD1
1
0
1
1
Connected to AVDD1
1
1
0
0
Connected to AVDD1
1
1
0
1
Connected to AVDD1
1
1
1
0
Connected to AVDD1
1
1
1
1
Connected to AVDD1
PRODUCT PREVIEW
LNA Input Channel Directed To:
Table 10 shows the default register configuration at device power-up, or after a reset cycle.
Table 10. Default Register Configuration
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
1
1
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SBOS390 – JANUARY 2008
WRITE/READ TIMING
•
•
•
•
•
•
All writes and reads are five bytes at a time. Each byte consists of 8 bits, for a total instruction set of 40 bits.
Data are latched on the falling edge of CLK.
Separate write (DIN) and read data (DOUT) lines.
Reads follow the same bitstream pattern seen in the write cycle.
Reads extract data from the FIFO buffer, not the latched register.
DOUT data are continuously available and do not need to be enabled with a read cycle. Selecting a read
cycle in the control register only prevents latching of data. The control register remains latched.
The Reset pin (RS) must be low in order to allow the register to update with new data. RST can be held low
permanently. To initiate a reset cycle, pull the RST pin high for at least 100ns.
•
WRITE CYCLE TIMING
RST (Low)
t2
CLK
t3
PRODUCT PREVIEW
DIN
D0 (LSB)
t1
t4
t5
D1
D2
D3
D5
D4
D6
D7 (MSB)
NOTE: Figure shows timing example for one data byte. A full register update cycle requires all five bytes (that is, 40 bits).
SERIAL PORT TIMING TABLE
PARAMETER
DESCRIPTION
MIN
t1
Serial CLK Period
100
ns
t2
Serial CLK HIGH Time
40
ns
t3
Serial CLK LOW Time
40
ns
t4
Data Hold Time
5
ns
Data Setup Time
5
ns
Reset Pulse (L - H - L)
100
ns
t5
12
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TYP
MAX
UNIT
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Jan-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
VCA8500IRGCR
PREVIEW
QFN
RGC
64
2000
TBD
Call TI
Call TI
VCA8500IRGCT
PREVIEW
QFN
RGC
64
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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