0 W245-30 Frequency Multiplying, Peak Reducing EMI Solution Features Key Specifications • Cypress PREMIS™ family offering • Generates an EMI optimized clocking signal at the output • Selectable output frequency range • Single 1.25%, 2.5%, 5% or 10% down or center spread output • Integrated loop filter components • Operates with a 3.3 or 5V supply • Low power CMOS design • Available in 20-pin SSOP (Small Shrunk Outline Package) Supply Voltages:......................................... VDD = 3.3V±0.3V or VDD = 5V±10% Frequency range: ........................... 13 MHz < Fin < 120 MHz Cycle to Cycle Jitter: .........................................250 ps (max) Output duty cycle: .................................40/60% (worst case) Pin Configuration [1, 2] Simplified Block Diagram 3.3V or 5.0V SSOP X1 XTAL Input W245-30 SDATA Spread Spectrum Output (EMI suppressed) IIC Interface SCLK 3.3V or 5.0V Oscillator or Reference Input 1 2 3 4 5 OR1^ SCLK GND 6 7 8 OR2* SSON#^ 9 10 W245-30 X1 X2 AVDD MW0^ SDATA X2 20 19 18 17 16 REFOUT VDD GND IR1* IR2* 15 SSOUT 14 13 MW1* GND 12 VDD 11 MW2^ X1 W245-30 SDATA IIC Interface Spread Spectrum Output (EMI suppressed) SCLK Cypress Semiconductor Corporation Document #: 38-07229 Rev. *B • 3901 North First Street Notes: 1. Pins marked with ^ are internal pull-down resistors with weak 250 kΩ. 2. Pins marked with * are internal pull-up resistors with weak 80 kΩ. • San Jose • CA 95134 • 408-943-2600 Revised August 13, 2002 W245-30 Pin Description Pin No. Pin Type SSOUT 15 O Output Modulated Frequency: Frequency modulated copy of the input clock (SSON# asserted). REFOUT 20 O Non-Modulated Output: This pin provides a copy of the reference frequency. This output will not have the Spread Spectrum feature enabled regardless of the state of logic input SSON#. X1 1 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. X2 2 I Crystal Connection: Input connection for an external crystal. If using an external reference, this pin must be left unconnected. SSON# 10 I Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. MW0:2 4, 11, 14 I Modulation Width Selection: When Spread Spectrum feature is turned on, these pins are used to select the amount of variation and peak EMI reduction that is desired on the output signal. MW1:Down, MW1:Up, MW2:Down (See Table 2). IR1:2 17, 16 I Reference Frequency Selection: Logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. Refer to Table 3. These pins have internal pull-up resistors. OR1:2 6, 9 I Output Frequency Selection Bits: These pins select the frequency operation for the output. Refer to Table 1. OR2 pin have internal pull-up resistors. OR1 pin have internal pull-down resistors. SCLK 7 I Clock pin for SMBus circuitry. SData 5 I/O Data pin for SMBus Circuitry. VDD 12, 19 P Power Connection: Connected to 3.3V or 5V power supply. AVDD 3 P Analog Power Connection: Connected to 3.3V or 5V power supply. GND 8, 13, 18 G Ground Connection: Connect all ground pins to the common ground plane. Pin Name Document #: 38-07229 Rev. *B Pin Description Page 2 of 12 W245-30 Table 1. Frequency Configuration (Frequencies in MHz) Range of Fin Frequency Min. Max. Multiplier Settings Output / Input OR2 OR1 Required R Settings Range of Fout Min. Max. IR2 IR1 Modulation & Power Down Settings MW2 MW1 14 30 0 1 1 14 30 0 1 Table 2 14 30 1 0 2 28 60 0 1 Table 2 14 30 1 1 4 56 120 0 1 Table 2 25 60 0 1 0.5 13 30 1 0 Table 2 25 60 1 0 1 25 60 1 0 Table 2 25 60 1 1 2 50 120 1 0 Table 2 50 120 0 1 0.25 13 30 1 1 Table 2 50 120 1 0 0.5 25 60 1 1 Table 2 120 50 1 1 1 50 120 1 1 Reserved 0 0 N/A N/A N/A As Set As Set 1 Table 2 0 Power Down Hi-Z 0 0 N/A N/A N/A As Set As Set 1 1 Power Down 0 0 0 N/A N/A N/A As Set As Set 0 0 Power Down 1 0 0 N/A N/A N/A As Set As Set 0 1 Table 2. Modulation Width Selection Table EMI Reduction Modulation Setting Bandwith Limit Frequencies as a% Value of Fout MW0 = 0 MW0 = 1 MW2 MW1 Low High Low High Minimum EMI Control 0 0 98.75% 100% 99.375% 100.625 Suggested Setting 0 1 97.5% 100% 98.75 101.25% Alternate Setting 1 0 95.0% 100% 97.5% 102.5% Maximum EMI reduction 1 1 90.0% 100% 95% 105% Overview The W245-30 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. Functional Description The W245-30 uses a phase locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q Document #: 38-07229 Rev. *B times the reference frequency. (Note: For the W245-30 the output frequency is nominally equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. Using frequency select bits (FS2:1 pins), the frequency range can be set (see Table 2). Spreading percentage is set with pins MW0:2 as shown in Table 2. A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentage options are provided. Page 3 of 12 W245-30 VDD Clock Input Reference Input Freq. Divider Q Phase Detector Charge Pump Σ VCO Post Dividers CLKOUT (EMI suppressed) Modulating Waveform Feedback Divider P PLL GND Figure 1. Functional Block Diagram Document #: 38-07229 Rev. *B Page 4 of 12 W245-30 Spread Spectrum Frequency Timing Generator Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2. The output clock is modulated with a waveform depicted in Figure 3. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is as described in Table 2. Figure 3 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 2, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Amplitude (dB) EMI Reduction Spread Spectrum Enabled NonSpread Spectrum Frequency Span (MHz) Down Spread Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX. MIN. Figure 3. Typical Modulation Profile Document #: 38-07229 Rev. *B Page 5 of 12 W245-30 Serial Data Interface The W245-30 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W245-30 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 3 summarizes the control functions of the serial data interface. Operation Data is written to the W245-30 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4. Table 3. Serial Data Interface Control Functions Summary Control Function Description Common Application Clock Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held low. Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. CPU Clock Frequency Selection Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Spread Spectrum Enabling Enables or disables spread spectrum clocking. For EMI reduction. Output Three-state Puts clock output into a high impedance state. Production PCB testing. (Reserved) Reserved function for future device revision or production device testing. No user application. Register bit must be written as 0. Table 4. Byte Writing Sequence Byte Sequence Byte Name Bit Sequence Byte Description 1 Slave Address 11010010 Commands the W245-30 to accept the bits in Data Bytes 0-6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W245-30 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W245-30, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W245-30, therefore bit values are ignored (don’t care). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 5 Data Byte 1 Refer to Table 5 6 Data Byte 2 7 Data Byte 3 The data bits in Data Bytes 0–7 set internal W245-30 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 3, Data Byte Serial Configuration Map. 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 11 Data Byte 7 Document #: 38-07229 Rev. *B Page 6 of 12 W245-30 Writing Data Bytes Each bit in Data Bytes 0–7 control a particular device function except for the “reserved” bits which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit 7. Table 5 gives the bit formats for registers located in Data Bytes 0–7. Table 5. Data Bytes 0–7 Serial Configuration Map Affected Pin Bit(s) Pin No. Bit Control Pin Name Control Function 0 1 Default Data Byte 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 Data Byte 1 Data Byte 2 Data Byte 3 Document #: 38-07229 Rev. *B Page 7 of 12 W245-30 Table 5. Data Bytes 0–7 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. Pin Name 0 -- -- 7 16 6 5 Bit Control Control Function 0 1 Default (Reserved) -- -- 0 IR2 MSB of Input Range Select Refer to Table 1 0 17 IR1 LSB of Input Range Select Refer to Table 1 0 9 OR2 MSB of Output Range Select Refer to Table 1 0 4 6 OR1 LSB of Output Range Select Refer to Table 1 0 3 -- -- Hardware/Software Frequency Select 2 -- -- Stop Function 1 10 SSON# 0 4 MW0 LSB of Modulation Width Selection Refer to Table 2 0 7 11 MW2 MSB of Modulation Width Selection Refer to Table 2 0 6 14 MW1 Modulation Width Selection Bit Refer to Table 2 0 5 20 REFOUT Output Enable Disabled Enabled 1 4 15 SSOUT Output Enable Disabled Enabled 1 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 Data Byte 4 Spread Spectrum Hardware Software 0 PLL Off PLL ON 0 Spread On Spread Off 0 Data Byte 5 Data Byte 6 Data Byte 7 Document #: 38-07229 Rev. *B Page 8 of 12 W245-30 Absolute Maximum Ratings[3] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±0.3V [4] Parameter Description IDD Supply Current tON Power Up Time Test Condition Min. Typ. Max. Unit 18 32 mA 5 ms First locked clock cycle after Power Good VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 4 -100 µA IIH Input High Current Note 4 10 µA IOL Output Low Current @ 0.4V, VDD = 3.3V 15 mA IOH Output High Current @ 2.4V, VDD = 3.3V 15 mA CI Input Capacitance RP Input Pull-Up Resistor 250 kΩ ZOUT Clock Output Impedance 25 Ω 0.8 2.4 V V 0.4 2.4 V V 7 pF Note: 3. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up. 4. Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor. Document #: 38-07229 Rev. *B Page 9 of 12 W245-30 DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10% Parameter Description Test Condition Min. Typ. Max. Unit 30 50 mA 5 ms 0.15VDD V IDD Supply Current tON Power Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 4 100 µA IIH Input High Current Note 4 10 µA IOL Output Low Current @ 0.4V, VDD = 5V 24 mA IOH Output High Current @ 2.4V, VDD = 5V 24 mA CI Input Capacitance RP Input Pull-Up Resistor 250 kΩ ZOUT Clock Output Impedance 25 Ω First locked clock cycle after Power Good 0.7VDD V 0.4 V 2.4 V 7 pF AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±0.3V or 5V±10% Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency Input Clock 14 120 MHz fOUT Output Frequency Spread Off 13 120 MHz tR Output Rise Time 15-pF load, 0.8V–2.4V 2 5 ns tF Output Fall Time 15-pF load, 2.4V–0.8V 2 5 ns tOD Output Duty Cycle 15-pF load 40 60 % tID Input Duty Cycle 40 60 % tJCYC Jitter, Cycle-to-Cycle 300 ps 250 Ordering Information Ordering Code Package Type Product Flow W245-30H 20-Pin Plastic SSOP (209-mil) Commercial, 0°C to 70°C W245-30HT 20-Pin Plastic SSOP (209-mil)- Tape and Reel Commercial, 0°C to 70°C Document #: 38-07229 Rev. *B Page 10 of 12 W245-30 Package Drawing and Dimension 20-Lead (5.3 mm) Shrunk Small Outline Package O20 51-85077-*C PREMIS is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be trademarks of their respective holders. Document #: 38-07229 Rev. *B Page 11 of 12 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W245-30 Document Title: W245-30 Frequency Multiplying, Peak Reducing EMI Solution Document Number: 38-07229 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110494 01/07/02 SZV Change from Spec number: 38-00912 to 38-07229 *A 117404 08/19/02 RGL Corrected the Ordering Information to match the DevMaster *B 122693 12/27/02 RBI Added power up requirements to maximum rating information. Document #: 38-07229 Rev. *B Page 12 of 12