ETC WE512K16

WE512K16-XG4X
HI-RELIABILITY PRODUCT
512Kx16 CMOS EEPROM MODULE
FEATURES
■ Access Time of 140, 150, 200ns
■ Automatic Page Write Operation
■ Packaging:
■ Page Write Cycle Time: 10ms Max
■ Data Polling for End of Write Detection
• 68 lead, 40mm Hermetic CQFP (Package 501)
■ Organized as 4 banks of 128Kx16
■ Hardware and Software Data Protection
■ Write Endurance 10,000 Cycles
■ TTL Compatible Inputs and Outputs
■ Data Retention Ten Years Minimum
■ 5 Volt Power Supply
■ Military Temperature Range
■ 8 Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
■ Low Power CMOS
■ Weight - 20 grams typical
FIG. 1
PIN CONFIGURATION
PIN DESCRIPTION
NC
A0
A1
A2
A3
A4
A5
CS1
GND
CS3
WE
A6
A7
A8
A9
A10
VCC
TOP VIEW
I/O0-15 Data Inputs/Outputs
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC
NC
INC
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
A0-16
Address Inputs
WE
Write Enable
CS1-4
Chip Selects
OE
Output Enable
VCC
Power Supply
GND
Ground
NC
Not Connected
BLOCK DIAGRAM
CS 1 C S 2 CS 3 CS 4
A0-16
OE
WE
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
128K x 8
128K x 8
VCC
A11
A12
A13
A14
A15
A16
CS2
OE
CS4
NC
NC
NC
NC
NC
NC
NC
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
128K x 8
I/O0-7
I/O8-15
NOTE:
CS 1-4 are used as bank selects. During reads, only one CSx can be
active at one time.
April 1999 Rev. 2
1
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WE512K16-XG4X
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Operating Temperature
Unit
-55 to +125
°C
T STG
-65 to +150
°C
VG
-0.6 to +6.25
V
-0.6 to +13.5
V
TA
Storage Temperature
Signal Voltage Relative to GND
TRUTH TABLE
Voltage on OE and A9
CS
H
L
L
X
X
X
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
WE
X
H
L
X
H
X
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
CAPACITANCE
(TA = +25°C)
Parameter
RECOMMENDED OPERATING CONDITIONS
Parameter
OE
X
L
H
H
X
L
Symbol
Conditions
Max
Unit
OE capacitance
COE
VIN = 0 V, f = 1.0 MHz
50
pF
WE capacitance
CWE
VIN = 0 V, f = 1.0 MHz
50
pF
Symbol
Min
Max
Unit
Supply Voltage
V CC
4.5
5.5
V
CS1-4 capacitance
CCS
VIN = 0 V, f = 1.0 MHz
25
pF
Input High Voltage
V IH
2.0
Vcc + 0.3
V
Data I/O capacitance
CI/O
VI/O = 0 V, f = 1.0 MHz
40
pF
Input Low Voltage
V IL
-0.3
+0.8
V
Address input capacitance
CAD
VIN = 0 V, f = 1.0 MHz
70
pF
Operating Temp. (Mil.)
TA
-55
+125
°C
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Parameter
Max
Unit
Input Leakage Current
Symbol
ILI
VCC = 5.5, VIN = GND to VCC
10
µA
Output Leakage Current
ILO
CS = VIH, OE = VIH, VOUT = GND to VCC
10
µA
CS1 = VIL, OE = CS2-4 = VIH, f = 5MHz, VCC = 5.5
160
mA
Operating Supply Current (x16)
ICCx16
Conditions
Min
Chip Erase Current
ICC1
CS = VIL, OE = VIH, f = 5MHz, VCC = 5.5
250
mA
Standby Current (CMOS)
ISB
CS = VIH, OE = VIH, f = 5MHz, VCC = 5.5
5
mA
Output Low Voltage
VOL
IOL = 2.1mA, VCC = 4.5V
Output High Voltage
VOH
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
0.45
IOH = -400µA, VCC = 4.5V
FIG. 2
AC TEST CIRCUIT
V
2.4
V
AC TEST CONDITIONS
Parameter
I OL
Current Source
VZ
D.U.T.
≈ 1.5V
(Bipolar Supply)
C eff = 50 pf
I OH
Current Source
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
2
Typ
Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall
5
ns
Input and Output Reference Level
1.5
V
Output Timing Reference Level
1.5
V
NOTES:
V Z is programmable from -2V to +7V.
I OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
V Z is typically the midpoint of VOH and V OL.
I OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
WE512K16-XG4X
AC WRITE CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
WRITE
A write cycle is initiated when OE is high and a low pulse is on WE
or CS with CS or WE low. The address is latched on the falling
edge of CS or WE whichever occurs last. The data is latched by
the rising edge of CS or WE, whichever occurs first. A word write
operation will automatically continue to completion.
Write Cycle Parameter
WRITE CYCLE TIMING
Figures 3 and 4 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the CS line
low. Write enable consists of setting the WE line low. The
write cycle begins when the last of either CS or WE goes low.
The WE line transition from high to low also initiates an
internal 150 µsec delay timer to permit page mode operation.
Each subsequent WE transition from high to low that occurs
before the completion of the 150 µsec time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.
3
Symbol
Min
Max
Unit
10
ms
Write Cycle Time, TYP = 6ms
tWC
Address Set-up Time
tAS
10
ns
Write Pulse Width (WE or CS)
tWP
120
ns
Chip Select Set-up Time
tCS
0
ns
Address Hold Time
tAH
100
ns
Data Hold Time
tDH
10
ns
Chip Select Hold Time
tCSH
0
ns
Data Set-up Time
tDS
100
ns
Output Enable Set-up Time
tOES
10
ns
Output Enable Hold Time
tOEH
10
ns
Write Pulse Width High
tWPH
50
ns
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WE512K16-XG4X
FIG. 3
WRITE WAVEFORM
WE CONTROLLED
t WC
OE
t OEH
t OES
ADDRESS
t AS
CS 1-4
tCSH
t AH
t CS
WE
t WP
t WPH
t DS
t DH
DATA IN
FIG. 4
WRITE WAVEFORM
CS CONTROLLED
t WC
OE
t OEH
t OES
ADDRESS
t AS
tCSH
t AH
WE
t CS
CS1 - 4
t WP
t WPH
t DS
DATA IN
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
4
t DH
WE512K16-XG4X
READ
The module stores data at the memory location determined by
the address pins. When CS and OE are low and WE is high,
this data is present on the outputs. When CS and OE are high,
the outputs are in a high impedance state. This two line
control prevents bus contention.
AC READ CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Read Cycle Parameter
Symbol
-140
Min
140
-150
Max
Min
150
-200
Max
Min
200
Unit
Max
Read Cycle Time
t RC
Address Access Time
t ACC
140
150
200
ns
Chip Select Access Time
t ACS
140
150
200
ns
Output Hold from Add. Change, OE or CS
t OH
0
Output Enable to Output Valid
t OE
0
Chip Select or OE to High Z Output
t DF
0
50
ns
0
0
55
50
70
0
ns
55
ns
70
ns
FIG. 5
READ WAVEFORM
t RC
ADDRESS
ADDRESS VALID
CS1-4
t ACS
t OE
OE
t DF
NOTES:
OE may be delayed up to tACS - tOE after the
OUTPUT
falling edge of CS without impact on tOE or by
t ACC - tOE after an address change without
impact on tACC .
CS1-4 are used as bank selects.
During reads, only one CSx can be active at one
time.
t ACC
HIGH Z
5
t OH
OUTPUT
VALID
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WE512K16-XG4X
DATA POLLING
The module offers a data polling feature which allows a faster
method of writing to the device. Figure 6 shows the timing
diagram for this function. During a word or page write cycle,
an attempted read of the last word written will result in the
complement of the written data on I/O7 and I/O15. Once the
write cycle has been completed, true data is valid on all
outputs and the next cycle may begin. Data polling may begin
at any time during the write cycle.
DATA POLLING CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Min
Data Hold Time
tDH
10
OE Hold Time
tOEH
10
OE To Output Valid
tOE
Write Recovery Time
tWR
Max
Unit
ns
ns
55
0
ns
ns
FIG. 6
DATA POLLING
WAVEFORM
WE
CS1-4
t OEH
OE
t DH
I/O7
I/O15
t OE
HIGH Z
t WR
ADDRESS
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
6
WE512K16-XG4X
PAGE WRITE OPERATION
PAGE WRITE CHARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C to +125°C)
The module has a page write operation that allows one to 128
words of data to be written into the device and consecutively loads
during the internal programming period. Successive words may be
loaded in the same manner after the first data word has been
loaded. An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 150µs or
less, a new time out period begins. Each write cycle restarts the
delay period. The write cycles can be continued as long as the
interval is less than the time out period.
Page Mode Write Characteristics
Symbol
Parameter
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In this
manner a page of up to 128 words can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.
Unit
Min
Max
Write Cycle Time, TYP = 6ms
tWC
Address Set-up Time
tAS
0
ns
Address Hold Time (1)
tAH
50
ns
Data Set-up Time
tDS
50
ns
Data Hold Time
tDH
0
ns
Write Pulse Width
tWP
100
ns
Word Load Cycle Time
tBLC
Write Pulse Width High
tWPH
10
150
50
ms
µs
ns
1. Page address must remain valid for duration of write cycle.
After the 150µs time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of words
will be written at the same time. The internal programming
cycle is the same regardless of the number of words accessed.
FIG. 7
PAGE MODE
WRITE WAVEFORM
OE
CS1-4
t WP
t WPH
t BLC
WE
t AS
ADDRESS
t AH
VALID
ADDRESS
t DS
DATA
WORD 0
t WC
t DH
WORD 1
WORD 2
7
WORD 3
WORD 126
WORD 127
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WE512K16-XG4X
FIG. 8
SOFTWARE DATA PROTECTION
ENABLE ALGORITHM(1)
LOAD DATA AAAA
TO
ADDRESS 5555
➞
LOAD DATA 5555
TO
ADDRESS 2AAA
➞
WRITES ENABLED(2)
➞
LOAD DATA A0A0
TO
ADDRESS 5555
➞
LOAD DATA XXXX
TO
ANY ADDRESS(4)
LOAD LAST WORD
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1. Data Format: I/O15- 0 (Hex);
Address Format: A16- 0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 words of data may be loaded.
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
8
WE512K16-XG4X
SOFTWARE DATA PROTECTION
FIG. 9
A software write protection feature may be enabled or disabled
by the user. When shipped by White Microelectronics, the
module has the feature disabled. Write access to the device is
unrestricted.
SOFTWARE DATA PROTECTION
DISABLE ALGORITHM(1)
To enable software write protection, the user writes three
access code words to three special internal locations. Once
write protection has been enabled, each write to the EEPROM
must use the same three-word write sequence to permit
writing. After setting software data protection, any attempt to
write to the device without the three-word command sequence
will start the internal write timers. No data will be written to
the device, however, for the duration of tWC. The write
protection feature can be disabled by a six-word write
sequence of specific data to specific locations. Power
transitions will not reset the software write protection.
LOAD DATA AAAA
TO
ADDRESS 5555
➞
LOAD DATA 5555
TO
ADDRESS 2AAA
➞
LOAD DATA 8080
TO
ADDRESS 5555
➞
Each 128K-word block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions, or
unauthorized modification using a PROM programmer.
LOAD DATA AAAA
TO
ADDRESS 5555
➞
LOAD DATA 5555
TO
ADDRESS 2AAA
➞
HARDWARE DATA PROTECTION
(3)
These features protect against inadvertent writes to the
module. These are included to improve reliability during
normal operation:
LOAD DATA XXXX
TO
ANY ADDRESS(4)
a) V CC power on delay
As VCC climbs past 3.8V typical the device will wait 5 msec
typical before allowing write cycles.
LOAD LAST WORD
TO
LAST ADDRESS
b) V CC sense
While below 3.8V typical write cycles are inhibited.
➞
EXIT DATA
PROTECT STATE
LOAD DATA 2020
TO
ADDRESS 5555
➞
c) Write inhibiting
Holding OE low and either CS or WE high inhibits write
cycles.
d) Noise filter
Pulses of <8ns (typ) on WE or CS will not initiate a write
cycle.
NOTES:
1. Data Format: I/O15- 0 (Hex);
Address Format: A16- 0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 words of data may be loaded.
9
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WE512K16-XG4X
PACKAGE 501:
68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G4)
39.6 (1.56) ± 0.38 (0.015) SQ
5.1 (0.200) MAX
1.27 (0.050)
± 0.1 (0.005)
PIN 1 IDENTIFIER
Pin 1
12.7 (0.500)
± 0.5 (0.020)
4 PLACES
5.1 (0.200)
± 0.25 (0.010)
4 PLACES
1.27 (0.050)
TYP
0.38 (0.015)
± 0.08 (0.003)
68 PLACES
0.25 (0.010)
± 0.05 (0.002)
38 (1.50) TYP
4 PLACES
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W E 512K16 - XXX G4 X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
PROCESSING:
Q = MIL-STD-883 Compliant
M = Military Screened
-55°C to +125°C
I = Industrial
-40°C to +85°C
C = Commercial
0°C to +70°C
PACKAGE:
G4 = 40mm Ceramic Quad Flat Pack, CQFP (Package 501)
ACCESS TIME (ns)
ORGANIZATION, 4 banks of 128Kx16
EEPROM
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
10