WED2DL32512V 512Kx32 Synchronous Pipeline Burst SR AM SRAM FEATURES DESCRIPTION n Fast clock speed: 200, 166, 150 & 133MHz The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16 SRAMs into a single BGA package to provide 512K x 32 configuration. All synchronous inputs pass through registers controlled by a positive-edgetriggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE), burst control input (ADSC) and byte write enables (BW 0-3). Asynchronous inputs include the output enable (OE), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. Write cycles can be from one to four bytes wide, as controlled by the write control inputs. Burst operation can be initiated with the address status controller (ADSC) input. n Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns n Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns n Single +3.3V power supply (V DD) n Separate +3.3V or +2.5V isolated output buffer supply (V DDQ) n Snooze Mode for reduced-power standby n Single-cycle deselect n Common data inputs and data outputs n Individual Byte Write control and Global Write n Clock-controlled and registered addresses, data I/Os and control signals n Burst control (interleaved or linear burst) n Packaging: • 119-bump BGA package n Low capacitive bus loading FIG. 1 PIN CONFIGURATION (TOP VIEW) A BLOCK DIAGRAM 1 2 3 4 5 6 7 VDDQ SA SA NC SA SA VDDQ SA CLK B NC SA SA ADSC SA SA NC C NC SA SA VDD SA SA NC OE D DQ C NC VSS NC VSS NC DQ B BWE E DQ C DQ C VSS CE F VDDQ G DQ C DQ C Vss DQ C BW C H DQ C DQ C J VDDQ K DQ D L DQ D M ADSC CE VSS DQ B DQ B OE VSS DQ B VDDQ ZZ NC BW B DQ B DQ B BWA VSS NC VSS DQ B DQ B VDD NC VDD NC VDD VDDQ DQ D VSS CLK VSS DQ A DQ A DQ D BW D NC BW A DQ A DQ A VDDQ DQ D VSS BWE VSS DQ A VDDQ N DQ D DQ D VSS SA 1 VSS DQ A DQ A P DQ D NC VSS SA 0 VSS NC DQ A R NC SA MODE VDD NC SA NC T NC NC SA SA SA NC ZZ U VDDQ DC DC DC DC NC VDDQ NOTE: 512K x 16 SSRAM DQA 512K x 16 SSRAM DQC DQB MODE BWB DQD BWC BWD DC = Do Not Connect January 2002 Rev. 2 ECO# 14663 1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WED2DL32512V PIN DESCRIPTION Symbol Type Description CLK 4P 4N 2A, 2C, 2R, 2B 3A, 3B, 3C, 3T 4T, 5A, 5B, 5C, 5T, 6A, 6B, 6C, 6R 5L 5G 3G 3L Input SA 0 SA 1 SA Pulse Input The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. BW A BW B BW C BW D Input 4M BWE Input 4K CLK Input 4E CE Input 7T ZZ Input 4F 4B OE ADSC Input Input 3R MODE Input DQ A Input/ Output Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BW A controls DQ A ’s and DQPA ; BW B controls DQ B ’s and DQP B; BW C controls DQ C ’s and DQPC ; BW D controls DQ D’s and DQP D. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP. CE is sampled only when a new external address is loaded. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE is LOW. ADSC is also used to place the chip into power-down state when CE is HIGH. Mode: This input selects the burst sequence. A LOW on MODE selects “linear burst.” NC or HIGH on this input selects “interleaved burst.” Do not alter input state while device is operating. SRAM Data I/Os: Byte “ A” is DQ A ’s; Byte “ B” is DQ B’s; Byte “ C” is DQ C ’s; Byte “ D” is DQd’s. Input data must meet setup and hold times around rising edge of CLK. (a) 6K, 6L, 6M, 6N, 7K, 7L, 7N, 7P (b) 6E, 6F, 6G, 6H, 7D, 7E, 7G, 7H (c) 1D, 1E, 1G, 1H 2E, 2F, 2G, 2H (d) 1K, 1L, 1N, 1P, 2K, 2L, 2M, 2N 2J, 4C, 4J, 4R, 6J, 1A, 1F, 1J, 1M 1U 7A, 7F, 7J, 7M, 7U 3D, 3E, 3F, 3H, 3K, 3M, 3N, 3P, 5D, 5E, 5F, 5H, 5K, 5M, 5N, 5P DQ B DQ C DQ D V DD VDDQ Supply Supply VSS Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 2 WED2DL32512V INTERLEAVED BURST TABLE INTERLEAVED BURST TABLE (MODE = NC OR HIGH) (MODE = LOW) First Address Second Address Third Address Four th Address First Address Second Address Third Address Fourth Address External Inter nal Inter nal Inter nal External Internal Internal Internal X...X00 X...X01 X...X10 X...X11 X...X01 X....X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 X...X00 X...X01 X...X10 X...X11 X...X01 X....X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 TRUTH TABLE Function Address CE ZZ ADSC WRITE OE CLK DQ Used Deselected Cycle, Power-Down None H L L X X L-H Deselected Cycle, Power-Down None L L L X X L-H SNOOZE MODE, Power-Down None X H X X X X WRITE Cycle, Begin Burst External L L L L X L-H READ Cycle, Begin Burst External L L L H L L-H READ Cycle, Begin Burst External L L L H H L-H READ Cycle, Suspend Burst Current X L H H L L-H READ Cycle, Suspend Burst Current X L H H H L-H READ Cycle, Suspend Burst Current H L H H L L-H READ Cycle, Suspend Burst Current H L H H H L-H WRITE Cycle, Suspend Burst Current X L H L X L-H WRITE Cycle, Suspend Burst Current H L H L X L-H NOTES : 1. X means “Don’t Care.” — means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE, L means any one or more byte write enable signals (BWA, BWB, BWC or BWD) and BWE are LOW. 3. BWA enables WRITEs to DQA’s and DQPA. BWB enables WRITEs to DQB’s. BWC enables WRITEs to DQC’s. BWD enables WRITEs to DQD’s. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH throughout the input data 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 3 High-Z High-Z High-Z D Q High-Z Q High-Z Q High-Z D D hold time. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WED2DL32512V A BSOLUTE M AXIMUM R ATINGS * PARTIAL TRUTH TABLE - WRITE COMMANDS Function BWE Read Read Write Byte “ A” Write All Bytes BW H L L L X H L L A BW B X H H L BW C BW X H H L Voltage on VDD Supply relative to VSS Voltage on VDDQ Supply relative to VSS VIN (DQX) VIN (Inputs) Storage Temperature (BGA) Short Circuit Output Current D X H H L Note: Using BWE and BWA through BWD, any one or more bytes may be written. -0.5V to +4.6V -0.5V to +4.6V -0.5V to V DDQ +0.5V -0.5V to VDD +0.5V -55°C to +125°C 100 mA *Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRIC AL C HARACTERISTIC S Description Symbol Conditions Min Max Units Notes 1 Input High (Logic 1)Voltage VIH 2.0 VDD +0.3 V Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1 Input Leakage Current I LI -1.0 1.0 µA 2 µA Ouptut Leakage Current I LO £ VIN £ V DD Output(s) disabled, 0V £ V IN £ V DD -1.0 1.0 Output High Voltage VOH IOH = -4.0mA 2.4 — V 1 Output Low Voltage VOL I OL = 8.0mA — 0.4 V 1 1 0V Supply Voltage VDD 3.135 3.6 V Isolated Output Buffer Supply V DDQ 3.134 3.6 V NOTES: 1. All voltages referenced to Vss (GND). 2. MODE has an internal pull-up, and input leakage = ±10µA. DC CHAR ACTERISTICS Description Symbol Power Supply Current: Operating I DD CMOS Standby ISB 2 TTL Standby ISB 3 Clock Running ISB 4 Conditions Typ 200 166 150 133 MHz MHz MHz MHz 950 800 740 10 20 20 20 40 80 220 £ Device selected; All inputs V IL or 3 V IH ; Cycle time 3 t KC MIN; VDD = MAX; Outputs open Device deselected; V DD = MAX; All inputs Vss + 0.2 or V DD - 0.2; All inputs static; CLK frequency = 0 Device deselected; V DD = MAX; All inputs V IL or VIH ; All inputs static; CLD frequency = 0 Device deselected; V DD = MAX; All inputs VSS + 0.2 or V DD -0.2; Cycle time 3 t KC MIN £ £ £ Units Notes 600 mA 1,2,3 20 20 mA 2,3 40 40 40 mA 2,3 180 160 140 mA 2,3 NOTES: 1. IDD is specified with no output current and increases with faster cycle times. I DD increases with faster cycle times and greater output loading. 2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode). 3. Typical values are measured at 3.3V, 25°C and 133MHz. BGA C APACITANCE Description Conditions Symbol Typ Max Units Notes Control Input Capacitance T A = 25°C; f = 1MHz CI 3 6 pF 1 Input/Output Capacitance (DQ) T A = 25°C; f = 1MHz CO 4 5 pF 1 Address Capacitance T A = 25°C; f = 1MHz CA 3 5 pF 1 Clock Capacitance T A = 25°C; f = 1MHz C CK 2.5 4 pF 1 NOTES: 1. This parameter is sampled. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 4 WED2DL32512V AC C HARACTERISTICS Symbol Parameter 200MHz Min Max 166MHz Min Max 150MHz Min Max 133MHz Min Max Units 133 ns MHz Clock Clock Cycle Time Clock Frequency t KC t KF 5.0 6.0 Clock HIGH Time t KH 2.0 2.4 2.6 2.6 ns Clock LOW Time tKL 2.0 2.4 2.6 2.6 ns 200 6.6 166 7.5 150 Output Times Clock to output valid t KQ Clock to output invalid 2 t KQX 1.5 1.25 1.25 1.5 Clock to output on Low-Z 2,3,4 tKQLZ 0 0 0 0 Clock to output in High-Z 2,3,4 t KQHZ OE to output valid5 tOEQ OE to output in Low-Z2,3,4 t OELZ OE to output in High Z 2,3,4 tOEHZ 2.5 3.5 3.0 3.5 2.5 0 3.8 3.8 3.5 0 2.5 4.0 3.8 0 3.5 ns ns ns 4.0 ns 4.0 ns 4.0 ns 0 3.8 ns Setup Times Address 6,7 t AS 1.5 1.5 1.5 1.5 ns t ADSS 1.5 1.5 1.5 1.5 ns Write signals (BW A -BW D, BWE) 6,7 t WS 1.5 1.5 1.5 1.5 ns Data-in 6,7 t DS 1.5 1.5 1.5 1.5 ns Chip enables (CE) 6,7 t CES 1.5 1.5 1.5 1.5 ns Address status (ADSC) 6,7 Hold Times Address 6,7 tAH 0.5 0.5 0.5 0.5 ns tADSH 0.5 0.5 0.5 0.5 ns Write Signals (BW A -BW D, BWE) 6,7 tWH 0.5 0.5 0.5 0.5 ns Data-in 6,7 tDH 0.5 0.5 0.5 0.5 ns Chip Enables (CE) 6,7 tCEH 0.5 0.5 0.5 0.5 ns Address status (ADSC) 6,7 NOTES: 1. Test conditions as specified with the output loading as shown in Figure 1 for 3.3V 1/0 and Figure 3 for 2.5V 1/0 unless otherwise noted. 2. This parameter is measured with output load as shown in Figure 2 for 3.3V 1/0 and Figure 4 for 2.5V 1/0. 3. This parameter is sampled. 4. Transition is measured ±500mV from steady state voltage. 5. OE is a “Don’t Care” when a byte write enable is sampled LOW. 6. A WRITE cycle is defined by at least one byte write enable LOW for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC LOW for the required setup and hold times. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADSC is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADSC is LOW to remain enabled. OUTPUT LOADS AC T EST C ONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load 3.3V I/O 2.5V I/O VSS to 3.0 VSS to 2.5 1 1 1.5 1.25 1.5 1.25 See figure, at left Unit V ns V V AC Output Load Equivalent 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WED2DL32512V SNOOZE MODE When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE is a low-current, “power-down” mode In which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. SNOOZE MODE Description Conditions Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current FIG. 2 ZZ Symbol ³ VIH I SB 2Z t ZZ t RZZ t ZZI tRZZI SNOOZE MODE TIMING DIAGRAM White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 6 Min Max Units Notes 10 2(t KC ) mA ns ns ns ns 1 1 1 1 2(t KC ) 2(t KC ) WED2DL32512V FIG. 3 READ TIMING DIAGRAM NOTES: 1. Q (A2) refers to output from address A2. Q (A2+1) refers to output from the next internal burst address following A2. 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WED2DL32512V FIG. 4 WRITE TIMING DIAGRAM NOTES: 1. D (A2) refers to output from address A2. D (A 2+1) refers to output from the next internal burst address following A2. 2. OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data content in for the time period prior to the byte write enable inputs being sampled. 3. Full-width WRITE can be initiated by BWE, BWA, - BWD LOW. Timing is shown assuming that the device was not enabled before entering into its sequence. OE does not cause Q to be driven until after the following clock rising edge. White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520 8 WED2DL32512V 119 BUMP PBGA PACKAGE DIMENSION: ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES Note: Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defined. ORDERING INFORMATION 512Kx32 Par t Number Config. t KQ Clock Package (ns) (MHz) No. 200 166 150 133 435 435 435 435 150 133 435 435 Commercial Temp Range (0°C to 70°C) WED2DL32512V25BC WED2DL32512V35BC WED2DL32512V38BC WED2DL32512V40BC 512Kx32 512Kx32 512Kx32 512Kx32 2.5 3.5 3.8 4.0 Industrial Temp Range (-40°C to +85°C)* WED2DL32512V38BI WED2DL32512V40BI * Advanced Information 512Kx32 512Kx32 3.8 4.0 9 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com