WIY2263 Current Mode PWM Controller GERNERAL DESCRIPTION FEATURES ■ Burst Mode function ■ Low startup current (4uA) ■ Low operating current (1.4mA) ■ Built-edge blanking ■ Built-in synchronized slope compensation ■ Current mode ■ External Programmable PWM Switching Frequency ■ By-cycle current limit protection (OCP) ■ VDD over-voltage clamping protection ■ Low voltage shut down function (UVLO) ■ Gate Drive Output Voltage Clamp (18V) ■ Frequency jitter feature ■ Constant output power limit ■ Overload protection (OLP) ■ Work does not produce audio noise APPLICATIONS Offline AC/DC flyback converter for ■ Power Adaptor ■ Open-frame SMPS ■ Battery Charger ■ Set-Top Box Power Supplies WIY2263 is a highly integrated current mode PWM control IC optimized for high performance, low standby power and cost effective offline flyback converter applications in sub 30W range. PWM switching frequency at normal operation is externally programmable and trimmed to tight range. At no load or light load condition, the IC operates in extended ‘burst mode’ to minimize switching loss. Lower standby power and higher conversion efficiency is thus achieved. VDD low startup current and low operating current contribute to a reliable power on startup design with WIY2263. A large value resistor could thus be used in the startup circuit to minimize the standby power. The internal slope compensation improves system large signal stability and reduces the possible sub-harmonic oscillation at high PWM duty cycle output. Leading-edge blanking on current sense(CS) input removes the signal glitch due to snubber circuit diode reverse recovery and thus greatly reduces the external component count and system cost in the design. WIY2263 offers complete protection coverage with automatic self-recovery feature including Cycle-by-Cycle current limiting (OCP), over load protection (OLP), VDD over voltage clamp and under voltage lockout (UVLO). The Gate-drive output is clamped to maximum 18V to protect the power MOSFET. Excellent EMI performance is achieved with Winsemi proprietary frequency shuffling technique together with soft switching control at the totem pole gate drive output. TYPICAL APPLICATION WIY2263 TL431 Rev. A Mar.2010 Copyright@WinSemi Semiconductor Co.,Ltd.,All rights reserved. P02-1 WIY2263 GENERAL INFORMATION Pin Configuration Marking Information Y: Year code(0:2010,1:2011……) ww: Week code(1-52) TERMINAL ASSIGNMENTS Pin Name Pin No. I/O Description GND 1 P FB 2 I RI 3 I SENSE 4 I Current sense input pin. Connected to MOSFET current sensing resistor node. VDD 5 P Chip DC power supply pin GATE 6 O Totem-pole gate drive output for the power MOSFET. Ground Feedback input pin. The PWM duty cycle is determined by voltage level into this pin and SENSE pin input Internal Oscillator frequency setting pin. A resistor connected between RI and GND sets the PWM frequency. BLOCK DIAGRAM 2/9 Steady, all for your advance WIY2263 RECOMMENDED OPERATING CONDITION Min Max Unit VDD Symbol VDD Supply Voltage Parameter 10 30 V RI RI Resistor Value 100 T Operating Ambient Temperature -20 KΩ ℃ 85 ABSOLUTE MAXIMUM RATINGS Pin Name Parameter Ratings Units VDD VDD Pin input voltage 30 V VFB VFB Pin input voltage -0.3~7 V VSENSE VSENSE Pin input voltage -0.3~7 V VRI VRI Pin input voltage -0.3~7 V TJ Operating Junction Temperature -20~150 ℃ TS Storage Temperature -55~160 ℃ Vcv VDD DC Clamping Voltage 34 V ICC VDD DC Clamping Current 10 mA Note: more than the limit specified in the table parameters will result in permanent damage to the device. The device is not recommended in these extreme conditions of work, working conditions in the limit above which may affect device reliability. Electrical Characteristics (Tc = 25°C) Characteristics Symbol Test Condition Min Typ Max Unit 30 V Supply Voltage (VDD) Operation voltage VDD_OP Turn on threshold Voltage UVLO_ON 7.8 8.8 9.8 V Turn-off threshold Voltage UVLO_OFF 13 14 15 V Start up current I_VDD_ST 4 20 μA Operation Current I_VDD_OP 1.4 2.4 mA VDD=13V,RI=100K VDD=16V,RI=100K,VFB=3V, GATE with 1nF to GND VDD Zener Clamp Voltage VDD_Clamp IVDD=10mA 33 V PWM Input Gain AVCS ΔVFB /ΔVcs 2.0 V/V VFB Open Loop Voltage VFB_Open 4.8 V FB pin short circuit current IFB_Short FB Shorted to GND 1.2 mA Zero Duty Cycle FB Threshold Voltage VTH_0D VDD = 16V,RI=100Kohm Power Limiting FB Threshold Voltage VTH_PL Power limiting Debounce Time TD_PL - 35 - ms Input Impedance ZFB_IN - 6 - KΩ Maximum Duty Cycle DC_MAX - 75 - % TLEB - 330 - 8ns Feedback Input Section(FB Pin) 0.75 3.7 V V Current Sense Input(Sense Pin) Leading edge Blanking Time 3/9 Steady, all for your advance WIY2263 Input impedance Zsense - Over Current Detection and Control Delay TD_OC GATE with 1nF to GND VTH_OC FB＝3V 40 - 80 kΩ ns Over Current Threshold Voltage at zero Duty Cycle 0.70 0.75 0.80 V 60 65 70 KHz - 22 - KHz Oscillator Section Oscillation Frequency Fosc @RI=100K,CS=0,FB=3V Oscillation Burst mode frequency Fosc_BM @RI=100K,CS=0,FB=1.1V Frequency variation versus temp. Deviation Δf_temp TEMP = -20 to 85℃ - 5 - % Frequency variation versus VDD Δf_VDD VDD = 12 to 25V - 5 - % Operating RI Range RI_range 50 100 150 KΩ open Load Voltage V_RI_Open - 2 - V Gate Output Section Output voltage Low level VOL VDD = 16V, Io = -20mA - - 0.8 V Output voltage high level VOH VDD = 16V, Io = 20mA 10 - - V Output clamp voltage VClamp - 18 - V Rising time tr - 200 - s - 70 - s -3 - 3 % VDD = 16V, GATE with 1nF to GND VDD = 16V, Falling time tf GATE with 1nF to GND Frequency Shuffling Frequency Modulation range Δf_OSC RI=100K f_shuffling RI=100K /Base frequency Shuffling Frequency 4/9 Steady, all for your advance 64 Hz WIY2263 5/9 Steady, all for your advance WIY2263 6/9 Steady, all for your advance WIY2263 OPERATION DESCRIPTION Gate drive output switches only when VDD voltage drops The WIY2263 is a highly integrated PWM controller IC below a preset level and FB input is active to output an on optimized for offline flyback converter applications in sub 30W state. Otherwise the gate drive remains at off state to power range. The extended burst mode control greatly standby power consumption to the greatest extend. The reduces the standby power consumption and helps the design frequency control also eliminates the audio noise at any easily meet the international power conservation requirements. loading conditions. Startup Current and Start up Control Startup current of WIY2263 is designed to be very low so Oscillator Operation that VDD could be charged up above UVLO threshold level and device starts up quickly. A large value startup resistor can therefore be used to minimize the power loss yet provides reliable startup in application. For AC/DC adaptor with universal input range design, a 2 MΩ, 1/8 W startup resistor could be used together with a VDD capacitor to provide a fast A resistor connected between RI and GND sets the constant current source to charge/discharge the internal cap and thus the PWM oscillator frequency is determined. The relationship between RI and switching frequency follows the below equation within the specified RI in Kohm range at nominal loading operational condition. startup and low power dissipation solution. Fosc = Operating Current The Operating current of WIY2263 is low at 1.4mA. Good 6500 ( KHz ) RI ( KΩ) efficiency is achieved with WIY2263 low operating current Current Sensing and Leading Edge Blanking together with extended burst mode control features. Cycle-by-Cycle current limiting is offered in WIY2263 Frequency shuffling for EMI improvement The frequency Shuffling/jittering (switching frequency modulation) is implemented in WIY2263. The oscillation frequency is modulated with a random source so that the tone energy is spread out. The spread spectrum minimizes the conduction band EMI and therefore reduces system design challenge. current mode PWM control. The switch current is detected by a sense resistor into the sense pin. An internal leading edge blanking circuit chops off the sense voltage spike at initial MOSFET on state due to Snubber diode reverse recovery so that the external RC filtering on sense input is no longer required. The current limit comparator is disabled and thus cannot turn off the external MOSFET during the Extended Burst Mode Operation At zero load or light load condition, majority of the power blanking period. PWM duty cycle is determined by the current sense input voltage and the FB input voltage. dissipation in a switching mode power supply is from switching loss on the MOSFET transistor, the core loss of the Internal Synchronized Slope Compensation transformer and the loss on the snubber circuit. The Built-in slope compensation circuit adds voltage ramp magnitude of power loss is in proportion to the number of onto the current sense input voltage for PWM generation. switching events within a fixed period of time. Reducing This greatly improves the close loop stability at CCM and switching events leads to the reduction on the power loss and prevents the sub-harmonic oscillation and thus reduces the thus conserves the energy. WIY2263 self adjusts the switching output ripple voltage. mode according to the loading condition. At from no load to light/medium load condition, the FB input drops below burst Gate Drive mode threshold level. Device enters Burst Mode control. The WIY2263 Gate is connected to an external MOSFET gate 7/9 Steady, all for your advance WIY2263 for power switch control. Too weak the gate drive strength UnderVoltage Lockout on VDD (UVLO) results in higher conduction and switch loss of MOSFET while With Winsemi Proprietary technology, the OCP threshold too strong gate drive output compromises the EMI. A good tracks PWM Duty cycles and is line voltage compensated to tradeoff is achieved through the built-in totem pole gate design achieve constant output power limit over the universal input with right output strength and dead time control. The low idle voltage range with recommended reference design. loss and good EMI system design is easier to achieve with this At overload condition when FB input voltage exceeds dedicated control scheme. An internal 18V clamp is added for power limit threshold value for more than TD_PL, control MOSFET gate protection at higher than expected VDD input. circuit reacts to shut down the output power MOSFET. Device restarts when VDD voltage drops below UVLO limit. Protection Controls VDD is supplied by transformer auxiliary winding output. It is Good power supply system reliability is achieved with its rich clamped when VDD is higher than threshold value. The protection features including Cycle-by-Cycle current limiting power MOSFET is shut down when VDD drops below UVLO (OCP), Over Load Protection (OLP) and over voltage clamp, limit and device enters power on start-up sequence thereafter. 8/9 Steady, all for your advance WIY2263 SOT23-6 Package Dimension 9/9 Steady, all for your advance